FREESCALE MC34716EPR2

Freescale Semiconductor
Advance Information
Document Number: MC34716
Rev. 3.0, 5/2007
1.0 MHz Dual Switch-Mode DDR
Power Supply
34716
The 34716 is a highly integrated, space-efficient, low cost, dual
synchronous buck switching regulator with integrated N-channel
power MOSFETs. It is a high performance point-of-load (PoL) power
supply with its second output having the ability to track an external
reference voltage. it provides a full power supply solution for DoubleData-Rate (DDR) Memories.
Channel one provides a source only 5.0 A drive capability, while
channel two can sink and source up to 3.0 A. Both channels are highly
efficient with tight output regulation. With its high current drive
capability, channel one can be used to supply the VDDQ to the
memory chipset. The second channel’s ability to track a reference
voltage makes it ideal to provide the termination voltage (VTT) for
modern data buses. The 34716 also provides a buffered output
reference voltage (VREFOUT) to the memory chipset
DUAL SWITCH-MODE DDR POWER
SUPPLY
The 34716 offers the designer the flexibility of many control,
supervisory, and protection functions to allow for easy implementation
of complex designs. It is housed in a Pb-Free, thermally enhanced,
and space efficient 26-Pin Exposed Pad QFN.
Features
• 50 mΩ Integrated N-Channel Power MOSFETs
• Input Voltage Operating Range from 3.0 V to 6.0 V
• ±1 % Accurate Output Voltages, Ranging from 0.7 V to 3.6 V
• The second output Tracks 1/2 an External Reference Voltage
• ±1 % Accurate Buffered Reference Output Voltage
• Programmable Switching Frequency Range from 200 kHz to
1.0 MHz
• Programmable Soft Start Timing for Channel One
• Over Current Limit and Short Circuit Protection on Both Channels
• Thermal Shutdown
• Output Overvoltage and Undervoltage Detection
• Active Low Power Good Output Signal
• Active Low Standby and Shutdown Inputs
• Pb-Free Packaging Designated by Suffix Code EP.
EP SUFFIX
98ASA10728D
26-PIN QFN
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC34716EP/R2
-40 to 85°C
26 QFN
34716
3.0V to 6.0V VIN
VIN
VDDQ
PVIN1
BOOT1
SW1
VOUT1
INV1
COMP1
PGND1
VDDI
FREQ
ILIM1
GND
PVIN2
VDDQ
VREFIN
BOOT2
SW2
VOUT2
VTT
INV2
DDR Memory
Chipset
COMP2
VREFOUT
PGND2
Termination
Resistors
VDDQ
VIN
Memory Bus
DDR Memory
Controller
VREF
PG
STBY
SD
Figure 1. 34716 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
MCU
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
STBY
SD
PG
System
Reset
M1
Thermal
Monitoring
System
Control
Oscillator
FREQ
Buck
Control
Logic
Discharge
VBG
Bandgap
Regulator
ILIM2
ISENSE2
ISENSE1
Current
Monitoring
VDDI
Internal
Voltage
Regulator
ILIM1
ILIM1
VIN
BOOT1
M2
PVIN1
BOOT2
M3
PVIN2
VIN
VIN
M4
SW1
M6
Gate
Driver
ISENSE
FSW
FSW
Gate
I
Driver SENSE
M5
M7
+
PGND2
–
–
+
+
COMP2
–
+
COMP1
–
Error
Amplifier
PWM
Comparator
Ramp
Generator
PWM
Comparator
Ramp
Generator
PGND1
Error
Amplifier
VBG
INV1
INV2
M8
M9
Discharge
Discharge
CHANNEL 1
CHANNEL 2
+
VOUT1
SW2
M10
VREFIN
–
Discharge
VOUT2
GND
VREFOUT
Figure 2. 34716 Simplified Internal Block Diagram
34716
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
ILIM1
NC
FREQ
VIN
VIN
GND
VDDI
STBY
PIN CONNECTIONS
26 25 24 23 22 21 20 19
BOOT1 1
18 BOOT2
PVIN1
PVIN2
2
17
PVIN1
PVIN2
Transparent
Top View
SW1
SW2
3
16
SW1
SW2
PGND2
PGND1
4
15
PGND1
PGND2
14 VOUT2
9
10
VREFIN
VREFOUT
PG
11 12 13
INV2
8
COMP2
7
SD
6
COMP1
5
INV1
VOUT1
Figure 3. 34716 Pin Connections
Table 1. 34716 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
1
BOOT1
Passive
Bootstrap
Channel 1 Bootstrap capacitor input pin
2
PVIN1
Supply
Power Input Voltage
Channel 1 Buck converter power input
3
SW1
Input/Output
Switching Node
Channel 1 Buck converter switching node
4
PGND1
Ground
Power Ground
Channel 1 Buck converter and discharge MOSFETs power ground
5
VOUT1
Input
Output Voltage
Discharge Path
Channel 1 Buck converter output voltage discharge pin
6
INV1
Input
Error Amplifier
Inverting Input
Channel 1 Buck converter error amplifier inverting input
7
COMP1
Input
Buck Convertor
Compensation Input
8
VREFIN
Input
Reference Voltage
Input
Voltage tracking reference voltage input
9
VREFOUT
Output
Reference Voltage
Output
This is a buffered reference voltage output
10
PG
Output
Power Good Output
Signal
It is an active low open drain power good status reporting output
11
SD
Input
Shutdown Input
12
COMP2
Input
Buck Convertor
Compensation Input
13
INV2
Input
Error Amplifier
Inverting Input
Channel 1 Buck converter external compensation network input
Shutdown mode input control pin
Channel 2 Buck converter external compensation network input
Channel 2 Buck converter error amplifier inverting input
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 34716 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.
Pin Number
Pin Name
Pin Function
Formal Name
Definition
14
VOUT2
Output
Output Voltage
Discharge Path
Channel 2 Buck converter output voltage discharge pin
15
PGND2
Ground
Power Ground
Channel 2 Buck converter and discharge MOSFETs power ground
16
SW2
Input/Output
Switching Node
Channel 2 Buck converter switching node
17
PVIN2
Power
Power Input Voltage
Channel 2 Buck converter power input
18
BOOT2
Input
Bootstrap Input
Channel 2 Bootstrap capacitor input pin
19
ILIM1
Input
Soft Start Adjustment
Input
20
NC
None
No Connect
21
FREQ
Input
Frequency Adjustment
Input
22,23
VIN
Power
Input Supply Voltage
24
GND
Ground
Signal Ground
Analog ground of the IC
25
VDDI
Output
Internal Supply
Voltage
Internal Supply Voltage Output
26
STBY
Input
Standby Input
Standby mode input control pin
Channel 1 soft start adjustment
No internal connections to this pin
The buck converters switching frequency adjustment input
Power supply voltage of the IC
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Input Supply Voltage (VIN) Pin
VIN
-0.3 to 7.0
V
High-Side MOSFET Drain Voltage (PVIN1, PVIN2) Pins
PVIN
-0.3 to 7.0
V
Switching Node (SW1, SW2) Pins
VSW
-0.3 to 7.5
V
VBOOT - VSW
-0.3 to 7.5
V
-
-0.3 to 7.0
V
-
-0.3 to 3.0
V
Channel 1 Continuous Output Current (1)
IOUT1
+5.0
A
Channel 2 Continuous Output Current (1)
IOUT2
±3.0
A
Human Body Model (3)
VESD1
±2000
Charge Device Model
VESD3
±750
ELECTRICAL RATINGS
BOOT1, BOOT2 Pins (Referenced to SW1, SW2 Pins Respectively)
PG, VOUT1, VOUT2, SD, and STBY Pins
VDDI, FREQ, ILIM1, INV1, INV2, COMP1, COMP2, VREFIN, and VREFOUT
Pins
ESD Voltage (2)
V
THERMAL RATINGS
Operating Ambient Temperature (4)
TA
-40 to 85
°C
Storage Temperature
TSTG
-65 to +150
°C
Peak Package Reflow Temperature During Reflow (5), (6)
TPPRT
Note 6
°C
Maximum Junction Temperature
TJ(MAX)
+150
°C
PD
2.03
W
Power Dissipation (TA = 85 °C) (7)
Notes
1. Continuous output current capability so long as TJ is ≤ TJ(MAX).
2.
3.
4.
5.
6.
7.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device
Model (CDM).
SW1 pin complies with ±1000V Human Body Model.
The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
Maximum power dissipation at indicated ambient temperature.
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
RθJA
93
°C/W
RθJMA
32
°C/W
RQJB
13.6
°C/W
THERMAL RESISTANCE (8)
Thermal Resistance, Junction to Ambient, Single-Layer Board (1s) (9)
Thermal Resistance, Junction to Ambient, Four-Layer Board (2s2p)
Thermal Resistance, Junction to Board
(11)
(10)
Notes
8. The PVIN, SW, and PGND pins comprise the main heat conduction paths.
9. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
10. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are thermal vias connecting the package to the two planes in the
board. (per JESD51-5)
11. Thermal resistance between the device and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Input Supply Voltage Operating Range
VIN
3.0
-
6.0
V
Input DC Supply Current (12)
IIN
-
-
35
mA
IINQ
-
-
25
mA
IINOFF
-
-
100
µA
VDDI
2.35
2.5
2.65
V
PVIN
2.5
-
6.0
V
VOUTHI1
0.7
-
3.6
V
-
-1.0
-
1.0
%
REGLN1
-1.0
-
1.0
%
REGLD1
-1.0
-
1.0
%
Error Amplifier Reference Voltage (13)
VREF1
-
0.7
-
V
Output Undervoltage Threshold
VUVR1
-1.5
-
-8.0
%
Output Overvoltage Threshold
VOVR1
1.5
-
8.0
%
Continuous Output Current
IOUT1
-
-
5.0
A
Over Current Limit
ILIM1
-
6.5
-
A
VILIM1
1.25
-
VDDI
V
ISHORT1
-
8.5
-
A
RDS(ON)HS1
15
-
50
mΩ
IC INPUT SUPPLY VOLTAGE (VIN)
(Normal Mode: SD = 1 & STBY = 1, Unloaded Outputs)
Input DC Supply Current (12)
(Standby Mode, SD = 1 & STBY = 0)
Input DC Supply Current (12)
(Shutdown Mode, SD = 0 & STBY = X)
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
Internal Supply Voltage Range
CHANNEL 1 BUCK CONVERTER (PVIN1, SW1, PGND1, BOOT1, INV1, COMP1, ILIM1)
CH 1 High-side MOSFET Drain Voltage Range
Output Voltage Adjustment Range
Output Voltage Accuracy
Line Regulation
(13)
(13), (14), (15)
(13)
(Normal Operation, VIN = 3.0 V to 6.0 V, IOUT1 = +5.0 A)
Load Regulation (13)
(Normal Operation, IOUT1 = 0.0 A to 5.0 A)
Soft Start Adjusting Reference Voltage Range
Short Circuit Current Limit
High-Side N-CH Power MOSFET (M4) RDS(ON)
(13)
(IOUT1 = 1.0 A, VBOOT1 - VSW1= 3.3 V)
Notes
12.
13.
14.
15.
Section “MODES OF OPERATION”, page 15 has a detailed description of the different operating modes of the 34716
Design information only, this parameter is not production tested.
Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended.
±1% is assured at room temperature.
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Low-Side N-CH Power MOSFET (M5) RDS(ON) (16)
Symbol
Min
Typ
Max
Unit
RDS(ON)LS1
15
-
50
mΩ
RDS(ON)M2
2.0
-
4.0
Ω
IPVIN1
-10
-
10
µA
(IOUT1 = 1.0 A, VIN = 3.3 V)
M2 RDS(ON)
(VIN = 3.3 V, M2 is on)
PVIN1 Pin Leakage Current
(Shutdown Mode)
INV1 Pin Leakage Current
IINV1
-1.0
-
1.0
µA
Thermal Shutdown Threshold (16)
TSDFET1
-
170
-
°C
Thermal Shutdown Hysteresis (16)
TSDHYFET1
-
25
-
°C
PVIN
2.5
-
6.0
V
VOUTHI2
0.7
-
1.35
V
-
-1.0
-
1.0
%
REGLN2
-1.0
-
1.0
%
REGLD2
-1.0
-
1.0
%
Error Amplifier Common Mode Voltage Range (16), (19)
VREF2
0.0
-
1.35
V
Output Undervoltage Threshold
VUVR2
-1.5
-
-8.0
%
Output Overvoltage Threshold
VOVR2
1.5
-
8.0
%
Continuous Output Current
IOUT2
-3.0
-
3.0
A
Over Current Limit
(Sinking and Sourcing)
ILIM2
-
4.0
-
A
ISHORT2
-
6.5
-
A
RDS(ON)HS2
15
-
50
mΩ
RDS(ON)LS2
15
-
50
mΩ
RDS(ON)M3
2.0
-
4.0
Ω
IPVIN2
-10
-
10
µA
CHANNEL 2 BUCK CONVERTER (PVIN2, SW2, PGND2, BOOT2, INV2, COMP2)
CH 2 High-side MOSFET Drain Voltage Range
Output Voltage Adjustment Range
Output Voltage Accuracy
Line Regulation
(16)
(16), (17), (18)
(16)
(Normal Operation, VIN = 3.0 V to 6.0 V, IOUT2 = ±3.0 A)
Load Regulation (16)
(Normal Operation, IOUT2 = -3.0 A to 3.0 A)
Short Circuit Current Limit
(Sinking and Sourcing)
High-Side N-CH Power MOSFET (M6) RDS(ON) (16)
(IOUT2 = 1.0 A, VBOOT2 - VSW2= 3.3 V)
Low-Side N-CH Power MOSFET (M7) RDS(ON) (16)
(IOUT2 = 1.0 A, VIN = 3.3 V)
M3 RDS(ON)
(VIN = 3.3 V, M3 is on)
PVIN2 Pin Leakage Current
(Standby and Shutdown Modes)
Notes
16.
17.
18.
19.
Design information only, this parameter is not production tested.
Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended
±1% is assured at room temperature
The 1 % output voltage regulation is only guaranteed for a common mode voltage range greater than or equal to 0.7V
34716
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
INV2 Pin Leakage Current
Symbol
Min
Typ
Max
Unit
IINV2
-1.0
-
1.0
µA
Thermal Shutdown
Threshold (20)
TSDFET2
-
170
-
°C
Thermal Shutdown
Hysteresis (20)
TSDHYFET2
-
25
-
°C
VFREQ
0.0
-
VDDI
V
VREFIN External Reference Voltage Range (20)
VREFIN
0.0
-
2.7
V
VREFOUT Buffered Reference Voltage Range
VREFOUT
0.0
-
1.35
V
OSCILLATOR (FREQ)
Oscillator Frequency Adjusting Reference Voltage Range
TRACKING (VREFIN, VREFOUT, VOUT1, VOUT2)
VREFOUT Buffered Reference Voltage Accuracy (21)
-
-1.0
-
1.0
%
VREFOUT Buffered Reference Voltage Current Capability
IREFOUT
0.0
-
8.0
mA
VREFOUT Buffered Reference Voltage Over Current Limit
IREFOUTLIM
-
11
-
mA
VREFOUT Total Discharge Resistance (20)
RTDR(M10)
-
50
-
Ω
VOUT1 Total Discharge Resistance (20)
RTDR(M8)
-
50
-
Ω
VOUT2 Total Discharge Resistance (20)
RTDR(M9)
-
50
-
Ω
VOUT2 Pin Leakage Current
IVOUTLKG2
-1.0
-
1.0
µA
STBY High Level Input Voltage
VSTBYHI
2.0
-
-
V
STBY Low Level Input Voltage
VSTBYLO
-
-
0.4
V
STBY Pin Internal Pull Up Resistor
RSTBYUP
1.0
-
2.0
MΩ
SD High Level Input Voltage
VSDHI
2.0
-
-
V
SD Low Level Input Voltage
VSDLO
-
-
0.4
V
SD Pin Internal Pull Up Resistor
RSDUP
1.0
-
2.0
MΩ
PG Low Level Output Voltage
VPGLO
-
-
0.4
V
IPGLKG
-
-
1.0
µA
(Standby Mode, VOUT2 = 3.6 V)
CONTROL AND SUPERVISORY (STBY, SD, PG)
(IPG = 3.0 mA)
PG Pin Leakage Current
(M1 is off, Pulled up to VIN)
Notes
20. Design information only, this parameter is not production tested.
21. The 1 % accuracy is only guaranteed for VREFOUT greater than or equal to 0.7 V at room temperature.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0 V ≤ VIN ≤ 6.0 V, - 40°C ≤ TA ≤ 85°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
tRISE1
-
8.0
-
ns
tFALL1
-
5.0
-
ns
CHANNEL 1 BUCK CONVERTER (PVIN1, SW1, PGND1, BOOT1, INV1, COMP1, ILIM1)
Switching Node (SW1) Rise Time (22)
(PVIN = 3.3 V, IOUT1 = 5.0 A)
Switching Node (SW1) Fall Time (22)
(PVIN = 3.3 V, IOUT1 = 5.0 A)
Soft Start Duration (Normal Mode)
tSS1
ms
ILIM1: 1.25V to 1.49V
-
3.2
-
1.5V to 1.81V
-
1.6
-
1.82V to 2.13V
-
0.8
-
2.14V to 2.5V
-
0.4
-
tLIM1
-
10
-
ms
tTIMEOUT1
80
-
120
ms
tFILTER1
5.0
-
25
µs
tRISE2
-
28
-
ns
tFALL2
-
12.0
-
ns
Soft Start Duration (Normal Mode)
tSS2
-
1.6
-
ms
Over Current Limit Timer
tLIM2
-
10
-
ms
tTIMEOUT2
80
-
120
ms
tFILTER2
5.0
-
25
µs
fSW
-
1.0
-
MHz
fSW
200
-
1000
kHz
PG Reset Delay
tPGRESET
8.0
-
12
ms
Thermal Shutdown Retry Time-out Period (22)
tTIMEOUT
80
-
120
ms
Over Current Limit Timer
Over Current Limit Retry Time-out Period
Output Undervoltage/Overvoltage Filter Delay Timer
CHANNEL 2 BUCK CONVERTER (PVIN2, SW2, PGND2, BOOT2, INV2, COMP2)
Switching Node (SW2) Rise Time (22)
(PVIN = 3.3 V, IOUT2 = ±3.0 A)
Switching Node (SW2) Fall Time (22)
(PVIN = 3.3 V, IOUT2 = ±3.0 A)
Over Current Limit Retry Time-out Period
Output Undervoltage/Overvoltage Filter Delay Timer
OSCILLATOR (FREQ)
(23)
Oscillator Default Switching Frequency
(FREQ = GND)
Oscillator Switching Frequency Range
CONTROL AND SUPERVISORY (STBY, SD, PG)
Notes
22. Design information only, this parameter is not production tested.
23. Oscillator Frequency tolerance is ±10%.
34716
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
In modern microprocessor/memory applications, address
commands and control lines require system level termination
to a voltage (VTT) equal to 1/2 the memory supply voltage
(VDDQ). Having the termination voltage at midpoint, the power
supply insures symmetry for switching times. Also, a
reference voltage (VREF) that is free of any noise or voltage
variations is needed for the DDR SDRAM input receiver,
VREF is also equal to 1/2 VDDQ. Varying the VREF voltage will
effect the setup and hold time of the memory. To comply with
DDR requirements and to obtain best performance, VTT and
VREF need to be tightly regulated to track 1/2 VDDQ across
voltage, temperature, and noise margins. VTT should track
any variations in the DC VREF value (VTT = VREF +/- 40 mV),
(See Figure 4) for a DDR system level diagram.
The 34716 supplies the VDDQ, VTT and a buffered VREF
output. To ensure compliance with DDR specifications, the
VDDQ line is applied to the VREFIN pin and divided by 2
internally through a precision resistor divider. This internal
voltage is then used as the reference voltage for the VTT
output. The same internal voltage is also buffered to give the
VREF voltage at the VREFOUT pin for the application to use
without the need for an external resistor divider. The 34716
provides the tight voltage regulation and power sequencing/
tracking required along with handling the DDR peak transient
current requirements. It gives the user a complete DDR
power supply solution with optimum performance. Buffering
the VREF output helps its immunity against noise and load
changes.
The 34716 utilizes a voltage mode synchronous buck
switching converter topology with integrated low RDS(ON)
(50 mΩ) N-channel power MOSFETs to provide an output
voltage with an accuracy of less than ±2.0 % output voltage.
It has a programmable switching frequency that allows for
flexibility and optimization over the operating conditions and
can operate at up to 1.0 MHz to significantly reduce the
external components size and cost. The 34716 can supply up
to 5.0 A from one output and sink and source up to 3.0 A of
continuous current from the other output. It provides
protection against output overcurrent, overvoltage,
undervoltage, and overtemperature conditions. It also
protects the system from short circuit events. It incorporates
a power good output signal to alert the host when a fault
occurs.
For boards that support the Suspend-To-RAM (S3) and
the Suspend-To-Disk (S5) states, the 34716 offers the STBY
and the SD pins respectively. Pulling any of these pins low,
puts the IC in the corresponding state.
By integrating the control/supervisory circuitry along with
the Power MOSFET switches for the buck converter into a
space-efficient package, the 34716 offers a complete, smallsize, cost-effective, and simple solution to satisfy the needs
of DDR memory applications.
Besides DDR memory termination, the 34716 can be used
to supply termination for other active buses and graphics card
memory. It can be used in Netcom/Telecom applications like
servers. It can also be used in desktop motherboards, game
consoles, set top boxes, and high end high definition TVs.
VDDQ
VTT
VDDQ
RT
RS
VREF
BUS
DDR Memory Controller
DDR Memory Input Receiver
Figure 4. DDR System Level Diagram
FUNCTIONAL PIN DESCRIPTION
BOOTSTRAP INPUT (BOOT1, BOOT2)
SWITCHING NODE (SW1, SW2)
Bootstrap capacitor input pin. Connect a capacitor (as
discussed in Bootstrap capacitor on page 20) between this
pin and the SW pin of the respective channel to enhance the
gate of the high-side Power MOSFET during switching.
Buck converter switching node. This pin is connected to
the output inductor.
POWER GROUND (PGND1, PGND2)
POWER INPUT VOLTAGE (PVIN1, PVIN2)
Buck converter and discharge MOSFETs power ground. It
is the source of the buck converter low-side power MOSFET.
Buck converter power input voltage. This is the drain of the
buck converter high-side power MOSFET.
COMPENSATION INPUT (COMP1, COMP2)
Buck converter external compensation network connects
to this pin. Use a type III compensation network.
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
ERROR AMPLIFIER INVERTING INPUT (INV1, INV2)
STANDBY INPUT (STBY)
Buck converter error amplifier inverting input. Connect the
VDDQ voltage (channel 1) to INV1 pin through a resistor
divider and connect the VTT voltage (channel 2) directly to
INV2 pin.
If this pin is tied to the GND pin, the device will be in
Standby Mode. If left unconnected or tied to the VIN pin, the
device will be in Normal Mode. The pin has an internal pull up
of 1.5 MΩ. This input accepts the S3 (Suspend-To-RAM)
control signal.
OUTPUT VOLTAGE DISCHARGE PATH (VOUT1,
VOUT2)
Buck converters output voltage are connected to these
pins. It only serves as the output discharge path once the SD
signal is asserted.
INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
This is the output of the internal bias voltage regulator.
Connect a 1.0 µF, 6 V low ESR ceramic filter capacitor
between this pin and the GND pin. Filtering any spikes on this
output is essential to the internal circuitry stable operation.
SIGNAL GROUND (GND)
Analog ground of the IC. Internal analog signals are
referenced to this pin voltage.
INPUT SUPPLY VOLTAGE (VIN)
IC power supply input voltage. Input filtering is required for
the device to operate properly.
POWER GOOD OUTPUT SIGNAL (PG)
This is an active low open drain output that is used to
report the status of the device to a host. This output activates
after a successful power up sequence and stays active as
long as the device is in normal operation and is not
experiencing any faults. This output activates after a 10 ms
delay and must be pulled up by an external resistor to a
supply voltage like VIN.
SHUTDOWN INPUT (SD)
If this pin is tied to the GND pin, the device will be in
Shutdown Mode. If left unconnected or tied to the VIN pin, the
device will be in Normal Mode. The pin has an internal pull up
of 1.5 MΩ. This input accepts the S5 (Suspend-To-Disk)
control signal.
REFERENCE VOLTAGE OUTPUT (VREFOUT)
This is a buffered reference voltage output that is equal to
1/2 VREFIN. It has a 10.0 mA current drive capability. This
output is used as the VREF voltage rail and should be filtered
against any noise. Connect a 0.1 µF, 6 V low ESR ceramic
filter capacitor between this pin and the GND pin and
between this pin and VDDQ rail. VREFOUT is also used as the
reference voltage for the buck converter error amplifier.
REFERENCE VOLTAGE INPUT (VREFIN)
The output of channel two will track 1/2 the voltage applied
at this pin.
FREQUENCY ADJUSTMENT INPUT (FREQ)
The buck converters switching frequency can be adjusted
by connecting this pin to an external resistor divider between
VDDI and GND pins. The default switching frequency (FREQ
pin connected to ground, GND) is set at 1.0 MHz.
CHANNEL 1 SOFT START ADJUSTMENT INPUT
(ILIM1)
Channel one Soft Start can be adjusted by applying a
voltage between 1.25V and VDDI.
34716
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Internal Bias
Circuits
System Control
& Logic
Oscillator
Protection
Functions
Control &
Supervisory
Functions
Tracking &
Sequencing
2 x Buck Converter
Figure 5. Block Illustration
INTERNAL BIAS CIRCUITS
This block contains all circuits that provide the necessary
supply voltages and bias currents for the internal circuitry. It
consists of:
• Internal Voltage Supply Regulator: This regulator
supplies the VDDI voltage that is used to drive the digital/
analog internal circuits. It is equipped with a Power-OnReset (POR) circuit that watches for the right regulation
levels. External filtering is needed on the VDDI pin. This
block will turn off during the shutdown mode.
• Internal Bandgap Reference Voltage: This supplies the
reference voltage to some of the internal circuitry.
• Bias Circuit: This block generates the bias currents
necessary to run all of the blocks in the IC.
PROTECTION FUNCTIONS
This block contains the following circuits:
• Over Current Limit and Short Circuit Detection: This
block monitors the output of the buck converters for
over current conditions and short circuit events and
alerts the system control for further command.
• Thermal Limit Detection: This block monitors the
temperature of the device for overheating events. If the
temperature rises above the thermal shutdown
threshold, this block will alert the system control for
further commands.
• Output Overvoltage and Undervoltage Monitoring: This
block monitors the buck converters output voltages to
ensure they are within regulation boundaries. If not, this
block alerts the system control for further commands.
SYSTEM CONTROL AND LOGIC
This block is the brain of the IC where the device
processes data and reacts to it. Based on the status of the
STBY and SD pins, the system control reacts accordingly and
orders the device into the right status. It also takes inputs
from all of the monitoring/protection circuits and initiates
power up or power down commands. It communicates with
the buck converter to manage the switching operation and
protects it against any faults.
OSCILLATOR
This block generates the clock cycles necessary to run the
IC digital blocks. It also generates the buck converters
switching frequency. The switching frequency can be
programmed by connecting a resistor divider to the FREQ
pin, between VDDI and GND pins (See Figure 1, page 1).
CONTROL AND SUPERVISORY FUNCTIONS
This block is used to interface with an outside host. It
contains the following circuits:
• Standby Control Input: An outside host can put the
34716 device into standby mode (S3 or Suspend-ToRAM mode) by sending a logic “0” to the STBY pin.
• Shutdown Control Input: An outside host can put the
34716 device into shutdown mode (S5 or Suspend-ToDisk mode) by sending a logic “0” to the SD pin.
• Power Good Output Signal: The 34716 can
communicate to an outside host that a fault has
occurred by pulling the voltage on the PG pin high
through a pull up resistor.
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
TRACKING AND SEQUENCING
This block allows the output of channel 2 of the 34716 to
track 1/2 the voltage applied at the VREFIN pin. This allows
the VREF and VTT voltages to track 1/2 VDDQ and assures that
none of them will be higher than VDDQ at any point during
normal operating conditions. For power down during a
shutdown (S5) mode, the 34716 uses internal discharge
MOSFETs (M8, M9, and M10 on Figure 2, page 2) to
discharge VDDQ, VTT, and VREF respectively. These
discharge MOSFETs are only active during shutdown mode.
Using this block along with controlling the SD and STBY pins
can offer the user the device for power sequencing by
controlling when to turn the 34716 outputs on or off.
BUCK CONVERTER
This block provides the main function of the 34716: DC to
DC conversion from an un-regulated input voltage to a
regulated output voltage used by the loads for reliable
operation. The buck converter is a high performance, fixed
frequency (externally adjustable), Syncronous buck PWM
voltage-mode control with a minimum on time of 100ns.
It drives integrated 50 mΩ N-channel power MOSFETs
saving board space and enhancing efficiency. The switching
regulator output voltage is adjustable with an accuracy of less
than ±2 % to meet DDR requirements. The regulator's
voltage control loop is compensated using a type III
compensation network, with external components to allow for
optimizing the loop compensation, for a wide range of
operating conditions. A typical Bootstrap circuit with an
internal PMOS switch is used to provide the voltage
necessary to properly enhance the high-side MOSFET gate.
The 34716 is designed to address DDR memory power
supplies. The integrated converter has the ability to supply up
to 5.0 A out of channel 1 and sink and source up to 3.0 A of
continuous current from channel 2, providing a full power
supply solution for DDR applications.
34716
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
VIN < 3.0V
SD = 1 &
STBY = 0
SD = 0 &
STBY = x
Power Off
VDDQ = OFF
VTT = OFF
VREF = OFF
PG = 1
Shutdown
VShutdown
Discharge
DDQ
VDDQ
= Discharge
VTT = Discharge
VTT = Discharge
V
= Discharge
VREF
REF = Discharge
VTT < = VUVF2
PG
= 11
PG =
VTT > = VOVR2
VTT
Overvoltage
VDDQ = ON
VTT = ON
VREF = ON
PG = 1
TJ > = 170˚C
VDDQ = ON
VTT = ON
VREF = ON
PG = 1
IOUT2 > = ILIM2
For > = 10ms
VDDQ < = VUVF1
VDDQ
Undervoltage
SD = 1 &
STBY = 1
VDDQ = ON
VTT = ON
VREF = ON
PG = 1
VTT > = VUVR2
VDDQ > = VUVR1
Normal
Normal
VTT < = VOVF2
FSW is
Fsw
is programmed
programmed
, is programmed
IILM1
LIM1 is programmed
VVDDQ
and TTttSS
= 11
ss =
DDQ and VTT
= ON
V
VDDQ
DDQ = ON
V
VTT
=
ON
TT
V
= ON
VREF
REF = ON
PG =
=0
0
PG
TJ < = 145˚C
tTIMEOUT Expired
Channel 2
Thermal Shutdown
VDDQ = ON
VTT = OFF
VREF = ON
PG = 1
VDDQ = ON
VTT = OFF
VREF = ON
PG = 1
3.0V < = VIN < = 6.0V
SD = 1 &
STBY = 1
VTT
Undervoltage
Standby
tTIMEOUT
Expired
Channel 2
Overcurrent
VDDQ = ON
VTT = OFF
VREF = ON
PG = 1
tTIMEOUT = 1
tTIMEOUT
Expired
VTT
Short Circuit
VDDQ
Short Circuit
VDDQ = ON
VTT = OFF
VREF = ON
PG = 1
tTIMEOUT = 1
VDDQ = OFF
VTT = ON
VREF = ON
PG = 1
tTIMEOUT = 1
IOUT2 > = ISHORT2
Channel 1
Overcurrent
VDDQ = OFF
VTT = ON
VREF = ON
PG = 1
tTIMEOUT = 1
TJ > = 170˚C
Channel 1
Thermal Shutdown
tTIMEOUT
Expired
tTIMEOUT
Expired
VDDQ
Overvoltage
VDDQ = ON
VTT = ON
VREF = ON
PG = 1
VDDQ < = VOVF1
TJ < = 145˚C
tTIMEOUT Expired
VDDQ > = VOVR1
VDDQ = OFF
VTT = ON
VREF = ON
PG = 1
IOUT1 > = ILIM1
For > = 10ms
IOUT1 > = ISHORT1
Figure 6. Operation Modes Diagram
MODES OF OPERATION
The 34716 has three primary modes of operation:
Normal Mode
In normal mode, all functions and outputs are fully
operational. To be in this mode, the VIN needs to be within its
operating range, both Shutdown and Standby inputs are
high, and no faults are present. This mode consumes the
most amount of power.
Standby Mode
This mode is predominantly used in Desktop memory
solutions where the DDR supply is desired to be ACPI
compliant (Advanced Configuration and Power Interface).
When this mode is activated by pulling the STBY pin low, VTT
is put in High Z state, IOUT2 = 0 A while VDDQ and VREF stay
active. This is the S3 state Suspend-To-Ram or Self Refresh
mode and it is the lowest DRAM power state. In this mode,
the DRAM will preserve the data. While in this mode, the
34716 consumes less power than in the normal mode,
because the buck converter and most of the internal blocks
are disabled.
Shutdown Mode
In this mode, activated by pulling the SD pin low, the chip
is in a shutdown state and the outputs are all disabled and
discharged. This is the S4/S5 power state or Suspend-ToDisk state, where the DRAM will loose all of its data content
(no power supplied to the DRAM). The reason to discharge
the VTT and VREF lines is to ensure upon exiting, the
Shutdown Mode that VTT and VREF are lower than VDDQ,
otherwise VTT can remain floating high, and be higher than
VDDQ upon powering up. In this mode, the 34716 consumes
the least amount of power since almost all of the internal
blocks are disabled.
START-UP SEQUENCE
When power is first applied, the 34716 checks the status
of the SD and STBY pins. If the device is in a shutdown mode,
no block will power up and the output will not attempt to ramp.
If the device is in a standby mode, only the VDDI internal
supply voltage and the bias currents are established and no
further activities will occur. Once the SD and STBY pins are
released to enable the device, the internal VDDI POR signal is
also released. The rest of the internal blocks will be enabled,
and the buck converters switching frequency and the VDDQ
Soft start values are determined by reading the FREQ and
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
ILIM1 pins respectively. A soft start cycle is then initiated to
ramp up the outputs. While channel 1 buck converter uses an
internal reference, channel 2 converter error amplifier uses
the voltage on the VREFOUT pin (VREF) as its reference
voltage. VREF is equal to 1/2 VDDQ, where VDDQ is applied to
the VREFIN pin. This way, the 34716 assures that VREF and
VTT voltages track 1/2 VDDQ to meet DDR requirements.
Soft start is used to prevent the output voltage from
overshooting during startup. At initial startup, the output
capacitor is at zero volts; VOUT = 0 V. Therefore, the voltage
across the inductor will be PVIN during the capacitor charge
phase which will create a very sharp di/dt ramp. Allowing the
inductor current to rise too high can result in a large
difference between the charging current and the actual load
current that can result in an undesired voltage spike once the
capacitor is fully charged. The soft start is active each time
the IC goes out of standby or shutdown mode, power is
recycled, or after a fault retry.
To fully take advantage of soft starting, it is recommended
not to enable the VTT output before introducing VDDQ on the
VREFIN pin. If this happens after a soft start cycle expires
and the VREFIN voltage has a high dv/dt, the output will
naturally track it immediately and ramp up with a fast dv/dt
itself and that will defeat the purpose of soft starting. For
reliable operation, it is best to have the VDDQ voltage
available before enabling the VTT output.
After a successful start-up cycle where the device is
enabled, no faults have occurred, and the output voltages
have reached their regulation point, the 34716 pulls the
power good output signal low after a 10 ms reset delay, to
indicate to the host that the device is in normal operation.
PROTECTION FUNCTIONS
The 34716 monitors the application for several fault
conditions to protect the load from overstress. The reaction of
the IC to these faults ranges from turning off the outputs to
just alerting the host that something is wrong. In the following
paragraphs, each fault condition is explained:
Output Overvoltage
An overvoltage condition occurs once the output voltage
goes higher than the rising overvoltage threshold (VOVR). In
this case, the power good output signal is pulled high, alerting
the host that a fault is present, but the outputs will stay active.
To avoid erroneous overvoltage conditions, a 20 µs filter is
implemented. The buck converter will use its feedback loop
to attempt to correct the fault. Once the output voltage falls
below the falling overvoltage threshold (VOVF), the fault is
cleared and the power good output signal is pulled low, the
device is back in normal operation. The condition is the same
for both outputs.
Output Undervoltage
An undervoltage condition occurs once the output voltage
falls below the falling undervoltage threshold (VUVF). In this
case, the power good output signal is pulled high, alerting the
host that a fault is present, but the outputs will stay active. To
avoid erroneous undervoltage conditions, a 20 µs filter is
implemented. The buck converter will use its feedback loop
to attempt to correct the fault. Once the output voltage rises
above the rising undervoltage threshold (VUVR), the fault is
cleared and the power good output signal is pulled low, the
device is back in normal operation. The condition is the same
for both outputs.
Output Over Current
This block detects over current in the Power MOSFETs of
the buck converter. It is comprised of a sense MOSFET and
a comparator for each channel. The sense MOSFET acts as
a current detecting device by sampling a ratio of the load
current. That sample is compared via the comparator with an
internal reference to determine if the output is in over current
or not. If the peak current in the output inductor reaches the
over current limit (ILIM), the converter will start a cycle-bycycle operation to limit the current, and a 10 ms over current
limit timer (tLIM) starts. The converter will stay in this mode of
operation until one of the following occurs:
• The current is reduced back to the normal level before
tLIM expires, and in this case normal operation is
regained.
• tLIM expires without regaining normal operation, at
which point the device turns off the output and the
power good output signal is pulled high. At the end of a
time-out period of 100 ms (tTIMEOUT), the device will
attempt another soft start cycle.
• The device reaches the thermal shutdown limit (TSDFET)
and turns off the output. The power good (PG) output
signal is pulled high.
• The output current keeps increasing until it reaches the
short circuit current limit (ISHORT). See below for more
details.
Short Circuit Current Limit
This block uses the same current detection mechanism as
the over current limit detection block. If the load current
reaches the ISHORT value, the device reacts by shutting down
the output immediately. This is necessary to prevent damage
in case of a permanent short circuit. Then, at the end of a
time-out period of 100 ms (tTIMEOUT), the device will attempt
another soft start cycle.
Thermal Shutdown
Each channel has its own thermal shutdown block.
Thermal limit detection block monitors the temperature of the
device and protects against excessive heating. If the
temperature reaches the thermal shutdown threshold
(TSDFET), the converter output switches off and the power
good output signal indicates a fault by pulling high. The
device will stay in this state until the temperature has
decreased by the hysteresis value and then After a time-out
period (TTIMEOUT) of 100 ms, the device will retry
automatically and the output will go through a soft start cycle.
If successful normal operation is regained, the power good
output signal is asserted low to indicate that.
34716
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
GND
FREQ
VDDI
STBY
VIN
STBY
ILIM1
ILIM1
C14
0.1uF
FREQ
VDDI
VIN
BOOT1
BOOT2
ILIM1
19
20
N/C
FREQ
22
VIN
VIN
GND
VDDI
1
24
25
26
STBY
C28
SW1
BOOT2
21
U1
BOOT1
23
BOOT1
C15
BOOT2
SW2
18
0.1uF
0.1uF
PVIN1 2
PVIN1
PVIN2
17
PVIN1
PVIN2
17
PVIN2
SW2
16
SW2
PVIN2
PVIN1
2
SW1
SW1
3
SW1
SW2
MC34716
3
SW1
4
PGND1
SW2
16
PGND2
15
PGND2
15
VOUT2
14
VREFIN
COMP1
0.1uF
GND
C11
VO2
INV2
VOUT1
INV1
VO1
COMP2
PGND1
5
C27
/SHTD
4
/PGOOD
GND
VREFOUT
GND
0.1uF
INV1
12
13
INV2
SD
PG
COMP1
COMP2
11
10
9
PG
8
VREFIN
VREFOUT
INV1
COMP1
7
VOUT2
6
VOUT1
COMP2
INV2
SD
VREFIN
VREFOUT
C13
0.1uF
C12
0.1uF
COMPENSATION
NETWORK SW1
COMPENSATION
NETWORK SW2
VO1
VO2
C20
0.910nF
C23
1nF
R1
20k
INV1
C18
COMP1
15pF
R15
COMP2
R18
300
20pF
C19
R4
20k
INV2
C21
R14
560
R19
R2
C22
R17
12.7k
17.4k_nopop
0.75nF
22k
1.8nF
15k
BUCK CONVERTER 1
Vo1_1
BUCK CONVERTER 2
Vo1_2
Vo2_1
L1
SW1
1
SW2
1
1uH
D3
VO2_2
L2
VO1
2
R20
4.7_nopop
PMEG2010EA_nopop
VO2
2
1.5uH
C10
100uF
C24
100uF
C25
100uF
D2
R3
4.7_nopop
C6
100uF
C7
100uF
C8
100uF
PMEG2010EA_nopop
C26
1nF_nopop
C9
1nF_nopop
Figure 7. 34716 Typical Application
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
TYPICAL APPLICATIONS
I/O SIGNALS
VIN CAPACITORS
VIN
PVIN13
2
1
C17
10uF
C16
0.1uF
VO2
GND
R8
10k
VMASTER
D1
LED
3
2
1
R9
10k
J4
VM
VM
R7
1k
J3
PVIN2
VMASTER
VIN
J2
VO1
GND
PGOOD LED
LED
3
2
1
JUMPERS
ILIM1,FREQ
VO1
VMASTER
LED
STBY
1
2
1
2
1
3
5
7
9
2
4
6
8
10
VDDI
J1
VREFIN
VDDI
VIN
GND
R16
10k
PG
R12
10k_nopop
STBY
SD
ILIM1
FREQ
R22
10k_nopop
CON10A
SD
R11
10k
PVIN1 CAPACITORS
PVIN2 CAPACITORS
PVIN1
PVIN2
C1
0.1uF
C2
1uF
C3
100uF
C4
100uF
C5
100uF
C30
0.1uF
C31
1uF
C32
100uF
C33
100uF
C29
100uF
TRIMPOTS nopop
VDDI
ILIM1
R21
POT_50K_nopop
FREQ
R6
POT_50K_nopop
Figure 8. 34716 Typical Application
34716
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
CONFIGURING THE OUTPUT VOLTAGE:
Channel 1 of the 34716 is a general purpose DC-DC
converter, the resistor divider to the -INV1 node is
responsible for setting the output voltage, according to the
following equation:
⎛ R1 ⎞
VOUT = V REF ⎜
+ 1⎟
⎝ R2 ⎠
Where VREF is the internal VBG=0.7V.
Channel 2 is a DDR specific voltage power supply, and the
output voltage is given by the equation:
VTT =
680
0.936 - 1.092
733
0.781 - 0.936
787
0.625 - 0.780
840
0.469 - 0.624
893
0.313 - 0.468
947
0.157 - 0.312
1000
0.000 - 0.156
Table 5. Frequency Selection Table
SOFT START ADJUSTMENT
Table 6 shows the voltage that should be applied to the
ILIM1 terminal to get the desired desired sort start timing on
channel 1 only.
V REFIN
2
SOFT START [MS]
Where VREFIN is equal to VDDQ.
SWITCHING FREQUENCY CONFIGURATION
The switching frequency will have a value of 1.0 MHz by
connecting the FREQ terminal to the GND. If the smallest
frequency value of 200 KHz is desired, then connect the
FREQ terminal to VDDI. To program the switching frequency
to another value, an external resistor divider will be
connected to the FREQ terminal to achieve the voltages
given by Table 5.
FREQUENCY
VOLTAGE APPLIED TO PIN FREQ
200
2.341 – 2.500
253
2.185 - 2.340
307
2.029 - 2.184
360
1.873 - 2.028
413
1.717 – 1.872
466
1.561 – 1.716
520
1.405 - 1.560
573
1.249 - 1.404
627
1.093 - 1.248
VOLTAGE APPLIED TO ILIM
3.2
1.19 - 1.49V
1.6
1.50 - 1.81V
0.8
1.82 - 2.13V
0.4
2.14 - 2.50V
Table 6. Soft Start Configurations
Figure 9. Resistor divider for Frequency and Soft Start
adjustment
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
TYPICAL APPLICATIONS
SELECTING INDUCTOR
Inductor calculation process is the same for both
Channels. The equation is the following:
(Vout + I out * ( Rds (on) _ ls + r _ w))
∆I out
Vout
Maximum Off Time Percentage
= 1−
Vin _ max
L = D'MAX ∗T ∗
D 'MAX
T
Switching Period
Rds(on) _ ls
Drain – to – Source
Resistance of FET
r_w
Winding Resistance of Inductor
∆I OUT = 0.4 * I OUT
Output Current Ripple
If channel 1 will be serving as power supply for channel 2,
it is necessary to locate the LC poles at different frequencies
in order to ensure that the input impedance of the second
converter is always higher than the output impedance of the
first converter, and thus, ensure system stability. This can be
achieved by selecting different values for L1 and L2 slightly
higher than the calculated value.
SELECTING THE OUTPUT FILTER CAPACITOR
For the output capacitor, the following considerations are
most important and not the actual Farad value: the physical
size, the ESR of the capacitor, and the voltage rating.
Calculate the minimum output capacitor using the
following formula:
Co =
I OUT * dt _ I _ rise
TR _ V _ dip
Transient Response percentage:
TR_%
Maximum Transient Voltage:
TR_V_dip = VOUT*TR_%
Maximum Current Step:
∆Iout _ step =
(Vin _ min − Vout ) * D _ max
Fsw * L
dt _ I _ rise =
T * I OUT
∆I OUT _ step
The following formula will be helpful to find the maximum
allowed ESR.
ESRmax =
∆VOUT * Fsw * L
VOUT (1 − D min)
The effects of the ESR is often neglected by the designers and may present a hidden danger to the ultimate supply
stability. Poor quality capacitors have widely disparate ESR
value, which can make the closed loop response inconsistent.
BOOTSTRAP CAPACITOR
The bootstrap capacitor is needed to supply the gate
voltage for the high side MOSFET. This N-Channel MOSFET
needs a voltage difference between its gate and source to be
able to turn on. The high side MOSFET source is the SW
node, so it is not at ground and it is floating and shifting in
voltage. We cannot just apply a voltage directly to the gate of
the high side that is referenced to ground. We need a voltage
referenced to the SW node. This is why the bootstrap
capacitor is needed. This capacitor charges during the highside off time. Since the low side will be on during that time,
the SW node and the bottom of the bootstrap capacitor will be
connected to ground, and the top of the capacitor will be
connected to a voltage source. The capacitor will charge up
to that voltage source (for example 5V). Now when the low
side MOSFET switches off and the high side MOSFET
switches on, the SW nodes rise to VIN, and the voltage on the
boot pin will be VCAP + VIN. The gate of the high side will have
VCAP across it and it will be able to stay enhanced. A 0.1µF
capacitor is a good value for this bootstrap element.
TYPE III COMPENSATION NETWORK
Power supplies are desired to offer accurate and tight
regulation output voltages. A high DC gain is required to
accomplish this, but with high gain comes the possibility of
instability. The purpose of adding compensation to the
internal error amplifier is to counteract some of the gains and
phases contained in the control-to-output transfer function
that could jeopardized the stability of the power supply. The
Type III compensation network used for 34716 is comprised
of two poles (one integrator and one high frequency, to
cancel the zero generated from the ESR of the output
capacitor) and two zeros to cancel the two poles generated
from the LC filter as shown in Figure 10.
Inductor Current Rise Time:
34716
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
This gives the result
RF =
1
2π * C F FZ 1
CS =
1
2π * R1 FZ 2
4. Calculate RS by placing the first pole at the ESR zero
frequency
Figure 10. Type III compensation network
1. Choose a value for R1 (R2only applies to Channel 1)
2. Consider a Crossover frequency of one tenth of the
switching frequency, set the Zero pole frequency to
Fcross/10
FP 0 =
1
1
FCROSS =
10
2π * R1C F
1
CF =
2π * R1 FPO
3. Knowing the LC frequency, the Frequency of Zero 1
and Zero 2 in the compensation network is equal to
FLC
1
= FP1
2π * Co X * ESR
1
1
RS =
FP1 =
2π * FP1C S
2π * RS C S
FESR =
5. Equating pole 2 at the Crossover Frequency to achieve
a faster response and a proper phase margin
FCROSS = FP 2 =
CX =
1
2π * R F
C F Cx
CF + Cx
CF
2π * R F C F FP 2 − 1
TRACKING CONFIGURATIONS
FLC =
FZ 1 =
1
= FZ 1 = FZ 2
2π LX COX
1
2π * RF C F
FZ 2 =
The 34716 allows default Ratiometric tracking on channel
2 by connecting VDDQ to the VREFIN terminal. It has an
internal resistor divider that allows an output of VDDQ/2.
1
2π * R1C S
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX
26-PIN
98ASA10728D
ISSUE 0
34716
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX
26-PIN
98ASA10728D
ISSUE 0
34716
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
REVISION HISTORY
REVISION HISTORY
REVISION
1.0
DATE
2/2006
DESCRIPTION OF CHANGES
•
Pre-release version
• Implemented Revision History page
2.0
2/2007
•
•
Initial release
Converted format from Market Assessment to Product Preview
• Major updates to the data, form, and style
3.0
5/2007
•
•
•
•
Changed Feature fom 2% to 1%, relabeled to include soft start
Change references for 45 mΩ Integrated N-Channel Power MOSFETs to 50 mΩ
Removed Machine Model in Maximum Ratings
Changed Input DC Supply Current (12) , Input DC Supply Current (12), and Input DC Supply Current
(12)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added CH 1 High-side MOSFET Drain Voltage Range
Changed Output Voltage Accuracy (13), (14), (15)
Changed Soft Start Adjusting Reference Voltage Range and Short Circuit Current Limit
Changed High-Side N-CH Power MOSFET (M4) RDS(ON) (13) and Low-Side N-CH Power
MOSFET (M5) RDS(ON) (16)
Changed M2 RDS(ON) and PVIN1 Pin Leakage Current
Added CH 2 High-side MOSFET Drain Voltage Range
Changed Output Voltage Accuracy (16), (17), (18)
Changed Short Circuit Current Limit (Sinking and Sourcing)
Changed High-Side N-CH Power MOSFET (M6) RDS(ON) (16) and Low-Side N-CH Power
MOSFET (M7) RDS(ON) (16)
Changed M3 RDS(ON) and PVIN2 Pin Leakage Current
Changed VREFOUT Buffered Reference Voltage Accuracy (21), VREFOUT Buffered Reference
Voltage Current Capability, and VREFOUT Buffered Reference Voltage Over Current Limit
Changed STBY Pin Internal Pull Up Resistor and SD Pin Internal Pull Up Resistor
Changed Soft Start Duration (Normal Mode)
Changed Over Current Limit Retry Time-out Period and Output Undervoltage/Overvoltage Filter
Delay Timer
Changed Oscillator Default Switching Frequency, PG Reset Delay, and Thermal Shutdown Retry
Time-out Period (22)
Changed definition for Channel 1 Soft Start ADJUStment input (ILIM1)
Changed drawings in 34716 Typical Application
Changed table for Soft Start Adjustment
Removed PC34716EP/R2 from the ordering information and added MC34716EP/R2
Changed data sheet status to Advance Information
34716
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
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MC34716
Rev. 3.0
5/2007
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