System Power Supply IC for Automotive

Ordering number : ENA2333A
LV5685PV
Bi-CMOS LSI
http://onsemi.com
System Power Supply IC
for Automotive Infotainment
Multiple-Output Linear Voltage Regulator
Overview
The LV5685PV is a multiple output linear regulator IC, which allows reduction of quiescent current. The LV5685PV is
specifically designed to address automotive infotainment systems power supply requirements.
The LV5685PV integrates 5 linear regulator outputs, 2 high side power switches, I2C-bus communication, ACC
detection, battery voltage detection, over-current limiter, overvoltage protection and thermal shut down. Supply for
VDD and SW33V outputs is low voltage specification, which enables drastic reduction of power dissipation compared
to the existing model.
Function
• Low consumption current: 65μA (typ, only VDD output is in operation)
• 5 regulator outputs
VDD for microcontroller: output voltage: 3.3V, maximum output current: 350mA
For system: output voltage: 3.3/5V(set by I2C-bus), maximum output current: 450mA
For audio: output voltage: 5/8.5/9/11.5V(set by I2C-bus), maximum output current: 250mA
For illumination: output voltage: 5/8/10.5/12V(set by I2C-bus), maximum output current: 300mA
For CD: output voltage: 5/6/7/8V(set by I2C-bus), maximum output current: 1300mA
• 2 high side switches
EXT: Maximum output current: 350mA, voltage difference between input and output: 0.5V
ANT: Maximum output current: 300mA, voltage difference between input and output: 0.5V
• ACC detection circuit
detection voltage 2.7/3.2/3.6/4.2V (set by I2C-bus)
• Battery voltage detection (BDET) : VCC2
Low voltage detection(UVDET): detection voltage 6/7/7.8/9V(set by I2C-bus)
Over voltage detection(OVDET): detection voltage 18V
• FLG output
CMOS output of ACC-detection/UVDET/OVDET/OVP
• I2C-bus communication interface
Each output except VDD is independently enabled/disabled. ILM/CD/AUDIO/ACC/UV voltage setting.
Read back supported: Output voltage setting, Output over-current, FLG(ACC/UV/OVDET/OVP)
• Supply input
V6IN: 6V for VDD, system(SW33V)
VCC1: For internal reference voltage, control circuitry
In case of voltage drop of V6IN, VCC1 supplies VDD output.
VCC2: For AUDIO/ILM/CD/EXT/ANT
• Over-current protection
• Overvoltage protection(OVP):
VCC1, VCC2 Typ 23V (All outputs except VDD are turned off)
• Thermal shutdown: Typ 175°C
HZIP15
* I2C Bus is a trademark of Philips Corporation.
ORDERING INFORMATION
See detailed ordering and shipping information on page 29 of this data sheet.
Semiconductor Components Industries, LLC, 2014
June, 2014
62414NK 20140611-S00002/60214NK No.A2333-1/29
LV5685PV
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
Vcc max
V6in max
VCC1,VCC2
V6IN
36
7
V
Input voltage
Vio max
SDA,SCL,FLG
ACCIN
7
36
V
Allowable power
dissipation
Pd max
Ta ≤ 25°C
-Independent IC
-Al heatsink (50 * 50 * 1.5mm3) is used
-Size of heatsink: infinite
1.3
5.3
26
W
Peak supply voltage
Vcc peak
VCC1/VCC2/ACCIN
• See the test waveform below
50
V
Topr
-40 to +85
°C
Tstg
Tjmax
-55 to +150
+150
°C
°C
Operating ambient
temperature
Storage temperature
Junction temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
• Waveform of surge test (VCC1,VCC2,ACCIN)
50V
90%
10%
16V
5msec
100ms
• Allowable power dissipation derating curve
(a) Independent IC
(b)Aluminum heat-sink (50×50×1.5mm3)
Heat-sink tightening condition
tightening torque: 39N•cm ,
with silicone grease
No.A2333-2/29
LV5685PV
Recommended Operating Conditions at Ta = 25°C
■VCC1
Parameter
Conditions
Operating supply voltage1
Ratings
Unit
VDD output
7 to 16
V
■VCC2
Parameter
Conditions
Ratings
ILM(10.5V) output
Operating supply voltage2
Operating supply voltage3
12.5 to 16
ILM(8V) output
10 to 16
AUDIO(8.5V) output
9.5 to 16
CD(8V) output(Io=1.3A)
Operating supply voltage4
Operating supply voltage5
Unit
V
V
10.5 to 16
CD(8V) output(Io≤ 1A)
10 to 16
EXT output, ANT output
7.5 to 16
V
V
■V6IN
Parameter
Conditions
Operating supply voltage6
Ratings
Unit
VDD output
5.1 to 6.5
V
SW33V(3.3V) output
5.1 to 6.5
V
SW33V(5V) output
5.7 to 6.5
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
• "Maximum Rating" and "Recommended operating range"
VCC2
VCC1
Out-of-Rating
36V
disabled(OVP)
23V
22.5V
V6IN
operating1
16V
14V
12.5V
12.5V
7V
10V
10V
7.5V
7V
10V
9.5V
9V
8V
7.5V
7.5V 7.5V
recommended
operation
range
operating2(*1)
6.5V
5.7V
ILM
AUDIO
5.1V
V6det
ANT
Vo=3.3V
EXT
CD(Io≤1A)
Vo=5V
Vo=5V
Vo=6V
drop out
region
Vo=7V
Vo=8V
Vo=5V
Vo=8.5V
Vo=9V
Vo=11.5V
Vo=5V
Vo=8V
Vo=10.5V
VDD
Vo=12V
5.1V
SW33
(*2)
VDD
(Io≤0.16A)
(*1) Each lower limit value is determined by "Output voltage"-"Dropout voltage".
(*2) Operating in VCC1→VDD current path
No.A2333-3/29
LV5685PV
Electrical Characteristics at Ta = 25°C(*1), VCC1=VCC2=14.4V, V6IN=6V
Parameter
Quiescent current
Symbol
Icc
Conditions
Min
VDD w/out load, V6IN=0V, ACCIN=0V
2
I C register Gr0/Gr1/Gr2=00h
Typ
Max
Unit
65
100
μA
3.3
3.47
V
VDD output (3.3V)
Output voltage
Vo1
Io1=200mA
3.13
Output current
Io1
Vo1≥ 3.1V
350
Line regulation
∆VoLN1
Load regulation
∆VoLD1 1 mA<Io1<200mA
Dropout voltage1
VDROP11
Dropout voltage2
VDROP12
Ripple rejection(*2)
5.7V<V6IN<6.5V, Io1=200mA or
V6IN=0V, 7.5V<VCC1<16V, Io1=200mA
Io1=200mA, V6IN=0V
(applicable to VCC1→VDD)
Io1=200mA
(applicable
V6IN→VDD, design target)
f=120Hz,V6IN or VCC1=0.5Vpp
RREJ1
Io1=200mA
to
V6IN detection voltage
V6det V6IN rising, VCC1→V6IN switch(*3)
V6IN detection hysterisis
V6hys
mA
30
90
mV
70
150
mV
0.5
1.0
V
1.1
1.3
V
40
50
4.7
4.85
dB
5.0
100
V
mV
(*3): Please use V6IN≥5.7V in the case of Io>160mA, or output voltage may be dropped when V6IN voltage is
decreased to approximately "V6IN detection voltage".
SW33V output (3.3V/5V) ; SW33_EN=1
Output voltage1
Vo21
Io2=200mA, SW_V=0
3.13
3.3
3.47
V
Output voltage2
Vo22
Io2=200mA, SW_V=1
4.75
5.0
5.25
V
Io2
Vo21≥3.1V, Vo22≥4.7V
450
Output current
mA
Line regulation
∆VoLN2 5.7V<V6IN<6.5V, Io2=200mA
30
90
mV
Load regulation
∆VoLD2 1 mA<Io2<200mA
70
150
mV
Dropout voltage
VDROP2 Io2=200mA
0.25
0.5
V
Ripple rejection(*2)
RREJ2
f=120Hz, V6IN or VCC1=0.5Vpp
Io2=200mA
40
50
dB
ILM output (5-12V); ILM_EN=1
Output voltage1
Vo31
Io3=200mA, ILM_V[1:0]=00
4.75
5.0
5.25
V
Output voltage2
Vo32
Io3=200mA, ILM_V[1:0]=01
7.6
8.0
8.4
V
Output voltage3
Vo33
Io3=200mA, ILM_V[1:0]=10
9.97
10.5
11.03
V
Output voltage4
Vo34
Io3=200mA, ILM_V[1:0]=11
11.4
12
12.6
V
Output current
Io3
300
mA
Line regulation
∆VoLN3 Vo+2V<VCC2<16V, Io3=200mA
30
90
mV
Load regulation
∆VoLD3 1 mA<Io3<200mA
70
150
mV
Dropout voltage1
VDROP3 Io3=200mA
0.6
1.05
V
Dropout voltage2
VDROP3’ Io3=100mA
0.3
0.53
V
Ripple rejection(*2)
RREJ3 f=120Hz ,Io3=200mA
40
50
dB
Continued on next page
No.A2333-4/29
LV5685PV
Continued from preceding page.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CD output (5-8V); CD_EN=1
Output voltage1
Vo41
Io4=1000 mA, CD_V[1:0]=00
4.75
5.0
5.25
V
Output voltage2
Vo42
Io4=1000 mA, CD_V[1:0]=01
5.7
6.0
6.3
V
Output voltage3
Vo43
Io4=1000 mA, CD_V[1:0]=10
6.65
7.0
7.35
V
Output voltage4
Vo44
Io4=1000 mA, CD_V[1:0]=11
7.6
8.0
8.4
V
Output current
Io4
Line regulation
∆VoLN4
Vo+2V<Vcc2<16V,Io4=1000mA
50
100
mV
Load regulation
∆VoLD4
10mA<Io4<1000mA
100
200
mV
Dropout voltage1
VDROP4
Io4=1000mA
0.9
1.5
V
Dropout voltage2
VDROP4’ Io4=500mA
0.45
0.75
V
Ripple rejection(*2)
RREJ4
Vo41≥4.7V, V44≥7.6V
f=120Hz ,Io4=1000mA
1300
mA
40
50
dB
AUDIO output (5-11.5V); AUDIO_EN=1
Output voltage1
Vo51
Io5=150mA, AUD_V[1:0]=00
4.75
5.0
5.25
V
Output voltage2
Vo52
Io5=150mA, AUD_V[1:0]=01
8.13
8.5
8.87
V
Output voltage3
Vo53
Io5=150mA, AUD_V[1:0]=10
8.55
9.0
9.45
V
Output voltage4
Vo54
Io5=150mA, AUD_V[1:0]=11
10.9
11.5
12.08
V
Output current
Io5
Line regulation
∆VoLN5
Vo+1V<VCC2<16V,Io5=150mA
30
90
mV
Load regulation
∆VoLD5
1mA<Io5<150mA
70
150
mV
Dropout voltage
VDROP5
Io5=150mA
0.25
0.45
V
Ripple rejection(*2)
RREJ5
250
f=120Hz, Io5=150mA
mA
40
50
dB
Vcc2-1.0
Vcc2-0.5
V
EXT_HS-SW; EXT_EN=1
Output voltage
Vo6
Io6=350mA
Output current
Io6
Vo6≥VCC2-1.0
350
mA
ANT_HS-SW; ANT_EN=1
Output voltage
Vo7
Io7=300mA
Output current
Io7
Vo7≥VCC2-1.0
300
Vcc2-1.0
V
Vcc2-0.5
mA
ACC detection
Detection voltage1
Vacc1
ACC_V[1:0]=00, ACCIN falling
2.62
2.7
2.78
V
Detection voltage 2
Vacc2
ACC_V[1:0]=01, ACCIN falling
3.1
3.2
3.3
V
Detection voltage 3
Vacc3
ACC_V[1:0]=10, ACCIN falling
3.49
3.6
3.71
V
Detection voltage 4
Vacc4
ACC_V[1:0]=11, ACCIN falling
4.07
4.2
4.33
V
Release voltage1
Vaccr1
ACC_V[1:0]=00, ACCIN rising
2.81
2.9
2.99
V
Release voltage 2
Vaccr2
ACC_V[1:0]=01, ACCIN rising
3.3
3.4
3.5
V
Release voltage 3
Vaccr3
ACC_V[1:0]=10, ACCIN rising
3.68
3.8
3.92
V
Release voltage 4
Vaccr4
ACC_V[1:0]=11, ACCIN rising
4.26
4.4
4.54
V
Threshold hysterisis
Vachs
0.2
V
Continued on next page
No.A2333-5/29
LV5685PV
Continued from preceding page.
Parameter
Symbol
Under-Voltage detection(UVDET)
Conditions
Min
Typ
Max
Unit
detection voltage1
Vuv1
VCC2 falling, UVD_V[1:0]=00
5.82
6.0
6.18
V
detection voltage2
Vuv2
VCC2 falling, UVD_V[1:0]=01
6.79
7.0
7.21
V
detection voltage3
Vuv3
VCC2 falling, UVD_V[1:0]=10
7.56
7.8
8.04
V
detection voltage4
Vuv4
VCC2 falling, UVD_V[1:0]=11
8.73
9.0
9.27
V
release voltage1
Vuvr1
VCC2 rising, UVD_V[1:0]=00
6.06
6.25
6.43
V
release voltage2
Vuvr2
VCC2 rising, UVD_V[1:0]=01
7.13
7.35
7.57
V
release voltage3
Vuvr3
VCC2 rising, UVD_V[1:0]=10
8.05
8.3
8.55
V
release voltage4
Vuvr4
VCC2 rising, UVD_V[1:0]=11
9.40
9.7
9.99
V
detection hysterisis1 Vuvhs1 UVD_V[1:0]=00
0.25
V
detection hysterisis2 Vuvhs2 UVD_V[1:0]=01
0.35
V
detection hysterisis3 Vuvhs3 UVD_V[1:0]=10
0.5
V
detection hysterisis4 Vuvhs4 UVD_V[1:0]=11
0.7
V
Over-Voltage detection(OVDET)
detection voltage
Vovd
detection hysterisis
Vodhys
VCC2 rising
17
18
19
V
0.5
V
23
V
0.5
V
Over-Voltage protection(OVP)
detection voltage
Vovp
detection hysterisis
Vovhys
VCC1/VCC2 rising, output disabled
V6IN Shutdown detection(V6SDN)
detection voltage
V6sdn
detection hysterisis
V6sdhs
V6IN falling, output disabled
0.6
1.02
1.4
80
V
mV
FLG output
FLG "H" voltage
VflgH
Isource=1mA
FLG "L" voltage
VflgL
Isink=1mA
VDD-0.3
VDD
V
0.3
0.4
V
0.4
V
3.3
5.5
V
0.3
0.4
V
2
I C-BUS I/F; SCL,SDA
Input "L" voltage
VIL
0
Input "H" voltage
VIH
2.8
SDA "L" voltage
VOL
Isink=1mA, ACK or data read
(*1) All the specification is defined based on the tests performed under the conditions where Tj and Ta(=25°C) are almost
equal. These tests were performed with pulse load to minimize the increase of junction temperature (Tj).
(*2) guaranteed by design
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2333-6/29
LV5685PV
TYPICAL CHARACTERISTICS
VCC=16V
VCC=14.4V
VCC=7V
125°C
85°C
25°C
-40°C
No.A2333-7/29
LV5685PV
V6IN=5.3V
V6IN=6V
V6IN=6.5V
-40°C
V6IN=6V
V6IN=6.5V
V6IN=5.3V
25°C
85°C
125°C
No.A2333-8/29
LV5685PV
V6IN=5.3V
V6IN=6V
V6IN=6.5V
-40°C
85°C
125°C
25°C
V6IN=5.3V
V6IN=6V
V6IN=6.5V
VCC2=12.5V
VCC2=14.4V
VCC2=16V
No.A2333-9/29
LV5685PV
VCC2=14.4V
85°C
125°C
-40°C
25°C
VCC2=16V
VCC2=12.5V
VCC2=10V
VCC2=14.4V
VCC2=16V
-40°C
85°C
125°C
VCC2=16V
VCC2=14.4V
25°C
VCC2=10V
No.A2333-10/29
LV5685PV
VCC2=9.5V
VCC2=14.4V
VCC2=16V
-40°C
125°C
25°C
85°C
VCC2=14.4V
VCC2=16V
VCC2=9.5V
-40°C
25°C
VCC2=7.5V
VCC2=14.4V
VCC2=16V
125°C
No.A2333-11/29
85°C
LV5685PV
-40°C
VCC2=7.5V
VCC2=14.4V
VCC2=16V
25°C
125°C
85°C
No.A2333-12/29
LV5685PV
I2C-bus Interface timing
Parameter
SCL clock frequency
Symbol
fSCL
min
typ
START condition hold time
tHD;STA
0.6
us
SCL ”L” pulse-width
tLOW
1.3
us
SCL ”H” pulse-width
tHIGH
0.6
us
DATA hold time
tHD;DAT
0
us
DATA setup time
tSU;DAT
0.1
us
SDA/SCL rise time
tr
0.3
us
SDA/SCL fall time
tf
0.3
us
STOP condition setup time
tSU;STO
0.6
us
Bus free time
tBUF
1.3
us
0
max
unit
400
kHz
between STOP and START condition
Bus line load capacitance
Cb
400
pF
SDA
tf
tSU;DAT
tLOW
SCL
K
tr
tHD;STA
ST
tHD;DAT tHIGH
tr
tBUF
tf
tSU;STO SP
ST
No.A2333-13/29
LV5685PV
I2C bus interface format (MSB first)
This part is I2C controlled power supply, using 2 wires of SCL,SDA.
The communication protocol comprises start-condition, device-address, sub-address, data and stop-condition.
Every 8bits are followed by ACK bit, and the receiver device pulls down SDA line during ACK period.
This part doesn't accept sub-address auto increment format. (Single data byte write per a communication.)
The protocol in Read-mode comprises start-condition, device-address, data1, data2 and stop-condition.
2
(Note)The I C-bus communication may be unstable when VDD voltage is not stable or out of specification range, since
2
I C-BUS circuitry is supplied by VDD.
Write mode
SCL
SDA
S6 S5 S4 S3 S2 S1 S0 W AK A7 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
Sub Address(A) + ACK
Device Address + R/W + ACK
Start
Condition
Data(address A) + ACK
Stop
Condition
Read mode
SCL
SDA
S6 S5 S4 S3 S2 S1 S0 R AK D15 D14 D13 D12 D11 D10 D9 D8 AK D7 D6 D5 D4 D3 D2 D1 D0 AK
Start
Condition
Device Address + R/W + ACK
Read data1 + ACK
Read data2 + ACK
Stop
Condition
• Device address
S6
S5
S4
S3
S2
S1
S0
R/W
0
0
0
1
0
0
0
1/0
• Register map
Write
D7
D6
D5
D4
D3
D2
PM
ILM_EN
CD_EN
AUDIO_EN
SW33_EN
EXT_EN
ANT_EN
VCTL
ILM_V1
ILM_V0
CD_V1
CD_V0
AUD_V1
AUD_V0
DET
ACC_V1
ACC_V0
UVD_V1
UVD_V0
FLGMD1
FLGMD0
D1
D0
init
00000000
SW_V
00000000
00000000
Read
VCTL
FLG
D15
D14
D13
D12
D11
D10
D9
D8
init
ILM_V1
ILM_V0
CD_V1
CD_V0
AUD_V1
AUD_V0
SW_V
V6DET
00000000
D7
D6
D5
D4
D3
D2
D1
D0
init
ACCUV
UV
OV
OVP
V6SDN
OC
0
0
00000000
No.A2333-14/29
LV5685PV
Write Register explanation
ADR
bit
Name
00h
7
ILM_EN
6
CD_EN
5
AUDIO_EN
4
SW33_EN
3
EXT_EN
2
ANT_EN
1
0
Description
0
ILM output enable 1: ON 0: OFF
0
CD output enable 1: ON 0: OFF
0
AUDIO output enable 1: ON 0: OFF
0
SW33 output enable 1: ON 0: OFF
0
EXT output enable 1: ON 0: OFF
0
ANT output enable 1: ON 0: OFF
0
0
ADR
bit
01h
[7:6]
ILM_V[1:0]
[5:4]
CD_V[1:0]
00
CD output voltage(*) 11: 8V 10: 7V 01: 6V 00: 5V
[3:2]
AUD_V[1:0]
00
AUDIO output voltage(*) 11: 11.5V 10: 9V 01: 8.5V 00: 5V
SW_V
0
SW33V output voltage(*) 1: 5V 0: 3.3V
1
Name
init
0
init
00
Description
ILM output voltage(*) 11: 12V 10: 10.5V 01: 8V 00: 5V
0
(*) "Output voltage setting" is only valid when corresponding output is set disabled(xxx_EN=0). It is ignored when the output
is set enabled(xxx_EN=1).
ADR
bit
Name
init
02h
[7:6]
ACC_V[1:0]
00
ACC detection voltage 11: 4.2V 10: 3.6V 01: 3.2V 00: 2.7V
[5:4]
UVD_V[1:0]
00
UVDET detection voltage 11: 9V 10: 7.8V 01: 7V 00: 6V
[3:2]
FLGMD[1:0]
00
FLG output mode 11/10: BDET only 01: ACC only, 00: ACC/BDET
1
0
0
0
Read Register explanation
ADR
bit
Name
[15:14] ILM_V[1:0]
[13:12] CD_V[1:0]
[11:10] AUD_V[1:0]
9
SW_V
8
V6DET
7
ACCUV
6
UV
5
OV
4
OVP
3
V6SDN
2
OC
1
0
Description
init
Description
00
ILM output voltage 11: 12V 10: 10.5V 01: 8V 00: 5V
00
CD output voltage 11: 8V 10: 7V 01: 6V 00: 5V
00
AUDIO output voltage 11: 11.5V 10: 9V 01: 8.5V 00: 5V
0
SW33V output voltage 1: 5V 0: 3.3V
0
V6INDET / Supply for VDD 1: V6IN 0: VCC1
0
ACC detection
0
Under voltage detection 1: Under voltage 0: Normal
0
Over voltage detection 1: Over Voltage 0: Normal
0
Over voltage protection 1: Over Voltage Protection 0: Normal
0
V6IN shutdown detection 1: V6IN shutdown 0: V6IN applied
0
Output Over Current
1: Under voltage 0: Nornmal
1: Over current 0: Normal
0
0
No.A2333-15/29
LV5685PV
Package Dimensions
unit : mm
HZIP15
CASE 945AB
ISSUE A
GENERIC
MARKING DIAGRAM*
XXXXXXXXXX
YMDDD
SOLDERING FOOTPRINT*
Through Hole Area
(Unit: mm)
Package name
HZIP15
2.54
1.2
2.54
(1.91)
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
2.54
2.54
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
No.A2333-16/29
LV5685PV
Application Circuit Example
D3
SW33V
14
15
FLG
C13
13
SDA
C10
FLG
V6IN
SDA
SCL
VCC1
VDD
12
11
ACC
ILM
AUDIO
VDD
CD
C7 C6
ANT
EXT
10
9
SCL
D2
D1
8
7
C5
C4
C3
C2
D4
6
5
GND
4
3
VCC2
ACCIN
CD
2
1
C1
AUDIO
ILM
EXT
ANT
LV5685PV
D5
C12 C11
SW33V
C8 C9
V6IN
+B
■Peripheral parts
Part name
Description
Recommended value
C1,C2
Capacitor for EXT/ANT output
greater than 2.2μF
Note
stabilization
C3,C4,C5,
output stabilization capacitor
greater than10μF(*1)
Capacitor
C7: greater than 100μF
for bypass power supply
C9,C12: greater than 47μF
C6,C8,C11
Capacitor for oscillation protector
greater than 0.22μF
D1,D2,D3,D4
Internal device protection diode
ON Semiconductor
C10,C13
C7,C9,C12
Make sure to
implement close
to VCC and GND.
SB1003M3
D5
Reverse current protection diode
ON Semiconductor
SB1003M3
(*1) Make sure that output capacitors are greater than 10uF and meets the condition of ESR=0.001 to 10Ω , in
which voltage/temperature dependence and unit differences are taken into consideration. Moreover, in case of
electrolytic capacitor, high-frequency characteristics should be sufficiently good.
No.A2333-17/29
LV5685PV
Block Diagram
6V input
13
V6IN
3.3V, 0.35A
VCC1
8
VDD
11
VREF
-
+
OVP
VREG
V6DET
5.1V
VREG
SW33_EN
VREF
SW33V
15
VREF
3.3V/5V, 0.45A
-
+
1.25V
TSD
VDD
ILM_EN
SCL
10
SDA
12
VREF
ILM
5/8/10.5/12V, 0.3A
3
-
+
I2C-bus
CTL
OVP
TSD
UV
OV
CD
5/6/7/8V, 1.3A
5
Power
on
reset
CD_EN
VREF
-
+
OVP→disable all outputs
except VDD
TSD→disable all putputs
VCC2
7
OVP
9
GND
UVDET
UV
OVDET
OV
AUDIO_EN
VREF
-
AUDIO
5/8.5/9/11.5V, 0.25A
4
+
BDET
EXT
VCC2-0.5V, 0.35A
2
ANT
VCC2-0.5V, 0.3A
EXT
ctrl
EXT_EN
ACC
ACCIN
1
ANT
ctrl
ANT_EN
6
VDD
VREF
+
UV
OV
OVP
14
FLG
FLGMD
No.A2333-18/29
LV5685PV
23V
18V
22.5V
17.5V
6V
6.25V
OVP release
VCC2
OVP detect
■Timing Chart
VCC1
V6IN
3.8V
1.0V
1.1V
ANT_EN=0
SW33_EN=0
EXT_EN=0
ILM_EN=0
CD_EN=0
AUDIO_EN=0
Output enable
Settings
Output enable
Settings
EXT_EN=1
ANT_EN=1
SW33_EN=1
CD_EN=1
ILM_EN=1
I2C inputs
(SCL/SDA)
Initial
Settings
VDD output
AUDIO_EN=1
V6IN lost
ILM output
CD output
AUDIO output
I
SW33V output
EXT output
ANT output
ACCIN
2.8V
2.7V
FLG
VDD
OVDET
UVDET
Note: The above values are obtained when typ. All the voltage setting are default values
No.A2333-19/29
LV5685PV
Functional Description
[Standby mode]
When VCC1 is applied, internal control circuitry is automatically reset and goes into Stand-by mode.
In Stand-by mode, following functions are active.
VDD(3.3V) output
I2C-bus communication (except for "PM" register)
Over voltage protection(OVP)/UVDET/OVDET/ACC detection/FLG output
Thermal shutdown(TSD)
[VCC1/VCC2/V6IN]
VCC1 supplies VDD and common circuitry such as reference voltage, internal control circuitry. So VCC1 input
is necessary for any operation of this device.
VCC2 is the supply for AUDIO/ILM/CD/EXT/ANT outputs.
LV5685PV has the tolerance value of 50V against VCC1/2 and ACCIN peak surge voltage, but for more safety
set design, adding power clamp, such as power zener diode, on battery connected line is recommended in
order to absorb applied surge.
LV5685PV has no protection against battery reverse connection, so adding Schottky diode is recommended to
prevent a negative voltage.
V6IN is the supply for SW33V. V6IN also supplies VDD when V6IN voltage exceeds 4.85V(typ).
When VCC2 and V6IN is applied, ILM/CD/AUDIO/SW33/EXT/ANT output can be set enable via I2C-bus.
When V6IN is lower than 1.1V(typ)(max:1.5V), output enable command above can't be accepted.
[Controls]
The functions of LV5685PV can be controlled via I2C bus. See "I2C bus interface format" term for details.
[Linear Regulators]
VDD output
When VCC1 is applied, VDD output is active regardless of control states. When V6IN is applied and the
voltage exceeds 4.85V(typ), supply for VDD output switches from VCC1 to V6IN in order to reduce power
dissipation.
See "VDD regulator circuit description" term for detail.
SW33V/CD/AUDIO/ILM output
These outputs are individually enabled or disabled via I2C-bus.
The voltage of each output can be selected via I2C-bus. These commands must be set prior to enabling
corresponding output. If you change the voltage for these outputs, be sure to do it after the output is set
disabled. In order to avoid unwanted output voltage change, each "output voltage setting" is accepted only
when corresponding output is set disabled(xxx_EN=0). The "output voltage setting" is ignored if the output is
set enabled(xxx_EN=1).
Output voltage setting can be referred by reading via I2C-bus(VCTL register). It is strongly recommended to
read and check VCTL register value just before setting enable the output in order to avoid unwanted output
voltage change even in case if communication error were to happen and incorrect voltage setting were written
to the device.
Each regulator output limits output current if the output gets over-loaded condition. The limit current decreases
as the output voltage gets lower, in order to reduce the stress applied to the device.
No.A2333-20/29
LV5685PV
All regulators in LV5685PV are low dropout outputs, because the output stage of all regulators is P-channel
LDMOS.
When you select output capacitors for linear regulators, you should consider three main characteristics: startup
delay, transient response and loop stability. The capacitor values and type should be based on cost, availability,
size and temperature constraints. Tantalum, Aluminum electrolytic, Film, or Ceramic capacitors are all
acceptable solutions. However, attention must be paid to ESR constraints. The aluminum electrolytic capacitor
is the least expensive solution, but if the circuit operates at low temperatures (-25 to -40°C ), both the value and
ESR of the capacitor will vary considerably. The capacitor manufacturer's datasheet usually provides this
information.
[High-side switches]
ANT and EXT are high-side power switches connected to VCC2. These outputs are individually enabled or
disabled via I2C-bus.
Each high-side switch limits output current if the output gets over-loaded condition. The limit current becomes
lower value, if the output voltage gets lower than 2.5V(typ) in order to reduce the stress applied to the device.
If these outputs are connected to inductive load or loads which have different ground potential, protection
diodes (D1-4) are necessary to protect the device from negative voltage.
[Current Limiting]
When the each output becomes in over load condition, the device limits the output current.
All outputs are also protected against short circuit by fold back current limiter.
If one of each output except VDD is in over-current condition, OC bit of FLG register is set 1, which can be read
via I2C-bus.
[FLG output]
FLG is the CMOS level logic output which indicates the combination of several detectors' results.
FLG output is set "High"(VDD voltage), if all the following conditions are satisfied.
ACC
BDET
OVP
TSD
Conditions
ACC input voltage>ACC detection
threshold
VCC2 voltage>UVDET threshold
VCC2 voltage<OVDET threshold
VCC1<OVP threshold and
VCC2<OVP threshold
Die temperature<175°C(typ)
VDD output current< Iomax
00
FLGMD[1:0]
01
10 or11
3
3
ignored
3
3
ignored
ignored
3
3
3
ignored
3
3
3
3
3
3
3
Note: I2C-bus "FLG" register bits is active regardless of FLGMD[1:0] setting.
No.A2333-21/29
LV5685PV
[Detections]
Under voltage detection (UVDET)
If the VCC2 voltage gets lower than set value (UVD_V[1:0]), Under-Voltage is detected and the UV bit of FLG
register is set 1, which can be read via I2C-bus. FLG pin keeps "Low" during UVDET condition except for at
FLGMD[1:0]=01. Each output status keeps the same condition even if UV is detected.
Over voltage detection (OVDET)
If the VCC2 voltage exceeds 18V(typ), Over-Voltage is detected and the OV bit of FLG register is set 1, which
can be read via I2C-bus. FLG pin keeps "Low" during OVDET condition except for at FLGMD[1:0]=01. Each
output status keeps the same condition even if OV is detected.
ACC Under voltage detection
If the ACCIN voltage gets lower than set value (ACC_V[1:0]), the ACCUV bit of FLG register is set 1, which can
be read via I2C-bus. FLG pin keeps "Low" during ACCUV is detected if FLGMD[1:0] is 00 or 01.
Each output status keeps the same condition even if ACCUV is detected.
Over voltage protection (OVP)
If the voltage of VCC1 or VCC2 exceed 23V(typ), OVP is detected and the OVP bit of FLG register is set 1,
which can be read via I2C-bus. And all the outputs except VDD are automatically turned off. When the voltage
of VCC1 and VCC2 get lower than 22.5V(typ), OVP detection is released. But output voltages are not
automatically restored, because once OVP is detected, PM register of I2C-bus is reset.
FLG pin keeps "Low" during OVP condition except for at FLGMD[1:0]=01.
V6IN shutdown detection
If the V6IN voltage decreases lower than 1.0V(typ), V6IN-shutown is detected and the V6SDN bit of FLG
register is set 1, which can be read via I2C-bus. And all the outputs except VDD are automatically turned off.
Output voltages are not automatically activated if V6IN voltage is restored, because once V6IN shutdown is
detected, PM register of I2C-bus is reset.
Thermal Shutdown
To protect the device from overheating, a thermal shutdown circuitry is included. If the junction temperature
reaches approximately 175°C(typ), all outputs are turned off regardless of control state. After the junction
temperature drops below 145°C(typ), VDD output is automatically restored and I2C-bus control becomes
available.
The thermal shutdown circuit does not guarantee the protection of the final product because it
operates out of maximum rating (exceeding Tjmax=150°C).
No.A2333-22/29
LV5685PV
VDD regulator circuit description
• Supply current switching
VDD output is always in operation except under thermal
shut down (TSD) condition. There are 2 supply inputs
(VCC1/V6IN) for this output. VCC1 is capable of
high-voltage input such as car-battery. V6IN is a low
voltage input and can be supplied from external DC/DC
converter in order to decrease power dissipation of the
device. Supply current path from VCC1 or V6IN is
automatically switched depending on V6IN voltage. If
V6IN voltage exceeds 4.85V(typ), V6IN supplies VDD
output. Output ripple may be occurred when supply
switching. This ripple can be improved by using proper
output capacitor. Select appropriate capacitor suitable
for your requirement.
Input voltage
VCC1
V6IN
4.85V(typ)
4.75V(typ)
Input current
IVDD_VCC1
IVDD_VCC1
IVDD_V6IN
IVDD_V6IN
Vout/Iout
VOUT_VDD
IOUT_VDD
IVDD_V6IN
V6IN
13
IVDD_VCC1
VCC1
VOUT_VDD
11
V6DET
IOUT_VDD
8
VREF
+
VDD supply switching diagram
-
• Reverse current protection for battery voltage black-out
There is no diode inside to prevent reverse current from VDD to VCC1. You have to add external circuit to
hold VDD voltage under battery voltage black-out. There is a parasitic diode from VDD to VCC1, so insert a
diode between VCC2 and VCC1 as shown figure below.
VIN
7
13
VCC2
VDD
V6IN
V6DET
back-up
capacitor
reverse
current
protection
8
VCC1
VREF
parasitic
diode
11
to uC
+
-
No.A2333-23/29
LV5685PV
■Pin description
Pin #
Pin name
Function
Equivalent circuit
VCC2
7
1
2
EXT
ANT
EXT output
VCC2-0.5V/350mA
1
9
GND
7
VCC2
ANT output
2
VCC2-0.5V/300mA
GND
9
VCC2
7
180kΩ
ILM
3
5V~12V
20.9~60kΩ
3
ILM output
1kΩ
9
GND
7
VCC2
4
180kΩ
AUDIO
5V~11.5V
22~60kΩ
4
AUDIO output
9
1kΩ
GND
Continued on next page.
No.A2333-24/29
LV5685PV
Continued from preceding page.
Pin #
Pin name
Function
Equivalent circuit
VCC2
7
5
180kΩ
CD
5V~8V/1.3A
33.3~60kΩ
5
CD output
1kΩ
GND
9
ACCIN
ACC detection input
36~78kΩ
6
90kΩ
6
9
7
VCC2
Supply terminal
8
VCC1
Supply terminal
9
GND
GND
13
V6IN
Supply terminal
GND
VCC2
VCC1
V6IN
7
8
13
GND
9
8
VCC1
VDD
11
10
SCL
I2C-bus clock input
1kΩ
10
GND
9
VCC1
VDD
VDD output
11
3.3V/0.35A
140kΩ
11
230kΩ
8
13
9
GND
Continued on next page
No.A2333-25/29
LV5685PV
Continued from preceding page.
Pin #
Pin name
Function
Equivalent circuit
VDD
11
12
SDA
100Ω
I2C-bus data input
1kΩ
12
GND
9
VDD
11
14
FLG
100Ω
FLG output
14
GND
9
V6IN
13
SW33V
3.3V/5V
0.45A
140kΩ
15
15
230/420kΩ
SW33V output
9
1kΩ
GND
No.A2333-26/29
LV5685PV
HZIP15 Heat sink attachment
Heat sinks are used to lower the semiconductor device junction temperature by leading the head generated by
the device to the outer environment and dissipating that heat.
a. Unless otherwise specified, for power ICs with tabs and power ICs with attached heat sinks, solder must not
be applied to the heat sink or tabs.
b. Heat sink attachment
• Use flat-head screws to attach heat sinks.
Binding-head
machine-screw
• Use also washer to protect the package.
Countersunk head
machine screw
• Use tightening torques in the ranges 39-59Ncm(4-6kgcm) .
• If tapping screws are used, do not use screws with a diameter larger than the holes in the semiconductor
device itself.
• Do not make gap, dust, or other contaminants to get between the semiconductor device and the tab or
heat sink.
• Take care a position of via hole.
• Do not allow dirt, dust, or other contaminants to get between the semiconductor device and the tab or heat
sink.
• Verify that there are no press burrs or screw-hole burrs on the heat sink.
• Warping in heat sinks and printed circuit boards must be no more than 0.05 mm between screw holes, for
either concave or convex warping.
• Twisting must be limited to under 0.05 mm.
• Heat sink and semiconductor device should be mounted in parallel.
Take care of electric or compressed air screw driver
• The speed of these torque wrenches must not exceed 700 rpm,
and should typically be about 400 rpm.
Heat sink
gap
via hole
No.A2333-27/29
LV5685PV
c. Silicone grease
• Spread the silicone grease evenly when mounting heat sinks.
• Sanyo recommends YG-6260 (Momentive Performance Materials Japan LLC)
d. Mount
• First mount the heat sink on the semiconductor device, and then mount that assembly on the printed circuit
board.
• When attaching a heat sink after mounting a semiconductor device into the printed circuit board, when
tightening up a heat sink with the screw, the mechanical stress which is impossible to the semiconductor
device and the pin doesn't hang.
e. When mounting the semiconductor device to the heat sink using jigs, etc.,
• Take care not to allow the device to ride onto the jig or positioning dowel.
• Design the jig so that no unreasonable mechanical stress is applied to the semiconductor device.
f. Heat sink screw holes
• Be sure that chamfering and shear drop of heat sinks must not be larger than the diameter of screw head
used.
• When using nuts, do not make the heat sink hole diameters larger than the diameter of the head of the
screws used. A hole diameter about 15% larger than the diameter of the screw is desirable.
• When tap screws are used, be sure that the diameter of the holes in the heat sink are not too small. A
diameter about 15% smaller than the diameter of the screw is desirable.
g. There is a method to mount the semiconductor device to the heat sink by using a spring band. But this
method is not recommended because of possible displacement due to fluctuation of the spring force with
time or vibration.
No.A2333-28/29
LV5685PV
ORDERING INFORMATION
Device
LV5685PV-XH
Package
HZIP15
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
20 / Fan-Fold
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any
such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
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PS No.A2333-29/29