FREESCALE MPC8313E

Freescale Semiconductor
Technical Data
Document Number: MPC8313EEC
Rev. 1, 3/2008
MPC8313E
PowerQUICC™ II Pro Processor
Hardware Specifications
This document provides an overview of the MPC8313E
PowerQUICC™ II Pro processor features, including a block
diagram showing the major functional components. The
MPC8313E is a cost-effective, low-power, highly integrated
host processor that addresses the requirements of several
printing and imaging, consumer, and industrial applications,
including main CPUs and I/O processors in printing systems,
networking switches and line cards, wireless LANs
(WLANs), network access servers (NAS), VPN routers,
intelligent NIC, and industrial controllers. The MPC8313E
extends the PowerQUICC™ family, adding higher CPU
performance, additional functionality, and faster interfaces
while addressing the requirements related to time-to-market,
price, power consumption, and package size.
1
Overview
The MPC8313E incorporates the e300c3 core, which
includes 16 Kbytes of L1 instruction and data caches and
on-chip memory management units (MMUs). The
MPC8313E has interfaces to dual enhanced three-speed 10,
100, 1000 Mbps Ethernet controllers, a DDR1/DDR2
SDRAM memory controller, an enhanced local bus
controller, a 32-bit PCI controller, a dedicated security
© Freescale Semiconductor, Inc., 2008. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 14
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Three-Speed Ethernet, MII Management . 21
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 54
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
System Design Information . . . . . . . . . . . . . . . . . . . 79
Document Revision History . . . . . . . . . . . . . . . . . . . 86
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 88
Overview
engine, a USB 2.0 dual-role controller and an on-chip full-speed PHY, a programmable interrupt
controller, dual I2C controllers, a 4-channel DMA controller, and a general-purpose I/O port. A block
diagram of the MPC8313E is shown in Figure 1.
DUART
Dual I 2C
Timers
GPIO
e300c3 Core w/FPU and
Power Management
Interrupt
Controller
I/O Sequencer
(IOS)
PCI
16-KB
I-Cache
Security Engine 2.2
16-KB
D-Cache
USB 2.0
Host/Device/OTG
ULPI On-Chip
FS PHY
Local Bus,
SPI
DDR1/DDR2
Controller
Gb Ethernet
MAC
Gb Ethernet
MAC
DMA
Note: The MPC8313 does not include
a security engine.
Figure 1. MPC8313E Block Diagram
The MPC8313E’s security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be
offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration
for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
1.1
MPC8313E Features
The following features are supported in the MPC8313E.
• Embedded PowerPC™ e300 processor core; operates at up to 333 MHz.
• High-performance, low-power, and cost-effective host processor
• DDR1/DDR2 memory controller—one 16-/32-bit interface at up to 333 MHz supporting both
DDR1 and DDR2
• e300c3 core, built on Power Architecture™ technology, with 16-Kbyte instruction cache and
16-Kbyte data cache, a floating point unit, and two integer units
• Peripheral interfaces such as 32-bit PCI interface with up to 66-MHz operation, 16-bit enhanced
local bus interface with up to 66-MHz operation, and USB 2.0 (full speed) with an on-chip PHY.
• Security engine provides acceleration for control and data plane security protocols
• Power management controller for low-power consumption
• High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Overview
1.2
Serial Interfaces
The following interfaces are supported in the MPC8313E:
• Dual UART, dual I2C, and an SPI interface
1.3
Security Engine
The security engine is optimized to handle all the algorithms associated with IPSec, IEEE Std 802.11i™,
and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution
units (EUs). The execution units are as follows:
• Data encryption standard execution unit (DEU), supporting DES and 3DES
• Advanced encryption standard unit (AESU), supporting AES
• Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-224, SHA-256, and
HMAC with any algorithm
• One crypto-channel supporting multi-command descriptor chains
1.4
DDR Memory Controller
The MPC8313E DDR1/DDR2 memory controller includes the following features:
• Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM
• Support for up to 333 MHz
• Support for two physical banks (chip selects), each bank independently addressable
• 64-Mbit to 1-Gbit devices with x8/x16/x32 data ports (no direct x4 support)
• Support for one 16-bit device or two 8-bit devices on a 16-bit bus, OR one 32-bit device or two
16-bit devices on a 32-bit bus
• Support for up to 16 simultaneous open pages
• Supports auto refresh
• On-the-fly power management using CKE
• 1.8-/2.5-V SSTL2 compatible I/O
1.5
PCI Controller
The MPC8313E PCI controller includes the following features:
• PCI specification revision 2.3 compatible
• Single 32-bit data PCI interface operates at up to 66 MHz
• PCI 3.3-V compatible (not 5-V compatible)
• Support for host and agent modes
• On-chip arbitration, supporting three external masters on PCI
• Selectable hardware-enforced coherency
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
3
Overview
1.6
USB Dual-Role Controller
The MPC8313E USB controller includes the following features:
• Supports USB on-the-go mode, which includes both device and host functionality, when using an
external ULPI (UTMI + low-pin interface) PHY
• Compatible with USB Specification, Rev. 2.0
• Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
• Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
• Supports full-speed (12 Mbps), and low-speed (1.5 Mbps) operation. Low-speed operation is
supported only in host mode.
• Supports UTMI + low pin interface (ULPI) or on-chip USB 2.0 full-speed PHY
1.7
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The MPC8313E eTSECs include the following features:
• Two RGMII/SGMII/MII/RMII/RTBI interfaces
• Two controllers designed to comply with IEEE Std 802.3™, 802.3u™, 802.3x™, 802.3z™,
802.3au™, and 802.3ab™
• Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
• MII management interface for external PHY control and status
• Three-speed support (10/100/1000 Mbps)
• On-chip high-speed serial interface to external SGMII PHY interface
• Support for IEEE Std 1588™
• Support for two full-duplex FIFO interface modes
• Multiple PHY interface configuration
• TCP/IP acceleration and QoS features available
• IP v4 and IP v6 header recognition on receive
• IP v4 header checksum verification and generation
• TCP and UDP checksum verification and generation
• Per-packet configurable acceleration
• Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2™, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
• Transmission from up to eight physical queues.
• Reception to up to eight physical queues
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Overview
•
•
•
•
•
•
1.8
Full- and half-duplex Ethernet support (1000 Mbps supports only full-duplex):
— IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
software-programmed PAUSE frame generation and recognition)
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
IEEE 802.1 virtual local area network (VLAN) tags and priority
— VLAN insertion and deletion
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
— Retransmission following a collision
— CRC generation and verification of inbound/outbound packets
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
MAC address recognition:
— Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
— Up to 16 exact-match MAC addresses supported
— Broadcast address (accept/reject)
— Hash table match on up to 512 multicast addresses
— Promiscuous mode
Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet
programming models
RMON statistics support
10-Kbyte internal transmit and 2-Kbyte receive FIFOs
MII management interface for control and status
Programmable Interrupt Controller (PIC)
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible
solution for general-purpose interrupt control. The PIC programming model supports 5 external and 34
internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller.
1.9
Power Management Controller (PMC)
The MPC8313E power management controller includes the following features:
• Provides power management when the device is used in both host and agent modes
• Supports PCI Power Management 1.2 D0, D1, D2, D3hot, and D3cold states
• On-chip split power supply controlled through external power switch for minimum standby power
• Support for PME generation in PCI agent mode, PME detection in PCI host mode
• Supports wake-up from Ethernet (magic packet), USB, GPIO, and PCI (PME input as host)
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
5
Electrical Characteristics
1.10
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the MPC8313E to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
1.11
DMA Controller, Dual I2C, DUART, Local Bus Controller, and
Timers
The MPC8313E provides an integrated four-channel DMA controller with the following features:
• Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
• Supports misaligned transfers
There are two I2C controllers. These synchronous, multi-master buses can be connected to additional
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The MPC8313E local bus controller (LBC) port allows connections with a wide variety of external DSPs
and ASICs. Three separate state machines share the same external pins and can be programmed separately
to access different types of devices. The general-purpose chip select machine (GPCM) controls accesses
to asynchronous devices using a simple handshake protocol. The three user programmable machines
(UPMs) can be programmed to interface to synchronous devices or custom ASIC interfaces. Each chip
select can be configured so that the associated chip interface can be controlled by the GPCM or UPM
controller. The FCM provides a glueless interface to parallel-bus NAND Flash E2PROM devices. The
FCM contains three basic configuration register groups—BRn, ORn, and FMR. Both may exist in the
same system. The local bus can operate at up to 66 MHz.
The MPC8313E system timers include the following features: periodic interrupt timer, real time clock,
software watchdog timer, and two general-purpose timer blocks.
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8313E. The MPC8313E is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Electrical Characteristics
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings 1
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.26
V
—
PLL supply voltage
AVDD
–0.3 to 1.26
V
—
Core power supply for SerDes transceivers
XCOREVDD
–0.3 to 1.26
V
—
Pad power supply for SerDes transceivers
XPADVDD
–0.3 to 1.26
V
—
GVDD
–0.3 to 2.75
–0.3 to 1.98
V
—
NVDD/LVDD
–0.3 to 3.6
V
—
LV DDA/LVDDB
–0.3 to 3.6
V
—
MVIN
–0.3 to (GV DD + 0.3)
V
2, 5
MVREF
–0.3 to (GV DD + 0.3)
V
2, 5
Enhanced Three-speed Ethernet signals
LV IN
–0.3 to (LVDDA + 0.3)
or
–0.3 to (LV DDB + 0.3)
V
4, 5
Local bus, DUART, SYS_CLK_IN, system
control, and power management, I2C, and
JTAG signals
OVIN
–0.3 to (NV DD + 0.3)
V
3, 5
PCI
OVIN
–0.3 to (NV DD + 0.3)
V
6
TSTG
–55 to 150
°C
—
DDR and DDR2 DRAM I/O voltage
PCI, local bus, DUART, system control and power management,
I2C, and JTAG I/O voltage
eTSEC, USB
Input voltage
DDR DRAM signals
DDR DRAM reference
Storage temperature range
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OV IN must not exceed NVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDDA/LVDDB by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. (L,M,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8313E. Note that the values in
Table 2 are the recommended and tested operating conditions. If a particular block is given a voltage
falling within the range in the Recommended Value column, the MPC8313E is capable of delivering the
amount of current listed in the Current Requirement column; this is the maximum current possible. Proper
device operation outside of these conditions is not guaranteed.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
7
Electrical Characteristics
Table 2. Recommended Operating Conditions
Symbol
Recommended
Value 1
Unit
Current
Requirement
Core supply voltage
VDD
1.0 V ± 50 mV
V
469 mA
Internal core logic constant power
VDDC
1.0 V ± 50 mV
V
377 mA
SerDes internal digital power
XCOREVDD
1.0
V
170 mA
SerDes internal digital ground
XCOREVSS
0.0
V
—
SerDes I/O digital power
XPADVDD
1.0
V
10 mA
SerDes I/O digital ground
XPADVSS
0.0
V
—
SerDes analog power for PLL
SDAVDD
1.0 V ± 50 mV
V
10 mA
SerDes analog ground for PLL
SDAVSS
0.0
V
—
Dedicated 3.3 V analog power for USB PLL
USB_PLL_PWR3
3.3 V ± 300 mV
V
2–3 mA
Dedicated 1.0 V analog power for USB PLL
USB_PLL_PWR1
1.0 V ± 50 mV
V
2–3 mA
USB_PLL_GND
0.0
V
—
Dedicated USB power for USB Bias circuit
USB_VDDA_BIAS
3.3 V ± 300 mV
V
4–5 mA
Dedicated USB ground for USB Bias circuit
USB_VSSA_BIAS
0.0
V
—
Dedicated power for USB Transceiver
USB_VDDA
3.3 V ± 300 mV
V
75 mA
Dedicated ground for USB transceiver
USB_VSSA
0.0
V
—
Analog power for e300 core APLL
AVDD1
1.0 V ± 50 mV
V
2–3 mA
Analog power for system APLL
AVDD2
1.0 V ± 50 mV
V
2–3 mA
DDR1 DRAM I/O voltage (333 MHz, 32-bit operation)
GVDD
2.5 V ± 125 mV
V
131 mA
DDR2 DRAM I/O voltage (333 MHz, 32-bit operation)
GVDD
1.8 V ± 80 mV
V
140 mA
Differential reference voltage for DDR controller
MVREF
1/2 DDR Supply
(0.49 × GVDD to
0.51 × GVDD)
V
—
Standard I/O voltage
NVDD
3.3 V ± 300 mV 2
V
74 mA
eTSEC2 IO supply
LV DDA
2.5 V ± 125 mV/3.3 V
± 300 mV
V
22 mA
eTSEC1/USB DR IO supply
LVDDB
2.5 V ± 125 mV/3.3 V
± 300 mV
V
44 mA
Supply for eLBC IOs
LVDD
3.3 V ± 300 mV
V
16 mA
Analog and digital ground
VSS
0.0
V
—
TJ
0 to 105
°C
—
Characteristic
Dedicated analog ground for USB PLL
Junction temperature
1
GVDD, NVDD, AVDD, and VDD must track each other and must vary in the same direction–either in the positive or negative
direction.
2
Some GPIO pins may operate from a 2.5-V supply when configured for other functions.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Driver Type
2.2
Output Impedance (Ω)
Supply Voltage
Local bus interface utilities signals
42
NVDD = 3.3 V
PCI signals
25
DDR signal
18
GVDD = 2.5 V
DDR2 signal
18
GVDD = 1.8 V
DUART, system control, I2C, JTAG,SPI
42
NVDD = 3.3 V
GPIO signals
42
NVDD = 3.3 V
eTSEC signals
42
LV DDA, LVDDB = 2.5/3.3 V
USB Signals
42
LVDDB = 2.5/3.3 V
Power Sequencing
The MPC8313E does not require the core supply voltage (VDD and VDDC) and IO supply voltages (GVDD,
LVDD, and OVDD) to be applied in any particular order. Note that during power ramp-up, before the power
supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of
time that all input and output pins are actively driven and cause contention and excessive current. In order
to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD
and VDDC) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise
to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 2. Once both the power supplies
(I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating
PORESET.
Note that there is no specific power down sequence requirement for the MPC8313E. I/O voltage supplies
(GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one another.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
9
Power Characteristics
I/O Voltage (GVDD, GV DD, and OVDD )
V
Core Voltage (VDD, VDDC)
0.7 V
90%
t
0
PORESET
tSYS_CLK_IN/tPCI_SYNC_IN >= 32 clocks
Figure 2. Power-Up Sequencing Example
3
Power Characteristics
The estimated typical power dissipation, not including I/O supply power, for this family of MPC8313E
devices is shown in Table 4, and Table 5 shows the estimated typical I/O power dissipation.
Table 4. MPC8313E Power Dissipation 1
Core Frequency (MHz)
CSB Frequency (MHz)
Typical 2, 3
Maximum 4, 3
Unit
333
167
820
1020
mW
1
The values do not include I/O supply power or AVdd but do include core, USB PLL, and a portion of
SerDes digital power (not including XCOREVDD, XPADVDD, or SDAVDD, which all have dedicated power
supplies for the SerDes PHY).
2 Typical power is based on a voltage of V
dd = 1.05 V and an artificial smoker test running at room
temperature.
3 These are preliminary estimates.
4
Maximum power is based on a voltage of Vdd = 1.05 V, a junction temperature of Tj = 105° C, and an
artificial smoker test.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Power Characteristics
Table 5 describes a typical scenario where blocks with the stated percentage of utilization and impedances
consume the amount of power described.
1
Table 5. MPC8313E Typical I/O Power Dissipation
GVDD GVDD NVDD LVDDA/LVDDB LV DDA/LVDDB LVDD
Unit Comments
(1.8 V) (2.5 V) (3.3 V)
(3.3 V)
(2.5 V)
(3.3 V)
Interface
Parameter
DDR 1, 60% utilzation,
50% read/write
Rs = 22 Ω
Rt = 50 Ω
single pair of clock
Capacitive Load:
Data = 8pF, Control
Address = 8pF,
Clock = 8pF
333 MHz, 32 bits
—
0.355
—
—
—
—
W
—
266 MHz, 32 bits
—
0.323
—
—
—
—
W
—
DDR 2, 60%
utilization, 50%
read/write
Rs = 22 Ω
Rt = 75 Ω
single pair of clock
Capacitive Load:
Data = 8pF, Control
Address = 8pF,
Clock = 8pF
333 MHz, 32 bits
0.266
—
—
—
—
—
W
—
266 MHz, 32 bits
0.246
—
—
—
—
—
W
—
PCI I/O load = 50pF
33 MHz
—
—
0.120
—
—
—
W
—
66 MHz
—
—
0.249
—
—
—
W
—
Local bus I/O
load = 20pF
66 MHz
—
—
—
—
—
0.056
W
—
50 MHz
—
—
—
—
—
0.040
W
—
TSEC I/O load = 20pF
MII, 25 MHz
—
—
—
0.008
—
—
W
RGMII, 125 MHz
—
—
—
0.078
0.044
—
W
Multiple by
number of
interface
used
USBDR controller
load = 20pF
60 MHz
—
—
—
0.078
—
—
W
—
Other I/O
—
—
—
0.015
—
—
—
W
—
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
11
Clock Input Timing
Table 6 shows the estimated core power dissipation of the MPC8313E while transitioning into the
D3warm low power state.
Table 6. MPC8313E Low Power Modes Power Dissipation 1,
333-MHz core, 167-MHz CSB 2
Maximum 3
Unit
D3 warm
400
mW
1
All interfaces are enabled. For further power savings, disable the clocks to unused
blocks.
2 The interfaces are run at the following frequencies: DDR: 167 MHz, eLBC 167 MHz,
PCI 33 MHz, eTSEC1 and 2: 167 MHz, SEC: 167 MHz, USB: 167 MHz. See the SCCR
register for more information.
3
Maximum power is based on a voltage of 1.05 V and a junction temperature of 105° C.
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8313E.
4.1
DC Electrical Characteristics
Table 7 provides the system clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for the
MPC8313E.
Table 7. SYS_CLK_IN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
VIH
2.7
NVDD + 0.3
V
Input low voltage
—
VIL
–0.3
0.4
V
SYS_CLK_IN Input current
0 V ≤ VIN ≤ NVDD
IIN
—
±10
μA
PCI_SYNC_IN Input current
0 V ≤ VIN ≤ 0.5 V
or
NVDD – 0.5 V ≤ VIN ≤ NV DD
IIN
—
±10
μA
PCI_SYNC_IN Input current
0.5 V ≤ VIN ≤ NVDD – 0.5 V
IIN
—
±50
μA
4.2
AC Electrical Characteristics
The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,
depending on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the system
clock input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8313E.
Table 8. SYS_CLK_IN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYS_CLK_IN/PCI_CLK frequency
fSYS_CLK_IN
24
—
66.67
MHz
1
SYS_CLK_IN/PCI_CLK cycle time
tSYS_CLK_IN
15
—
—
ns
—
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
12
Freescale Semiconductor
RESET Initialization
Table 8. SYS_CLK_IN AC Timing Specifications (continued)
SYS_CLK_IN/PCI_CLK rise and fall time
SYS_CLK_IN/PCI_CLK duty cycle
tKH, tKL
0.6
0.8
1.2
ns
2
tKHK/tSYS_CLK_IN
40
—
60
%
3
—
—
—
±150
ps
4, 5
SYS_CLK_IN/PCI_CLK jitter
Notes:
1. Caution: The system, core, security block must not exceed their respective maximum or minimum operating frequencies.
2. Rise and fall times for SYS_CLK_IN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8313E.
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins.
Table 9. RESET Pins DC Electrical Characteristics
Characteristic
5.2
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.1
NVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ NVDD
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET (input) to activate reset flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock and power applied to
SYS_CLK_IN when the device is in PCI host mode
32
—
tSYS_CLK_IN
2
Required assertion time of PORESET with stable clock and power applied to
PCI_SYNC_IN when the device is in PCI agent mode
32
—
tPCI_SYNC_IN
1
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
13
DDR and DDR2 SDRAM
Table 10. RESET Initialization Timing Specifications (continued)
HRESET/ SRESET assertion (output)
512
—
tPCI_SYNC_IN
1
HRESET negation to SRESET negation (output)
16
—
tPCI_SYNC_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3] and
CFG_SYS_CLK_IN_DIV ) with respect to negation of PORESET when the device is
in PCI host mode
4
—
tSYS_CLK_IN
2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the device is in PCI
agent mode
4
—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of HRESET
0
—
ns
—
Time for the device to turn off POR configuration signals with respect to the assertion
of HRESET
—
4
ns
3
Time for the device to turn on POR configuration signals with respect to the negation
of HRESET
1
—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.
2. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.
3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 11 provides the PLL lock times.
Table 11. PLL Lock Times
Parameter/Condition
PLL lock times
6
Min
Max
Unit
Notes
—
100
μs
—
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface. Note that
DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) when
GVDD(typ) = 1.8 V.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.7
1.9
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.125
GVDD + 0.3
V
—
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
14
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Input low voltage
VIL
–0.3
MVREF – 0.125
V
—
Output leakage current
IOZ
–9.9
9.9
μA
4
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
—
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
Notes:
1. GV DD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MV REF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GV DD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when
GVDD(typ) = 2.5 V.
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.3
2.7
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.15
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.15
V
—
Output leakage current
IOZ
–9.9
–9.9
μA
4
Output high current (VOUT = 1.95 V)
IOH
–16.2
—
mA
—
Output low current (VOUT = 0.35 V)
IOL
16.2
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GV DD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
15
DDR and DDR2 SDRAM
Table 15 provides the DDR capacitance when GVDD (typ)=2.5 V.
Table 15. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GV DD /2, VOUT (peak-to-peak) = 0.2 V.
Table 16 provides the current draw characteristics for MVREF.
Table 16. Current Draw Characteristics for MVREF
Parameter / Condition
Current draw for MVREF
Symbol
Min
Max
Unit
Note
IMVREF
—
500
μA
1
1. The voltage regulator for MVREF must be able to supply up to 500 μA current.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ)=1.8 V.
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 ±5%
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF – 0.25
V
—
AC input high voltage
VIH
MVREF + 0.25
—
V
—
Table 18 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V.
Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions with GVDD of 2.5 ±5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF – 0.31
V
—
AC input high voltage
VIH
MVREF + 0.31
—
V
—
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
16
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 19 provides the input AC timing specifications for the DDR2 SDRAM interface.
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions. with GVDD of 2.5 ±5%
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for MDQS—MDQ
tCISKEW
—
—
ps
1, 2
333 MHz
—
–750
750
—
—
266 MHz
—
–750
750
—
—
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = +/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
Figure 3 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
MCK[n]
MCK[n]
tMCK
MDQS[n]
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 3. DDR Input Timing Diagram
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
17
DDR and DDR2 SDRAM
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions.
Parameter
MCK[n] cycle time, MCK[n]/MCK[n] crossing
ADDR/CMD output setup with respect to MCK
Symbol 1
Min
Max
Unit
Notes
tMCK
6
10
ns
2
ns
3
ns
3
ns
3
ns
3
ns
4
ps
5
ps
5
tDDKHAS
333 MHz
2.1
—
266 MHz
2.5
—
ADDR/CMD output hold with respect to MCK
tDDKHAX
333 MHz
2.40
—
266 MHz
3.15
—
MCS[n] output setup with respect to MCK
tDDKHCS
333 MHz
2.40
—
266 MHz
3.15
—
MCS[n] output hold with respect to MCK
tDDKHCX
333 MHz
2.40
—
266 MHz
3.15
—
–0.6
0.6
MCK to MDQS Skew
tDDKHMH
MDQ//MDM output setup with respect to MDQS
tDDKHDS,
tDDKLDS
333 MHz
800
—
266 MHz
900
—
MDQ//MDM output hold with respect to MDQS
tDDKHDX,
tDDKLDX
333 MHz
900
—
266 MHz
1100
—
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
18
Freescale Semiconductor
DDR and DDR2 SDRAM
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions.
Symbol 1
Min
Max
Unit
Notes
MDQS preamble start
tDDKHMP
–0.5 × tMCK – 0.6
–0.5 × tMCK + 0.6
ns
6
MDQS epilogue end
tDDKHME
–0.6
0.6
ns
6
Parameter
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until
outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8313E PowerQUICC™ II Pro Host Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
NOTE
For the ADDR/CMD setup and hold specifications in Table 20, it is
assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n]
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns
MDQS
tDDKHMH(min) = –0.6 ns
MDQS
Figure 4. Timing Diagram for tDDKHMH
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
19
DDR and DDR2 SDRAM
Figure 5 shows the DDR and DDR2 SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS ,tDDKHCS
tDDKHAX ,tDDKHCX
ADDR/CMD
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 5. DDR and DDR2 SDRAM Output Timing Diagram
Figure 6 provides the AC test load for the DDR bus.
Output
Z0 = 50 Ω
RL = 50 Ω
GVDD/2
Figure 6. DDR AC Test Load
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
20
Freescale Semiconductor
DUART
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface.
7.1
DUART DC Electrical Characteristics
Table 21 provides the DC electrical characteristics for the DUART interface.
Table 21. DUART DC Electrical Characteristics
Parameter
7.2
Symbol
Min
Max
Unit
High-level input voltage
VIH
2.0
NVDD + 0.3
V
Low-level input voltage NVDD
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 μA
VOH
NVDD – 0.2
—
V
Low-level output voltage, IOL = 100 μA
VOL
—
0.2
V
Input current (0 V ≤VIN ≤ NVDD)
IIN
—
±5
μA
DUART AC Electrical Specifications
Table 22 provides the AC timing parameters for the DUART interface.
Table 22. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
256
baud
—
Maximum baud rate
> 1,000,000
baud
1
16
—
2
Oversample rate
Notes:
1. Actual attainable baud rate is limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit.
Subsequent bit values are sampled each 16th sample.
8
Ethernet: Three-Speed Ethernet, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII
management.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to all the media independent interface (MII), reduced
gigabit media independent interface (RGMII), serial gigabit media independent interface (SGMII), and
reduced ten-bit interface (RTBI) signals except management data input/output (MDIO) and management
data clock (MDC). The MII interface is defined for 3.3 V, while the RMII, RGMII, SGMII, and RTBI
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
21
Ethernet: Three-Speed Ethernet, MII Management
interfaces can be operated at 3.3 V or 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard
reduced pin-count interface for Gigabit Ethernet Physical Layer Device Specification Version 1.2a
(9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.4, “Ethernet
Management Interface Electrical Characteristics.”
8.1.1
TSEC DC Electrical Characteristics
All RGMII, SGMII, RMII, and RTBI drivers and receivers comply with the DC parametric attributes
specified in Table 23 and Table 24. The potential applied to the input of a MII, RGMII, SGMII, or RTBI
receiver may exceed the potential of the receiver’s power supply (that is, a RGMII driver powered from a
3.6-V supply driving VOH into a RGMII receiver powered from a 2.5-V supply). Tolerance for dissimilar
RGMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI
signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 23. MII/RGMII/RTBI (When Operating at 3.3V) DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage 3.3 V
LVDDA/LVDDB
—
2.97
3.63
V
Output high voltage
VOH
IOH = –4.0 mA
LVDDA or LVDDB =
Min
2.40
LVDDA + 0.3
or
LV DDB + 0.3
V
Output low voltage
VOL
IOL = 4.0 mA
LVDDA or LVDDB = Min
VSS
0.50
V
Input high voltage
VIH
—
—
2.0
LVDDA + 0.3
or
LV DDB + 0.3
V
Input low voltage
VIL
—
—
–0.3
0.90
V
Input high current
IIH
VIN 1 = LVDDA or LVDDB
—
40
μA
Input low current
IIL
VIN 1 = VSS
–600
—
μA
Note:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
22
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Table 24. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics
Parameters
Symbol
Conditions
Min
Max
Unit
Supply voltage 2.5 V
LVDDA/LVDDB
—
2.37
2.63
V
Output high voltage
VOH
IOH = –1.0 mA LVDDA or LVDDB = Min
2.00
LVDDA + 0.3
or
LVDDB + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDDA or LVDDB = Min
VSS – 0.3
0.40
V
Input high voltage
VIH
—
LVDDA or LVDDB = Min
1.7
LVDDA + 0.3
or
LVDDB + 0.3
V
Input low voltage
VIL
—
LVDDA or LVDDB = Min
–0.3
0.70
V
—
10
μA
–15
—
μA
Input high current
IIH
Input low current
IIL
VIN
1=
LVDDA or LV DDB
VIN 1 = VSS
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
8.2
MII, RGMII, SGMII, and RTBI AC Timing Specifications
The AC timing specifications for MII, RMII, RGMII, SGMII, and RTBI are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1
MII Transmit AC Timing Specifications
Table 25 provides the MII transmit AC timing specifications.
Table 25. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB /NVDD of 3.3 V ± 10%.
Symbol 1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—
40
—
ns
tMTXH/tMTX
35
—
65
%
tMTKHDX
1
5
15
ns
Parameter/Condition
TX_CLK duty cycle
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
23
Ethernet: Three-Speed Ethernet, MII Management
Table 25. MII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDDA/LVDDB /NVDD of 3.3 V ± 10%.
Symbol 1
Min
Typ
Max
Unit
TX_CLK data clock rise VIL(min) to VIH(max)
tMTXR
1.0
—
4.0
ns
TX_CLK data clock fall VIH(max) to VIL(min)
tMTXF
1.0
—
4.0
ns
Parameter/Condition
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII
transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
Figure 7 shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXH
tMTXF
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 7. MII Transmit AC Timing Diagram
8.2.1.2
MII Receive AC Timing Specifications
Table 26 provides the MII receive AC timing specifications.
Table 26. MII Receive AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB /NVDD of 3.3 V ± 10%.
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—
400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—
40
—
ns
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
—
ns
Parameter/Condition
RX_CLK duty cycle
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Table 26. MII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDDA/LVDDB /NVDD of 3.3 V ± 10%.
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0
—
4.0
ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0
—
4.0
ns
Parameter/Condition
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference
(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
Figure 8 provides the AC test load for TSEC.
Output
Z0 = 50 Ω
RL = 50 Ω
LVDDA/2 or LVDDB/2
Figure 8. TSEC AC Test Load
Figure 9 shows the MII receive AC timing diagram.
tMRX
tMRXR
RX_CLK
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRXF
Valid Data
tMRDVKH
tMRDXKH
Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
25
Ethernet: Three-Speed Ethernet, MII Management
8.2.1.3
RMII Transmit AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
Table 27 provides the RMII transmit AC timing specifications.
Table 27. RMII Transmit AC Timing Specifications
At recommended operating conditions with NVDD of 3.3 V ± 10%.
Symbol 1
Min
Typical
Max
Unit
tRMX
—
20
—
ns
tRMXH/tRMX
35
—
65
%
REF_CLK to RMII data TXD[1:0], TX_EN delay
tRMTKHDX
2
—
10
ns
REF_CLK data clock rise VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK data clock fall VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Parameter/Condition
REF_CLK clock
REF_CLK duty cycle
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX
symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid
(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock
of a particular functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 10 shows the RMII transmit AC timing diagram.
tRMXR
tRMX
REF_CLK
tRMXH
tRMXF
TXD[1:0]
TX_EN
tRMTKHDX
Figure 10. RMII Transmit AC Timing Diagram
8.2.1.4
RMII Receive AC Timing Specifications
Table 28 provides the RMII receive AC timing specifications.
Table 28. RMII Receive AC Timing Specifications
At recommended operating conditions with NVDD of 3.3 V ± 10%.
Symbol 1
Min
Typical
Max
Unit
tRMX
—
20
—
ns
tRMXH/tRMX
35
—
65
%
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
—
—
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
—
—
ns
Parameter/Condition
REF_CLK clock period
REF_CLK duty cycle
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Table 28. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with NVDD of 3.3 V ± 10%.
Symbol 1
Min
Typical
Max
Unit
REF_CLK clock rise VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK clock fall time VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Parameter/Condition
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH
symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the
tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with
respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state
or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock
of a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 11 provides the AC test load.
Z0 = 50 Ω
Output
RL = 50 Ω
NVDD/2
Figure 11. AC Test Load
Figure 12 shows the RMII receive AC timing diagram.
tRMX
tRMXR
REF_CLK
tRMXF
tRMXH
RXD[1:0]
CRS_DV
RX_ER
Valid Data
tRMRDVKH
tRMRDXKH
Figure 12. RMII Receive AC Timing Diagram
8.2.2
RGMII and RTBI AC Timing Specifications
Table 29 presents the RGMII and RTBI AC timing specifications.
Table 29. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB of 2.5 V ± 5%.
Parameter/Condition
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock cycle duration
3
2
Symbol 1
Min
Typ
Max
Unit
tSKRGT
–0.5
—
0.5
ns
tSKRGT
1.0
—
2.8
ns
tRGT
7.2
8.0
8.8
ns
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
27
Ethernet: Three-Speed Ethernet, MII Management
Table 29. RGMII and RTBI AC Timing Specifications (continued)
At recommended operating conditions with LVDDA/LVDDB of 2.5 V ± 5%.
Duty cycle for 1000Base-T 4, 5
tRGTH/tRGT
45
50
55
%
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
—
0.75
ns
6
—
8.0
—
ns
47
—
53
%
Duty cycle for 10BASE-T and 100BASE-TX
3, 5
GTX_CLK125 reference clock period
tG12
GTX_CLK125 reference clock duty cycle
tG125H/tG125
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the RTBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is
added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
between.
5. Duty cycle reference is LVDDA/2 or LVDDB/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
Figure 13 shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At Transmitter)
tSKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CTL
TXD[8:5]
TXD[3:0] TXD[7:4]
TXD[4]
TXEN
TXD[9]
TXERR
tSKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[3:0] RXD[7:4]
tSKRGT
RX_CTL
RXD[4]
RXDV
RXD[9]
RXERR
tSKRGT
RX_CLK
(At PHY)
Figure 13. RGMII and RTBI AC Timing and Multiplexing Diagrams
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
8.3
eTSEC IEEE 1588 AC Specifications
Figure 14 provides the data and command output timing diagram.
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_CLK_OUT
tT1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
1
The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is count starting falling edge.
Figure 14. eTSEC IEEE 1588 Output AC Timing
Figure 15 provides the data and command input timing diagram.
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
tT1588TRIGH
Figure 15. eTSEC IEEE 1588 Input AC Timing
The IEEE 1588 AC timing specifications are in Table 30.
Table 30. eTSEC IEEE 1588 AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
tT1588CLK
3.8
—
TRX_CLK × 9
ns
1, 3
tT1588CLKH/tT1588CLK
40
50
60
%
—
TSEC_1588_CLK peak-to-peak jitter
tT1588CLKINJ
—
—
250
ps
—
Rise time eTSEC_1588_CLK (20%–80%)
tT1588CLKINR
1.0
—
2.0
ns
—
Fall time eTSEC_1588_CLK (80%–20%)
tT1588CLKINF
1.0
—
2.0
ns
—
TSEC_1588_CLK_OUT clock period
tT1588CLKOUT
2*tT1588CLK
—
—
ns
—
TSEC_1588_CLK clock period
TSEC_1588_CLK duty cycle
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
29
Ethernet: Three-Speed Ethernet, MII Management
Table 30. eTSEC IEEE 1588 AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
TSEC_1588_CLK_OUT duty cycle
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_IN pulse width
Symbol
Min
Typ
Max
Unit
Note
tT1588CLKOTH
/tT1588CLKOUT
30
50
70
%
—
tT1588OV
0.5
—
3.0
ns
—
tT1588TRIGH
2*tT1588CLK_MAX
—
—
ns
2
Note:
1.TRX_CLK is the max clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the MPC8313E
PowerQUICC™ II Pro Integrated Processor Reference Manual for a description of TMR_CTRL registers.
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8313E PowerQUICC™
II Pro Integrated Processor Reference Manual for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK is 3600, 280, and 56 ns, respectively.
8.4
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
MII, RMII, RGMII, SGMII, and RTBI are specified in Section 8.1, “Enhanced Three-Speed Ethernet
Controller (eTSEC) (10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical Characteristics.”
8.4.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. Table 31 and Table 32
provide the DC electrical characteristics for MDIO and MDC.
Table 31. MII Management DC Electrical Characteristics When Powered at 2.5 V
Parameter
Symbol
Supply voltage (2.5 V) NVDDA/NVDDB
Conditions
Min
Max
Unit
—
2.37
2.63
V
Output high voltage
VOH
IOH = –1.0 mA
NVDDA or NVDDB = Min
2.00
NVDDA + 0.3
or
NVDDB + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
NVDDA or NVDDB = Min
VSS – 0.3
0.40
V
Input high voltage
VIH
—
NVDDA or NVDDB = Min
1.7
—
V
Input low voltage
VIL
—
NVDDA or NVDDB = Min
–0.3
0.70
V
—
10
μA
–15
—
μA
Input high current
IIH
Input low current
IIL
VIN
1
= NVDDA or NVDDB
VIN = NVDDA or NV DDB
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Table 32. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Symbol
Conditions
Min
Max
Unit
—
2.97
3.63
V
Supply voltage (3.3 V) NVDDA/NVDDB
Output high voltage
VOH
IOH = –1.0 mA
NVDDA or NVDDB = Min
2.10
NVDDA + 0.3
or
NVDDB + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDDA or LVDDB = Min
VSS
0.50
V
Input high voltage
VIH
—
2.0
—
V
Input low voltage
VIL
—
—
0.80
V
Input high current
IIH
NVDDA or NVDDB = Max
VIN 1 = 2.1 V
—
40
μA
Input low current
IIL
NVDDA or NVDDB = Max
VIN = 0.5 V
–600
—
μA
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
8.4.2
MII Management AC Electrical Specifications
Table 33 provides the MII management AC timing specifications.
Table 33. MII Management AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 10% or 2.5 V ± 5%
Symbol 1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—
2.5
—
MHz
2
MDC period
tMDC
—
400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
—
ns
—
MDC to MDIO delay
tMDKHDX
10
—
170
ns
—
MDIO to MDC setup time
tMDDVKH
5
—
—
ns
—
MDIO to MDC hold time
tMDDXKH
0
—
—
ns
—
MDC rise time
tMDCR
—
—
10
ns
—
MDC fall time
tMDHF
—
—
10
ns
—
Parameter/Condition
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
31
Ethernet: Three-Speed Ethernet, MII Management
Figure 16 shows the MII management AC timing diagram.
tMDCR
tMDC
MDC
tMDCF
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 16. MII Management Interface Timing Diagram
8.4.3
SGMII DC Electrical Characteristics
The SGMII Solution in the MPC8313 is designed for use in a 4-wire, AC-Coupled SGMII link. Table 34
andTable 35describe the SGMII AC-Coupled DC electrical characteristics. Transmitter characteristics are
measured at the transmitter outputs, SD_TX and SD_TX_B, as depicted in Figure 17.
Table 34. DC Transmitter Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Output high voltage
VOH
—
0.7*XPADVDD1
mV
Output low voltage
VOL
0.3*XPADVDD
—
mV
Output ringing
VRING
—
10
%
—
Output differential voltage
|VOD|
(XPADVDD/2)/1.7
(XPADVDD/2)/1.3
mV
—
Output offset voltage
VOS
Output impedance (single ended)
RO
40
60
Ω
—
Mismatch in a pair
ΔRO
—
10
%
—
Change in VOD between “0” and “1”
Δ|VOD|
—
25
mV
—
Change in VOS between “0” and “1”
Δ VOS
—
25
mV
—
Output current on short to GND
ISA, ISB
—
40
mA
—
1 XPADVDDrefers
(XPADVDD/2) – 50 mV (XPADVDD/2) + 50 mV
mV
Notes
Does not align to
DC-coupled
SGMII
Does not align to
DC-coupled
SGMII
to the SGMII transmitter output supply voltage.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
SD_TX
Transmitter
100 ohms
SD_TX_B
Figure 17. Transmitter Reference Circuit
Table 35. DC Receiver Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Notes
DC input voltage range
—
—
—
—
Input must be externally ac-coupled.
Input differential voltage
Vrx_diffpp
100
1200
mV Peak to peak input differential
voltage.
Loss of signal threshold
Vlos
30
100
mV
Vcm_acpp
—
100
mV Peak to peak ac common mode
voltage.
Receiver differential input impedance
Zrx_diff
80
120
Ω
—
Receiver common mode input impedance
Zrx_cm
20
35
Ω
—
Vcm
xcorevss
xcorevss
V
Input AC common mode voltage
Common mode input voltage
8.4.3.1
—
On-chip termination to xcorevss.
SGMII Transmit AC Timing Specifications
Table 36 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.
Table 36. SGMII Transmit AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Deterministic Jitter
JD
—
0.17
UI p-p
—
Total Jitter
JT
—
0.35
UI p-p
—
Unit Interval
UI
800
800
ps
VOD fall time (80%–20%)
tfall
50
120
ps
—
VOD rise time (20%–80%)
trise
50
120
ps
—
+/– 100ppm
Source synchronous clock is not supported
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
33
Ethernet: Three-Speed Ethernet, MII Management
8.4.3.2
SGMII Receive AC Timing Specifications
Table 37 provides the SGMII transmit AC timing targets. A source synchronous clock is not supported.
Table 37. SGMII Receiver AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Deterministic Jitter Tolerance
JD
0.37
—
UI p-p
Measured at receiver
Combined Deterministic and Random Jitter Tolerance
JDR
0.55
—
UI p-p
Measured at receiver
Sinusoidal Jitter Tolerance
Jsin
0.1
—
UI p-p
Measured at receiver
JT
0.65
—
UI p-p
Measured at receiver
BER
—
10-12
UI
800
800
Total Jitter Tolerance
Bit Error Ratio
Unit Interval
—
ps
+/– 100ppm
Vrx_diffpp_max/2
Vrx_diffpp_min/2
0
–Vrx_diffpp_min/2
–Vrx_diffpp_max/2
0
.275
.4
.6
Time (UI)
.625
1
Figure 18. Receive Input Compliance Mask
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
34
Freescale Semiconductor
USB
9
9.1
USB
USB Dual-Role Controllers
This section provides the AC and DC electrical specifications for the USB interface.
9.1.1
USB DC Electrical Characteristics
Table 38 provides the DC electrical characteristics for the USB interface.
Table 38. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2.0
LVDDB+ 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—
±5
μA
High-level output voltage, IOH = –100 μA
VOH
LV DDB – 0.2
—
V
Low-level output voltage, IOL = 100 μA
VOL
—
0.2
V
9.1.2
USB AC Electrical Specifications
Table 39 describes the general timing parameters of the USB interface.
Table 39. USB General Timing Parameters (ULPI Mode Only)
Symbol 1
Min
Max
Unit
Notes
tUSCK
15
—
ns
—
Input setup to USB clock - all inputs
tUSIVKH
4
—
ns
—
input hold to USB clock - all inputs
tUSIXKH
1
—
ns
—
USB clock to output valid - all outputs
tUSKHOV
—
7
ns
—
Output hold from USB clock - all outputs
tUSKHOX
2
—
ns
—
Parameter
USB clock cycle time
Note:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB
timing (USB) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX
symbolizes us timing (USB) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or
output hold time.
Figure 19 and Figure 20 provide the AC test load and signals for the USB, respectively.
Output
Z0 = 50 Ω
RL = 50 Ω
NVDD/2
Figure 19. USB AC Test Load
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
35
USB
USBDR_CLK
tUSIXKH
tUSIVKH
Input Signals
tUSKHOX
tUSKHOV
Output Signals:
Figure 20. USB Signals
9.2
On-Chip USB PHY
This section describes the DC and AC electrical specifications for the on-chip USB PHY of the
MPC8313E. See chapter 7 in the USB Specifications Rev 2.0 for more information.
Table 40 provides the USB clock input (USB_CLK_IN) DC timing specifications.
Table 40. USB_CLK_IN DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Input high voltage
VIH
2.7
NVDD + 0.3
V
Input low voltage
VIL
–0.3
0.4
V
Table 41 provides the USB clock input (USB_CLK_IN) AC timing specifications.
Table 41. USB_CLK_IN AC Timing Specifications
Parameter/Condition
Conditions
Symbol
Min
Frequency range
—
fUSB_CLK_IN
—
24
—
MHz
Clock frequency tolerance
—
tCLK_TOL
–0.05
0
0.05
%
tCLK_DUTY
40
50
60
%
tCLK_PJ
—
—
200
ps
Reference clock duty cycle
Measured at 1.6 V
Total input jitter/Time interval error Peak to peak value measured with a second
order high-pass filter of 500 kHz bandwidth
Typical Max Unit
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Local Bus
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface.
10.1 Local Bus DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the local bus interface.
Table 42. Local Bus DC Electrical Characteristics at 3.3 V
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
LVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
IIN
—
±5
μA
High-level output voltage, (LVDD = min, IOH = -2 mA)
VOH
LVDD – 0.2
—
V
Low-level output voltage, (LVDD = min, IOH = 2 mA)
VOL
—
0.2
V
1
Input current, (VIN = 0 V or VIN = LVDD)
10.2
Local Bus AC Electrical Specifications
Table 43 describes the general timing parameters of the local bus interface.
Table 43. Local Bus General Timing Parameters
Symbol 1
Min
Max
Unit
Notes
tLBK
15
—
ns
2
Input setup to local bus clock
tLBIVKH
7
—
ns
3, 4
Input hold from local bus clock
tLBIXKH
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3
—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
LALE output rise to LCLK negative edge
tLALEHOV
—
3.0
ns
—
LALE output fall to LCLK negative edge
tLALETOT1
–1.5
—
ns
5
LALE output fall to LCLK negative edge
tLALETOT2
–5.0
—
ns
6
LALE output fall to LCLK negative edge
tLALETOT3
–4.5
—
ns
7
Parameter
Local bus cycle time
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
37
Local Bus
Table 43. Local Bus General Timing Parameters (continued)
Symbol 1
Min
Max
Unit
Notes
Local bus clock to output valid
tLBKHOV
—
3
ns
3
Local bus clock to output high impedance for LAD
tLBKHOZ
—
4
ns
8
Parameter
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local
bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this
case for clock one(1).
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from NVDD/2 of the rising/falling edge of LCLK0 to 0.4 × NVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5.tLBOTOT1 and tLALETOT1 should be used when RCWH[LALE] is not set and the load on LALE output pin is at least 10pF less
than the load on LAD output pins.
6.tLBOTOT2 and tLALETOT2 should be used when RCWH[LALE] is set and the load on LALE output pin is at least 10pF less than
the load on LAD output pins.
7.tLBOTOT3 and tLALETOT3 should be used when RCWH[LALE] is set and the load on LALE output pin equals to the load on LAD
output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Figure 21 provides the AC test load for the local bus.
Output
Z0 = 50 Ω
RL = 50 Ω
NVDD/2
Figure 21. Local Bus AC Test Load
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
38
Freescale Semiconductor
Local Bus
Figure 22 through Figure 25 show the local bus signals.
LCLK[n]
tLBIVKH
Input Signals:
LAD[0:15]
tLBIXKH
tLBIXKH
tLBIVKH
Input Signal:
LGTA
tLBIXKH
Output Signals:
LBCTL/LBCKE/LOE/
tLBKHOV
tLBKHOV
tLBKHOZ
Output Signals:
LAD[0:15]
tLBOTOT
LALE
Figure 22. Local Bus Signals, Non-Special Signals Only
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
39
Local Bus
LCLK
T1
T3
tLBKHOV
tLBKHOZ
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:15]
tLBKHOV
tLBKHOZ
UPM Mode Output Signals:
LCS[0:3]/LBS[0:1]/LGPL[0:5]
Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
40
Freescale Semiconductor
Local Bus
LCLK
T1
T2
T3
T4
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH
tLBIVKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:15]
tLBKHOZ
tLBKHOV
UPM Mode Output Signals:
LCS[0:3]/LBS[0:1]/LGPL[0:5]
Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4
LCLK[n]
t LBIXKH
t LBIVKH
Input Signals:
LAD[0:15]
tLBIXKH
t LBIVKH
Input Signal:
LGTA
tLBIXKH
Output Signals:
LBCTL/LBCKE/LOE
t LBKHOV
tLBKHOZ
Output Signals:
LAD[0:15]
t LBKHOV
t LBOTOT
t LALEHOV
t LALETOT
LALE
Figure 25. Local Bus Signals, LALE with Respect to LCLK
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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41
JTAG
11 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std 1149.1™ (JTAG)
interface.
11.1
JTAG DC Electrical Characteristics
Table 44 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface.
Table 44. JTAG Interface DC Electrical Characteristics
Characteristic
11.2
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.1
NVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
—
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface.
Table 45 provides the JTAG AC timing specifications as defined in Figure 27 through Figure 30.
Table 45. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1
At recommended operating conditions (see Table 2).
Symbol 2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
—
JTAG external clock cycle time
t JTG
30
—
ns
—
tJTKHKL
15
—
ns
—
tJTGR & tJTGF
0
2
ns
—
tTRST
25
—
ns
3
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
4
—
—
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
2
11
11
Parameter
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
ns
Input setup times:
4
Input hold times:
ns
4
Valid times:
ns
5
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
JTAG
Table 45. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1 (continued)
At recommended operating conditions (see Table 2).
Symbol 2
Min
Max
Unit
Notes
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
2
—
—
ns
5
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
2
19
9
ns
5, 6
Parameter
Output hold times:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 19).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock
reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time
data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
Figure 26 provides the AC test load for TDO and the boundary-scan outputs.
Z0 = 50 Ω
Output
R L = 50 Ω
NVDD/2
Figure 26. AC Test Load for the JTAG Interface
Figure 27 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTGR
tJTKHKL
tJTG
tJTGF
VM = Midpoint Voltage (NV DD/2)
Figure 27. JTAG Clock Input Timing Diagram
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
43
JTAG
Figure 28 provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (NVDD/2)
Figure 28. TRST Timing Diagram
Figure 29 provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (NVDD /2)
Figure 29. Boundary-Scan Timing Diagram
Figure 30 provides the test access port timing diagram.
JTAG
External Clock
VM
VM
tJTIVKH
tJTIXKH
Input
Data Valid
TDI, TMS
tJTKLOV
tJTKLOX
Output Data Valid
TDO
tJTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (NVDD/2)
Figure 30. Test Access Port Timing Diagram
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
I2C
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface.
12.1
I2C DC Electrical Characteristics
Table 46 provides the DC electrical characteristics for the I2C interface.
Table 46. I2C DC Electrical Characteristics
At recommended operating conditions with NVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit Notes
Input high voltage level
VIH
0.7 × NV DD
NVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3 × NVDD
V
—
Low level output voltage
VOL
0
0.2 × NVDD
V
1
250
ns
2
Output fall time from VIH(min) to V IL(max) with a bus capacitance from 10
to 400 pF
tI2KLKV 20 + 0.1 × CB
Pulse width of spikes which must be suppressed by the input filter
tI2KHKL
0
50
ns
3
Capacitance for each I/O pin
CI
—
10
pF
—
Input current, (0 V ≤VIN ≤ NVDD)
IIN
—
±5
μA
4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C B = capacitance of one bus line in pF.
3. Refer to the MPC8313E PowerQUICC™ II Pro Integrated Host Processor Reference Manual for information on the digital
filter used.
4. I/O pins obstruct the SDA and SCL lines if NVDD is switched off.
12.2
I2C AC Electrical Specifications
Table 47 provides the AC timing parameters for the I2C interface.
Table 47. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Symbol 1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
—
μs
High period of the SCL clock
tI2CH
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
Hold time (repeated) START condition (after this period, the first clock pulse is generated)
tI2SXKL
0.6
—
μs
Data setup time
tI2DVKH
100
—
ns
Data hold time:
tI2DXKL
—
02
—
0.9 3
Parameter
CBUS compatible masters
I2C bus devices
μs
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
45
I2C
Table 47. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Symbol 1
Min
Max
Unit
tI2CF
—
300
ns
Setup time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including hysteresis)
VNL
0.1 × NVDD
—
V
Noise margin at the HIGH level for each connected device (including hysteresis)
VNH
0.2 × NVDD
—
V
Parameter
Fall time of both SDA and SCL signals5
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. The MPC8313E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
5. The MPC8313E does not follow the “I2C-BUS Specifications” version 2.1 regarding the tI2CF AC parameter.
Figure 31 provides the AC test load for the I2C.
Output
Z0 = 50 Ω
RL = 50 Ω
NVDD/2
Figure 31. I2C AC Test Load
Figure 32 shows the AC timing diagram for the I2C bus.
SDA
tI2CF
tI2DVKH
tI2CL
tI2KHKL
tI2SXKL
tI2CF
tI2CR
SCL
tI2SXKL
S
tI2CH
tI2DXKL
tI2SVKH
Sr
tI2PVKH
P
S
Figure 32. I2C Bus AC Timing Diagram
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
PCI
13 PCI
This section describes the DC and AC electrical specifications for the PCI bus.
13.1
PCI DC Electrical Characteristics
Table 48 provides the DC electrical characteristics for the PCI interface.
Table 48. PCI DC Electrical Characteristics 1
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
0.5 x NVDD
NVDD + 0.3
V
Low-level input voltage
VIL
VOUT ≤ VOL (max)
–0.5
0.3 × NVDD
V
High-level output voltage
VOH
NVDD = min,IOH = –100 μA
0.9 x NVDD
—
V
Low-level output voltage
VOL
NVDD = min, IOL = 100 μA
—
0.1 × NVDD
V
IIN
0 V ≤ VIN ≤ NVDD
—
±5
μA
Input current
Note:
1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
13.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or
PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8313E is configured
as a host or agent device.
Table 49 shows the PCI AC timing specifications at 66 MHz.
.
Table 49. PCI AC Timing Specifications at 66 MHz
Symbol 1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
6.0
ns
2
Output hold from Clock
tPCKHOX
1
—
ns
2
Clock to output high impedance
tPCKHOZ
—
14
ns
2, 3
Input setup to Clock
tPCIVKH
3.0
—
ns
2, 4
Input hold from Clock
tPCIXKH
0
—
ns
2, 4
Parameter
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
47
PCI
Table 50 shows the PCI AC Timing Specifications at 33 MHz.
Table 50. PCI AC Timing Specifications at 33 MHz
Symbol 1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
11
ns
2
Output hold from Clock
tPCKHOX
2
—
ns
2
Clock to output high impedance
tPCKHOZ
—
14
ns
2, 3
Input setup to Clock
tPCIVKH
3.0
—
ns
2, 4
Input hold from Clock
tPCIXKH
0
—
ns
2, 4
Parameter
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN
clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to
the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
Figure 33 provides the AC test load for PCI.
Output
Z0 = 50 Ω
RL = 50 Ω
NVDD/2
Figure 33. PCI AC Test Load
Figure 34 shows the PCI input AC timing conditions.
CLK
tPCIVKH
tPCIXKH
Input
Figure 34. PCI Input AC Timing Measurement Conditions
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Timers
Figure 35 shows the PCI output AC timing conditions.
CLK
tPCKHOV
tPCKHOX
Output Delay
tPCKHOZ
High-Impedance
Output
Figure 35. PCI Output AC Timing Measurement Condition
14 Timers
This section describes the DC and AC electrical specifications for the timers.
14.1
Timers DC Electrical Characteristics
Table 51 provides the DC electrical characteristics for the MPC8313E timers pins, including TIN, TOUT,
TGATE, and RTC_CLK.
Table 51. Timers DC Electrical Characteristics
Characteristic
14.2
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.1
NVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ NVDD
—
±5
μA
Timers AC Timing Specifications
Table 52 provides the Timers input and output AC timing specifications.
Table 52. Timers Input AC Timing Specifications 1
Characteristic
Timers inputs—minimum pulse width
Symbol 2
Min
Unit
tTIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any
external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
49
GPIO
Figure 36 provides the AC test load for the Timers.
Z0 = 50 Ω
Output
NVDD/2
RL = 50 Ω
Figure 36. Timers AC Test Load
15 GPIO
This section describes the DC and AC electrical specifications for the GPIO.
15.1
GPIO DC Electrical Characteristics
Table 53 provides the DC electrical characteristics for the GPIO when the GPIO pins are operating from
a 3.3-V supply.
Table 53. GPIO (When Operating at 3.3V ) DC Electrical Characteristics 1
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.0
NVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ NVDD
—
±5
μA
1
This specification only applies to GPIO pins that are operating from a 3.3-V supply. See Table 60 for the power
supply listed for the individual GPIO signal.
Table 54 provides the DC electrical characteristics for the GPIO when the GPIO pins are operating from
a 2.5-V supply.
Table 54. GPIO (When Operating at 2.5 V) DC Electrical Characteristics 1
Parameters
Symbol
Conditions
Min
Max
Unit
Supply voltage 2.5 V
NVDD
—
2.37
2.63
V
Output high voltage
VOH
IOH = –1.0 mA
NVDD = Min
2.00
NVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
NVDD = Min
VSS – 0.3
0.40
V
Input high voltage
VIH
—
NVDD = Min
1.7
NVDD + 0.3
V
Input low voltage
VIL
—
NVDD = Min
–0.3
0.70
V
Input high current
IIH
VIN = NVDD
—
10
μA
Input low current
IIL
VIN = VSS
–15
—
μA
1
This specification only applies to GPIO pins that are operating from a 2.5-V supply. See Table 60 for the power supply listed
for the individual GPIO signal.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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IPIC
15.2
GPIO AC Timing Specifications
Table 55 provides the GPIO input and output AC timing specifications.
Table 55. GPIO Input AC Timing Specifications 1
Characteristic
Symbol 2
Min
Unit
tPIWID
20
ns
GPIO inputs—minimum pulse width
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of
SYS_CLKIN. Timings are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized
before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to
ensure proper operation.
Figure 37 provides the AC test load for the GPIO.
Output
Z0 = 50 Ω
RL = 50 Ω
NVDD/2
Figure 37. GPIO AC Test Load
16 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins.
16.1
IPIC DC Electrical Characteristics
Table 56 provides the DC electrical characteristics for the external interrupt pins.
Table 56. IPIC DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.1
NVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
—
—
±5
μA
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
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51
SPI
16.2
IPIC AC Timing Specifications
Table 57 provides the IPIC input and output AC timing specifications.
Table 57. IPIC Input AC Timing Specifications 1
Characteristic
IPIC inputs—minimum pulse width
Symbol 2
Min
Unit
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge
of SYS_CLK_IN. Timings are measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized
before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns
to ensure proper operation when working in edge triggered mode.
17 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8313E
17.1 SPI DC Electrical Characteristics
Table 58 provides the DC electrical characteristics for the MPC8313E SPI.
Table 58. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.1
NVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤ VIN ≤ NVDD
—
±5
μA
17.2 SPI AC Timing Specifications
Table 59 and provide the SPI input and output AC timing specifications.
Table 59. SPI AC Timing Specifications 1
Symbol 2
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
tNIKHOV
0.5
6
ns
SPI outputs—Slave mode (external clock) delay
tNEKHOV
2
8
ns
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
6
—
ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0
—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4
—
ns
Characteristic
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SPI
Table 59. SPI AC Timing Specifications 1
Characteristic
SPI inputs—Slave mode (external clock) input hold time
Symbol 2
Min
Max
Unit
tNEIXKH
2
—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of SYS_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
Figure 38 provides the AC test load for the SPI.
Output
Z0 = 50 Ω
RL = 50 Ω
NVDD/2
Figure 38. SPI AC Test Load
Figure 39 through Figure 40 represent the AC timing from Table 59. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 39 shows the SPI timing in Slave mode (external clock).
SPICLK (input)
Input Signals:
SPIMOSI
(See Note)
tNEIVKH
Output Signals:
SPIMISO
(See Note)
tNEIXKH
tNEKHOV
Note: The clock edge is selectable on SPI.
Figure 39. SPI AC Timing in Slave Mode (External Clock) Diagram
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Package and Pin Listings
Figure 40 shows the SPI timing in Master mode (internal clock).
SPICLK (output)
Input Signals:
SPIMISO
(See Note)
tNIIVKH
Output Signals:
SPIMOSI
(See Note)
tNIIXKH
tNIKHOV
Note: The clock edge is selectable on SPI.
Figure 40. SPI AC Timing in Master Mode (Internal Clock) Diagram
18 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8313E is available in
a thermally enhanced plastic ball grid array (TEPBGAII), see Section 18.1, “Package Parameters for the
MPC8313E TEPBGAII,” and Section 18.2, “Mechanical Dimensions of the MPC8313E TEPBGAII,” for
information on the TEPBGAII.
18.1
Package Parameters for the MPC8313E TEPBGAII
The package parameters are as provided in the following list. The package type is 27 mm × 27 mm, 516
TEPBGAII.
Package outline
27 mm × 27 mm
Interconnects
516
Pitch
1.00 mm
Module height (typical)
2.25 mm
Solder Balls
95.5 Sn/0.5 Cu/4Ag (VR package)
Ball diameter (typical)
0.6 mm
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Package and Pin Listings
18.2
Mechanical Dimensions of the MPC8313E TEPBGAII
Figure 41 shows the mechanical dimensions and bottom surface nomenclature of the 516-TEPBGAII
package.
Figure 41. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8313E TEPBGAII
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
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Package and Pin Listings
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Package code 5368 is to account for PGE and the built–in heat spreader.
18.3
Pinout Listings
Table 60 provides the pin-out listing for the MPC8313E, TEPBGAII package.
Table 60. MPC8313E TEPBGAII Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
DDR Memory Controller Interface
MEMC_MDQ[0]
A8
IO
GVDD
—
MEMC_MDQ[1]
A9
IO
GVDD
—
MEMC_MDQ[2]
C10
IO
GVDD
—
MEMC_MDQ[3]
C9
IO
GVDD
—
MEMC_MDQ[4]
E9
IO
GVDD
—
MEMC_MDQ[5]
E11
IO
GVDD
—
MEMC_MDQ[6]
E10
IO
GVDD
—
MEMC_MDQ[7]
C8
IO
GVDD
—
MEMC_MDQ[8]
E8
IO
GVDD
—
MEMC_MDQ[9]
A6
IO
GVDD
—
MEMC_MDQ[10]
B6
IO
GVDD
—
MEMC_MDQ[11]
C6
IO
GVDD
—
MEMC_MDQ[12]
C7
IO
GVDD
—
MEMC_MDQ[13]
D7
IO
GVDD
—
MEMC_MDQ[14]
D6
IO
GVDD
—
MEMC_MDQ[15]
A5
IO
GVDD
—
MEMC_MDQ[16]
A19
IO
GVDD
—
MEMC_MDQ[17]
D18
IO
GVDD
—
MEMC_MDQ[18]
A17
IO
GVDD
—
MEMC_MDQ[19]
E17
IO
GVDD
—
MEMC_MDQ[20]
E16
IO
GVDD
—
MEMC_MDQ[21]
C18
IO
GVDD
—
MEMC_MDQ[22]
D19
IO
GVDD
—
MEMC_MDQ[23]
C19
IO
GVDD
—
MEMC_MDQ[24]
E19
IO
GVDD
—
MEMC_MDQ[25]
A22
IO
GVDD
—
MEMC_MDQ[26]
C21
IO
GVDD
—
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Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
MEMC_MDQ[27]
C20
IO
GVDD
—
MEMC_MDQ[28]
A21
IO
GVDD
—
MEMC_MDQ[29]
A20
IO
GVDD
—
MEMC_MDQ[30]
C22
IO
GVDD
—
MEMC_MDQ[31]
B22
IO
GVDD
—
MEMC_MDM0
B7
O
GVDD
—
MEMC_MDM1
E6
O
GVDD
—
MEMC_MDM2
E18
O
GVDD
—
MEMC_MDM3
E20
O
GVDD
—
MEMC_MDQS[0]
A7
IO
GVDD
—
MEMC_MDQS[1]
E7
IO
GVDD
—
MEMC_MDQS[2]
B19
IO
GVDD
—
MEMC_MDQS[3]
A23
IO
GVDD
—
MEMC_MBA[0]
D15
O
GVDD
—
MEMC_MBA[1]
A18
O
GVDD
—
MEMC_MBA[2]
A15
O
GVDD
—
MEMC_MA0
E12
O
GVDD
—
MEMC_MA1
D11
O
GVDD
—
MEMC_MA2
B11
O
GVDD
—
MEMC_MA3
A11
O
GVDD
—
MEMC_MA4
A12
O
GVDD
—
MEMC_MA5
E13
O
GVDD
—
MEMC_MA6
C12
O
GVDD
—
MEMC_MA7
E14
O
GVDD
—
MEMC_MA8
B15
O
GVDD
—
MEMC_MA9
C17
O
GVDD
—
MEMC_MA10
C13
O
GVDD
—
MEMC_MA11
A16
O
GVDD
—
MEMC_MA12
C15
O
GVDD
—
MEMC_MA13
C16
O
GVDD
—
MEMC_MA14
E15
O
GVDD
—
MEMC_MWE
B18
O
GVDD
—
MEMC_MRAS
C11
O
GVDD
—
MEMC_MCAS
B10
O
GVDD
—
Signal
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
MEMC_MCS[0]
D10
O
GVDD
—
MEMC_MCS[1]
A10
O
GVDD
—
MEMC_MCKE
B14
O
GVDD
3
MEMC_MCK
A13
O
GVDD
—
MEMC_MCK
A14
O
GVDD
—
MEMC_MODT[0]
B23
O
GVDD
—
MEMC_MODT[1]
C23
O
GVDD
—
Signal
Local Bus Controller Interface
LAD0
K25
IO
LVDD
—
LAD1
K24
IO
LVDD
—
LAD2
K23
IO
LVDD
—
LAD3
K22
IO
LVDD
—
LAD4
J25
IO
LVDD
—
LAD5
J24
IO
LVDD
—
LAD6
J23
IO
LVDD
—
LAD7
J22
IO
LVDD
—
LAD8
H24
IO
LVDD
—
LAD9
F26
IO
LVDD
—
LAD10
G24
IO
LVDD
—
LAD11
F25
IO
LVDD
—
LAD12
E25
IO
LVDD
—
LAD13
F24
IO
LVDD
—
LAD14
G22
IO
LVDD
—
LAD15
F23
IO
LVDD
—
LA16
AC25
O
LVDD
—
LA17
AC26
O
LVDD
—
LA18
AB22
O
LVDD
—
LA19
AB23
O
LVDD
—
LA20
AB24
O
LVDD
—
LA21
AB25
O
LVDD
—
LA22
AB26
O
LVDD
—
LA23
E22
O
LVDD
—
LA24
E23
O
LVDD
—
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Freescale Semiconductor
Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
LA25
D22
O
LVDD
—
LCS[0]
D23
O
LVDD
—
LCS[1]
J26
O
LVDD
—
LCS[2]
F22
O
LVDD
—
LCS[3]
D26
O
LVDD
—
LWE[0]
E24
O
LVDD
—
LWE[1]
H26
O
LVDD
—
LBCTL
L22
O
LVDD
—
LALE/M1LALE/M2LALE
E26
O
LVDD
—
LGPL0
AA23
O
LVDD
—
LGPL1
AA24
O
LVDD
—
LGPL2
AA25
O
LVDD
—
LGPL3
AA26
O
LVDD
—
LGPL4
Y22
IO
LVDD
—
LGPL5
E21
O
LVDD
—
LCLK0
H22
O
LVDD
—
LCLK1
G26
O
LVDD
—
LA0/GPIO[0]
AC24
IO
LVDD
—
LA1/GPIO[1]
Y24
IO
LVDD
—
LA2/GPIO[2]
Y26
IO
LVDD
—
LA3/GPIO[3]
W22
IO
LVDD
—
LA4/GPIO[4]
W24
IO
LVDD
—
LA5/GPIO[5]
W26
IO
LVDD
—
LA6/GPIO[6]
V22
IO
LVDD
—
LA7/GPIO[7]/TSEC_TMR_TRIG2
V23
IO
LVDD
8
LA8/GPIO[13]/TSEC_TMR_ALARM1
V24
IO
LVDD
8
LA9/GPIO[14]/TSEC_TMR_PP3
V25
IO
LVDD
8
LA10/TSEC_TMR_CLK
V26
O
LVDD
8
LA11/TSEC_TMR_GCLK
U22
O
LVDD
8
LA12/TSEC_TMR_PP1
AD24
O
LVDD
8
LA13/TSEC_TMR_PP2
L25
O
LVDD
8
LA14/TSEC_TMR_TRIG1
L24
O
LVDD
8
LA15/TSEC_TMR_ALARM2
K26
O
LVDD
8
Signal
DUART
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
UART_SOUT1/MSRCID0
N2
O
NVDD
—
UART_SIN1/MSRCID1
M5
IO
NVDD
—
UART_CTS[1]/GPIO[8]/MSRCID2
M1
IO
NVDD
—
UART_RTS[1]/GPIO[9]/MSRCID3
K1
IO
NVDD
—
UART_SOUT2/MSRCID4/TSEC_TMR_CLK
M3
O
NVDD
8
UART_SIN2/MDVAL/TSEC_TMR_GCLK
L1
IO
NVDD
8
UART_CTS[2]/TSEC_TMR_PP1
L5
IO
NVDD
8
UART_RTS[2]/TSEC_TMR_PP2
L3
IO
NVDD
8
IIC1_SDA/CKSTOP_OUT/TSEC_TMR_TRIG1
J4
IO
NVDD
2, 8
IIC1_SCL/CKSTOP_IN/TSEC_TMR_ALARM2
J2
IO
NVDD
2, 8
IIC2_SDA/PMC_PWR_OK/GPIO[10]
J3
IO
NVDD
2
IIC2_SCL/GPIO[11]
H5
IO
NVDD
2
MCP_OUT
G5
O
NVDD
2
IRQ[0]/MCP_IN
K5
I
NVDD
—
IRQ[1]
K4
I
NVDD
—
IRQ[2]
K2
I
NVDD
—
IRQ[3] /CKSTOP_OUT
K3
IO
NVDD
—
IRQ[4]/ CKSTOP_IN/GPIO[12]
J1
IO
NVDD
—
CFG_CLKIN_DIV
D5
I
NVDD
—
EXT_PWR_CTRL
J5
O
NVDD
—
R24
I
NVDD
—
TCK
E1
I
NVDD
—
TDI
E2
I
NVDD
4
TDO
E3
O
NVDD
3
TMS
E4
I
NVDD
4
TRST
E5
I
NVDD
4
F4
I
NVDD
6
Signal
I2C interface
Interrupts
Configuration
CFG_LBIU_MUX_EN
JTAG
TEST
TEST_MODE
DEBUG
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Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
F5
O
NVDD
—
HRESET
F2
IO
NVDD
1
PORESET
F3
I
NVDD
—
SRESET
F1
I
NVDD
—
SYS_CR_CLK_IN
U26
I
NVDD
—
SYS_CR_CLK_OUT
U25
O
NVDD
—
SYS_CLK_IN
U23
I
NVDD
—
USB_CR_CLK_IN
T26
I
NVDD
—
USB_CR_CLK_OUT
R26
O
NVDD
—
USB_CLK_IN
T22
I
NVDD
—
PCI_SYNC_OUT
U24
O
NVDD
3
RTC_PIT_CLOCK
R22
I
NVDD
—
PCI_SYNC_IN
T24
I
NVDD
—
THERM0
N1
I
NVDD
7
THERM1
N3
I
NVDD
7
PCI_INTA
AF7
O
NVDD
—
PCI_RESET_OUT
AB11
O
NVDD
—
PCI_AD[0]
AB20
IO
NVDD
—
PCI_AD[1]
AF23
IO
NVDD
—
PCI_AD[2]
AF22
IO
NVDD
—
PCI_AD[3]
AB19
IO
NVDD
—
PCI_AD[4]
AE22
IO
NVDD
—
PCI_AD[5]
AF21
IO
NVDD
—
PCI_AD[6]
AD19
IO
NVDD
—
PCI_AD[7]
AD20
IO
NVDD
—
PCI_AD[8]
AC18
IO
NVDD
—
PCI_AD[9]
AD18
IO
NVDD
—
PCI_AD[10]
AB18
IO
NVDD
—
PCI_AD[11]
AE19
IO
NVDD
—
Signal
QUIESCE
System Control
Clocks
MISC
PCI
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
PCI_AD[12]
AB17
IO
NVDD
—
PCI_AD[13]
AE18
IO
NVDD
—
PCI_AD[14]
AD17
IO
NVDD
—
PCI_AD[15]
AF19
IO
NVDD
—
PCI_AD[16]
AB14
IO
NVDD
—
PCI_AD[17]
AF15
IO
NVDD
—
PCI_AD[18]
AD14
IO
NVDD
—
PCI_AD[19]
AE14
IO
NVDD
—
PCI_AD[20]
AF12
IO
NVDD
—
PCI_AD[21]
AE11
IO
NVDD
—
PCI_AD[22]
AD12
IO
NVDD
—
PCI_AD[23]
AB13
IO
NVDD
—
PCI_AD[24]
AF9
IO
NVDD
—
PCI_AD[25]
AD11
IO
NVDD
—
PCI_AD[26]
AE10
IO
NVDD
—
PCI_AD[27]
AB12
IO
NVDD
—
PCI_AD[28]
AD10
IO
NVDD
—
PCI_AD[29]
AC10
IO
NVDD
—
PCI_AD[30]
AF10
IO
NVDD
—
PCI_AD[31]
AF8
IO
NVDD
—
PCI_C/BE[0]
AC19
IO
NVDD
—
PCI_C/BE[1]
AB15
IO
NVDD
—
PCI_C/BE[2]
AF14
IO
NVDD
—
PCI_C/BE[3]
AF11
IO
NVDD
—
PCI_PAR
AD16
IO
NVDD
—
PCI_FRAME
AF16
IO
NVDD
5
PCI_TRDY
AD13
IO
NVDD
5
PCI_IRDY
AC15
IO
NVDD
5
PCI_STOP
AF13
IO
NVDD
5
PCI_DEVSEL
AC14
IO
NVDD
5
PCI_IDSEL
AF20
I
NVDD
—
PCI_SERR
AE15
IO
NVDD
5
PCI_PERR
AD15
IO
NVDD
5
PCI_REQ0
AB10
IO
NVDD
—
Signal
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
62
Freescale Semiconductor
Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
PCI_REQ1/CPCI_HS_ES
AD9
I
NVDD
—
PCI_REQ2
AD8
I
NVDD
—
PCI_GNT0
AC11
IO
NVDD
—
PCI_GNT1/CPCI_HS_LED
AE7
O
NVDD
—
PCI_GNT2/CPCI_HS_ENUM
AD7
O
NVDD
—
M66EN
AD21
I
NVDD
—
PCI_CLK0
AF17
O
NVDD
—
PCI_CLK1
AB16
O
NVDD
—
PCI_CLK2
AF18
O
NVDD
—
PCI_PME
AD22
IO
NVDD
—
Signal
ETSEC1/_USBULPI
TSEC1_COL/USBDR_TXDRXD0
AD2
IO
LVDDB
—
TSEC1_CRS/USBDR_TXDRXD1
AC3
IO
LVDDB
—
TSEC1_GTX_CLK/USBDR_TXDRXD2
AF3
IO
LVDDB
3
TSEC1_RX_CLK/USBDR_TXDRXD3
AE3
IO
LVDDB
—
TSCE1_RX_DV/USBDR_TXDRXD4
AD3
IO
LVDDB
—
TSEC1_RXD[3]/USBDR_TXDRXD5
AC6
IO
LVDDB
—
TSEC1_RXD[2]/USBDR_TXDRXD6
AF4
IO
LVDDB
—
TSEC1_RXD[1]/USBDR_TXDRXD7
AB6
IO
LVDDB
—
TSEC1_RXD[0]/USBDR_NXT/TSEC_1588_TRIG1
AB5
I
LVDDB
—
TSEC1_RX_ER/USBDR_DIR/TSEC_1588_TRIG2
AD4
I
LVDDB
—
TSEC1_TX_CLK/USBDR_CLK/TSEC_1588_CLK
AF5
I
LVDDB
—
TSEC1_TXD[3]/TSEC_1588_GCLK
AE6
O
LVDDB
—
TSEC1_TXD[2]/TSEC_1588_PP1
AC7
O
LVDDB
—
TSEC1_TXD[1]/TSEC_1588_PP2
AD6
O
LVDDB
—
TSEC1_TXD[0]/USBDR_STP/TSEC_1588_PP3
AD5
O
LVDDB
—
TSEC1_TX_EN/TSEC_1588_ALARM1
AB7
O
LVDDB
—
TSEC1_TX_ER/TSEC_1588_ALARM2
AB8
O
LVDDB
—
TSEC1_GTX_CLK125
AE1
I
LVDDB
—
TSEC1_MDC/LB_POR_CFG_BOOT_ECC_DIS
AF6
O
NVDD
—
TSEC1_MDIO
AB9
IO
NVDD
2
TSEC2_COL/GTM1_TIN4/GTM2_TIN3/GPIO[15]
AB4
IO
LVDDA
—
TSEC2_CRS/GTM1_TGATE4/GTM2_TGATE3/GPIO[16]
AB3
IO
LVDDA
—
ETSEC2
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
63
Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
TSEC2_GTX_CLK/GTM1_TOUT4/GTM2_TOUT3/GPIO[17]
AC1
IO
LVDDA
—
TSEC2_RX_CLK/GTM1_TIN2/GTM2_TIN1/GPIO[18]
AC2
IO
LVDDA
—
TSCE2_RX_DV/GTM1_TGATE2/GTM2_TGATE1/GPIO[19]
AA3
IO
LVDDA
—
TSEC2_RXD[3]/GPIO[20]
Y5
IO
LVDDA
—
TSEC2_RXD[2]/GPIO[21]
AA4
IO
LVDDA
—
TSEC2_RXD[1]/GPIO[22]
AB2
IO
LVDDA
—
TSEC2_RXD[0]/GPIO[23]
AA5
IO
LVDDA
—
TSEC2_RX_ER/GTM1_TOUT2/GTM2_TOUT1/GPIO[24]
AA2
IO
LVDDA
—
TSEC2_TX_CLK/GPIO[25]
AB1
IO
LVDDA
—
TSEC2_TXD[3]/CFG_RESET_SOURCE[0]
W3
IO
LVDDA
—
TSEC2_TXD[2]/CFG_RESET_SOURCE[1]
Y1
IO
LVDDA
—
TSEC2_TXD[1]/CFG_RESET_SOURCE[2]
W5
IO
LVDDA
—
TSEC2_TXD[0]/CFG_RESET_SOURCE[3]
Y3
IO
LVDDA
—
TSEC2_TX_EN/GPIO[26]
AA1
IO
LVDDA
—
TSEC2_TX_ER/GPIO[27]
W1
IO
LVDDA
—
—
SGMII PHY
TXA
U3
O
—
TXA
V3
O
—
RXA
U1
I
—
RXA
V1
I
—
TXB
P4
O
—
TXB
N4
O
—
RXB
R1
I
—
RXB
P1
I
—
SD_IMP_CAL_RX
V5
I
SD_REF_CLK
T5
I
—
SD_REF_CLK
T4
I
—
SD_PLL_TPD
T2
O
—
SD_IMP_CAL_TX
N5
I
SDAVDD
R5
IO
—
SD_PLL_TPA_ANA
R4
O
—
SDAVSS
R3
IO
—
200 Ω to
GND
100 Ω to
GND
—
—
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
64
Freescale Semiconductor
Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
USB PHY
USB_DP
P26
IO
—
USB_DM
N26
IO
—
USB_VBUS
P24
IO
—
USB_TPA
L26
IO
—
USB_RBIAS
M24
IO
—
USB_PLL_PWR3
M26
IO
—
USB_PLL_GND
N24
IO
—
USB_PLL_PWR1
N25
IO
—
USB_VSSA_BIAS
M25
IO
—
USB_VDDA_BIAS
M22
IO
—
USB_VSSA
N22
IO
—
USB_VDDA
P22
IO
—
USBDR_DRIVE_VBUS/GTM1_TIN1/GTM2_TIN2/LSRCID0
AD23
IO
NVDD
—
USBDR_PWRFAULT/GTM1_TGATE1/GTM2_TGATE2/LSR
CID1
AE23
IO
NVDD
—
USBDR_PCTL0/GTM1_TOUT1/LSRCID2
AC22
O
NVDD
—
USBDR_PCTL1/LBC_PM_REF_10/LSRCID3
AB21
O
NVDD
—
SPIMOSI/GTM1_TIN3/GTM2_TIN4/GPIO[28]
H1
IO
NVDD
—
SPIMISO/GTM1_TGATE3/GTM2_TGATE4/GPIO[29]/LDVAL
H3
IO
NVDD
—
SPICLK/GTM1_TOUT3/GPIO[30]
G1
IO
NVDD
—
SPISEL/GPIO[31]
G3
IO
NVDD
—
GTM/USB
SPI
Power and Ground Supplies
AVDD1
F14
Power for
e300 core
APLL (1.0 V)
—
—
AVDD2
P21
Power for
system APLL
(1.0 V)
—
—
GV DD
A2,A3,A4,A24,A25,B3,
B4,B5,B12,B13,B20,
B21,B24,B25,B26,D1,
D2,D8,D9,D16,D17
Power for
DDR1 and
DDR2 DRAM
I/O voltage
(1.8 V/2.5 V)
—
—
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
65
Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Power
Supply
Notes
Power for
local bus
(3.3 V)
—
—
W2,Y2
Power for
eTSEC2
(2.5 V, 3.3 V)
—
—
LVDDB
AC8,AC9,AE4,AE5
Power for
eTSEC1
/USB DR
(2.5 V, 3.3 V)
—
—
MV REF
C14,D14
Reference
voltage signal
for DDR
—
—
NVDD
Standard I/O
G4,H4,L2,M2,AC16,
voltage
AC17,AD25,AD26,AE12,
(3.3 V)
AE13,AE20,AE21,AE24,
AE25,AE26,AF24,
AF25
—
—
VDD
K11,K12,K13,K14,K15,K
16,L10,L17,M10,M17,
N10,N17,U12,U13, ,
Power for
core (1.0 V)
—
—
VDDC
F6,F10,F19,K6,K10,K17, Internal core
K21,P6,P10,P17,R10, logic constant
R17,T10,T17,U10,U11, power (1.0 V)
U14,U15,U16,U17,W6,
W21,AA6,AA10,AA14,
AA19
—
—
Signal
Package Pin Number
Pin Type
LVDD
D24,D25,G23,H23,R23,
T23,W25,Y25,
AA22,AC23
LVDDA
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Package and Pin Listings
Table 60. MPC8313E TEPBGAII Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
B1,B2,B8,B9,B16,B17,
C1,C2,C3,C4,C5,C24,
C25,C26,D3,D4,D12,
D13,D20,D21,F8,F11,
F13,F16,F17,F21,G2,
G25,H2,H6,H21,H25,
L4,L6,L11,L12,L13,L14,
L15,L16,L21,L23,M4,
M11,M12,M13,M14,
M15,M16,M23,
N6,N11,N12,N13,
N14,N15,N16,N21,N23,
P11,P12,P13,P14,P15,
P16,P23,P25,R11,R12,
R13,R14,R15,R16,R25,
T6,T11,T12,T13,T14,
T15,T16,T21,T25,U5,
U6,U21,W4,W23,Y4,
Y23,AA8,AA11,AA13,
AA16,AA17,AA21,AC4,
AC5,AC12,AC13,AC20,
AC21,AD1,AE2,AE8,
AE9,AE16,AE17,AF2,
—
—
—
XCOREVDD
T1, U2, V2
Core power
for SerDes
transceivers
(1.0 V)
—
—
XCOREVSS
P2, R2, T3
—
—
—
XPADVDD
P5, U4
Pad power
for SerDes
transceivers
(1.0 V)
—
—
XPADVSS
P3, V4
—
—
—
Signal
VSS
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to NVDD
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to NVDD.
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. This pin must always be tied to VSS.
7. Internal thermally sensitive resistor, resistor value varies linearly with temperature. Useful for determining the junction
temperature.
8. CFG_LBIU_MUX_EN must be asserted during power-on reset to select timer functionality.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
67
Clocking
19 Clocking
Figure 42 shows the internal distribution of clocks within the MPC8313E.
MPC8313E
e300c3 core
core_clk
Core PLL
USB Mac
xM
1
USB PHY
PLL
mux
csb_clk
to DDR
memory
controller
DDR
Clock
Divider
/2
USB_CLK_IN
USB_CR_CLK_IN
MEMC_MCK
ddr_clk
x
Crystal
USB_CR_CLK_OUT
DDR
Memory
Device
MEMC_MCK
/1,/2
L2
System
PLL
Clock
Unit
lbc_clk
/n
To local bus
LCLK[0:1]
LBC
Clock
Divider
csb_clk to rest
of the device
CFG_CLKIN
_DIV
Local Bus
Memory
Device
PCI_CLK/
PCI_SYNC_IN
SYS_CLK_IN
SYS_CR_CLK_IN
1
0
Crystal
PCI_SYNC_OUT
PCI Clock
Divider (÷2)
SYS_CR_CLK_OUT
GTX_CLK125
125-MHz source
3
eTSEC
Protocol
Converter
RTC
Sys Ref
1
2
PCI_CLK_OUT[0:2]
RTC_CLK (32 kHz)
Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL].
Multiplication factor L = 2, 3, 4, 5 and 6. Value is decided by RCWLR[SPMF].
Figure 42. MPC8313E Clock Subsystem
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
68
Freescale Semiconductor
Clocking
The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,
depending on whether the device is configured in PCI host or PCI agent mode. When the device is
configured as a PCI host device, SYS_CLK_IN is its primary input clock. SYS_CLK_IN feeds the PCI
clock divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The
CFG_CLKIN_DIV configuration input selects whether SYS_CLK_IN or SYS_CLK_IN/2 is driven out
on the PCI_SYNC_OUT signal. The OCCR[PCICOEn] parameters select whether the PCI_SYNC_OUT
is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the SYS_CLK_IN signal should be tied to VSS.
As shown in Figure 42, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbc_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV) is the SYS_CLK_IN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the MPC8313E PowerQUICC II Pro Integrated Host Processor Reference
Manual for more information on the clock subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWL[DDRCM])
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbc_clk frequency is determined by the following equation:
lbc_clk = csb_clk × (1 + RCWL[LBCM])
Note that lbc_clk is not the external local bus frequency; lbc_clk passes through the a LBC clock divider
to create the external local bus clock outputs (LCLK[0:1]). The LBC clock divider ratio is controlled by
LCCR[CLKDIV].
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset. Table 61 specifies which units have a configurable clock
frequency.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
69
Clocking
Table 61. Configurable Clock Units
Default
Frequency
Options
TSEC1
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
TSEC2
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Security Core, I2C, SAP, TPR
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
USB DR
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
PCI and DMA complex
csb_clk
Off, csb_clk
Unit
Table 62 provides the operating frequencies for the MPC8313E TEPBGA II under recommended
operating conditions (see Table 2).
Table 62. Operating Frequencies for TEPBGA I I
Characteristic1
Max Operating Frequency
Unit
e300 core frequency (core_clk)
333
MHz
Coherent system bus frequency (csb_clk)
167
MHz
DDR1/2 memory bus frequency (MCK)2
167
MHz
Local bus frequency (LCLKn)3
66
MHz
PCI input frequency (SYS_CLK_IN or PCI_CLK)
66
MHz
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the
resulting csb_clk, MCK, LCLK[0:1], and core_clk frequencies do not exceed their respective maximum or
minimum operating frequencies. The value of SCCR[ENCCM] and SCCR[USBDRCM] must be
programmed such that the maximum internal operating frequency of the Security core and USB modules
do not exceed their respective value listed in this table.
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on LCCR[CLKDIV]) which
is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBCM]).
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
70
Freescale Semiconductor
Clocking
19.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 63 shows the multiplication factor
encodings for the system PLL.
Table 63. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication
Factor
0000
Reserved
0001
Reserved
0010
×2
0011
×3
0100
×4
0101
×5
0110
×6
0111–1111
Reserved
As described in Section 19, “Clocking,” The LBCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (SYS_CLK_IN or PCI_SYNC_IN) and the internal coherent system bus clock
(csb_clk). Table 64 shows the expected frequency values for the CSB frequency for select csb_clk to
SYS_CLK_IN/PCI_SYNC_IN ratios.
Table 64. CSB Frequency Options
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV at reset 1
SPMF
csb_clk :Input Clock Ratio
2
24
25
33.33
66.67
csb_clk Frequency (MHz)
High
0010
2:1
High
0011
3:1
High
0100
4:1
High
0101
5:1
High
0110
6:1
Low
0010
2:1
Low
0011
3:1
Low
0100
4:1
133
100
100
133
120
125
167
144
150
133
100
100
133
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
71
Clocking
Table 64. CSB Frequency Options (continued)
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV at reset 1
SPMF
csb_clk :Input Clock Ratio
2
24
25
33.33
66.67
csb_clk Frequency (MHz)
1
2
Low
0101
5:1
120
125
Low
0110
6:1
144
150
167
CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT.
SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
19.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 65 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 65 should be considered as reserved.
NOTE
Core VCO frequency = Core frequency × VCO divider. The VCO divider,
which is determined by RCWLR[COREPLL], must be set properly so that
the core VCO frequency is in the range of 400–800 MHz.
Table 65. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio 1
VCO divider (vcod) 2
0–1
2–5
6
nn
0000
0
PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
11
nnnn
n
n/a
n/a
00
0001
0
1:1
2
01
0001
0
1:1
4
10
0001
0
1:1
8
00
0001
1
1.5:1
2
01
0001
1
1.5:1
4
10
0001
1
1.5:1
8
00
0010
0
2:1
2
01
0010
0
2:1
4
10
0010
0
2:1
8
00
0010
1
2.5:1
2
01
0010
1
2.5:1
4
10
0010
1
2.5:1
8
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
72
Freescale Semiconductor
Thermal
Table 65. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk : csb_clk Ratio 1
VCO divider (vcod) 2
0–1
2–5
6
00
0011
0
3:1
2
01
0011
0
3:1
4
10
0011
0
3:1
8
1
For core_clk:csb_clk ratios of 2.5:1 and 3:1, the core_clk must not exceed its maximum operating frequency of
333 MHz.
2
Core VCO frequency = Core frequency × VCO divider. Note that VCO divider has to be set properly so that the
core VCO frequency is in the range of 400–800 MHz.
19.3
Example Clock Frequency Combinations
Table 66 shows several possible frequency combinations that can be selected based on the indicated input
reference frequencies, with RCWLR[LBCM] = 0 and RCWLR[DDRCM] =1, such that the LBC operates
with a frequency equal to the frequency of csb_clk and the DDR controller operates at twice the frequency
of csb_clk.
Table 66. System Clock Frequencies
LBC(lbc_clk)
SYS_
DDR
CSB
CLK_IN/ SPMF 1 vcod 2 vco 3
(csb_clk) 4 (ddr_clk)
PCI_CLK
1
2
3
4
5
6
e300 Core(core_clk)
/2
/4
/8
USB
ref 5
×1
× 1.5
×2
× 2.5
×3
—
37.5
18.8
Note 6
150.0
225
300
375
—
62.5 31.25 15.6
Note 6
125.0
188
250
313
375
41.63 20.8
Note 6
166.5
250
333
—
—
25.0
6
2
600.0
150.0
300.0
25.0
5
2
500.0
125.0
250.0
33.3
5
2
666.0
166.5
333.0
—
33.3
4
2
532.8
133.2
266.4
66.6
33.3
16.7
Note 6
133.2
200
266
333
400
48.0
3
2
576.0
144.0
288.0
—
36
18.0
48.0
144.0
216
288
360
—
66.7
2
2
533.4
133.3
266.7
Note 6
133.3
200
267
333
400
66.7 33.34 16.7
System PLL multiplication factor
System PLL VCO divider
When considering operating frequencies, the valid core VCO operating range of 400–800 MHz must not be violated.
Due to erratum eTSEC40, csb_clk frequencies of less than 133 MHz do not support Gigabit Ethernet data rates. The core
frequency must be 333 MHz for Gigabit Ethernet operation. This erratum will be fixed in revision 2 silicon.
Frequency of USB PLL input reference.
USB reference clock must be supplied from a separate source as it must be 24 or 48 MHz, the USB reference must be
supplied from a separate external source using USB_CLK_IN.
20 Thermal
This section describes the thermal specifications of the MPC8313E.
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Thermal
20.1
Thermal Characteristics
Table 67 provides the package thermal characteristics for the 516 27 × 27 mm TEPBGAII.
Table 67. Package Thermal Characteristics for TEPBGAII
Characteristic
Board type
Symbol
TEPBGAII
Unit
Notes
Junction to Ambient Natural Convection
Single layer board (1s)
RθJA
25
°C/W
1,2
Junction to Ambient Natural Convection
Four layer board (2s2p)
RθJA
18
°C/W
1,2,3
Junction to Ambient (@200 ft/min)
Single layer board (1s)
RθJMA
20
°C/W
1,3
Junction to Ambient (@200 ft/min)
Four layer board (2s2p)
RθJMA
15
°C/W
1,3
Junction to Board
—
RθJB
10
°C/W
4
Junction to Case
—
RθJC
8
°C/W
5
Natural Convection
ΨJT
7
°C/W
6
Junction to Package Top
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
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Thermal
20.2
Thermal Management Information
For the following sections, PD = (VDD x IDD) + PI/O where PI/O is the power dissipation of the I/O drivers.
20.2.1
Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA × PD)
where:
TJ = junction temperature (°C)
TA = ambient temperature for the package (°C)
RθJA = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. As a general statement, the value obtained on a single layer board is
appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
Test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible.
20.2.2
Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package is approximately the same as the local air temperature near the device. Specifying
the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RθJB × PD)
where:
TJ = junction temperature (°C)
TB = board temperature at the package perimeter (°C)
RθJB = junction to board thermal resistance (°C/W) per JESD51–8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
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Thermal
20.2.3
Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the
Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
TJ = junction temperature (°C)
TT = thermocouple temperature on top of package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
20.2.4
Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink is required to provide the necessary thermal management of
the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case
thermal resistance and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction to ambient thermal resistance (°C/W)
RθJC = junction to case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to
change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been
simulated with a few commercially available heat sinks. The heat sink choice is determined by the
application environment (temperature, air flow, adjacent component power dissipation) and the physical
space available. Because there is not a standard application environment, a standard heat sink is not
required.
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Thermal
Table 68. Thermal Resistance for TEPBGAII with Heat Sink in Open Flow
Heat Sink Assuming Thermal Grease
Air Flow
Thermal Resistance
(°C/W)
Wakefield 53 x 53 x 2.5 mm Pin Fin
Natural Convection
13.0
0.5 m/s
10.6
1 m/s
9.7
2 m/s
9.2
4 m/s
8.9
Natural Convection
14.4
0.5 m/s
11.3
1 m/s
10.5
2 m/s
9.9
4 m/s
9.4
Natural Convection
16.5
0.5 m/s
13.5
1 m/s
12.1
2 m/s
10.9
4 m/s
10.0
Natural Convection
14.5
0.5 m/s
11.7
1 m/s
10.5
2 m/s
9.7
4 m/s
9.2
Aavid 35 x 31 x 23 mm Pin Fin
Aavid 30 x 30 x 9.4 mm Pin Fin
Aavid 43 x 41 x 16.5 mm Pin Fin
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More
detailed thermal models can be made available on request.
Heat sink Vendors include the following list:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
Alpha Novatech
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovatech.com
408-749-7601
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Thermal
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-thermal.com
818-842-7277
408-436-8770
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105
Internet: www.chipcoolers.com
800-522-6752
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
603-635-2800
Interface material vendors include the following:
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01801
Internet: www.chomerics.com
781-935-4850
Dow-Corning Corporation
Corporate Center
PO BOX 994
Midland, MI 48686-0994
Internet: www.dowcorning.com
800-248-2481
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
888-642-7674
The Bergquist Company
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
800-347-4572
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System Design Information
20.3
Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use
thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the
board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would
lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.
If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic
surfaces and its performance verified under the application requirements.
20.3.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction to case
thermal resistance.
TJ = TC + (RθJC x PD)
Where:
TJ = junction temperature (°C)
TC = case temperature of the package
RθJC = junction-to-case thermal resistance
PD = power dissipation
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8313E SYS_CLK_IN
21.1
System Clocking
The MPC8313E includes three PLLs.
1. The platform PLL (AVDD2) generates the platform clock from the externally supplied
SYS_CLK_IN input in PCI host mode or SYS_CLK_IN/PCI_SYNC_IN in PCI agent mode. The
frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio
configuration bits as described in Section 19.1, “System PLL Configuration.”
2. The e300 Core PLL (AVDD1) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 19.2, “Core PLL Configuration.”
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System Design Information
3. There is a PLL for the SerDes block.
21.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AVDD2, and SDAVDD respectively). The AVDD level should always be equivalent to VDD, and preferably
these voltages are derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 43, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
Figure 43 shows the PLL power supply filter circuits.
V DD
10 Ω
AVDD1 and AVDD2
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
Figure 43. PLL Power Supply Filter Circuit
The SDAVDD signal provides power for the analog portions of the SerDes PLL. To ensure stability of the
internal clock, the power supplied to the PLL is filtered using a circuit like the one shown in Figure 44.
For maximum effectiveness, the filter circuit should be placed as closely as possible to the SDAVDD ball
to ensure it filters out as much noise as possible. The ground connection should be near the SDAVDD ball.
The 0.003-µF capacitor is closest to the ball, followed by the two 2.2-µF capacitors, and finally the 1-Ω
resistor to the board supply plane. The capacitors are connected from traces from SDAVDD to the ground
plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be
kept short, wide, and direct.
1Ω
SDAVDD
XCOREVDD
1
2.2 µF
2.2
µF1
0.003 µF
SDAVSS
1. An 0805 sized capacitor is recommended for system initial bring-up.
Figure 44. SerDes PLL Power Supply Filter Circuit
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System Design Information
Note the following:
• SDAVDD should be a filtered version of XCOREVDD.
• Output signals on the SerDes interface are fed from the XPADVDD power plane. Input signals and
sensitive transceiver analog circuits are on the XCOREVDD supply.
• Power: XPADVDD consumes less than 300 mW; XCOREVDD + SDAVDD consumes less than
750 mW.
21.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8313E system, and the
MPC8313E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, LVDD, LVDDA,
and LVDDB pin of the device. These decoupling capacitors should receive their power from separate VDD,
NVDD, GVDD, LVDD, LVDDA, LVDDB and VSS power planes in the PCB, utilizing short traces to
minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern.
Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, NVDD, GVDD, LVDD, LVDDA, and LVDDB planes, to enable quick recharging of the
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor
for best values and types of bulk capacitors.
21.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (XCOREVDD and XPADVDD) to
ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling
scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
• First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
• Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (XCOREVDD
and XPADVDD) to the board ground plane on each side of the device. This should be done for all
SerDes supplies.
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System Design Information
•
21.5
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to NVDD, GVDD, LVDD, LVDDA or LVDDB as required.
Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain
unconnected.
Power and ground connections must be made to all external VDD, NVDD, GVDD, LVDD, LVDDA, LVDDB,
and VSS pins of the device.
21.6
Output Buffer DC Impedance
The MPC8313E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to NVDD
or VSS. Then, the value of each resistor is varied until the pad voltage is NVDD/2 (see Figure 45). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
NVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
NVDD
RN
SW2
Data
Pad
SW1
RP
VSS
Figure 45. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured
while driving logic 1 with an external precision differential termination resistor of value Rterm. The
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System Design Information
measured voltage is V2 = (1/(1/R1 + 1/R2)) × Isource. Solving for the output impedance gives Rsource =
Rterm × (V1/V2 – 1). The drive current is then Isource = V1/Rsource.
Table 69 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal NVDD, 105°C.
Table 69. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI Signals
(not including PCI
output clocks)
PCI Output Clocks
(including
PCI_SYNC_OUT)
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
42 Target
20 Target
Z0
Ω
RP
42 Target
25 Target
42 Target
20 Target
Z0
Ω
Differential
NA
NA
NA
NA
ZDIFF
Ω
Note: Nominal supply voltages. See Table 1, Tj = 105°C.
21.7
Configuration Pin Muxing
The MPC8313E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should
minimize the disruption of signal quality or speed for output pins thus configured.
21.8
Pull-Up Resistor Requirements
The MPC8313E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
including I2C pins, Ethernet Management MDIO pin and EPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 46. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions because most have asynchronous behavior and spurious assertion,
which give unpredictable results.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
21.9
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in
IEEE 1149.1, but is provided on all processors that implement the PowerPC architecture. The device
requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere
with normal chip operation. While it is possible to force the TAP controller to the reset state using only the
TCK and TMS signals, systems generally assert TRST during power-on reset. Because the JTAG interface
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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System Design Information
is also used for accessing the common on-chip processor (COP) function, simply tying TRST to
PORESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert TRST without causing
PORESET. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these
signals with logic.
The arrangement shown in Figure 46 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used,
TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is
asserted.
The COP header shown in Figure 46 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header).
There is no standardized way to number the COP header shown in Figure 46; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 46 is common to all known emulators.
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System Design Information
PORESET
PORESET
From Target
Board Sources
(if any)
SRESET
SRESET
HRESET
HRESET
13
11
10 kΩ
HRESET
NVDD
SRESET
NVDD
10 kΩ
NVDD
10 kΩ
NVDD
1
2
3
4
5
6
7
8
9
10
11
12
4
61
5
15
10 kΩ
TRST
VDD_SENSE
TRST
2 kΩ
NVDD
NC
CHKSTP_OUT
CHKSTP_OUT
10 kΩ
NVDD
14
KEY
13 No
pin
16
COP Connector
Physical Pin Out
NVDD
CHKSTP_IN
COP Header
15
10 kΩ
2
8
CHKSTP_IN
TMS
TMS
9
1
3
TDO
TDI
TDO
TDI
TCK
7
2
TCK
NC
10
NC
12
NC
16
Notes:
1. Some systems require power to be fed from the application board into the debugger repeater card
via the COP header. In this case the resistor value for VDD_SENSE should be around 20Ω.
2. Key location; pin 14 is not physically present on the COP header.
Figure 46. JTAG Interface Connection
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Document Revision History
22 Document Revision History
Table 70 provides a revision history for this hardware specification.
Table 70. Document Revision History
Rev.
Number
Date
1
3/2008
Substantive Change(s)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Replaced OVDD with NV DD everywhere
Added XCOREVDD and XPADVDD to Table 1
Moved VDD and VDDC to the top of the table before SerDes supplies in Table 2
In Table 2 split DDR row into two from total current requirement of 425 mA. One for DDR1 (131 mA)
and other for DDR2 (140 mA).
In Table 2 corrected current requirment numbers for NVDD from 27 mA to 74 mA, LV DD from 60 mA to
16 mA, LVDDA from 85 mA to 22 mA and LVDDB from 85 mA to 44 mA.
In Table 2 corrected Vdd and Vddc current requirements from 560 mA and 454 mA to 469 and 377
mA, respectively. Corrected Avdd1 and Avdd2 current requirements from 10 mA to 2–3 mA, and
XCOREVDD from 100 mA to 170 mA.
In Table 2, added row stating junction temperature range of 0 to 105°C. Added footnote 2 stating GPIO
pins may operate from 2.5-V supply as well when configured for different functionality.
In Section 2.1.2, “Power Supply Voltage Specification,” added a note describing the purpose of
Table 2.
In Section 3, “Power Characteristics,” added a note describing the purpose of Table 5.
Rewrote Section 2.2, “Power Sequencing,” and added Figure 2.
In Table 4, added “but do include core, USB PLL, and a portion of SerDes digital power...” to Note 1.
In Table 4 corrected “Typical power” to “Maximum power” in note 2 and added a note for Typical Power.
In Table 4 removed 266-MHz row as 266-MHz core parts are not offered.
In Table 5, moved Local bus typical power dissipation under LVdd.
Added Table 6 to show the low power mode power dissipation for D3warm mode.
In Table 8 corrected SYS_CLK_IN frequency range from 25–66 MHz to 24–66.67 MHz.
Added Section 8.3, “eTSEC IEEE 1588 AC Specifications”
In Table 39 changed minimum value of USB input hold tUSIXKH from 0 to 1ns
Added Table 40 and Table 41 showing USB clock in specifications
In Table 43, added rows for tLALEHOV, tLALETOT1, tLALETOT2, and tLALETOT3 parameters. Added
Figure 25.
In Table 47, removed row for rise time (tI2CR). Removed minimum value of tI2CF. Added note 5 stating
that the device does not follow the I2C-BUS Specifications version 2.1 regarding the tI2CF AC
parameter.
In Table 53, added a note stating: “This specification only applies to GPIO pins that are operating from
a 3.3-V supply. See Table 60 for the power supply listed for the individual GPIO signal.” [
Added Table 54 to show DC characteristics for GPIO pins supplied by a 2.5-V supply. Same as eTSEC
DC characteristics when operating at 2.5 V.
In Section 19, “Clocking,” corrected the sentence “When the device is configured as a PCI agent
device, PCI_SYNC_IN is the primary input clock.” to state “When the device is configured as a PCI
agent device, PCI_CLK is the primary input clock.”
Added “Value is decided by RCWLR[COREPLL]” to note 1 of Figure 42
Added paragraph and Figure 44 to Section 21.2, “PLL Power Supply Filtering.”
Added Section 21.4, “SerDes Block Power Supply Decoupling Recommendations
Removed the two figures on PCI undershoot/overshoot voltages and maximum AC waveforms from
Section 2.1.2, “Power Supply Voltage Specification,”
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
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Freescale Semiconductor
Document Revision History
Table 70. Document Revision History
1
3/2008
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
In Table 60, added LBC_PM_REF_10 & LSRCID3 as muxed with USBDR_PCTL1
In Table 60, added LSRCID2 as muxed with USBDR_PCTL0
In Table 60, added LSRCID1 as muxed with USBDR_PWRFAULT
In Table 60, added LSRCID0 as muxed with USBDR_DRIVE_VBUS
In Table 60, moved T1, U2,& V2 from VDD to XCOREVDD.
In Table 60, moved P2, R2, & T3 from V SS to XCOREVSS.
In Table 60, moved P5, & U4 from VDD to XPADVDD.
In Table 60, moved P3, & V4 from VSS to XPADVSS.
In Table 60, removed “Double with pad” for AVDD1 and AVDD2 and moved AVDD1 and AVDD2 to Power
and Ground Supplies section
In Table 60, added impedance control requirements for SD_IMP_CAL_TX (100 ohms to GND) and
SD_IMP_CAL_RX (200 ohms to GND).
In Table 60, updated muxing in pinout to show new options for selecting IEEE 1588 functionality.
Added footnote 8
In Table 60, updated muxing in pinout to show new LBC ECC boot enable control muxed with
eTSEC1_MDC
Added pin type information for power supplies.
Removed N1 and N3 from Vss section of Table 60. Added Therm0 and Therm1 (N1 and N3,
respectively). Added note 7 to state: “Internal thermally sensitive resistor, resistor value varies linearly
with temperature. Useful for determining the junction temperature.”
In Table 62 corrected maximum frequency of Local Bus Frequency from “33–66” to 66 MHz
In Table 62 corrected maximum frequency of PCI from “24–66” to to 66 MHz
Added “which is determined by RCWLR[COREPLL],” to the note in Section 19.2, “Core PLL
Configuration” about the vco divider.
Added “(vcod)” next to VCO divider column in Table 65. Added footnote stating that core_clk
frequency must not exceed its maximum, so 2.5:1 and 3:1 core_clk:csb_clk ratios are invalid for
certain csb_clk values.
In Table 66, notes were confusing. Added note 3 for vco column, note 4 for CSB (csb_clk) column,
note 5 for USB ref column, and note 6 to replace “Note 1”. Clarified note 4 to explain erratum
eTSEC40.
In Table 66, updated note 6 to specify USB reference clock frequencies limited to 24 and 48 for rev. 2
silicon.
Replaced Table 68 “Thermal Resistance for TEPBGAII with Heat Sink in Open Flow”.
Removed last row of Table 19.
Removed 200 MHz rows from Table 20 and Table 5.
Changed VIH minimum spec from 2.0 to 2.1 for clock, PIC, JTAG, SPI, and reset pins in Table 9,
Table 44, Table 51, Table 56, and Table 58.
Added Figure 3 showing the DDR input timing diagram.
• In Table 19, removed “/MDM" from the "MDQS-MDQ/MECC/MDM" text under the
Parameter column for the tCISKEW parameter. MDM is an output signal and should be
removed from the input AC timing spec table (tCISKEW).
0
6/2007
• Added “and power” to rows 2 and 3 in Table 10
• Added the sentence “Once both the power supplies...” and PORESET to Section 2.2, “Power
Sequencing,” and Figure 2.
• In Figure 20, corrected “USB0_CLK/USB1_CLK/DR_CLK” with “USBDR_CLK”
• In Table 39, clarified that AC specs are for ULPI only.
Initial release.
MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
87
Ordering Information
23 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 23.1, “Part Numbers Fully Addressed by This Document.”
23.1 Part Numbers Fully Addressed by This Document
Table 71 provides the Freescale part numbering nomenclature for the MPC8313E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
Table 71. Part Numbering Nomenclature
MPC
nnnn
e
t
pp
aa
a
x
Product
Code
Part
Identifier
Encryption
Acceleration
Temperature
Range 3
Package 1
e300 core
Frequency 2
DDR
Frequency
Revision
Level
MPC
8313
Blank = 0 to 105°C
C= –40 to 105°C
VR= PB free
TEPBGAII
AF = 333 MHz F = 333 MHz
Contact
local
Freescale
sales office
Blank = Not
included
E = included
Notes:
1. See Section 18, “Package and Pin Listings,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
3. Contact local Freescale office on availability of parts with C temperature range
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91
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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
The Power Architecture and Power.org word marks and the Power and Power.org logos
and related marks are trademarks and service marks licensed by Power.org. The
described product contains a PowerPC processor core. The PowerPC name is a
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Document Number: MPC8313EEC
Rev. 1
3/2008
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