FUJITSU SEMICONDUCTOR DATA SHEET DS06-20112-2E Semicustom CMOS Embedded array CE77 Series ■ DESCRIPTION The CE77 series 0.25 µm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed and low power consumption at the same time. CE77 series is available in 15 frames with the enhanced lineup of 470 K to 6980 K gates. ■ FEATURES • • • • • • • • • • • • • • • • • Technology : 0.25 µm silicon-gate CMOS, 3- to 4-layer wiring Supply voltage : +2.5 V ± 0.2 V (normal) to +1.5 V ± 0.1 V Junction temperature range : −40 °C to +125 °C Gate delay time : tpd = 33 ps (2.5 V, inverter cell High Speed type, F/O = 1, No load) Gate power consumption : 0.02 µW/MHz (1.5 V, F/O = 1, No load) High-load driving capability : IOL = 2 mA/4 mA/8 mA/12 mA mixable Output buffer cells with noise reduction circuits Inputs with on-chip input pull-up/pull-down resistors (25 kΩ typical) and bidirectional buffer cells Buffer cells dedicated to crystal oscillator Special interface (P-CML, LVDS, T-LVTTL, SSTL, PCI, USB, GTL+, and others including those under development) IP macros (CPU, PCI, USB, IrDA, PLL, DAC, ADC, and others including those under development) Capable of incorporating compiled cells (RAM/ROM/FIFO/Delay line, and others.) Configurable internal bus circuits Advanced hardware/software co-design environment Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time Hierarchical design environment for supporting large-scale circuits Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture (Continued) Copyright©2002-2007 FUJITSU LIMITED All rights reserved CE77 Series (Continued) • Support for memory (RAM/ROM) SCAN • Support for memory (RAM) BIST • Support for boundary SCAN • Support for path delay test • A variety of package options (SQFP, HQFP, PBGA, LQFP, FBGA under development) ■ MACRO LIBRARY (Including macros being prepared) 1. Logic cells (about 700 types) • • • • • • • • • • • Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR SCAN Flip Flop BUS Driver EOR Others • • • • • • • • • • AND-OR Decoder Non-SCAN Flip Flop Inverter Buffer OR-AND Inverter OR Selector ENOR Boundary Scan Register 2. IP macros CPU SPARClite, ARM7 Interface macro USB, IrDA, etc. Multimedia processing macros JPEG, etc. Mixed signal macros ADC, DAC, Analog switch, etc. Compiled macros RAM, ROM, FIFO, Delay Line, PLL Analog PLL 3. Special I/O interface macros • P-CML • USB 2 CE77 Series ■ CHIP STRUCTURE The chip layout of the CE77 series consists of two major areas : chip peripheral area and basic cell area. The chip peripheral area contains the input/output buffer cells for interfacing with external devices and the associated bonding pads. The basic cell area contains some of input/output buffer cells, the unit cells and the compiled cells. • Chip configuration Bonding pad I/O buffer cell Basic cell area 3 CE77 Series ■ COMPILED CELLS Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CE77 series has the following types of compiled cells (Note that each macro is different in word/bit range depending on the column type) . 1. Clock synchronous single-port RAM (1 address, 1 RW) (High density type) / (Partial write type) Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Word range Bit range Unit (Ultra high density type) Column type Memory capacity 4 64 to 72 K 32 to 1 K 2 to 72 bit 4 2064 to 512 K 1032 to 4 K 2 to 128 bit 16 4160 to 512 K 2080 to 16 K 2 to 32 bit Word range Bit range Unit (Low power consumption type) Column type Memory capacity 4 128 to 72 K 32 to 1 K 4 to 72 bit 8 256 to 72 K 64 to 2 K 4 to 36 bit Memory capacity Word range Bit range Unit 128 to 144 K 32 to 2 K 4 to 72 bit (High speed type) Column type 8 2. Clock synchronous dual-port RAM (2 addresses, 1 RW/1 R) Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit 3. Clock synchronous register file (3 addresses, 1W/2R) Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 bit 4. Clock synchronous register file (4 addresses, 2W/2R) 4 Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 bit CE77 Series 5. Clock synchronous ROM (1 address, 1R) Column type Memory capacity Word range Bit range Unit 8 128 to 512 K 32 to 4 K 4 to 128 bit 16 128 to 512 K 64 to 8 K 2 to 64 bit 6. Clock synchronous delay line memory (2 addresses, 1W/1R) Column type Memory capacity Word range Bit range Unit 8 512 to 32 K 32 to 1 K 16 to 32 bit 16 512 to 32 K 64 to 2 K 8 to 16 bit 32 512 to 32 K 128 to 4 K 4 to 8 bit 7. Clock synchronous FIFO memory (2 addresses, 1W/1R) Column type Memory capacity Word range Bit range Unit 8 512 to 32 K 32 to 1 K 16 to 32 bit 16 512 to 32 K 64 to 2 K 8 to 16 bit 32 512 to 32 K 128 to 4 K 4 to 8 bit 5 CE77 Series ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power supply voltage*1 VDD Application VDD = 1.4 V to 2.7 V VDD = 2.7 V to 3.6 V Rating Min − 0.5 Max +3.0*4 +4.0*5 VDD + 0.5 ( ≤ 3.0 V) *4 Unit V Input voltage *1 VI ⎯ − 0.5 Output voltage*1 VO ⎯ − 0.5 Storage temperature Tst ⎯ −55 +125 °C Junction temperature Tj ⎯ −40 +125 °C Output current* VDD + 0.5 ( ≤ 4.0 V) *5 VDD + 0.5 ( ≤ 3.0 V) *4 VDD + 0.5 ( ≤ 4.0 V) *5 L type Powerless type (IOL = 2 mA) ⎯ ±13 M type Normal type (IOL = 4 mA) ⎯ ±13 H type Power type (IOL = 8 mA) ⎯ ±13 V type High power type (IOL = 12 mA) ⎯ ±26 Per VDD, GND pin ⎯ 60 2 IO Power-supply pin current *3 ID V V mA mA *1 : VSS = 0 V *2 : Maximum output current which can be supplied constantly. *3 : Maximum supply current which can be supplied constantly. *4 : Internal gate part in case of single power supply or dual power supply. *5 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 6 CE77 Series ■ RECOMMENDED OPERATING CONDITIONS 1. Single power supply • Conditions: VDD = 2.5 V±0.2 V, VSS = 0 V Parameter Power supply voltage “H” level input voltage “L” level input voltage Symbol VDD CMOS normal CMOS schmitt CMOS normal CMOS schmitt Junction temperature VIH Value Unit Min Typ Max 2.3 2.5 2.7 V ⎯ VDD + 0.3 V 1.7 VDD × 0.8 VIL −0.3 ⎯ Tj −40 ⎯ +0.7 VDD × 0.2 +125 V °C • Conditions: VDD = 1.8 V±0.15 V, VSS = 0 V Parameter Power supply voltage “H” level input voltage “L” level input voltage Symbol VDDI CMOS normal CMOS schmitt CMOS normal CMOS schmitt Junction temperature VIH Value Unit Min Typ Max 1.65 1.8 1.95 V ⎯ VDD + 0.3 V VDD × 0.65 VDD × 0.8 VIL −0.3 ⎯ Tj −40 ⎯ VDD × 0.35 VDD × 0.2 +125 V °C • Conditions: VDD = 1.5 V±0.1 V, VSS = 0 V Parameter Power supply voltage “H” level input voltage “L” level input voltage Junction temperature Symbol VDDI CMOS normal CMOS schmitt CMOS normal CMOS schmitt VIH Value Unit Min Typ Max 1.4 1.5 1.6 V ⎯ VDD + 0.3 V VDD × 0.7 VDD × 0.8 VIL −0.3 ⎯ Tj −40 ⎯ VDD × 0.3 VDD × 0.2 +125 V °C 7 CE77 Series 2. Dual power supply • Conditions: VDDE = 3.3 V±0.3 V/VDDI = 2.5 V±0.2 V, VDDI = 1.8 V±0.15 V, VDDI = 1.5 V±0.1 V, VSS = 0 V Value Parameter Symbol Min Typ Max Power supply voltage “H” level input voltage VDDE 3.0 3.3 3.6 VDDI 1.4 ⎯ 2.7 1.5 V CMOS normal VDDI × 0.7 1.8 V CMOS normal VDDI × 0.65 2.5 V CMOS normal 1.7 3.3 V CMOS normal 2.0 1.5 V CMOS schmitt 1.8 V CMOS schmitt V VDDI + 0.3 VDDE + 0.3 ⎯ VIH Unit V VDDI × 0.8 VDDI + 0.3 VDDE × 0.8 VDDE + 0.3 2.0 5.5 2.5 V CMOS schmitt 3.3 V CMOS schmitt 5 V Tolerant “L” level input voltage 1.5 V CMOS normal VDDI × 0.3 1.8 V CMOS normal VDDI × 0.35 2.5 V CMOS normal + 0.7 3.3 V CMOS normal + 0.8 1.5 V CMOS schmitt VIL −0.3 ⎯ V VDDI × 0.2 1.8 V CMOS schmitt 2.5 V CMOS schmitt VDDE × 0.2 3.3 V CMOS schmitt + 0.8 5 V Tolerant Junction temperature 8 Tj −40 ⎯ +125 °C CE77 Series • Conditions: VDDE = 2.5 V±0.2 V/VDDI = 1.8 V±0.15 V, VDDI = 1.5 V±0.1 V, VSS = 0 V Value Parameter Symbol Min Typ Power supply voltage “H” level input voltage VDDE 2.3 2.5 2.7 VDDI 1.4 ⎯ 1.95 1.5 V CMOS normal VDDI × 0.7 1.8 V CMOS normal VDDI × 0.65 2.5 V CMOS normal 1.5 V CMOS schmitt VIH 1.8 V CMOS schmitt 2.5 V CMOS schmitt “L” level input voltage 1.7 ⎯ VDDE + 0.3 VDDI × 0.8 VDDI + 0.3 VDDE × 0.8 VDDE + 0.3 1.5 V CMOS normal VDDI × 0.3 1.8 V CMOS normal VDDI × 0.35 2.5 V CMOS normal 1.5 V CMOS schmitt VIL −0.3 Unit V VDDI + 0.3 ⎯ 0.7 V V VDDI × 0.2 1.8 V CMOS schmitt VDDE × 0.2 2.5 V CMOS schmitt Junction temperature Max Tj −40 ⎯ +125 °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 9 CE77 Series ■ DC CHARACTERISTICS • Single power supply : VDD = 2.5 V (Standard) Parameter Power supply current*1 Symbol IDDS (VDD = 2.5 V ± 0.2 V, VSS = 0 V, Tj = −40 °C to +125 °C) Conditions Value Unit Min Typ Max T2 ⎯ ⎯ 0.1 T3, T4 ⎯ ⎯ 0.2 T5 to T7 ⎯ ⎯ 0.3 T8, T9 ⎯ ⎯ 0.4 TA ⎯ ⎯ 0.5 TB, TC ⎯ ⎯ 0.6 TD ⎯ ⎯ 0.8 TE ⎯ ⎯ 1.0 TF ⎯ ⎯ 1.1 TG ⎯ ⎯ 1.3 VDD − 0.2 ⎯ VDD V mA “H” level output voltage VOH IOH = −100 µA “L” level output voltage VOL IOL = 100 µA 0 ⎯ 0.2 V “H” level output voltage V-I characteristics ⎯ 2.5 V VDD = 2.5 V±0.2 V *2 ⎯ ⎯ ⎯ “L” level output current V-I characteristics ⎯ 2.5 V VDD = 2.5 V±0.2 V *2 ⎯ ⎯ ⎯ Input leakage current IL ⎯ ⎯ ±5 µA Pull-up/pull-down resistance RP 10 25 120 kΩ ⎯ Pull-up VIL = 0 V Pull-down VIH = VDD *1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS. 10 CE77 Series • Single power supply : VDD = 1.8 V Parameter Power supply current*1 Symbol IDDS (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Conditions Value Unit Min Typ Max T2 ⎯ ⎯ 0.1 T3, T4 ⎯ ⎯ 0.2 T5 to T7 ⎯ ⎯ 0.3 T8, T9 ⎯ ⎯ 0.4 TA ⎯ ⎯ 0.5 TB, TC ⎯ ⎯ 0.6 TD ⎯ ⎯ 0.8 TE ⎯ ⎯ 1.0 TF ⎯ ⎯ 1.1 TG ⎯ ⎯ 1.3 VDD − 0.2 ⎯ VDD V mA “H” level output voltage VOH IOH = −100 µA “L” level output voltage VOL IOL = 100 µA 0 ⎯ 0.2 V “H” level output voltage V-I characteristics ⎯ 1.8 V VDD = 1.8 V±0.15 V *2 ⎯ ⎯ ⎯ “L” level output current V-I characteristics ⎯ 1.8 V VDD = 1.8 V±0.15 V *2 ⎯ ⎯ ⎯ Input leakage current IL ⎯ ⎯ ±5 µA Pull-up/pull-down resistance RP 10 40 120 kΩ ⎯ Pull-up VIL = 0 V Pull-down VIH = VDD *1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS. 11 CE77 Series • Single power supply : VDD = 1.5 V Parameter Power supply current*1 Symbol IDDS (VDD = 1.5 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Conditions Value Unit Min Typ Max T2 ⎯ ⎯ 0.1 T3, T4 ⎯ ⎯ 0.2 T5 to T7 ⎯ ⎯ 0.3 T8, T9 ⎯ ⎯ 0.4 TA ⎯ ⎯ 0.5 TB, TC ⎯ ⎯ 0.6 TD ⎯ ⎯ 0.8 TE ⎯ ⎯ 1.0 TF ⎯ ⎯ 1.1 TG ⎯ ⎯ 1.3 VDD − 0.2 ⎯ VDD V mA “H” level output voltage VOH IOH = −100 µA “L” level output voltage VOL IOL = 100 µA 0 ⎯ 0.2 V “H” level output voltage V-I characteristics ⎯ 1.5 V VDD = 1.5 V±0.1 V *2 ⎯ ⎯ ⎯ “L” level output current V-I characteristics ⎯ 1.5 V VDD = 1.5 V±0.1 V *2 ⎯ ⎯ ⎯ Input leakage current IL ⎯ ⎯ ±5 µA Pull-up/pull-down resistance RP 10 55 120 kΩ ⎯ Pull-up VIL = 0 V Pull-down VIH = VDD *1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS. 12 CE77 Series • Dual power supply : VDDE = 3.3 V/VDDI = 2.5 V, 1.8 V, 1.5 V (VDDE = 3.3 V ± 0.3 V/VDDI = 2.5 V±0.2 V, 1.8 V ± 0.15 V, 1.5 V ±0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Power supply current*1 “H” level output voltage “L” level output voltage “H” level output V-I characteristics “L” level output V-I characteristics Input leakage current Pull-up/pull-down resistance Symbol IDDS Conditions Value Min Typ Max T2 ⎯ ⎯ 0.1 T3, T4 ⎯ ⎯ 0.2 T5 to T7 ⎯ ⎯ 0.3 T8, T9 ⎯ ⎯ 0.4 TA ⎯ ⎯ 0.5 TB, TC ⎯ ⎯ 0.6 TD ⎯ ⎯ 0.8 TE ⎯ ⎯ 1.0 TF ⎯ ⎯ 1.1 TG ⎯ ⎯ 1.3 VOH4 3.3 V output IOH = −100 µA VDDE − 0.2 ⎯ VDDE VOH3 2.5 V output IOH = −100 µA VDDI − 0.2 ⎯ VDDI VOH2 1.8 V output IOH = −100 µA VDDI − 0.2 ⎯ VDDI VOH1 1.5 V output IOH = −100 µA VDDI − 0.2 ⎯ VDDI VOL4 3.3 V output IOL = 100 µA 0 ⎯ 0.2 VOL3 2.5 V output IOL = 100 µA 0 ⎯ 0.2 VOL2 1.8 V output IOL = 100 µA 0 ⎯ 0.2 VOL1 1.5 V output IOL = 100 µA 0 ⎯ 0.2 ⎯ 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ ⎯ ⎯ 2.5 V VDDI = 2.5 V±0.2 V *3 ⎯ ⎯ ⎯ 1.8 V VDDE = 1.8 V±0.15 V *4 ⎯ ⎯ ⎯ 1.5 V VDDI = 1.5 V±0.1 V *5 ⎯ ⎯ ⎯ 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ ⎯ ⎯ 2.5 V VDDI = 2.5 V±0.2 V *3 ⎯ ⎯ ⎯ 1.8 V VDDE = 1.8 V±0.15 V *4 ⎯ ⎯ ⎯ 1.5 V VDDI = 1.5 V±0.1 V *5 ⎯ ⎯ ⎯ ⎯ ±5 ⎯ IL 3.3 V Pull-up VIL = 0 Pull-down VIH = VDDE 10 25 70 2.5 V Pull-up VIL = 0 Pull-down VIH = VDDI 10 25 120 1.8 V Pull-up VIL = 0 Pull-down VIH = VDDI 10 40 120 1.5 V Pull-up VIL = 0 Pull-down VIH = VDDI 10 55 120 RP Unit mA V V ⎯ ⎯ µA kΩ *1: When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2: Refer to “(1) 3.3 V” in ■ V-I CHARACTERISTICS. *3: Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS. *4: Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS“. *5: Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS. 13 CE77 Series • Dual power supply : VDDE = 2.5 V/VDDI = 2.5 V, 1.8 V, 1.5 V (VDDE = 2.5 V ± 0.2 V/VDDI = 1.8 V±0.15 V, 1.5 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Power supply current*1 “H” level output voltage “L” level output voltage “H” level output V-I characteristics “L” level output V-I characteristics Input leakage current Pull-up/pull-down resistance Symbol IDDS Conditions Value Min Typ Max T2 ⎯ ⎯ 0.1 T3, T4 ⎯ ⎯ 0.2 T5 to T7 ⎯ ⎯ 0.3 T8, T9 ⎯ ⎯ 0.4 TA ⎯ ⎯ 0.5 TB, TC ⎯ ⎯ 0.6 TD ⎯ ⎯ 0.8 TE ⎯ ⎯ 1.0 TF ⎯ ⎯ 1.1 TG ⎯ ⎯ 1.3 VOH3 2.5 V output IOH = −100 µA VDDE − 0.2 ⎯ VDDE VOH2 1.8 V output IOH = −100 µA VDDI − 0.2 ⎯ VDDI VOH1 1.5 V output IOH = −100 µA VDDI − 0.2 ⎯ VDDI VOL3 2.5 V output IOL = 100 µA 0 ⎯ 0.2 VOL2 1.8 V output IOL = 100 µA 0 ⎯ 0.2 VOL1 1.5 V output IOL = 100 µA 0 ⎯ 0.2 ⎯ 2.5 V VDDE = 2.5 V±0.2 V *2 ⎯ ⎯ ⎯ 1.8 V VDDI = 1.8 V±0.15 V *3 ⎯ ⎯ ⎯ 1.5 V VDDI = 1.5 V±0.1 V *4 ⎯ ⎯ ⎯ 2.5 V VDDE = 2.5 V±0.2 V *2 ⎯ ⎯ ⎯ 1.8 V VDDI = 1.8 V±0.15 V *3 ⎯ ⎯ ⎯ 1.5 V VDDI = 1.5 V±0.1 V *4 ⎯ ⎯ ⎯ ⎯ ±5 ⎯ IL RP 2.5 V Pull-up VIL = 0 Pull-down VIH = VDDE 10 25 120 1.8 V Pull-up VIL = 0 Pull-down VIH = VDDI 10 40 120 1.5 V Pull-up VIL = 0 Pull-down VIH = VDDI 10 55 120 Unit mA V V ⎯ ⎯ µA kΩ *1: When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2: Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS. *3: Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS“. *4: Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS. 14 CE77 Series ■ V-I CHARACTERISTICS (1) 3.3 V • 3.3 V normal I/O V-I characteristics [ Condition : VDD = 3.0 V ] “L” level output V-I characteristics (VDD = 3.0 V) “H” level output V-I characteristics (VDD = 3.0 V) 3.0 V normal I/O VOL-IOL (Min) <VDD = 3.0 V> 3.0 V normal I/O VOH-IOH (Min) <VDD = 3.0 V> 40.0 VOH (V) 1.0 2.0 3.0 V type L type −10.0 M type −20.0 H type −30.0 V type IOL (Min) (mA) IOH (Min) (mA) 0.0 0.0 30.0 H type 20.0 M type 10.0 L type −40.0 0.0 0.0 1.0 −50.0 2.0 3.0 VOL (V) • 3.3 V normal I/O V-I characteristics [ Condition : VDD = 3.3 V ] “H” level output V-I characteristics (VDD = 3.3 V) “L” level output V-I characteristics (VDD = 3.3 V) 3.3 V normal I/O VOH-IOH (Min) <VDD = 3.3 V> 3.3 V normal I/O VOL-IOL (Min) <VDD = 3.3 V> 40.0 VOH (V) 0.0 0.0 −20.0 2.0 V type 3.0 L type IOL (Min) (mA) IOH (Min) (mA) −10.0 1.0 M type H type −30.0 30.0 H type 20.0 M type 10.0 L type V type −40.0 0.0 0.0 1.0 −50.0 2.0 3.0 VOL (V) • 3.3 V normal I/O V-I characteristics [ Condition : VDD = 3.6 V ] “H” level output V-I characteristics (VDD = 3.6 V) 3.3 V normal I/O VOH-IOH (Min) <VDD = 3.6 V> “L” level output V-I characteristics (VDD = 3.6 V) 3.3 V normal I/O VOL-IOL (Min) <VDD = 3.6 V> VOH (V) IOH (Min) (mA) −10.0 1.0 40.0 3.0 V type L type M type −20.0 H type −30.0 −40.0 2.0 IOL (Min) (mA) 0.0 0.0 30.0 H type 20.0 M type 10.0 V type 0.0 0.0 −50.0 L type 1.0 2.0 3.0 VOL (V) 15 CE77 Series (2) 2.5 V • 2.5 V normal I/O V-I characteristics [ Condition : VDD = 2.3 V ] “H” level output V-I characteristics (VDD = 2.3 V) 2.5 V normal I/O VOH-IOH (Min) <VDD = 2.3 V> “L” level output V-I characteristics (VDD = 2.3 V) 2.5 V normal I/O VOL-IOL (Min) <VDD = 2.3 V> VOH (V) 0.0 0.0 30.0 2.0 1.0 3.0 L type V type IOL (Min) (mA) IOH (Min) (mA) M type −10.0 H type −20.0 20.0 H type M type 10.0 L type V type 0.0 0.0 −30.0 2.0 1.0 3.0 VOL (V) • 2.5 V normal I/O V-I characteristics [ Condition : VDD = 2.5 V ] “H” level output V-I characteristics (VDD = 2.5 V) 2.5 V normal I/O VOH-IOH (Min) <VDD = 2.5 V> “L” level output V-I characteristics (VDD = 2.5 V) 2.5 V normal I/O VOL-IOL (Min) <VDD = 2.5 V> VOH (V) 0.0 0.0 1.0 30.0 2.0 3.0 V type IOL (Min) (mA) IOH (Min) (mA) L type M type −10.0 H type −20.0 V type 20.0 M type 10.0 L type 0.0 0.0 −30.0 H type 2.0 1.0 3.0 VOL (V) • 2.5 V normal I/O V-I characteristics [ Condition : VDD = 2.7 V ] “H” level output V-I characteristics (VDD = 2.7 V) 2.5 V normal I/O VOH-IOH (Min) <VDD = 2.7 V> “L” level output V-I characteristics (VDD = 2.7 V) 2.5 V normal I/O VOL-IOL (Min) <VDD = 2.7 V> VOH (V) −10.0 M type H type −30.0 30.0 2.0 V type 3.0 L type −20.0 −40.0 16 1.0 IOL (Min) (mA) IOH (Min) (mA) 0.0 0.0 20.0 H type 10.0 M type L type V type 0.0 0.0 1.0 2.0 VOL (V) 3.0 CE77 Series (3) 1.8 V • 1.8 V normal I/O V-I characteristics [ Condition : VDD = 1.65 V ] “H” level output V-I characteristics (VDD = 1.65 V) 1.8 V normal I/O VOH-IOH (Min) <VDD = 1.65 V> “L” level output V-I characteristics (VDD = 1.65 V) 1.8 V normal I/O VOL-IOL (Min) <VDD = 1.65 V> VOH (V) 1.0 20.0 2.0 L type IOL (Min) (mA) IOH (Min) (mA) 0.0 0.0 M type −10.0 H type V type H type 10.0 M type L type V type 0.0 0.0 −20.0 1.0 2.0 VOL (V) • 1.8 V normal I/O V-I characteristics [ Condition : VDD = 1.8 V ] “H” level output V-I characteristics (VDD = 1.8 V) “L” level output V-I characteristics (VDD = 1.8 V) 1.8 V normal I/O VOH-IOH (Min) <VDD = 1.8 V> 1.8 V normal I/O VOL-IOL (Min) <VDD = 1.8 V> VOH (V) 0.0 0.0 1.0 20.0 2.0 V type IOL (Min) (mA) IOH (Min) (mA) L type M type −10.0 H type H type 10.0 M type L type V type 0.0 0.0 −20.0 1.0 2.0 VOL (V) • 1.8 V normal I/O V-I characteristics [ Condition : VDD = 1.95 V ] “H” level output V-I characteristics (VDD = 1.95 V) 1.8 V normal I/O VOH-IOH (Min) <VDD = 1.95 V> “L” level output V-I characteristics (VDD = 1.95 V) 1.8 V normal I/O VOL-IOL (Min) <VDD = 1.95 V> VOH (V) 1.0 IOH (Min) (mA) V type L type M type −10.0 20.0 2.0 H type V type IOL (Min) (mA) 0.0 0.0 H type 10.0 M type L type −20.0 −30.0 0.0 0.0 1.0 2.0 VOL (V) 17 CE77 Series (4) 1.5 V • 1.5 V normal I/O V-I characteristics [ Condition : VDD = 1.4 V ] “H” level output V-I characteristics (VDD = 1.4 V) “L” level output V-I characteristics (VDD = 1.4 V) 1.5 V normal I/O VOH-IOH (Min) <VDD = 1.4 V> 1.5 V normal I/O VOL-IOL (Min) <VDD = 1.4 V> VOH (V) 0.5 1.0 15.0 1.5 V type L type IOL (Min) (mA) IOH (Min) (mA) 0.0 0.0 M type −5.0 H type −10.0 10.0 H type M type 5.0 L type V type 0.0 0.0 0.5 −15.0 1.0 1.5 VOL (V) • 1.5 V normal I/O V-I characteristics [ Condition : VDD = 1.5 V ] “H” level output V-I characteristics (VDD = 1.5 V) “L” level output V-I characteristics (VDD = 1.5 V) 1.5 V normal I/O VOH-IOH (Min) <VDD = 1.5 V> 1.5 V normal I/O VOL-IOL (Min) <VDD = 1.5 V> VOH (V) 0.0 0.0 0.5 1.0 15.0 1.5 V type IOL (Min) (mA) IOH (Min) (mA) L type M type −5.0 H type 10.0 H type M type 5.0 L type −10.0 V type 0.0 0.0 0.5 −15.0 1.0 1.5 VOL (V) • 1.5 V normal I/O V-I characteristics [ Condition : VDD = 1.6 V ] “H” level output V-I characteristics (VDD = 1.6 V) “L” level output V-I characteristics (VDD = 1.6 V) 1.5 V normal I/O VOH-IOH (Min) <VDD = 1.6 V> 1.5 V normal I/O VOL-IOL (Min) <VDD = 1.6 V> 15.0 VOH (V) −5.0 −10.0 −15.0 0.5 1.0 1.5 V type L type M type H type IOL (Min) (mA) IOH (Min) (mA) 0.0 0.0 18 M type 5.0 L type V type 0.0 0.0 −20.0 H type 10.0 0.5 1.0 VOL (V) 1.5 CE77 Series ■ AC CHARACTERISTICS (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter tpd*1 Delay time Value Symbol Unit Min Typ Max typ*2 × tmin*3 typ*2 × ttyp*3 typ*2 × tmax*3 ns *1 : Delay time = propagation delay time, enable time, disable time *2 : “typ” is calculated from the cell specification. *3 : Measurement condition Measurement condition tmin ttyp tmax VDD = 2.5V ± 0.2 V, VSS = 0 V, Tj = −40 °C to +125 °C 0.60 1.00 1.64 VDD = 1.8V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C 0.84 1.57 2.84 VDD = 1.5V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C 1.14 2.22 4.09 Note : tpd Max is calculated according to the maximum junction temperature (Tj) . ■ INPUT/OUTPUT CAPACITANCE (f = 1 MHz, VDD = VI = 0 V, Tj = +25 °C) Parameter Symbol Value Unit CIN Max 16 pF Output pin COUT Max 16 pF Input/output capacitance CI/O Max 16 pF Input pin ■ DESIGN METHOD Linking a floor plan tool and a logic synthesis tool enables automatic circuit optimization using floor plan information. In addition, CDDM (Clock Driven Design Method) clock tree synthesis tools using floor plan information is also available. Using floor plan information at a pre-layout stage prevents major problems with setup and hold timings which can occur after layout. Using a hierarchical layout method to support larger-scale circuit design considerably shortens the overall design cycle time. 19 CE77 Series ■ THE NUMBER OF GATES USED AND PACKAGES 1. Counting the number of the gates used Evaluation of the basic cell count used has revealed some problems including the circuit complexities, difference of the utilization depending on the circuit design scheme (whether it is designed with the logic synthesis) or being unable to achieve the minimum layout with the logically synthesized circuit. To cope with those problems, Fujitsu developed the AREA as a criteria where the circuit size and the layout feasibility is determined. The AREA is a basic cell conceived from the viewpoint of congestion of the wiring; it has been calculated from the actual basic cell count and pin count in units of BC. Estimate method for the frame include the conventional one by the basic cell count and the one by the AREA for more detailed estimate. Hard macro basic cell count and AREA count for unit cell, I/O buffer cell or compiled cell are listed in the respective cell characteristic table. 2. Packages The table below lists the package types available and the reference number of gates used. Consult Fujitsu for the combination of each package and the availability. CE77 (V-FRAME) Package Pin 0k & Pitch Pin Count (mm) S Q F P 176 208 240 0.5 0.5 0.5 H Q F P 208 240 256 304 0.5 0.5 0.4 0.5 P B G A 256 1.27 1000k 2000k 3000k 4000k 5000k 6000k 7000k 8000k~ 274k 803k 965k 1776k 2276k 1776k 7128k 618k Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu. 20 CE77 Series CE77 (T-FRAME) Package Pin 0k & Pitch Pin Count (mm) L Q F P 144 176 208 256 0.5 0.5 0.5 0.4 H Q F P 208 240 256 304 0.5 0.5 0.4 0.5 F B G A 144 176 224 228 0.8 0.8 0.8 0.75 P B G A 256 352 420 1.27 1.27 1.27 500k 1000k 1500k 2000k 2500k 3000k 3500k 4000k 4500k 5000k 5500k 1241k 744k 1375k 2109k 2678k 2109k 2109k 4538k 461k 646k 1375k 2109k 2109k 2678k 3789k Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu. 21 CE77 Series ■ BASIC CHARACTERISTICS Transfer characteristics (Typical CMOS input buffer) 1 Transfer characteristics (Typical CMOS input buffer) 2 3.0 VDD = 1.95 V VDD = 1.8 V 2.0 VDD = 2.3 V 2.0 VOUT (V) VOUT (V) 2.5 VDD = 1.6 V VDD = 1.5 V 1.5 VDD = 2.7 V VDD = 2.5 V VDD = 1.4 V 1.5 1.0 1.0 0.5 0.5 0.0 0.6 0.7 0.8 0.9 1.0 0.0 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.1 VIN (V) VIN (V) Transfer characteristics (Typical schmitt input buffer) 1 VDD = 1.95 V VDD = 1.8 V VDD = 1.6 V VDD = 1.5 V VDD = 1.4 V 0.0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VDD =1.95 V VDD = 1.8 V 0.5 VDD = 1.6 V 1.0 VDD = 1.5 V 1.5 VDD = 1.4 V VOUT (V) 2.0 1.2 1.3 1.4 VIN (V) Transfer characteristics (Typical schmitt input buffer) 2 3.0 VDD = 2.7 V VDD = 2.5 V VDD = 2.3 V 2.5 VDD = 2.7 V 1.0 VDD = 2.5 V 1.5 VDD = 2.3 V VOUT (V) 2.0 0.5 0.0 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 VIN (V) (Continued) 22 CE77 Series (Continued) Transfer characteristics (3.3 V normal CMOS input buffer VDDI = 2.5 V) 3.00 1.50 VDDE = 3.6 V VOUT (V) 2.00 VDDE = 3.3 V VDDE = 3.0 V 2.50 1.00 0.50 0.00 −0.50 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 VIN (V) Transfer characteristics (3.3 V normal schmitt input buffer VDDI = 2.5 V) 1.00 VDDE = 3.3 V VDDE = 3.0 V VDDE = 3.6 V 1.50 VDDE = 3.0 V VOUT (V) 2.00 VDDE = 3.3 V 2.50 VDDE = 3.6 V 3.00 0.50 0.00 0.80 1.30 1.80 2.30 VIN (V) 23 CE77 Series FUJITSU LIMITED All Rights Reserved. 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