FUJITSU SEMICONDUCTOR DATA SHEET DS06-20110-5E Semicustom CMOS Embedded array CE81 Series ■ DESCRIPTION The CE81 series 0.18 µm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 34 million gates which have a gate delay time of 12 ps, resulting in both integration and speed about three times higher than conventional products. In addition, CE81 series can operate at a power-supply voltage of down to 1.1 V, substantially reducing power consumption. ■ FEATURES • • • • • • • • • • • • • • • • Technology : 0.18 µm silicon-gate CMOS, 3- to 5-layer wiring Supply voltage : + 1.8 V ± 0.15 V (normal) to + 1.1 V ± 0.1 V Junction temperature range : −40 to +125 °C Gate delay time : tpd = 12 ps (1.8 V, inverter, F/O = 1) Gate power consumption : Pd = 8 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1) High-load driving capability : IOL = 2/4/8/12 mA mixable Output buffer cells with noise reduction circuits Inputs with on-chip input pull-up/pull-down resistors (33 kΩ typical) and bidirectional buffer cells Buffer cells dedicated to crystal oscillator Special interface : P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, and others (including those under development) IP macros : CPU, DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others (including those under development) Capable of incorporating compiled cells (RAM/ROM/multiplier, and others) Configurable internal bus circuits Advanced hardware/software co-design environment Short-term development using a timing driven layout tool Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time (Continued) Copyright©1999-2006 FUJITSU LIMITED All rights reserved CE81 Series (Continued) • Hierarchical design environment for supporting large-scale circuits • Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture • Support for memory (RAM/ROM) SCAN • Support for memory (RAM) BIST • Support for boundary SCAN • Support for path delay test • A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, LQFP) ■ MACRO LIBRARY (Including macros being prepared) 1. Logic cells (about 800 types) • • • • • • • • • • Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR SCAN Flip Flop ENOR AND-OR • • • • • • • • • • Decoder Non-SCAN Flip Flop Inverter Buffer OR-AND Inverter OR Selector BUS Driver EOR Others 2. IP macros CPU/DSP FR, SPARClite, standard CPU (under preparation) Communications DSP, DSP for AV Interface macro PCI, IEEE1394, USB, IrDA, etc. Multimedia processing macros JPEG, MPEG, etc. Mixed signal macros ADC, DAC, OPAMP, etc. Compiled macros RAM, ROM, multiplier, adder, multiplier-accumulator, etc. PLL Analog PLL, digital PLL 3. Special I/O interface macros • T-LVTTL • LVDS • IEEE1394 2 • SSTL • PCI • HSTL • AGP • P-CML • USB CE81 Series ■ CHIP STRUCTURE The chip layout of the CE81 series consists of two major areas : chip peripheral area and basic cell area. The chip peripheral area contains the input/output buffer cells for interfacing with external devices and the associated bonding pads. The basic cell area contains some of input/output buffer cells, the unit cells and the compiled cells. • Chip configuration Bonding pad I/O buffer cell Basic cell area 3 CE81 Series ■ COMPILED CELLS Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CE81 series has the following types of compiled cells (Note that each macro is different in word/bit range depending on the column type) . 1. Clock synchronous single-port RAM (1 address : 1 RW) • High density/Partial write type Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 Bit 16 64 to 72 K 64 to 4 K 1 to 18 Bit Memory capacity Word range Bit range Unit 256 to 144 K 64 to 2 K 4 to 72 Bit Word range Bit range Unit 4 to 16 K 6 to 72 Bit Word range Bit range Unit • High speed type Column type 8 • Large scale partial write type Column type Memory capacity 16 24.5 K to 1179 K 2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R) • High density/Partial write type Column type Memory capacity 4 16 to 72 K 16 to 1 K 1 to 72 Bit 16 64 to 72 K 64 to 4 K 1 to 18 Bit 3. Clock synchronous register file (3 addresses : 1 W, 2 R) Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 Bit 4. Clock synchronous register file (4 addresses : 2 W, 2 R) Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 K 1 to 72 Bit 5. Clock synchronous ROM (1 addresses : 1 R) Column type Memory capacity Word range Bit range Unit 16 256 to 512 K 128 to 4 K 2 to 128 Bit 6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R) 4 Column type Memory capacity Word range Bit range Unit 8 256 to 32 K 32 to 1 K 8 to 32 Bit 16 384 to 32 K 64 to 2 K 6 to 16 Bit 32 512 to 32 K 128 to 4 K 4 to 8 Bit CE81 Series ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Min Unit Max +2.5 *2 VDD −0.5 Input voltage*1 VI −0.5 Output voltage*1 VO −0.5 Storage temperature Tst −55 +125 °C Junction temperature Tj −40 +125 °C Output current *4 IO ⎯ ±4 Supply voltage*1 V +4.0 *3 VDD+0.5 ( ≤ 2.5 V) *2 V VDD+0.5 ( ≤ 4.0 V) *3 VDD+0.5 ( ≤ 2.5 V) *2 V VDD+0.5 ( ≤ 4.0 V) *3 mA 5 Input signal transmitting rate RI ⎯ Clock Input * : 200 Normal Input : 100 Mbps *6 Output signal transmitting rate RO ⎯ 100 Mbps *6 Output load capacitance CO ⎯ 3000/RO pF Continuous time of indefinite input signal tZ ⎯ 10 ms Supply pin current ID ⎯ *7 mA *1 : The parameter is based on VSS = 0 V. *2 : Internal gate part in case of signal power supply or dual power supply *3 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply *4 : DC current which continues more than 10 ms, or average DC current *5 : In case of using I/O cell for clock input *6 : bps = bit per second *7 : Supply pin current for one VDD/GND pin Frame Source type Maximum current [mA] Standard source Additional source Number of layer VDDE, VDDI, VDD, VSS 68 68 VDDE 39 39 VDDI, VDD, VSS 68 68 A VDDE, VDDI, VDD, VSS 34 34 ⎯ B VDDE, VDDI, VDD, VSS 43 30 ⎯ YS/S, YI/I 4, 5 3 WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 5 CE81 Series ■ RECOMMENDED OPERATING CONDITIONS • Single power supply (VDD = + 1.8 V ± 0.15 V) Parameter (VSS = 0 V) Symbol Value Min Typ Max Supply voltage (1.8 V supply voltage) VDD 1.65 1.8 1.95 V “H” level input voltage (1.8 V CMOS) VIH VDD × 0.65 ⎯ VDD + 0.3 V “L” level input voltage (1.8 V CMOS) VIL −0.3 ⎯ VDD × 0.35 V Junction temperature Tj −40 ⎯ +125 °C • Dual power supply (VDDE = + 3.3 V ± 0.3 V, VDDI = + 1.8 V ± 0.15 V) Parameter Supply voltage “H” level input voltage “L” level input voltage Symbol (VSS = 0 V) Value Min Typ Max 1.8 V supply voltage VDDI 1.65 1.8 1.95 3.3 V supply voltage VDDE 3.0 3.3 3.6 VDD × 0.65 ⎯ VDDI + 0.3 2.0 ⎯ VDDE + 0.3 −0.3 ⎯ VDD × 0.35 −0.3 ⎯ +0.8 −40 ⎯ +125 1.8 V CMOS 3.3 V CMOS 1.8 V CMOS 3.3 V CMOS Junction temperature VIH VIL Tj • Dual power supply (VDDE = + 3.3 V ± 0.3 V, VDDI = + 1.5 V ± 0.1 V / + 1.1 V ± 0.1 V) Parameter Symbol VDDE Supply voltage VDDI Unit V V V °C (VSS = 0 V) Value Unit Min Typ Max 3.0 3.3 3.6 V 1.0 1.1 1.2 V 1.4 1.5 1.6 V “H” level input voltage 3.3 V CMOS VIH 2.0 ⎯ VDDE + 0.3 V “L” level input voltage VIL −0.3 ⎯ +0.8 V Tj −40 ⎯ +125 °C Junction temperature 6 Unit 3.3 V CMOS CE81 Series • Dual power supply (VDDE = + 2.5 V ± 0.2 V, VDDI = + 1.8 V ± 0.15 V) Parameter Supply voltage “H” level input voltage “L” level input voltage 1.8 V CMOS 2.5 V CMOS 1.8 V CMOS 2.5 V CMOS Junction temperature Symbol (VSS = 0 V) Value Typ Max VDDE 2.3 2.5 2.7 V VDDI 1.65 1.8 1.95 V VDDI × 0.65 ⎯ VDDI + 0.3 V 1.7 ⎯ VDDE + 0.3 V −0.3 ⎯ VDDI × 0.35 V −0.3 ⎯ +0.7 V −40 ⎯ +125 °C VIH VIL Tj • Dual power supply (VDDE = + 2.5 V ± 0.2 V, VDDI = + 1.5 V ± 0.1 V / + 1.1 V ± 0.1 V) Parameter Symbol VDDE Supply voltage Unit Min VDDI (VSS = 0 V) Value Unit Min Typ Max 2.3 2.5 2.7 V 1.0 1.1 1.2 V 1.4 1.5 1.6 V “H” level input voltage 2.5 V CMOS VIH 1.7 ⎯ VDDE + 0.3 V “L” level input voltage 2.5 V CMOS VIL −0.3 ⎯ +0.7 V Junction temperature Tj −40 ⎯ +125 °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 7 CE81 Series ■ ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS • Static supply current (single power supply/Dual power supply) A frame Frame CATLG value [mA] S frame Frame CATLG value [mA] I frame Frame CATLG value [mA] A4 A5 A6 A7 A8 A9 AA AB AC AD AE 0.5 0.7 1 1.4 2 2.6 3.3 4 4.6 5.3 6.6 SA SB SC SD SE SF SG 3.7 4.4 5 5.8 7.1 9.2 10.9 I1 I2 I3 I4 I5 I6 I7 I8 I9 IA 0.3 0.4 0.6 0.7 0.8 1.2 1.5 2 2.8 3.4 Note : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = + 25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resister or a crystal oscillator buffer is used. The above values may not be guaranteed when a High-speed cell library is used. • Single power supply : VDD = 1.8 V Parameter (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Symbol Conditions Supply current IDDS ⎯ “H” level output voltage VOH IOH = −100 µA “L” level output voltage VOL “H” level output V-I characteristics Value Typ Max ⎯ ⎯ * mA VDD − 0.2 ⎯ VDD V IOL = 100 µA 0 ⎯ 0.2 V ⎯ VDD = 1.8 V±0.15 V ⎯ ⎯ ⎯ ⎯ “L” level output V-I characteristics ⎯ VDD = 1.8 V±0.15 V ⎯ ⎯ ⎯ ⎯ Input leakage current IL ⎯ ⎯ ⎯ ±5 µA Pull-up/pull-down resistance RP Pull-up VIL = 0 Pull-down VIH = VDD ⎯ 18 ⎯ kΩ * : Refer to the table on the previous page “Static supply current (single power supply/Dual power supply) ”. 8 Unit Min CE81 Series • Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V / 1.5 V / 1.1 V (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V / 1.5 V ± 0.1 V / 1.1 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Supply current Symbol Conditions IDDS ⎯ Input leakage current Max ⎯ ⎯ *1 mA VDDE − 0.2 ⎯ VDDE V VOH2 1.8 V output IOH = −100 µA VDDI − 0.2 ⎯ VDDI V VOL4 3.3 V output IOL = 100 µA 0 ⎯ 0.2 V VOL2 1.8 V output IOL = 100 µA 0 ⎯ 0.2 V ⎯ IOL 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯ ⎯ 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ 1.8 V VDDE = 1.8 V±0.15 V ⎯ ⎯ ⎯ IL 1.8 V Pull-up/pull-down resistance Typ 3.3 V output IOH = −100 µA “L” level output voltage “L” level output V-I characteristics Unit Min VOH4 “H” level output voltage “H” level output V-I characteristics Value RP Pull up VIL = 0 Pull down VIH = VDDI ⎯ ⎯ ±5 ⎯ 18 ⎯ kΩ 3.3 V Pull up VIL = 0 Pull down VIH = VDDE µA 10 33 80 *1 : Refer to the table on the previous page “Static supply current (single power supply/Dual power supply) ”. *2 : Refer to the “• V-I Characteristics” Fig. 1, Fig. 2. 9 CE81 Series • Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V / 1.5 V / 1.1 V (VDDE = 2.5 V ± 0.2 V, VDDI = 1.8 V ± 0.15 V / 1.5 V ± 0.1 V / 1.1 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Supply current Symbol Conditions IDDS ⎯ Input leakage current Max ⎯ ⎯ * mA VDDE − 0.2 ⎯ VDDE V VOH2 1.8 V output IOH = −100 µA VDDI − 0.2 ⎯ VDDI V VOL3 2.5 V output IOL = 100 µA 0 ⎯ 0.2 V VOL2 1.8 V output IOL = 100 µA 0 ⎯ 0.2 V IOH IOL 2.5 V VDDE = 2.5 V±0.2 V ⎯ ⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯ ⎯ 2.5 V VDDE = 2.5 V±0.2 V ⎯ ⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯ ⎯ ⎯ IL 1.8 V Pull-up/pull-down resistance Typ 2.5 V output IOH = −100 µA “L” level output voltage “L” level output V-I characteristics RP Pull up VIL = 0 Pull down VIH = VDDI 2.5 V Pull up VIL = 0 Pull down VIH = VDDE ⎯ ⎯ ±5 ⎯ 18 ⎯ µA kΩ ⎯ 25 ⎯ * : Refer to the table on the previous page “Static supply current (single power supply/Dual power supply) ”. 10 Unit Min VOH3 “H” level output voltage “H” level output V-I characteristics Value CE81 Series • V-I Characteristics Min : Process = Slow, Tj = + 125 °C, VDD = 3.6 V Typ : Process = Typical, Tj = + 25 °C, VDD = 3.3 V Max : Process = Fast, Tj = −40 °C, VDD = 3.0 V VOH−VDD (V) −3.0 −4.0 −2.0 −1.0 0.0 0 120 −20 100 −40 80 −60 Max IOL (mA) Typ IOH (mA) Max Min 60 −80 40 −100 20 −120 0 Typ Min 0.0 1.0 2.0 3.0 4.0 VOL (V) Fig.1 V-I characteristics (3.3 V normal I/O L, M type) Min : Process = Slow, Tj = + 125 °C, VDD = 3.6 V Typ : Process = Typical, Tj = + 25 °C, VDD = 3.3 V Max : Process = Fast, Tj = −40 °C, VDD = 3.0 V VOH−VDD (V) −4.0 −3.0 −2.0 −1.0 0.0 0 140 −40 120 −60 100 −80 IOL (mA) Typ −20 IOH (mA) Min 160 60 −120 40 −140 20 −160 Typ 80 −100 Max Max Min 0 0.0 2.0 1.0 3.0 4.0 VOL (V) Fig.2 V-I characteristics (3.3 V normal I/O H, V type) 11 CE81 Series 2. AC Characteristics Parameter (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Rating Symbol tpd*1 Delay time Unit Min Typ Max typ*2 × tmin*3 typ*2 × ttyp*3 typ*2 × tmax*3 ns *1 : Delay time = propagation delay time, Enable time, Disable time *2 : “typ” is calculated based on the cell specification. *3 : Measurement conditions. Measurement condition tmin ttyp tmax VDD = 2.5 V±0.2 V, VSS = 0 V, Tj = −40 °C to +125 °C 0.60 1.00 1.64 VDD = 1.8 V±0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C 0.84 1.57 2.84 VDD = 1.5 V±0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C 1.14 2.22 4.09 Note : tpd max is calculated according to the maximum junction temperature (Tj) . ■ INPUT/OUTPUT PIN CAPACITANCE (f = 1 MHz, VDD = VI = 0 V, Ta = +25 °C) Parameter Input pin Output pin I/O pin Symbol CIN COUT CI/O Value Max 16 Max 16 Max 16 Unit pF pF pF Note : Capacitance varies according to the package and the location of the pin. ■ DESIGN METHOD Linking a floor plan tool and a logic synthesis tool enables automatic circuit optimization using floor plan information. In addition, also available are CDDM (Clock Driven Design Method) clock tree synthesis tools using floor plan information. Using floor plan information at a pre-layout stage prevents major problems with setup and hold timings which can occur after layout. Using a hierarchical layout method to support larger-scale circuit design considerably shortens the overall design cycle time. 12 CE81 Series ■ PACKAGES The table below lists the package types available and the reference number of gates used. Consult Fujitsu for the combination of each package and the availability. • Number of gates used and package types Package & Pin Count Pin Pitch (mm) 0 2000k 304 352 480 560 660 720 0.80 0.80 1.00 1.00 1.00 1.00 576 660 672 1.27 1.00 1.27 208 240 256 304 304 0.50 0.50 0.40 0.50 0.50 T Q F P 100 120 0.50 0.40 L Q F P 144 176 208 0.50 0.50 0.50 722k 963k 1098k 112 176 192 240 272 288 0.80 0.80 0.80 0.50 0.80 0.75 514k 722k 1098k T A B B G A E B G A H Q F P F B G A 4000k 6000k 8000k 10000k 12000k 14000k 16000k 18000k 20000k 891k 1254k 1905k 2689k 3609k 9129k 5982k 12727k 7952k 1098k 2085k 3764k 4712k 15158k 514k 514k 2697k 1550k 2697k Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu. 13 CE81 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0612