FUJITSU CS101_07

FUJITSU MICROELECTRONICS
DATA SHEET
DS06-20210-3Ea
Semicustom
CMOS
Standard Cell
CS101 Series
■ DESCRIPTION
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power
consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three
types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use.
As well as providing a maximum of 91 million gates, approximately twice the level of integration achieved in
previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the highspeed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
■ FEATURES
• Technology
•
•
•
•
•
•
•
•
•
•
•
: 90 nm Si gate CMOS
6- to 10-metal layers.
Low-K (low permittivity) material is used for all dielectric inter-layers.
Three different types of core transistors (low leak, standard, and high speed)
can be used on the same chip.
The design rules comply with industry standard processes.
Power supply voltage
: + 0.9 V to + 1.3 V (A wide range is supported.)
Operation junction temperature : − 40 °C to + 125 °C (standard)
Gate delay time
: tpd = 12 ps (1.2 V, Inverter, F/O = 1)
Gate power consumption
: 2.7 nW/gate (1.2 V, 2 NAND, F/O = 1, operating rate 0.5) ,
1.8 nW/gate (1.0 V, 2 NAND, F/O = 1, operating rate 0.5)
High level of integration
: Up to 91 million gates
Reduced chip sized realized by I/O with pad.
Two types of library sets are supported. (Performance focused (1.2 V) , Low power consumption supported
(0.9 V to 1.3 V) )
Low power consumption design (multi-power supply design and power gating) is supported.
Compliance with industry standard design rules enables non-Fujitsu Microelectronics commercial macros to
be easily incorporated.
Compiled cell (RAM, ROM, others)
Support for ultra high speed (up to 10 Gbps) interface macros.
(Continued)
Copyright©2003-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2007.11
CS101 Series
(Continued)
• Special interfaces (LVDS, SSTL2, others)
• Supports use of industry standard libraries (.LIB).
• Uses industry standard tools and supports the optimum tools for the application.
• Short-term development using a physical prototyping tool
• One pass design using a physical synthesis tool
• Hierarchical design environment for supporting large-scale circuits
• Support for Signal Integrity, EMI noise reduction
• Support for static timing sign-off
• Optimum package range : FBGA, FC-BGA, PBGA,TEBGA
Note : Items under development are included.
■ MACRO LIBRARIES (including those in preparation)
1. Logic cells (about 400 types)
Unit cell having three different types of core transistors with a different threshold value are provided.
• Adder
• AND
• AND-OR
• AND-OR Inverter
• Buffer
• Clock Buffer
• Decoder
• Delay Buffer
• ENOR
• EOR
• Inverter
• Latch
• NAND
• NOR
• OR
• OR-AND
• OR-AND Inverter
• SCAN Flip flop
• Non-SCAN Flip Flop
• Selector
• Others
2. IP macros
Compliance with the design rules recommended by the industry standard STARC (Semiconductor Technology
Academic Research Center) recommendations which means a wide range of commercially available IP macros
can be used.
ARM core (ARM7TDMI-S/ARM946E-S/ARM1176JZF-S),
CPU/DSP
FR71E core, Peripherals IP
Mixed signal macro
ADC, DAC, OPAMP, others
Compiled macro
RAM (1-port, 2-port), ROM, product sum calculator, others
PLL
Analog PLL
3. Special I/O interface macro
2
Interface macro (PHY)
LVDS, SSTL2, SSTL18, PCI, I2C
Interface macro (Controller)
USB2.0 Device/host, Serial ATA, PCI-Express, DDR2, HDMI, others
CS101 Series
■ COMPILED CELL
Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The
CS101 series has the following types of compiled cells. (Note that each macro is different in word/bit range
depending on the column type.)
1.
Clock synchronous single-port RAM (1 address : 1 read/write)
Column type
Memory capacity (bit)
Word range (word)
Bit range (bit)
4
16 to 144 K
16 to 1 K
1 to 144
8
32 to 576 K
32 to 8 K
1 to 72
16
64 to 576 K
64 to 16 K
1 to 36
2. Clock synchronous dual port RAM (2 address : 2 read/write)
Column type (bit)
Memory capacity (bit)
Word range (word)
Bit range (bit)
4
16 to 144 K
8 to 1 K
2 to 144
16
64 to 144 K
32 to 4 K
2 to 36
Column type
Memory capacity (bit)
Word range (word)
Bit range (bit)
16
256 to 4 M
128 to 16 K
2 to 256
64
1 K to 4 M
512 to 64 K
2 to 64
3. Clock synchronous ROM
4. Clock synchronous register file (2 address : 1 read, 1 write)
Column type
Memory capacity (bit)
Word range (word)
Bit range (bit)
1
8 to 18 K
4 to 128
2 to 144
5. Clock synchronous register file (4 address : 2 read, 2 write)
Column type
Memory capacity (bit)
Word range (word)
Bit range (bit)
1
8 to 18 K
4 to 128
2 to 144
■ LARGE CAPACITY MEMORY
Clock synchronous single-port RAM (1 address : 1 read/write)
Column type
Memory capacity (bit)
Word range (word)
16
64 K to 9 M
8 K to 64 K
Bit range (bit)
8 to 144
3
CS101 Series
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage *
1
Output voltage
Storage temperature
Symbol
VDD
VI
VO
TSTG
Operation junction
temperature
TJ
Power supply pin
current *2
ID
Output current *3
IO
Application
Rating
Unit
Min
Max
VDDI (Internal)
− 0.5
+ 1.8
V
VDDE (External 1.8 V)
− 0.5
+ 2.5
V
VDDE (External 2.5 V)
− 0.5
+ 3.6
V
VDDE (External 3.3 V)
− 0.5
+ 4.6
V
1.8 V
− 0.5
VDDE + 0.5 ( ≤ 2.5)
V
2.5 V
− 0.5
VDDE + 0.5 ( ≤ 3.6)
V
3.3 V
− 0.5
VDDE + 0.5 ( ≤ 4.6)
V
1.8 V
− 0.5
VDDE + 0.5 ( ≤ 2.5)
V
2.5 V
− 0.5
VDDE + 0.5 ( ≤ 3.6)
V
3.3 V
− 0.5
VDDE + 0.5 ( ≤ 4.6)
V
Plastic package
− 55
+ 125
°C
− 40
+ 125
°C
⎯
*4
mA
⎯
*4
mA
⎯
per VDDI, VDDE VSS pin
⎯
*1 : The values vary depending on the type of macros.
*2 : Maximum power supply current that can steadily flow.
*3 : Maximum output current that can steadily flow.
*4 : Contact your Fujitsu Microelectronics representative for details.
Note : VSS = 0 V
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
4
CS101 Series
■ RECOMMENDED OPERATING CONDITIONS
• Dual power supply (VDDE = 1.8 V ± 0.15 V , VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V)
Parameter
Symbol
VDDE
Power supply voltage
“H” level input voltage
“L” level input voltage
VDDI
1.8 V CMOS Normal
1.8 V CMOS Schmitt
1.8 V CMOS Normal
1.8 V CMOS Schmitt
VIH
VIL
(VSS = 0 V)
Value
Unit
Min
Typ
Max
1.65
1.8
1.95
0.9
1.0
1.1
1.1
1.2
1.3
VDDE × 0.65
⎯
VDDE+0.3
V
VDDE × 0.70
⎯
VDDE + 0.3
V
−0.3
⎯
VDDE × 0.35
V
−0.3
⎯
VDDE × 0.30
V
V
V
Schmitt hysteresis voltage
VH
VDDE × 0.10
⎯
VDDE × 0.40
V
Operation junction temperature
TJ
−40
⎯
+125
°C
• Dual power supply (VDDE = 2.5 V ± 0.2 V , VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V)
Parameter
Symbol
VDDE
Power supply voltage
“H” level input voltage
“L” level input voltage
VDDI
2.5 V CMOS Normal
2.5 V CMOS Schmitt
2.5 V CMOS Normal
2.5 V CMOS Schmitt
VIH
VIL
(VSS = 0 V)
Value
Unit
Min
Typ
Max
2.3
2.5
2.7
0.9
1.0
1.1
1.1
1.2
1.3
1.7
⎯
VDDE + 0.3
V
1.7
⎯
VDDE + 0.3
V
−0.3
⎯
+ 0.7
V
−0.3
⎯
+ 0.7
V
V
V
Schmitt hysteresis voltage
VH
0.2
⎯
1.0
V
Operation junction temperature
TJ
−40
⎯
+125
°C
5
CS101 Series
• Dual power supply (VDDE = 3.3 V ± 0.3 V , VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V)
Parameter
Symbol
VDDE
Power supply voltage
“H” level input voltage
“L” level input voltage
VDDI
3.3 V CMOS Normal
3.3 V CMOS Schmitt
3.3 V CMOS Normal
3.3 V CMOS Schmitt
VIH
VIL
(VSS = 0 V)
Value
Unit
Min
Typ
Max
3.0
3.3
3.6
0.9
1.0
1.1
1.1
1.2
1.3
2.0
⎯
VDDE + 0.3
V
2.1
⎯
VDDE + 0.3
V
−0.3
⎯
+ 0.8
V
−0.3
⎯
+ 0.7
V
V
V
Schmitt hysteresis voltage
VH
0.2
⎯
1.4
V
Operation junction temperature
TJ
−40
⎯
+125
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
6
CS101 Series
■ ELECTRICAL CHARACTERISTICS
• Dual power supply : VDDE = 1.8 V, VDDI = 1.0 V/VDDI = 1.2 V
(VDDE = 1.8 V ± 0.15 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C)
Parameter
Symbol
Conditions
Value
Min
Typ
Max
Unit
“H” level output voltage
VOH
1.8 V output,
IOH = −100 μA
VDDE − 0.2
⎯
VDDE
V
“L” level output voltage
VOL
1.8 V output,
IOL = 100 μA
0
⎯
0.2
V
Input leakage current*
IL
⎯
− 10
⎯
+ 10
μA
Pull-up/Pull-down resistor
RP
1.8 V
VIL = 0 V at pull-up/
VIH = VDDE at pull-down
40
80
155
kΩ
* : The input leakage current may exceed the above value when an input buffer with pull-up or pull-down resistor
is used.
• Dual power supply : VDDE = 2.5 V, VDDI = 1.0 V/VDDI = 1.2 V
(VDDE = 2.5 V ± 0.2 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C)
Parameter
Symbol
Conditions
Value
Min
Typ
Max
Unit
“H” level output voltage
VOH
2.5 V output,
IOH = −100 μA
VDDE − 0.2
⎯
VDDE
V
“L” level output voltage
VOL
2.5 V output,
IOL = 100 μA
0
⎯
0.2
V
Input leakage current*
IL
− 10
⎯
+ 10
μA
Pull-up/Pull-down resistor
RP
25
50
85
kΩ
⎯
2.5 V
VIL = 0 V at pull-up/
VIH = VDDE at pull-down
* : The input leakage current may exceed the above value when an input buffer with pull-up or pull-down resistor
is used.
• Dual power supply : VDDE = 3.3 V, VDDI = 1.0 V/VDDI = 1.2 V
(VDDE = 3.3 V ± 0.3 V, VDDI = 1.0 V ± 0.1 V/VDDI = 1.2 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C)
Parameter
Symbol
Conditions
Value
Min
Typ
Max
Unit
“H” level output voltage
VOH
3.3 V output,
IOH = −100 μA
VDDE − 0.2
⎯
VDDE
V
“L” level output voltage
VOL
3.3 V output,
IOL = 100 μA
0
⎯
0.2
V
Input leakage current*
IL
−10
⎯
+ 10
μA
Pull-up/Pull-down resistor
RP
15
33
70
kΩ
⎯
3.3 V
VIL = 0 V at pull-up/
VIH = VDDE at pull-down
* : The input leakage current may exceed the above value when an input buffer with pull-up or pull-down resistor
is used.
7
CS101 Series
■ AC CHARACTERISTICS
Parameter
Symbol
Delay time
tpd *1
Value
Min
Typ
Max
typ *2 × tmin *3
typ *2 × ttyp *3
typ *2 × tmax *3
Unit
ns
*1 : Delay time = propagation delay time, enable time, disable time
*2 : “typ” is calculated based on the cell specifications.
*3 : Measurement condition
Measurement condition
VDD = 1.2 V ± 0.1 V, VSS = 0 V, Tj = − 40 °C to +125 °C
tmin
ttyp
tmax
0.62
1.00
1.57
Note : The values are reference values, which vary depending on the cells.
■ I/O PIN CAPACITANCE
Parameter
Symbol
Value
Unit
Input pin
CIN
Max16
pF
Output pin
COUT
Max16
pF
I/O pin
CI/O
Max16
pF
Note : The capacitance values vary depending on the package and pin positions.
■ DESIGN METHODS
Fujitsu Microelectronics’s Reference Design Flow provides the following functions that help shorten the development time of large scale and high quality LSIs.
• High reliability design estimation in the early stage of physical design realized by physical prototyping.
• Layout synthesis with optimized timing realized by physical synthesis tools.
• High accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and
crosstalk.
• I/O design environment (power line design, assignment and selection of I/Os, package selection) considering
noise.
■ PACKAGES
Packages available for existing series can be used for CS101 series. This allows smooth replacement with
previously developed products.
Please contact your Fujitsu Microelectronics agent for details of delivery times.
FBGA package
: Max 424 pins
FC-BGA package : Max 2116 pins
PBGA package
: Max 420 pins
TEBGA package
: Max 900 pins
(Packages under planning are included.)
8
CS101 Series
MEMO
9
CS101 Series
MEMO
10
CS101 Series
MEMO
11
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
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Tel: +1-408-737-5600 Fax: +1-408-737-5999
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Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
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Germany
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Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
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Korea
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Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
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of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information.
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
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Edited
Strategic Business Development Dept.