FUJITSU MB85RS256PNF-G-JNE1

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-13105-2E
Memory FRAM
CMOS
256 K (32 K × 8) Bit SPI
MB85RS256
■ DESCRIPTION
MB85RS256 is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words × 8 bits,
using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory
cells.
MB85RS256 adopts the Serial Peripheral Interface (SPI).
Unlike SRAM, MB85RS256 is able to retain data without back-up battery.
The memory cells used for the MB85RS256 has improved at least 1010 times of read/write operation significantly
outperforming Flash memory and E2PROM in the number.
MB85RS256 does not take long time to write data unlike Flash memories nor E2PROM, and MB85RS256 takes
no wait time.
■ FEATURES
•
•
•
•
•
•
•
•
32,768 × 8 bits
3.0 V to 3.6 V
15 MHz (Max)
SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
Operating temperature range
: −20 °C to +85 °C
Data retention
: 10 years (+55 °C)
High endurance 10 Billion Read/writes (Min)
Package
: 8-pin plastic SOP (FPT-8P-M02)
Bit configuration
Operating power supply voltage
Operating frequency
Serial Peripheral Interface
:
:
:
:
Copyright©2005-2007 FUJITSU LIMITED All rights reserved
MB85RS256
■ PIN ASSIGNMENT
(TOP VIEW)
CS
1
8
VDD
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
(FPT-8P-M02)
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
2
Functional description
1
CS
Chip Select
This is an input pin to make chips select. When CS is “H”, device is in deselect (standby)
status as long as device is not write status internally, and SO becomes High-Z. Other inputs
from pins are ignored for this time. When CS is “L”, device is in select (active) status. CS has
to be “L” before inputting op-code.
3
WP
Write Protect
This is a pin to control writing to a status register. When WP is “L”, writing to a status register
is not operated.
7
HOLD
Hold
This pin is used to interrupt serial input/output without making chips deselect. When HOLD
is “L”, hold operation is activated, SO becomes High-Z, SCK and SI become don’t care.
While the hold operation, CS has to be retained “L”.
6
SCK
5
SI
Serial Data Input
This is an input pin of serial data. This inputs op-code, address, and writing data.
2
SO
Serial Data Output
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
8
VDD
Supply Voltage
4
VSS
Ground
Serial Clock
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
MB85RS256
■ BLOCK DIAGRAM
SCK
HOLD
Control Circuit
CS
Row-Decoder
Serial-Parallel Converter
Address Counter
SI
FRAM Cell Array
32,768 ✕ 8
FRAM
Status Register
Column Decoder/Sense Amp/
Write Amp
WP
Data Register
SO
Parallel-Serial Converter
3
MB85RS256
■ SPI MODE
MB85RS256 is corresponding to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) .
CS
SCK
SI
7
6
5
MSB
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
6
5
4
MSB
2
1
0
LSB
SPI Mode 3
4
3
MB85RS256
■ SERIAL PERIPHERAL INTERFACE (SPI)
MB85RS256 works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped
with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use.
SCK
MOSI
MISO
SO
SPI
Microcontroller
SI
SO
SCK
MB85RS256
CS
SI
SCK
MB85RS256
CS
HOLD
HOLD
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS
: Slave Select
System Configuration with SPI Port
Microcontroller
SO
SI
SCK
MB85RS256
CS
HOLD
System Configuration without SPI Port
5
MB85RS256
■ STATUS REGISTER
Bit No.
Bit Name
Function
WPEN
Status Register Write Protect
This is a bit composed of nonvolatile memories (FRAM). WPEN is related
to WP input to protect writing to a status register (refer to “■ WRITING
PROTECT”). Writing with the WRSR command and reading with the
RDSR command are possible.
6 to 4
⎯
Not Used Bits
These are bits composed of nonvolatile memories, writing with the WRSR
command is possible, and “000” is written before shipment. These bits are
not used but they are read with the RDSR command.
3
BP1
2
BP0
7
1
WEL
0
0
Block Protect
This is a bit composed of nonvolatile memory (FRAM). This defines block
size for writing protect with the WRITE command (refer to “■ BLOCK
PROTECT”). Writing with the WRSR command and reading with the
RDSR command are possible.
Write Enable Latch
This indicates FRAM memory and status register are writable. The WREN
command is for setting, and the WRDI command is for resetting. With the
RDSR command, reading is possible but writing is not possible with the
WRSR command. WEL is reset after the following operations.
The time when power is up.
The time when the WRDI command is input.
The time when the WRSR command is input.
The time when the WRITE command is input.
This is a bit fixed to “0”.
■ OP-CODE
MB85RS256 accepts 6 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown
in the table below. When invalid codes other than codes below are input, they are ignored. If CS is risen while
inputting op-code, the command are not performed.
Name
Description
Op-code
6
WREN
Set Write Enable Latch
0000 0110B
WRDI
Reset Write Enable Latch
0000 0100B
RDSR
Read Status Register
0000 0101B
WRSR
Write Status Register
0000 0001B
READ
Read Memory Code
0000 0011B
WRITE
Write Memory Code
0000 0010B
MB85RS256
■ COMMAND
• WREN
The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before
writing operation (WRSR command and WRITE command) .
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
1
Invalid
0
High-Z
SO
• WRDI
The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRITE command and WRSR
command) are not performed when WEL is reset.
CS
0
1
2
3
4
5
6
7
SCK
SI
SO
Invalid
0
0
0
0
0
1
0
0
Invalid
High-Z
7
MB85RS256
• RDSR
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to
SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. Continuously
reading status register is enabled by keep on sending SCK before rising CS with the RDSR command.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
Invalid
1
Data Out
High-Z
SO
Invalid
LSB
MSB
• WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR opcode to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR
command. a SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be
written. The SI value corresponding to bit 0 is ignored.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data In
Instruction
SI
SO
8
0
0
0
0
0
0
0
1
7
MSB
High-Z
6
5
4
3
2
1
0
LSB
MB85RS256
• READ
The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ are
input to SI. The most significant address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command
is completed, but keep on reading address with automatic increment is enabled by continuously sending clock
for 8 cycles each to SCK before CS is risen. When it reaches the most significant address, it rolls over to come
back to the starting address, and reading cycle keeps on infinitely.
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
SO
16-bit Address
OP-CODE
0 0 0 0 0 0 1 1 X 14 13 12 11 10
5 4
MSB
High-Z
3
2
1
Invalid
0
LSB MSB
7
6
LSB
Data Out
5
4
3
2
1
0
Invalid
• WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address and
8 bits of writing data are input to SI. The most significant address bit is invalid. When 8 bits of writing data is
input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you
continue sending the writing data for 8 bits each before CS is risen, it is possible to continue writing with automatic
address increment. When it reaches the most significant address, it rolls over, comes back to the starting address,
and writing cycle can be continued infinitely.
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
SO
16-bit Address
OP-CODE
0 0 0 0 0 0 1 0 X 14 13 12 11 10
5 4
MSB
High-Z
Data In
3
2
1
0
7
6
LSB MSB
5
4
3
2
1
0
LSB
9
MB85RS256
■ BLOCK PROTECT
Writing protect block is configured by the WRITE command with BP1, BP0 value of the status register.
BP1
BP0
Protected Block
0
0
None
0
1
6000H to 7FFFH (upper 1/4)
1
0
4000H to 7FFFH (upper 1/2)
1
1
0000H to 7FFFH (all)
■ WRITING PROTECT
Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN,
WP as shown in the table.
WEL
WPEN
WP
Protected Blocks
Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
■ HOLD OPERATION
Hold status is retained without aborting a command if HOLD is “L” while CS is “L”. The timing for starting and
ending hold status depends on the SCK to be “H” or “L” when a HOLD pin input is transited as shown in the
diagram below. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become don’t care.
And, SO becomes High-Z while reading command (RDSR, READ) . If CS is risen with hold status, a command
is aborted and device is reset.
CS
SCK
HOLD
Hold Condition
10
Hold Condition
MB85RS256
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Power supply voltage
VDD
− 0.5
+ 4.0
V
Input voltage
VIN
− 0.5
VDD + 0.5
V
VOUT
− 0.5
VDD + 0.5
V
TA
− 20
+ 85
°C
Tstg
− 20
+ 85
°C
Output voltage
Operating temperature
Storage temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
0.8 × VDD
⎯
VDD + 0.5
V
Input low voltage
VIL
− 0.5
⎯
+ 0.6
V
Operating temperature
TA
− 20
⎯
+ 85
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
11
MB85RS256
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Parameter
12
Symbol
Condition
Input leakage current
ILI
Output leakage current
Value
Unit
Min
Typ
Max
VIN = 0 V to VDD
⎯
⎯
10
µA
ILO
VOUT = 0 V to VDD
⎯
⎯
10
µA
Operating power supply current
IDD
SCK = 15 MHz
⎯
5
10
mA
Standby current
ISB
All inputs VSS or
SCK = SI = CS = VDD
⎯
3
50
µA
Output high voltage
VOH
IOH = −0.1 mA
VDD × 0.8
⎯
⎯
V
Output low voltage
VOL
IOL = 2 mA
⎯
⎯
0.4
V
MB85RS256
2. AC Characteristics
(within recommended operating conditions)
Parameter
Symbol
Value
Min
Max
Unit
SCK clock frequency
fCK
0
15
MHz
Clock high time
tCH
30
⎯
ns
Clock low time
tCL
30
⎯
ns
Chip select set up time
tCSU
10
⎯
ns
Chip select hold time
tCSH
10
⎯
ns
Output disable time
tOD
⎯
20
ns
Output data valid time
tODV
⎯
35
ns
Output hold time
tOH
0
⎯
ns
Deselect time
tD
60
⎯
ns
Data in rise time
tR
⎯
50
ns
Data fall time
tF
⎯
50
ns
Data set up time
tSU
5
⎯
ns
Data hold time
tH
5
⎯
ns
HOLD set up time
tHS
10
⎯
ns
HOLD hold time
tHH
10
⎯
ns
HOLD output floating time
tHZ
⎯
20
ns
HOLD output active time
tLZ
⎯
20
ns
AC Test Condition
Power supply voltage
Operation temperature
Input voltage magnitude
Input rise time
Input fall time
Input judge level
Output judge level
: 3.0 V to 3.6 V
: − 20 °C to + 85 °C
: 0.3 V to 2.7 V
: 5 ns
: 5 ns
: VDD/2
: VDD/2
13
MB85RS256
AC Load Equivalent Circuit
3.3 V
1.2 k
Output
30 pF
0.95 k
3. Pin Capacitance
Parameter
14
Symbol
Value
Min
Max
Unit
Output capacitance
CO
⎯
10
pF
Input capacitance
CI
⎯
10
pF
MB85RS256
■ TIMING DIAGRAM
• Serial Data Timing
tD
CS
tCSH
tCSU
tCH
tCL
SCK
tSU
SI
tH
Valid in
tODV
SO
tOH
tOD
High-Z
High-Z
: don't care
• Hold Timing
CS
SCK
tHS
tHS
tHH
tHS
tHH
tHS
tHH
tHH
HOLD
High-Z
SO
tHZ
tLZ
High-Z
tHZ
tLZ
15
MB85RS256
■ POWER ON/OFF SEQUENCE
tpu
tpd
VDD
3.0 V
VIH (Min)
1.0 V
VIL (Max)
GND
CS >VDD × 0.8 *
CS
CS : don't care
CS >VDD × 0.8 *
CS
* : CS (Max) < VDD + 0.5 V
Parameter
Symbol
Value
Min
Max
CS level hold time at power OFF
tpd
85
⎯
ns
CS level hold time at power ON
tpu
85
⎯
ns
■ NOTES ON USE
After IR reflow, the hold of data that was written before IR reflow is not guaranteed.
16
Unit
MB85RS256
■ ORDERING INFORMATION
Part number
MB85RS256PNF-G-JNE1
Package
8-pin plastic SOP
(FPT-8P-M02)
17
MB85RS256
■ PACKAGE DIMENSION
8-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
3.9 × 5.05 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.75 mm MAX
Weight
0.06 g
(FPT-8P-M02)
8-pin plastic SOP
(FPT-8P-M02)
+0.25
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
+.010
+0.03
*1 5.05 –0.20 .199 –.008
0.22 –0.07
+.001
.009 –.003
8
5
*2 3.90±0.30 6.00±0.40
(.154±.012) (.236±.016)
Details of "A" part
45˚
1.55±0.20
(Mounting height)
(.061±.008)
0.25(.010)
0.40(.016)
1
"A"
4
1.27(.050)
0.44±0.08
(.017±.003)
0.13(.005)
0~8˚
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.15±0.10
(.006±.004)
(Stand off)
0.10(.004)
C
2002 FUJITSU LIMITED F08004S-c-4-7
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
18
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB85RS256
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
The company names and brand names herein are the trademarks or
registered trademarks of their respective owners.
Edited
Business Promotion Dept.
F0702