FUJITSU SEMICONDUCTOR FACT SHEET NP501-00017-2v0-E FRAM MB85RS64V MB85RS64V is a 64K-bits FRAM LSI with serial interface (SPI), using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. FEATURES Bit configuration Serial Peripheral Interface ：8,192 words × 8 bits ：SPI(Serial Peripheral Interface) Correspondent to SPI mode 0 (0,0) and mode 3 (1,1) Operating frequency ：20 MHz (Max.) High endurance ：1012 times / byte Data retention ：10 years ( + 85°C), 95 years ( + 55°C), over 200 years ( + 35°C) Operating power supply voltage ：3.0V to 5.5V Low power consumption ：Operating power supply current 1.5mA (Typ＠20MHz) Standby current 10μA (Typ) Operation ambient temperature range ：-40℃ to +85℃ Package ：8-pin plastic SOP (FPT-8P-M02) RoHS compliant ORDERING INFORMATION Product name Package Shipping form MB85RS64VPNF-G-JNE1 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Tube MB85RS64VPNF-G-JNERE1 8-pin plastic SOP (FPT-8P-M02) 3.90mm×5.05mm,1.27mm pitch Embossed Carrier tape PACKAGE EXAMPLE OF REFERENCE 8-pin plastic SOP (FPT-8P-M02) June 2013 1/2 Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85RS64V PIN ASSIGNMENT Pin No. Pin name CS 1 8 VDD SO 2 7 HOLD 3 WP 6 4 GND Description Chip Select pin (TOP VIEW) 5 1 /CS 3 /WP Write Protect pin SCK SI This is an input pin to make chips select. When /CS is the "H" level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time. When /CS is the "L" level, device is in select (active) status. /CS has to be the "L" level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. This is a pin to control writing to a status register. The writing of status register is protected in related with /WP and WPEN bit of the status register. Hold pin 7 /HOLD 6 SCK 5 SI 2 SO 8 4 VDD GND This pin is used to interrupt serial input/output without making chips deselect. When /HOLD is the "L" level, hold operation is activated, SO becomes High-Z, SCK and SI become don't care. While the hold operation, /CS has to be retained the "L" level. Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. Supply Voltage pin Ground pin BLOCK DIAGRAM SCK HOLD Control Circuit CS Row Decoder Serial-Parallel Converter Address Counter SI FRAM Cell Array 8,192 8 FRAM Status Register Column Decoder/Sense Amp/ Write Amp WP Data Register SO Parallel-Serial Converter NP501-00017-2v0-E June 2013 2/2 Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved