FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12559-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89480/MB89480L Series
MB89485/485L/P485/P485L/PV480
■ DESCRIPTION
The MB89480 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit single-chip microcontrollers.
In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21bit timebase timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, 6-bit PPG, LCD controller/
driver, external interrupt 1 (edge), external interrupt 2 (level), 10-bit A/D converter, UART/SIO, buzzer, watchdog
timer reset.
The MB89480 series is designed suitable for LCD remote controller as well as in a wide range of applications for
consumer product.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Package used
LQFP package and SH-DIP package for MB89P485/P485L, MB89485/485L
MDIP package and MQFP package for MB89PV480
• High speed operating capability at low voltage
• Minimum execution time: 0.32 µs at 12.5 MHz
(Continued)
■ PACKAGES
64-pin Plastic SH-DIP
64-pin Plastic LQFP
64-pin Ceramic MDIP
64-pin Ceramic MQFP
(DIP-64P-M01)
(FPT-64P-M09)
(MDP-64C-P02)
(MQP-64C-P01)
MB89480/480L Series
(Continued)
• F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Bit manipulation instructions, etc.
• Six timers
PWC timer (also usable as an interval timer)
PWM timer
8/16-bit timer/counter x 2
21-bit timebase timer
Watch prescaler
• Programmable pulse generator
6-bit PPG with program-selectable pulse width and period
• External interrupt
Edge detection (selectable edge) : 4 channels
Low level interrupt (wake-up function) : 8 channels
• A/D converter (4 channels)
10-bit successive approximation type
• UART/SIO
Synchronous/asynchronous data transfer capability
• LCD controller/driver
Max 31 segments output x 4 commons
Booster for LCD driving (selected by mask option)
• Buzzer
7 frequencies are selectable by software
• Low-power consumption mode
Stop mode (oscillation stops so as to minimize the current consumption.)
Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.)
Watch mode (everything except the watch prescaler stops so as to reduce the power comsumption to an
extremely low level.)
Sub-clock mode
• Watchdog timer reset
• I/O ports: Max 42 channels
2
MB89480/480L Series
■ PRODUCT LINEUP
Part number
Parameter
MB89485L
MB89485
MB89P485L
MB89P485
MB89PV480
Classification
Mass production products
(mask ROM product)
OTP
Piggy-back
ROM size
16K x 8-bit (internal ROM)
16K x 8-bit (internal PROM
with read protection) *2
32K x 8-bit
(external ROM)*1
RAM size
1K × 8-bit
512 x 8-bit
CPU functions
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Minimum interrupt processing time
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, 16 bits
: 0.32 µs at 12.5 MHz
: 2.88 µs at 12.5 MHz
Ports
I/O ports (CMOS)
N-channel open drain I/O ports
Output ports (N-channel open drain)
Input port
Total
: 11 pins
: 28 pins
: 2 pins
: 1 pin
: 42 pins
21-bit timebase
timer
Interrupt period (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz.
Watchdog timer
Reset period (167.8 ms to 335.5 ms) at 12.5 MHz.
Pulse width count
timer
1 channel.
8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 tinst,
external).
8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst,
external).
8-bit pulse width measurement operation (supports continuous measurement, H width,
L width, rising edge to rising edge, falling edge to falling edge measurement and both edge
measurement).
PWM timer
8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst,
external).
8-bit resolution PWM operation.
6- bit programmable
pulse generator
Can generate square pulse with programmable period.
Can be operated either as a 2-channel 8-bit timer/counter (timer 11 and timer 12, each with its
8/16-bit timer/counter own independent operating clock cycle), or as one 16-bit timer/counter.
11, 12
In timer 11 or 16-bit timer/counter operation, event counter operation (external clock-triggered)
and square wave output capability.
Can be operated either as a 2-channel 8-bit timer/counter (timer 21 and timer 22, each with its
8/16-bit timer/counter own independent operating clock cycle), or as one 16-bit timer/counter.
21, 22
In timer 21 or 16-bit timer/counter operation, event counter operation (external clock-triggered)
and square wave output capability.
External interrupt
4 independent channels (selectable edge, interrupt vector, request flag).
8 channels (low level interrupt).
(Continued)
3
MB89480/480L Series
(Continued)
Part number
Parameter
MB89485L
MB89485
MB89P485L
MB89P485
MB89PV480
10-bit resolution × 4 channels.
A/D conversion function (conversion time: 60 tinst ).
Supports repeated activation by internal clock.
A/D converter
Common output
Segment output
LCD controller/driver
Bias power supply pins
LCD display RAM size
Dividing resistor/booster
: 4 (Max)
: 31 (Max) (selected resistor ladder)
: 26 (Max) (selected booster)
:4
: 31 × 4 bits
: selected by mask option
UART/SIO
Synchronous/asynchronous data transfer capability.
(Max baud rate: 97.656 Kbps at 12.5 MHz).
(7 and 8 bits with parity bit; 8 and 9 bits without parity bit).
Buzzer output
7 frequencies are selectable by software.
Standby mode
Sleep mode, stop mode, watch mode, sub-clock mode.
Process
CMOS
Operating voltage
2.2 V to 3.6 V 2.2 V to 5.5 V 2.7 V to 3.6 V 3.5 V to 5.5 V
2.7 V to 5.5 V
*1 : Use MBM27C256A as the external ROM.
*2 : Read protection feature is selected by part number, detail please refer to MASK OPTIONS.
Note : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock.
■ PACKAGE AND CORRESPONDING PRODUCTS
Part number
MB89485/485L
MB89P485/P485L
MB89PV480
DIP-64P-M01
O
O
X
FPT-64P-M09
O
O
X
MDP-64C-P02
X
X
O
MQP-64C-P01
X
X
O
Package
O : Availabe
X : Not available
4
MB89480/480L Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following point:
• The stack area is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV480, the current consumed by the EPROM mounted in the piggy-back socket is needed to
be included.
• When operating at low speed, the current consumed by the one-time PROM product is greater than that for
the mask ROM product. However, the current consumption is roughly the same in sleep and stop mode.
• For more information, see “■ ELECTRICAL CHARACTERISTICS”.
3. Oscillation Stabilization Time after Power-on Reset
•
•
•
•
For MB89PV480, MB89P485L and MB89485L, there is no power-on stabilization time after power-on reset.
For MB89P485, there is power-on stabilization time after power-on reset.
For MB89485, the power-on stabilization time can be selected.
For more information, please refer to “■ MASK OPTION”.
5
MB89480/480L Series
■ PIN ASSIGNMENT
(TOP VIEW)
COM0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
P40/SEG8
P41/SEG9
P42/SEG10
P43/SEG11
P44/SEG12
P45/SEG13
P46/SEG14
P47/SEG15
P50/SEG16
P51/SEG17
P52/SEG18
P53/SEG19
P54/SEG20
P55/SEG21
P56/SEG22
P57
P10/SEG23/INT10
P11/SEG24/INT11
P12/SEG25/INT12
P13/SEG26/INT13
X0A
X1A
C *2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
*3
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
92
91
90
89
88
87
86
85
84
83
82
81
80
79
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vcc
COM1
P30/COM2
P31/COM3
V3
P27/V2/EC1
P26/V1/TO1
V0/SEG0
P25/C0/EC2 *1
P24/C1/TO2 *1
P23/SI
P22/SO
P21/SCK
P20/PWM
P00/INT20
P01/INT21
P02/INT22
P03/INT23 *1
P04/INT24 *1
P05/INT25/PWC
P06/INT26/PPG
P07/INT27/BUZ
AVss
AVcc
P17/SEG30/AN3 *1
P16/SEG29/AN2 *1
P15/SEG28/AN1 *1
P14/SEG27/AN0 *1
RST
MODE
X1
X0
(DIP-64P-M01)
(MDP-64C-P02)
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively.
Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled.
*2: For product other than MB89P485, pin 31 is NC pin.
*3: Pin assignment on package top.
Pin no.
Pin
symbol
Pin no.
Pin
symbol
Pin no.
Pin
symbol
Pin no.
Pin
symbol
65
A15
73
A1
81
O6
89
A8
66
A12
74
A0
82
O7
90
A13
67
A7
75
O1
83
O8
91
A14
68
A6
76
O2
84
CE
92
Vcc
69
A5
77
O3
85
A10
70
A4
78
VSS
86
OE
71
A3
79
O4
87
A11
72
A2
80
O5
88
A9
N.C.: As connected internally, do not use.
(Continued)
6
MB89480/480L Series
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM0
Vcc
COM1
P30/COM2
P31/COM3
V3
P27/V2/EC1
P26/V1/TO1
V0/SEG0
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P25/C0/EC2 *1
P24/C1/TO2 *1
P23/SI
P22/SO
P21/SCK
P20/PWM
P00/INT20
P01/INT21
P02/INT22
P03/INT23 *1
P04/INT24 *1
P05/INT25/PWC
P06/INT26/PPG
P07/INT27/BUZ
AVss
AVcc
P10/SEG23/INT10
P11/SEG24/INT11
P12/SEG25/INT12
P13/SEG26/INT13
X0A
X1A
*2 C
Vss
X0
X1
MODE
RST
*1 P14/SEG27/AN0
1
* P15/SEG28/AN1
*1 P16/SEG29/AN2
*1 P17/SEG30/AN3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P40/SEG8
P41/SEG9
P42/SEG10
P43/SEG11
P44/SEG12
P45/SEG13
P46/SEG14
P47/SEG15
P50/SEG16
P51/SEG17
P52/SEG18
P53/SEG19
P54/SEG20
P55/SEG21
P56/SEG22
P57
(FPT-64P-M09)
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively.
Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled.
*2: For product other than MB89P485, pin 23 is NC pin.
(Continued)
7
MB89480/480L Series
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM0
Vcc
COM1
P30/COM2
P31/COM3
V3
P27/V2/EC1
(Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
(TOP VIEW)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
84
83
82
81
80
79
78
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
77
76
75
74
73
72
71
70
69
94
95
96
65
66
67
68
85
86
87
88
89
90
91
92
93
P26/V1/TO1
V0/SEG0
P25/C0/EC2 *1
P24/C1/TO2 *1
P23/SI
P22/SO
P21/SCK
P20/PWM
P00/INT20
P01/INT21
P02/INT22
P03/INT23 *1
P04/INT24 *1
P05/INT25/PWC
P06/INT26/PPG
P07/INT27/BUZ
AVss
AVcc
P17/SEG30/AN3 *1
P12/SEG25/INT12
P13/SEG26/INT13
X0A
X1A
*2 C
Vss
X0
X1
MODE
RST
*1 P14/SEG27/AN0
*1 P15/SEG28/AN1
*1 P16/SEG29/AN2
20
21
22
23
24
25
26
27
28
29
30
31
32
SEG7
P40/SEG8
P41/SEG9
P42/SEG10
P43/SEG11
P44/SEG12
P45/SEG13
P46/SEG14
P47/SEG15
P50/SEG16
P51/SEG17
P52/SEG18
P53/SEG19
P54/SEG20
P55/SEG21
P56/SEG22
P57
P10/SEG23/INT10
P11/SEG24/INT11
(MQP-64C-P01)
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively.
Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled.
*2: Pin 24 is NC pin.
Pin assignment on package top
Pin
no.
Pin
symbol
Pin
no.
Pin
Pin
Pin no.
symbol
symbol
Pin
no.
Pin
symbol
65
N.C.
73
A2
81
N.C.
89
OE
66
VPP
74
A1
82
O4
90
N.C.
67
A12
75
A0
83
O5
91
A11
68
A7
76
N.C.
84
O6
92
A9
69
A6
77
O1
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
71
A4
79
O3
87
CE
95
A14
72
A3
80
VSS
88
A10
96
VCC
N.C.: As connected internally, do not use.
8
MB89480/480L Series
■ PIN DESCRIPTION
Pin number
SH-DIP*1
MQFP*2
MDIP*4
33
26
QFP*3
25
Pin name
X0
Connection pins for a crystal or other oscillator.
An external clock can be connected to X0. In this case,
leave X1 open.
A
Connection pins for a crystal or other oscillator.
An external clock can be connected to X0A. In this case,
leave X1A open.
B
Input pin for setting the memory access mode.
Connect directly to VSS.
RST
C
Reset I/O pin. The pin is an N-ch open-drain type with pullup resistor and a hysteresis input. The pin outputs an “L”
level when an internal reset request is present. Inputting
an “L” level initializes internal circuits.
P00/INT20
to
P02/INT22
D
General-purpose CMOS I/O port.
A hysteresis input.
The pin is shared with external interrupt 2 input.
D
General-purpose CMOS I/O port.
A hysteresis input.
The pin is shared with external interrupt 2 input, and
shared with 8/16-bit timer/counter 21, 22 input when
booster is selected.
D
General-purpose CMOS I/O port.
A hysteresis input.
The pin is shared with external interrupt 2 input, and
shared with 8/16-bit timer/counter 21, 22 output when
booster is selected.
D
General-purpose CMOS I/O port.
A hysteresis input.
The pin is shared with external interrupt 2 input, and PWC
input.
D
General-purpose CMOS I/O port.
A hysteresis input.
The pin is shared with external interrupt 2 input, and 6-bit
PPG output.
D
General-purpose CMOS I/O port.
A hysteresis input.
The pin is shared with external interrupt 2 input and buzzer
output.
F/K
General-purpose N-ch open-drain I/O port.
A hysteresis input.
The pin is shared with external interrupt 1 input and LCD
segment output.
27
26
X1
29
22
21
X0A
30
23
22
X1A
35
28
27
MODE
29
28
50 to 48 43 to 41 42 to 40
47
46
45
44
43
40
39
38
37
36
39
Function
A
34
36
I/O
circuit
type
P03/INT23
38
P04/INT24
37
P05/INT25/
PWC
36
P06/INT26/
PPG
35
P07/INT27/
BUZ
P10/SEG23/
25 to 28 18 to 21 17 to 20 INT10 to P13/
SEG26/INT13
(Continued)
9
MB89480/480L Series
Pin number
SH-DIP*1
MQFP*2
MDIP*4
QFP*3
37 to 40 30 to 33 29 to 32
Pin name
I/O
circuit
type
P14/SEG27/
AN0 to P17/
SEG30/AN3
G/K
Function
General-purpose N-ch open-drain I/O port.
An analog input.
The pin is shared with A/D converter input and LCD
segment output.
LCD segment output will be disabled when booster is
selected.
51
44
43
P20/PWM
E
General-purpose CMOS I/O port.
The pin is shared with PWM output.
52
45
44
P21/SCK
E
General-purpose CMOS I/O port.
The pin is shared with UART/SIO clock I/O.
53
46
45
P22/SO
E
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data output.
54
47
46
P23/SI
D
General-purpose CMOS I/O port.
The pin is shared with UART/SIO data input.
H
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer 21, 22 output (it is
redirected to P04/INT24 when booster is selected), and
as a capacitor connecting pin when booster is selected.
55
48
47
P24/C1/TO2
56
49
48
P25/C0/EC2
F
General-purpose CMOS I/O port.
A hysteresis input.
The pin is shared with 8/16-bit timer 21, 22 input (it is
redirected to P03/INT23 when booster is selected), and
as a capacitor connecting pin when booster is selected.
58
51
50
P26/V1/TO1
H
General-purpose CMOS I/O port.
The pin is shared with 8/16-bit timer 11, 12 output, and
LCD power driving pin.
General-purpose CMOS I/O port.
A hysteresis input.
The pin is shared with 8/16-bit timer 11, 12 input, and
LCD power driving pin.
59
52
51
P27/V2/EC1
F
62
55
54
P30/COM2
I/K
General-purpose N-ch open-drain output port.
The pin is shared with the LCD common output.
61
54
53
P31/COM3
I/K
General-purpose N-ch open-drain output port.
The pin is shared with the LCD common output.
9 to 16
2 to 9
1 to 8
P40/SEG8 to
P47/SEG15
H/K
General-purpose N-ch open-drain I/O port.
The pin is shared with LCD segment output.
17 to 23 10 to 16 9 to 15
P50/SEG16 to
P56/SEG22
H/K
General-purpose N-ch open-drain I/O port.
The pin is shared with LCD segment output.
P57
J
24
17
16
General-purpose CMOS input port.
(Continued)
10
MB89480/480L Series
(Continued)
Pin number
SH-DIP*1
MQFP*2
MDIP*4
QFP*3
Pin name
I/O
circuit
type
Function
2 to 8
59 to
64, 1
58 to 64
SEG1 to
SEG7
K
LCD segment output-only pins.
1, 63
58, 56
57, 55
COM0 to
COM1
K
LCD common output-only pins.
60
53
52
V3
—
LCD driving power supply pin.
57
50
49
V0/SEG0
—/K
LCD driving power supply pin when booster is selected.
LCD segment output when booster is not selected.
When MB89P485 is used, connect an external 0.1 µF
capacitor between this pin and the ground.
31
24
23
C
—
64
57
56
VCC
—
Power supply pin (+3 V or +5 V).
32
25
24
VSS
—
Power supply pin (GND).
41
34
33
AVCC
—
A/D converter power supply pin.
42
35
34
AVSS
—
A/D converter power supply pin.
Use at the same voltage level as VSS.
N.C. pin when MB89485/485L, MB89P485L or
MB89PV480 is used.
*1: DIP-64P-M01
*2: MQP-64C-P01
*3: FPT-64P-M09
*4: MDP-64C-P02
11
MB89480/480L Series
■ External EPROM Socket (MB89PV480 only)
Pin number
MDIP*1
MQFP*2
Pin
name
I/O
91
90
66
87
85
88
89
67
68
69
70
71
72
73
74
95
94
67
91
88
92
93
68
69
70
71
72
73
74
75
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins.
83
82
81
80
79
77
76
75
86
85
84
83
82
79
78
77
O8
O7
O6
O5
O4
O3
O2
O1
I
Data input pins.
65
76
81
90
65
76
81
90
N.C.
—
Internally connected pins. Always leave open.
65
66
VPP
O
“H” level output pin.
78
80
VSS
O
Power supply pin (GND).
84
87
CE
O
Chip enable pin for the EPROM. Outputs “H” in standby mode.
86
89
OE
O
Output enable pin for the EPROM. Always outputs “L”.
92
96
VCC
O
Power supply pin for the EPROM.
*1: MDP-64C-P02
*2: MQP-64C-P01
12
Function
MB89480/480L Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Main/Sub-clock circuit
• Oscillation feedback resistance
is approx. 500 kΩ for main clock
circuit and 5 MΩ for sub-clock
circuit.
X1 (X1A)
N-ch P-ch
P-ch
X0 (X0A)
A
N-ch
N-ch
Stop mode control signal
B
• Hysteresis input
• The pull-down resistor (not
available in MB89P485/P485L)
Approx. 50 kΩ
R
• The pull-up resistor (P-channel)
Approx. 50 kΩ
• Hysteresis input
R
P-ch
C
N-ch
pull-up
resistor register
R
P-ch
P-ch
D
•
•
•
•
CMOS output
CMOS input
Hysteresis input
Selectable pull-up resistor
Approx. 50 kΩ
N-ch
port
resource
pull-up
resistor register
R
P-ch
P-ch
• CMOS output
• CMOS input
• Selectable pull-up resistor
Approx. 50 kΩ
E
N-ch
port
(Continued)
13
MB89480/480L Series
(Continued)
Type
Circuit
Remarks
• N-ch open-drain output
• CMOS input
• Hysteresis input
F
N-ch
port
resources
• N-ch open-drain output
• CMOS input
• Analog input
G
N-ch
port
analog input
• N-ch open-drain output
• CMOS input
H
N-ch
port
• N-ch open-drain output
I
N-ch
• CMOS input
J
port
• LCD segment output
P-ch
N-ch
K
P-ch
N-ch
14
MB89480/480L Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur on CMOS IC if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in ■ ELECTRICAL CHARACTERISTICS is applied between VCC and VSS.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC) and analog input from exceeding the digital power
supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/DConverter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up
from stop mode.
7. Notes on noise in the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
15
MB89480/480L Series
■ PROGRAMMING OTPROM IN MB89P485/P485L WITH SERIAL PROGRAMMER
1. Programming the OTPROM with Serial Programmer
• All OTP products can be programmed with serial programmer.
2. Programming the OTPROM
• To program the OTPROM using FUJITSU MCU programmer MB91919-001.
Inquiry : Fujitsu Microelectronics Asia Pte Ltd. :TEL (65)-2810770
FAX (65)-2810220
3. Programming Adapter for OTPROM
• To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter
listed below.
Package
Compatible socket adapter
DIP-64P-M01
MB91919-812
FPT-64P-M09
MB91919-813
Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770
FAX (65)-2810220
4. OTPROM Content Protection
For product with OTPROM content protection feature (MB89P485/P485L-103, MB89P485/P485L-104), OTPROM content can be read using serial programmer if the OTPROM content protection mechanism is not
activated.
One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM
content. If the protection code "00H" is written in this address (FFFCH), the OTPROM content cannot be read by
any serial programmer.
Note: The program written into the OTPROM cannot be verified once the OTPROM protection code is written ("00H"
in FFFCH). It is advised to write the OTPROM protection code at last.
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
16
MB89480/480L Series
■ PROGRAMMING OTPROM IN MB89P485/P485L WITH PARALLEL PROGRAMMER
1. Programming OTPROM with Parallel Programmer
• Only products without protection feature (i.e. MB89P485/P485L-101 and MB89P485/P485L-102) can be programmed with parallel programmer. Product with protection feature (i.e. MB89P485/P485L-103 and
MB89P485/P485L-104) cannot be programmed with parallel programmer.
2. ROM Writer Adapters and Recommended ROM Writers
• The following shows ROM writer adapters and recommended ROM writers.
Ando Electric Co., Ltd. (Parallel programmer)
Package name
Applicable adapter model
DIP-64P-M01
ROM2-64SD-32DP-8LA2
FPT-64P-M09
ROM2-64QF2-32DP-8LA3
Recommended writer
AF9708*
AF9709*
AF9723*
* : For the programmer and the version of the programmer, contact the Flash Support Group, Inc.
Fujitsu Microelectronics Asia Pte Ltd. (Serial programmer)
Package name
Applicable adapter model
DIP-64P-M01
MB91919-604
FPT-64P-M09
MB91919-605
Recommended writer
MB91919-001
Inquiries : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770
Sunhayato Corp.
: TEL 81-(3)-3986-7791
: FAX 81-(3)-3971-0535
E-mail : [email protected]
Flash Support Group, Inc
: FAX 81-(53)-428-8377
E-mail : [email protected]
3. Writing Data to the OTPROM using Writer from Minato Electronics Co., Ltd.
(1) Set the OTPROM writer for the CU50-OTP (device code: cdB6DC).
(2) Load the program data to the OTPROM writer.
(3) Write data using the OTPROM writer.
4. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
17
MB89480/480L Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403
3. Memory Space
Memory space in each mode is shown in the diagram below.
Address Normal operating mode
0000H
I/O
0080H
RAM
0480H
Not available
8000H
Corresponding addresses on the EPROM programmer
0000H
PROM
32KB
FFFFH
EPROM
32KB
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
18
MB89480/480L Series
■ BLOCK DIAGRAM
CMOS I/O port
Main clock
oscillator
X0
X1
Buzzer output
P07/INT27/BUZ
Clock controller
6-bit PPG
Sub-clock
oscillator
8-bit
PWC timer
Reset circuit
(Watchdog timer)
RST
P06/INT26/PPG
External interrupt 2
(level)
Port 0
X0A
X1A
P05/INT25/PWC
P04/INT24 *1
8
P03/INT23 *1
21-bit timebase
timer
P02/INT22
to P00/INT20
AVcc
AVss
8-bit PWM timer
P20/PWM
P24/C1/TO2 *1
P25/C0/EC2 *1
P26/V1/TO1
P27/V2/EC1
UART/SIO
Port 2 *4
P21/SCK
P22/SO
P23/SI
8/16-bit
timer/counter 21,22
10-bit
A/D converter
N-ch open-drain I/O port
External interrupt 1
(edge)
8/16-bit
timer/counter 11,12
2
4
4
Port 1
CMOS I/O port *4
Internal data bus
Watch prescaler
4
4
P14/SEG27/AN0
to
P17/SEG30/AN3
*1
*1
P10/SEG23/INT10
to
P13/SEG26/INT13
8
Booster
7
SEG1 to SEG7
2
2
P31/COM3
2
LCD controller/driver
V3
V0/SEG0 *3
N-ch open-drain output port
RAM
32 × 4-bit display
RAM (16 bytes)
16
F2MC-8L
CPU
ROM
Port 4 and Port 5 *4
P30/COM2
Port 3
COM0 to COM1
N-ch open-drain I/O port
P57
3
P56/SEG22
to P54/SEG20
4
P53/SEG19
to P50/SEG16
4
P47/SEG15
to P44/SEG12
4
P43/SEG11
to P40/SEG8
Other pins
Vcc, Vss, MODE, C *2
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively.
Segment output of P14/SEG27/AN0 to P17/SEG30/AN3 will be disabled.
*2: For product other than MB89P485, C pin is NC pin.
*3: If booster is selected, it serves as V0. If booster is not selected, it serves as SEG0.
*4: P20 to P23 are CMOS I/O ports. P24 to P27 are N-ch open-drain I/O ports. P57 is input-only port.
19
MB89480/480L Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89480 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89480 series is structured as illustrated below.
Memory Space
MB89485/485L
0000H
MB89P485/P485L
0080H
RAM
0080H
0280H
RAM
RAM
0100H
0100H
Generalpurpose
registers
I/O
I/O
0080H
0100H
0200H
0000H
0000H
I/O
MB89PV480
0200H
Generalpurpose
registers
0200H
Generalpurpose
registers
0280H
0480H
Vacant
Vacant
Vacant
8000H
C000H
C000H
FFC0H
FFFFH
ROM
FFC0H
FFFFH
ROM
FFC0H
FFFFH
Vector table (reset, interrupt, vector call instruction)
20
External
ROM
(32KB)
MB89480/480L Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following registers are provided:
Program counter (PC)
: A 16-bit register for indicating instruction storage positions.
Accumulator (A)
: A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T) : A 16-bit register for performing arithmetic operations with the accumulator.
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX)
: A 16-bit register for index modification.
Extra pointer (EP)
: A 16-bit pointer for indicating a memory address.
Stack pointer (SP)
: A 16-bit register for indicating a stack area.
Program status (PS)
: A 16-bit register for storing a register pointer, a condition code.
Initial value
16 bits
PC
FFFDH
: Program counter
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
11
10
9
8
Vacancy Vacancy Vacancy
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
21
MB89480/480L Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
22
H-flag
: Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear
to "0" otherwise. This flag is for decimal adjustment instructions.
I-flag
: Interrupt is allowed when this flag is set to "1". Interrupt is prohibited when the flag is set to "0". Clear
to "0" when reset.
IL1, 0
: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
Priority
High
1
Low = no interrupt
N-flag
: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Clear to "0" otherwise.
Z-flag
: Set to "1" when an arithmetic operation results in "0". Clear to "0" otherwise.
V-flag
: Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Clear to "0" if the
overflow does not occur.
C-flag
: Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to
"0" otherwise. Set to the shift-out value in the case of a shift instruction.
MB89480/480L Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 32 banks can be used on the MB89480 series. The bank currently in use is
indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
23
MB89480/480L Series
■ I/O MAP
Address
Register name
Register description
00H
PDR0
Port 0 data register
01H
DDR0
Port 0 data direction register
02H
PDR1
Port 1 data register
03H
DDR1
Port 1 data direction register
04H
PDR2
Port 2 data register
05H
Read/Write
Initial value
R/W
XXXXXXXXB
W*
00000000B
R/W
XXXXXXXXB
W*
00000000B
R/W
00000000B
(Reserved)
06H
DDR2
Port 2 data direction register
R/W
00000000B
07H
SYCC
System clock control register
R/W
X-1MM100B
08H
STBC
Standby control register
R/W
00010XXXB
09H
WDTC
Watchdog timer control register
W*
0---XXXXB
0AH
TBTC
Timebase timer control register
R/W
00---000B
0BH
WPCR
Watch prescaler control register
R/W
00--0000B
0CH
PDR3
Port 3 data register
R/W
------11B
R
XXXX----B
R/W
11111111B
R/W
X1111111B
0DH
0EH
(Reserved)
RSFR
Reset flag register
0FH
10H
(Reserved)
PDR4
Port 4 data register
11H
12H
(Reserved)
PDR5
Port 5 data register
13H to 1FH
(Reserved)
20H
SMC1
UART/SIO mode control register 1
R/W
00000000B
21H
SMC2
UART/SIO mode control register 2
R/W
00000000B
22H
SRC
UART/SIO rate control register
R/W
XXXXXXXXB
23H
SSD
UART/SIO status/data register
R
00001---B
24H
SIDR/SODR
UART/SIO data register
R/W
XXXXXXXXB
25H
EIC1
External interrupt 1 control register 1
R/W
00000000B
26H
EIC2
External interrupt 1 control register 2
R/W
00000000B
27H
EIE2
External interrupt 2 enable register
R/W
00000000B
28H
EIF2
External interrupt 2 flag register
R/W
-------0B
29H to 2BH
(Reserved)
2CH
ADC1
A/D control register 1
R/W
-0000000B
2DH
ADC2
A/D control register 2
R/W
-0000001B
2EH
ADDH
A/D data register (Upper byte)
R
------XXB
2FH
ADDL
A/D data register (Lower byte)
R
XXXXXXXXB
30H
ADEN
A/D input enable register
R/W
1111----B
31H
PCR1
PWC control register 1
R/W
0-0--000B
32H
PCR2
PWC control register 2
R/W
00000000B
33H
PLBR
PWC reload buffer register
R/W
XXXXXXXXB
(Continued)
24
MB89480/480L Series
(Continued)
Address
Register name
Register description
Read/Write
Initial value
R/W
0-000000B
W*
XXXXXXXXB
34H
CNTR
PWM timer control register
35H
COMR
PWM timer compare register
36H
T22CR
Timer 22 control register
R/W
000000X0B
37H
T21CR
Timer 21 control register
R/W
000000X0B
38H
T22DR
Timer 22 data register
R/W
XXXXXXXXB
39H
T21DR
Timer 21 data register
R/W
XXXXXXXXB
3AH
T12CR
Timer 12 control register
R/W
000000X0B
3BH
T11CR
Timer 11 control register
R/W
000000X0B
3CH
T12DR
Timer 12 data register
R/W
XXXXXXXXB
3DH
T11DR
Timer 11 data register
R/W
XXXXXXXXB
3EH
PPGC1
PPG control register 1
R/W
00000000B
3FH
PPGC2
PPG control register 2
R/W
0-000000B
40H
BUZR
Buzzer control register
R/W
-----000B
41H to 5DH
(Reserved)
5EH
LCR1
LCD controller control register 1
R/W
00010000B
5FH
LCR2
LCD controller control register 2
R/W
-0000000B
60H to 6FH
VRAM
LCD data RAM
R/W
XXXXXXXXB
70H
PURC0
Port 0 pull up resistor control register
R/W
11111111B
R/W
----1111B
71H
(Reserved)
72H
PURC2
Port 2 pull up resistor control register
73H to 7AH
(Reserved)
7BH
ILR1
Interrupt level setting register 1
W*
11111111B
7CH
ILR2
Interrupt level setting register 2
W*
11111111B
7DH
ILR3
Interrupt level setting register 3
W*
11111111B
7EH
ILR4
Interrupt level setting register 4
W*
11111111B
7FH
(Reserved)
* : Bit manipulation instruction cannot be used.
• Read/write access symbols
R/W : Readable and writable
R
: Read-only
W
: Write-only
• Initial value symbols
0
1
X
M
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
: Unused bit.
: The initial value of this bit is determined by mask option.
25
MB89480/480L Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min
Max
VCC
AVCC
VSS – 0.3
VSS + 6.0
V
MB89PV480, MB89P485,
MB89485
AVCC must not exceed VCC
VCC
AVCC
VSS – 0.3
VSS + 4.0
V
MB89P485L, MB89485L
AVCC must not exceed VCC
V0 to V3
VSS – 0.3
VSS + 6.0
V
Input voltage
VI
VSS – 0.3
VCC + 0.3
V
P00 to P07, P10 to P17, P20 to
P27, P40 to P47, P50 to P57
Output voltage
VO
VSS – 0.3
VCC + 0.3
V
P00 to P07, P10 to P17, P20 to
P27, P30 to P31, P40 to P47, P50
to P56
ICLAMP
– 2.0
+ 2.0
mA
*
∑ |ICLAMP|
20
mA
*
IOL
15
mA
“L” level average output current
IOLAV
4
mA
“L” level total maximum output
current
∑IOL
100
mA
∑IOLAV
40
mA
IOH
–15
mA
“H” level average output current
IOHAV
–4
mA
“H” level total maximum output
current
∑IOH
–50
mA
∑IOHAV
–20
mA
Power consumption
PD
300
mW
Operating temperature
TA
–40
+85
°C
Tstg
–55
+150
°C
Power supply voltage
LCD power supply voltage
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
“L” level total average output
current
“H” level maximum output current
“H” level total average output
current
Storage temperature
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
Average value (operating current ×
operating rate)
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
* : • Applicable to pins: P00 to P07, P20 to P23, AN0 to AN3
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
26
MB89480/480L Series
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V), the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on result.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannnot accept +B signal input.
• Sample recommended circuits :
Input/Output Equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
LCD power supply voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min
Max
2.2*
5.5
V
Operation assurance
range
MB89485
3.5*
5.5
V
Operation assurance
range
MB89P485
2.7*
5.5
V
Operation assurance
range
MB89PV480
1.5
5.5
V
Retains the RAM state in
stop mode
MB89485,
MB89P485,
MB89PV480
2.2*
3.6
V
Operation assurance
range
1.5
3.6
V
Retains the RAM state in
stop mode
V0 to V3
Vss
Vcc
V
TA
–40
+85
°C
VCC
AVCC
MB89485L,
MB89P485L
27
MB89480/480L Series
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, 2, 3 and
“5. A/D Converter Electrical Characteristics.”
Operating
voltage (V)
5.5
Analog accuracy
assurance range :
Vcc = AVcc =4.5V~5.5V
5.0
4.5
4.0
3.5
3.0
2.7
2.2
2.0
Main clock
operating freq. (MHz)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0 12.0 12.5
4.0
2.0
1.33
1.0
0.8
0.66
0.57
0.50
0.44
0.4
0.36 0.33 0.32
Min execution
time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89P485
Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MB89P485/485)
Operating
voltage (V)
3.6
Analog accuracy
assurance range :
Vcc = AVcc = 2.7V~3.6V
3.0
2.7
2.2
2.0
Main clock
operating freq. (MHz)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0 12.0 12.5
4.0
2.0
1.33
1.0
0.8
0.66
0.57
0.50
0.44
0.4
0.36 0.33 0.32
Min execution
time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89P485L
Figure 2 Operating Voltage vs. Main Clock Operating Frequency (MB89P485L/485L)
28
MB89480/480L Series
Operating
voltage (V)
5.5
Analog accuracy
assurance range :
Vcc = AVcc = 4.5V~5.5V
5.0
4.5
4.0
3.5
3.0
2.7
Main clock
operating Freq. (MHz)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0 12.0 12.5
4.0
2.0
1.33
1.0
0.8
0.66
0.57
0.50
0.44
0.4
0.36 0.33 0.32
Min execution
time (inst. cycle) (µs)
Figure 3 Operating Voltage vs. Main Clock Operating Frequency (MB89PV480)
Figure 1, 2 and 3 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
29
MB89480/480L Series
3. DC Characteristics
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
VIH
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P57
—
0.7 VCC
—
VCC + 0.3
V
VIHS
RST, MODE, EC1,
EC2, PWC, SCK,
SI, INT10 to INT13,
INT20 to INT27
—
0.8 VCC
—
VCC + 0.3
V
VIL
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P57
—
VSS − 0.3
—
0.3 VCC
V
VILS
RST, MODE, EC1,
EC2, PWC, SCK,
SI, INT10 to INT13,
INT20 to INT27
—
VSS − 0.3
—
0.2 VCC
V
VD
P10 to P17,
P24 to P27,
P30 to P31,
P40 to P47,
P50 to P56
“H” level
input voltage
“L” level
input voltage
Open-drain
output pin
application
voltage
“H” level
output
voltage
“L” level
output
voltage
VOH
P00 to P07,
P20 to P23
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P31,
P40 to P47,
P50 to P56, RST
VOL
—
VSS − 0.3
V
—
V3
—
—
V
MB89PV480,
MB89P485,
MB89485
2.2
—
—
V
MB89P485L,
MB89485L
—
—
0.4
V
MB89PV480,
MB89P485,
MB89485
—
—
0.4
V
MB89P485L,
MB89485L
—
—
0.4
V
MB89P485L,
MB89485L
IOL = 4.0 mA
IOL = 2.0 mA
Product with
booster
4.0
IOH = –2.0 mA
P00 to P07,
P20 to P23, RST
P10 to P17,
P24 to P27,
P30 to P31,
P40 to P47,
P50 to P56
Product without booster
VCC + 0.3
(Continued)
30
MB89480/480L Series
(Continued)
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
ILI
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P57
0.45 V < VI < VCC
−5
—
+5
µA
Open-drain
output
leakage
current
ILOD
P10 to P17,
P24 to P27,
P30 to P31,
P40 to P47,
P50 to P56
0.45 V < VI < VCC
−5
—
+5
µA
Pull-down
resistance
RDOWN
MODE
VI = VCC
25
50
100
kΩ
Except
MB89P485,
MB89P485L
RPULL
P00 to P07,
P20 to P23,
RST
kΩ
When pull-up
resistor is
selected
(except RST)
Input
leakage
current
Pull-up
resistance
FCH = 10 MHz,
tinst = 0.4 µs,
Main clock run
mode
ICC1
FCH = 10 MHz,
tinst = 6.4 µs,
Main clock run
mode
ICC2
Power
supply
current
ICCS1
ICCS2
ICCL
VI = 0.0 V
VCC
FCH = 10 MHz,
tinst = 0.4 µs,
Main clock sleep
mode
FCH = 10 MHz,
tinst = 6.4 µs,
Main clock sleep
mode
FCL = 32.768 kHz,
TA = +250C,
Sub-clock run
mode
Without
pull-up
resistor
25
50
100
—
6
13
—
3
7
—
5
10
—
4
8
MB89P485L
—
0.9
3
MB89485
—
0.4
1.5
—
0.9
3
—
0.5
2
MB89P485L
—
2
5
MB89485
—
1
2.5
—
2.5
5
—
1.2
2.5
—
0.7
2
—
0.3
1
—
0.9
2
—
0.4
1
MB89P485L
—
40
85
MB89485
—
22
50
—
400
800
—
25
50
MB89485
mA
mA
mA
MB89485L
MB89P485
MB89485L
MB89P485
MB89485L
MB89P485
MB89P485L
MB89485
mA
µA
MB89485L
MB89P485
MB89485L
MB89P485
MB89P485L
(Continued)
31
MB89480/480L Series
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
FCL = 32.768 kHz,
TA = +250C,
Sub-clock sleep mode
ICCLS
0
ICCT
Power
supply
current
TA = +25 C,
Watch mode,
Main clock stop mode
VCC
TA = +250C,
Sub-clock stop mode
ICCH
IA
A/D conversion active
AVcc
TA = +250C,
A/D conversion stop
IAH
Common
output
impedance
—
15
30
MB89485
—
7
15
—
12
30
—
7
15
MB89P485L
—
2
10
MB89485
—
1
5
—
5
15
—
1
5
MB89P485L
—
1
5
MB89485
—
0.8
4
—
3
10
—
0.8
4
MB89P485L
—
1.3
6
MB89485
—
1
3
—
1.3
6
—
1
3
MB89P485L
—
1
5
MB89485
—
0.8
4
—
1
5
—
0.8
4
µA
µA
µA
mA
µA
Segment
output
impedance
RVSEG
LCD
divided
resistance
RLCD
COM0 to
COM3
SEG0 to
SEG30
—
MB89P485
MB89485L
MB89P485
MB89485L
MB89P485
MB89485L
MB89P485
MB89485L
MB89P485
MB89P485L
MB89P485L,
MB89485L
V1 to V3 = +3.0 V
RVCOM
MB89485L
—
—
2.5
kΩ
V1 to V3 = +5.0 V
MB89PV480,
MB89P485,
MB89485
V1 to V3 = +3.0 V
MB89P485L,
MB89485L
—
—
15
kΩ
300
500
750
kΩ
V1 to V3 = +5.0 V
Between VCC and VSS
MB89PV480,
MB89P485,
MB89485
(Continued)
32
MB89480/480L Series
(Continued)
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
LCD
controller/
driver
leakage
current
Booster for
LCD driving
output
voltage
ILCDL
V0 to V3,
COM0 to
COM3,
SEG0 to
SEG30
VV3
V3
VV2
V2
Reference
input voltage
for LCD
driving
VV1
V1
Reference
voltage input
impedance
RRIN
V1
Input
CIN
capacitance
Other than
VCC, VSS,
AVCC, AVSS
—
—
±1
µA
V1 = 1.5 V
4.3
4.5
4.7
V
V1 = 1.5 V
2.9
3.0
3.1
V
—
IIN = 0.0 µA
—
f = 1 MHz
1.4
1.5
1.7
V
8.5
9.8
11
kΩ
—
5
15
pF
Products
with booster
only
33
MB89480/480L Series
4. AC Characteristics
(1) Reset Timing
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min
Max
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
Note : tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Condition
—
Value
Unit
Min
Max
—
50
ms
1
—
ms
Remarks
Due to repeated operations
Note : Make sure that power supply rises within the selected oscillation stabilization time.
Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be
varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
Vth
VCC
0.2 V
Vth = 3.5 V for MB89PV480, MB89P485 and MB89485
Vth = 1.8 V for MB89P485L and MB89485L
34
0.2 V
0.2 V
MB89480/480L Series
(3) Clock Timing
Parameter
Symbol
Pin
FCH
X0, X1
1
—
12.5
MHz
FCL
X0A, X1A
—
32.768
—
kHz
tHCYL
X0, X1
80
—
1000
ns
tLCYL
X0A, X1A
—
30.5
—
µs
PWH
PWL
X0
20
—
—
ns
PWHL
PWLL
X0A
—
15.2
—
µs
tCR
tCF
X0, X0A
—
—
10
ns
Clock frequency
Clock cycle time
Input clock pulse width
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Typ
Max
Input clock rising/falling time
Min
External clock
X0 and X1 Timing and Conditions
tHCYL
PWH
PWL
tCR
tCF
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal
or
ceramic reasonator is used
X0
When an external clock is used
X1
X0
X1
Open
FCH
C1
C2
FCH
35
MB89480/480L Series
Sub-clock Timing and Conditions
tLCYL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCR
tCF
Sub-clock Conditions
When a crystal
or
ceramic oscillator is used
X0A
When an external clock is used
X0A
X1A
FCL
X1A
Rd
When subclock is not used
X0A
Open
Open
FCL
C0
X1A
C1
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
36
Symbol
Value
Unit
Remarks
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
(4/FCH)tinst = 0.32 µs when operating
at FCH = 12.5 MHz
2/FCL
µs
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
tinst
MB89480/480L Series
(5) Serial I/O Timing
Parameter
Serial clock cycle time
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485,
AVCC = VCC = 3.0 V for MB89P485L, MB89485L
AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit
Min
Max
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Internal
shift clock
mode
SCK
External
shift clock
mode
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
37
MB89480/480L Series
Internal Clock Operation
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
SO
2.4 V
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Clock Operation
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO
2.4 V
0.8 V
tIVSH
SI
38
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB89480/480L Series
(6) Peripheral Input Timing
Parameter
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485
AVCC = VCC = 3.0 V for MB89P485L, MB89485L
AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Unit
Remarks
Min
Max
Symbol
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
INT10 to INT13,
INT20 to INT27, EC1,
EC2, PWC
2 tinst*
—
µs
2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
t IHIL1
INT10 to 13,
INT20 to INT27,
EC1, EC2,
PWC
t ILIH1
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
39
MB89480/480L Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics
( AVCC = VCC = 4.5 V to 5.5 V for MB89PV480, MB89P485, MB89485,
AVCC = VCC = 2.7 V to 3.6 V for MB89P485L, MB89485L,
AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin
Unit Remarks
Min
Typ
Max
Resolution
Total error
Linearity error
—
Differential linearity error
—
—
10
—
bit
—
—
±4.0
LSB
—
—
±2.5
LSB
—
—
±1.9
LSB
Zero transition voltage
VOT
AVSS – 1.5
LSB
AVSS + 0.5
LSB
AVSS + 2.5
LSB
mV
Full-scale transition
voltage
VFST
AVCC – 4.5
LSB
AVCC – 2.5
LSB
AVCC - 0.5
LSB
mV
A/D mode conversion time
—
—
—
60 tinst*
µs
Analog port input current
IAIN
—
—
10
µA
Analog input voltage
VAIN
AVSS
—
AVCC
V
AN0 to
AN3
* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics".
(2) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point ("00 0000 0000" ↔ "00 0000 0001")
with the full-scale transition point ("11 1111 1111" ↔ "11 1111 1110") from actual conversion characteristics.
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.
• Total error (unit: LSB)
The difference between theoretical and actual conversion values.
40
MB89480/480L Series
Theoretical I/O characteristics
3FF
Total error
3FF
VFST
3FE
3FE
004
003
Actual conversion
value
3FD
1.5 LSB
Digital output
Digital output
3FD
{1 LSB × N + VOT}
004
VNT
003
VOT
002
Actual conversion
value
002
1 LSB
Theoretical value
001
001
0.5 LSB
AVCC
AVSS
1 LSB =
Analog input
VFST – VOT
1022
Total error = VNT – {1 LSB × N + 0.5 LSB}
1 LSB
(V)
Full-scale transition error
Zero transition error
004
Theoretical value
Actual conversion
value
3FF
Actual conversion
value
Digital output
003
Digital output
AVCC
AVSS
Analog input
002
3FE
VFST
(Actual
measurement)
3FD
Actual conversion
value
001
Actual conversion value
3FC
VOT (Actual measurement)
AVCC
AVSS
Analog input
Analog input
Differential linearity error
Linearity error
Theoretical value
3FF
Actual conversion
value
3FE
N+1
{1 LSB × N + VOT}
Actual conversion
value
VNT
VFST
(Actual
measurement)
004
Digital output
Digital output
3FD
V(N + 1)T
N
N–1
003
VNT
Actual conversion value
Actual conversion value
002
Theoretical value
001
N–2
VOT (Actual measurement)
AVCC
AVSS
Analog input
Linearity error =
VNT – {1 LSB × N + VOT}
1 LSB
AVCC
AVSS
Analog input
Differential linearity error =
V(N + 1)T – VNT
1 LSB
–1
41
MB89480/480L Series
(3) Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter used for the MB89480 series contains a sample and hold circuit as illustrated below to
fetch analog input voltage into the sample and hold capacitor for 16 instruction cycles after activation A/D
conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input
voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep
the output impedance of the external circuit low.
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Analog Input Circuit Model
Sample hold circuit
Analog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
R
C
Close for 16 instruction cycles after
activating A/D conversion.
Analog channel selector
R: analog input equivalent resistance
C: analog input equivalent capacitance
42
MB89485
MB89PV480
2.2 kΩ
45 pF
MB89485L
MB89P485
MB89P485L
2.8 kΩ
46 pF
2.6 kΩ
28 pF
7.1 kΩ
48.3 pF
MB89480/480L Series
■ EXAMPLE CHARACTERISTICS
(1) "L" level output voltage
VOL vs. IOL (MB89485)
VOL [V]
VCC
3.0 V
1.2
VCC
VCC
VCC
VCC
VCC
VCC
3.5 V
4.0 V
4.5 V
5.0 V
5.5 V
6.0 V
1.0
0.8
TA
VOL vs. IOL (MB89485L)
VOL [V]
25 C
VCC
TA
0.6
0.4
2.5 V
25 C
VCC
2.0 V
0.8
0.6
VCC
3.0 V
VCC
3.5 V
VCC
4.0 V
0.4
0.2
0.2
IOL [mA]
0
2
4
6
8
IOL [mA]
0.0
0.0
0
10
2
4
6
8
10
(2) "H" level output voltage
VCC-VOH vs. IOH (MB89485)
2.0
VCC-VOH [V]
TA
VCC
3.0 V
VCC-VOH vs. IOH (MB89485L)
VCC
3.5 V
2.0
VCC-VOH [V]
25 C
TA
1.6
VCC
2.0 V
VCC
2.5 V
25 C
1.6
1.2
VCC
4.0 V
VCC
VCC
VCC
VCC
4.5 V
5.0 V
5.5 V
6.0 V
1.2
0.8
0.8
0.4
0.4
IOH [mA]
0.0
0
2
4
6
8
10
VCC
3.0 V
VCC
VCC
3.5 V
4.0 V
IOH [mA]
0.0
0
2
4
6
8
10
43
MB89480/480L Series
(3) "H" level input voltage/"L" level input voltage
CMOS input (MB89485)
CMOS hysteresis input (MB89485)
VIN [V]
4.0
VIN [V]
4.0
TA = +25 oC
TA = +25oC
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
VIHS
VILS
1
2
3
4
5
6
7
Vcc [V]
1
2
3
4
5
6
7
Vcc [V]
VIHS : Threshold when input voltage in hysteresis
characteristics is set to “H” level.
VILS : Threshold when input voltage in hysteresis
characteristics is set to “L” level.
44
MB89480/480L Series
(4) Power supply current (External clock)
ICC1 vs. VCC (MB89485)
ICC2 vs. VCC (MB89485)
ICC1 [mA]
ICC2 [mA]
10.0
1.6
TA
25 C
FCH
TA
12.5 MHz
25 C
FCH
12.5 MHz
1.2
FCH
10.0 MHz
1.0
FCH
8.0 MHz
0.6
FCH
4.0 MHz
0.4
FCH
FCH
2.0 MHz
1.0 MHz
1.4
8.0
6.0
FCH
10.0 MHz
FCH
8.0 MHz
0.8
4.0
FCH
2.0
4.0 MHz
FCH
2.0 MHz
FCH
1.0 MHz
0.0
0.2
0.0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC [V]
VCC [V]
ICCS1 vs. VCC (MB89485)
ICCS2 vs. VCC (MB89485)
ICCS1 [mA]
ICCS2 [mA]
3.5
1.2
TA
FCH
25 C
12.5 MHz
3.0
TA
25 C
FCH
12.5 MHz
FCH
10.0 MHz
FCH
8.0 MHz
FCH
4.0 MHz
FCH
FCH
2.0 MHz
1.0 MHz
1.0
FCH
10.0 MHz
FCH
8.0 MHz
2.5
0.8
2.0
0.6
1.5
FCH
4.0 MHz
FCH
FCH
2.0 MHz
1.0 MHz
1.0
0.5
0.0
0.4
0.2
0.0
1
2
3
4
5
6
7
VCC [V]
1
2
3
4
5
6
7
VCC [V]
(Continued)
45
MB89480/480L Series
(Continued)
ICC1 vs. VCC (MB89485L)
7.0
ICC2 vs. VCC (MB89485L)
ICC1 [mA]
ICC2 [mA]
1.0
TA
25 C
FCH
6.0
TA
12.5 MHz
25 C
FCH
12.5 MHz
FCH
10.0 MHz
FCH
8.0 MHz
FCH
4.0 MHz
FCH
FCH
2.0 MHz
1.0 MHz
0.8
5.0
FCH
10.0 MHz
4.0
FCH
8.0 MHz
3.0
0.6
0.4
2.0
FCH
4.0 MHz
1.0
FCH
FCH
2.0 MHz
1.0 MHz
0.2
0.0
0.0
1
2
3
5
4
1
VCC [V]
2
ICCS1 vs. VCC (MB89485L)
3
4
5
VCC [V]
ICCS2 vs. VCC (MB89485L)
ICCS1 [mA]
ICCS2 [mA]
0.7
2.4
TA
25 C
TA
2.0
FCH
12.5 MHz
1.6
FCH
10.0 MHz
FCH
8.0 MHz
1.2
25 C
0.6
FCH
12.5 MHz
0.5
FCH
10.0 MHz
0.4
FCH
8.0 MHz
FCH
4.0 MHz
FCH
FCH
2.0 MHz
1.0 MHz
0.3
0.8
0.4
FCH
4.0 MHz
0.2
FCH
FCH
2.0 MHz
1.0 MHz
0.1
0.0
0.0
1
46
2
3
4
5
VCC [V]
1
2
3
4
5
VCC [V]
MB89480/480L Series
(Continued)
ICCL vs. VCC (MB89485)
ICCT vs. VCC (MB89485)
ICCL [ A]
ICCT [ A]
2.8
60
TA
25 C
FCL
32.768 kHz
50
TA
25 C
2.4
FCL
32.768 kHz
2.0
40
1.6
30
1.2
20
0.8
10
0.4
0.0
0
1
2
3
4
5
6
7
VCC [V]
1
2
3
4
5
6
7
VCC [V]
ICCLS vs. VCC (MB89485)
ICCLS [ A]
16
TA
25 C
14
FCL
32.768 kHz
12
10
8
6
4
2
0
1
2
3
4
5
6
7
VCC [V]
47
MB89480/480L Series
(5) Pull-up resistance
RPULL vs. VCC (MB89485)
RPULL vs. VCC (MB89485L)
RPULL [k ]
200
320
RPULL [k ]
280
160
240
200
120
160
80
120
80
TA
TA
TA
40
85 C
25 C
40 C
0
1
2
3
4
5
6
7
VCC [V]
48
TA
TA
TA
40
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
85 C
25 C
40 C
5.0
VCC [V]
MB89480/480L Series
■ MASK OPTIONS
Part number
No.
MB89485
MB89485L
MB89P485 MB89P485L
MB89PV480
Setting not possible
Setting not possible
Specifying procedure
Specify when
ordering mask
1
Booster selection (KSV)
• Internal resistor ladder
• Booster
Selectable
2
Selection of OTPROM
content protection feature
• No protection feature
• With protection feature
—
101/102 : No protection
103/104 : With protection
—
3
Selection of oscillation
stabilization time (OSC)
214/FCH (approx.1.3 ms)
217/FCH (approx.10.5 ms)
218/FCH (approx.21.0 ms)
Selectable OSC
218/FCH (approx.21.0 ms)
218/FCH (approx.21.0 ms)
4
Selection of power-on
stabilization time
• Nil
• 217/FCH
Selectable
Fixed to nil
101/103 : Internal resistor 101 : Internal resistor
ladder
ladder
102/104: Booster
102: Booster
217/FCH
Fixed to nil
Fixed to nil
49
MB89480/480L Series
■ ORDERING INFORMATION
Part number
50
Package
MB89485PFM
MB89P485-101PFM
MB89P485-102PFM
MB89P485-103PFM
MB89P485-104PFM
MB89485LPFM
MB89P485L-101PFM
MB89P485L-102PFM
MB89P485L-103PFM
MB89P485L-104PFM
64-pin Plastic QFP
(FPT-64P-M09)
MB89485P-SH
MB89P485-101P-SH
MB89P485-102P-SH
MB89P485-103P-SH
MB89P485-104P-SH
MB89485LP-SH
MB89P485L-101P-SH
MB89P485L-102P-SH
MB89P485L-103P-SH
MB89P485L-104P-SH
64-pin Plastic SH-DIP
(DIP-64P-M01)
MB89PV480-101C-SH
MB89PV480-102C-SH
64-pin Ceramic MDIP
(MDP-64C-P02)
MB89PV480-101CF
MB89PV480-102CF
64-pin Ceramic MQFP
(MQP-64C-P01)
Remarks
101: With internal resistor ladder,
without content protection
102: With booster, without content
protection
103: With internal resistor ladder,
with content protection
104: With booster, with content protection
MB89480/480L Series
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
Note: Pins width and pins thickness include plating thickness.
+0.22
+.009
58.00 –0.55 2.283 –.022
INDEX-1
17.00±0.25
(.669±.010)
INDEX-2
+0.70
4.95 –0.20
+.028
.195 –.008
+0.50
0.70 –0.19
+.020
.028 –.007
0.27±0.10
(.011±.004)
+0.20
3.30 –0.30
+.008
.130 –.012
+0.40
1.378 –0.20
.0543
C
+.016
–.008
1.778(.0700)
0.47±0.10
(.019±.004)
19.05(.750)
+0.50
0.25(.010)
M
1.00 –0
.039
+.020
–.0
0~15
2001 FUJITSU LIMITED D64001S-c-4-5
Dimensions in mm (inches)
Note : The values in parenthese are reference values.
(Continued)
51
MB89480/480L Series
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar remainder.
64-pin Plastic LQFP
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8˚
64
17
1
0.65(.026)
C
"A"
16
0.32±0.05
(.013±.002)
0.13(.005)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
52
MB89480/480L Series
64-pin Ceramic MDIP
(MDP-64C-P02)
0˚~9˚
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
INDEX AREA
2.54±0.25
(.100±.010)
33.02(1.300)REF
0.25±0.05
(.010±.002)
1.27±0.25
(.050±.010)
10.16(.400)MAX
1.778±0.25
(.070±.010)
C
19.05±0.30
(.750±.012)
+0.13
0.46 –0.08
+.005
.018 –.003
55.12(2.170)REF
0.90±0.13
(.035±.005)
3.43±0.38
(.135±.015)
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
53
MB89480/480L Series
(Continued)
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
+0.40
1.20 –0.20
.047
1.00±0.25
(.039±.010)
+.016
–.008
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
1.27±0.13
(.050±.005)
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
0.40±0.10
(.016±.004)
0.30(.012)TYP
7.62(.300)TYP
18.00(.709)
TYP
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP
C
10.82(.426)
0.15±0.05 MAX
(.006±.002)
1994 FUJITSU LIMITED M64004SC-1-3
Dimensions in mm (inches)
Note : The values in parentheses are referent value.
54
MB89480/480L Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
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function and schematic diagrams, shall not be construed as license
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Fujitsu assumes no liability for any infringement of the intellectual
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The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0312
FUJITSU LIMITED Printed in Japan