FUJITSU MB89PV910

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12521-3E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89910 Series
MB89913/915/P915/PV910
■ DESCRIPTION
The MB89910 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as
dual-clock control system, five operating speed control stages, timers, a serial interface, an A/D converter, a
buzzer output, a low-voltage detection reset, high-voltage driver, a watch prescaler, and external interrupts.
The MB89910 series is applicable to a wide range of applications from consumer products to industrial
equipments.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Minimum execution time: 0.50 µs/8.0 MHz oscillation
• Interrupt processing time: 4.50 µs/8.0 MHz oscillation
• F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Bit manipulation instructions, etc.
• Dual-clock control system
(Continued)
■ PACKAGE
48-pin Plastic SH-DIP
48-pin Plastic QFP
64-pin Ceramic MDIP
(DIP-48P-M01)
(FPT-48P-M15)
(MDP-64C-P02)
MB89910 Series
(Continued)
• High-voltage ports (built-in a pull-down resistor capable)
8 ports for large current
10 ports for small current
• 8-bit PWM timer: 1 channel
• 16-bit timer/counter: 1 channel
• 21-bit timebase timer
• 8-bit serial I/O: 1 channel
• 8-bit A/D converter: 8 channels
• External interrupt
Edge detection function
Two channels, including one of which voltage can be applied from –0.3 to +7.0 V
• Low-voltage detection reset (excluding the MB89PV910)
• Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode)
• Reset output and power-on reset function
• Watch prescaler
2
MB89910 Series
■ PRODUCT LINEUP
Parameter
Partnumber
MB89915
MB89913
MB89P915
Classification
Mass production product
(mask ROM product)
ROM size
8 K × 8 bits
(internal mask
ROM)
RAM size
256 × 8 bits
CPU functions
16 K × 8 bits
(internal mask
ROM)
Timebase timer
(Timer 1)
Piggyback/
evaluation product
(for evaluation and
development)
16 K × 8 bits
32K × 8 bits
(internal PROM, (Piggyback)
programmable with (External ROM)
general-purpose
EPROM
programmer)
512 × 8 bits
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
Ports
One-time PROM
product
MB89PV910
1 K × 8 bits
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.50 µs/8.0 MHz to 8.00 µs/8.0 MHz, or
61 µs/32.768 kHz
4.5 µs/8.0 MHz to 72.0 µs/8.0 MHz, or
549.3 µs/32.768 kHz
Note: The above times depend on the gear
function.
High-voltage output ports (P-ch open-drain):
8 (P10 to P17 for large current)
10 (P20 to P27 and P50 to P51 for small current)
I/O ports (CMOS):
13 (P00 to P07, P34 to P37, and P40)
I/O ports (N-ch open-drain): 6 (P30 to P33, P41, P42)
Input ports (CMOS):
2 (P60 and P61 also serve as a subclock pin)
Total:
39
Capable of generating four different intervals at 8.0-MHz oscillation: 0.26, 0.51, 1.02,
and 524.0 ms
8-bit PWM timer (Timer 2) 8-bit timer operation (square wave output capable. Operation clock: 1, 2, 8, or 16
instruction cycles)
8-bit resolution PWM operation (Conversion cycle: 128 µs to 2.0 ms at 8.0 MHz)
16-bit timer/counter
(Timer 3)
8-bit serial I/O
8-bit A/D converter
16-bit timer operation (operating clock: 1 instruction cycle)
16-bit event counter operation (Rising/falling/both edges selectable)
8 bits
LSB first/MSB first selectable
Transfer clock (external, 4/8/16 instruction cycles)
8-bit resolution × 8 channels
A/D conversion mode (conversion time of 22.0 µs/8.0 MHz)
Sense mode (conversion time of 6.0 µs/8.0 MHz)
Continuous activation enabled by external clock or internal clock
Reference voltage input (AVR) is provided.
(Continued)
3
MB89910 Series
(Continued)
Parameter
Partnumber
MB89913
External interrupt
Low-voltage detection
reset
MB89915
MB89P915
MB89PPV910
2 independent channels (edge selection, interrupt vector, factor flag)
Rising/ falling/both edges selectable
Built-in analog noise canceller
Used also for wake-up stop/sleep modes.
(Edge detection is also permitted in stop mode.)
Continuous operation
(detection power supply voltage of 4.0±0.3 V, 3.6±0.3 V or
3.3±0.3 V)
Intermittent operation
(Activated for each watch interrupt under the dual-clock system)
Low-power consumption
(Standby mode)
Not available
Sleep mode, stop mode, and watch mode
Process
CMOS
Operating voltage*
3.8 V to 5.5 V
4.5 V to 5.5 V
EPROM for use
MBM27C256A20CZ

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
In the case of the MB89PV910, the voltage varies with the ICE or the EPROM to be connected.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB89913
MB89915
MB89P915
×
DIP-48P-M01
FPT-48P-M15
*1
MDP-64C-P02
: Available
MB89PV910
×
×
*2
×: Not available
*1: Under examination for development
*2: Available by conversion from MDIP-64 to SH-DIP-48
64SD-48SD-8L2: For conversion (MDP-64C-P02) → DIP-48P-M01
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89910 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV910, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see sections
“■ Electrical Characteristics” and “■ Example Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-down resistor for P10 to P17, P20 to P27, and for P50 to P51 cannot be set for the MB89P915 and
MB89PV910. The MB89915 and MB89913 allow a pull-down resistor to be set for individual pins. Such pins
on the MB89P915 and MB89PV910 are fixed to have no pull-down resistor.
• The low-voltage detection reset cannot be used on the MB89PV910. The voltage to be detected by the lowvoltage detection reset is set by using a register for the MB89P915 and by using a mask option for the MB89915
and MB89913. If the detection voltage has been set to a lower value than the operating voltage, however, use
the gear function to operate the device with the faster clock at a lower speed, or operate the device with the
slower clock. Note that the results of operation are unpredictable if the device is attempted to operate at a
lower voltage than the operating voltage with the faster clock put in top gear.
5
MB89910 Series
■ PIN ASSIGNMENT
(Top view)
AVSS
AVR
P37/AN7
P36/AN6
P35/AN5
P34/AN4
P33/AN3
P32/AN2
P31/AN1
P30/AN0
P07/SCK
P06/SO
P05/SI
P04/PWO
P03/EC
P02/ADST
P01/BZ2
P00
P61/X1A
P60/X0A
P42
P41/INT1
P40/INT0
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VCC
P10
P11
P12
P13
P14
P15
P16
P17
VFDP
P20
P21
P22
P23
P24
P25
P26
P27
P50
P51/BZ1
TEST
X1
X0
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(DIP-48P-M01)
48
47
46
45
44
43
42
41
40
39
38
37
P34/AN4
P35/AN5
P36/AN6
P37/AN7
AVR
AVSS
VCC
P10
P11
P12
P13
P14
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
Under examination
for development
X1A/P61
X0A/P60
P42
P41/INT1
P40/INT0
RST
V SS
X0
X1
TEST
P51/BZ1
P50
13
14
15
16
17
18
19
20
21
22
23
24
P33/AN3
P32/AN2
P31/AN1
P30/AN0
P07/SCK
P06/SO
P05/SI
P04/PWO
P03/EC
P02/ADST
P01/BZ2
P00
(FPT-48P-M15)
6
36
35
34
33
32
31
30
29
28
27
26
25
P15
P16
P17
VFDP
P20
P21
P22
P23
P24
P25
P26
P27
MB89910 Series
(Top view)
AVSS
AVR
P37/AN7
P36/AN6
P35/AN5
P34/AN4
P33/AN3
P32/AN2
P31/AN1
P30/AN0
P07/SCK
P06/SO
P05/SI
P04/PWO
P03/EC
P02/ADST
P01/BZ2
P00
P61/X1A
P60/X0A
P42
P41/INT1
P40/INT0
RST
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
92
91
90
89
88
87
86
85
84
83
82
81
80
79
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P10
P11
P12
P13
P14
P15
P16
P17
VFDP
P20
P21
P22
P23
P24
P25
P26
P27
P50
P51/BZ1
TEST
X1
X0
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(MDP-64C-P02)
7
MB89910 Series
■ PIN DESCRIPTION
Pin no.
QFP*2
MDIP*3
26
20
42
X0
27
21
43
X1
20
14
20
X0A/P60
19
13
19
X1A/P61
24
18
24
18
12
17
Circuit
type
Function
A
Main clock crystal oscillator pins
I
These pins can select either general-purpose CMOS
inputs or subclock oscillator pins by the mask options.
When these pins are used as a general-purpose input
pin, the pin is a hysteresis input with a built-in noise
canceller.
RST
C
Reset I/O pin
This pin is an N-ch open-drain output type with pull-up
resistor and a hysteresis input type. “L” is output from
this pin by an internal source. The internal circuit is
initialized by the input of “L”. This pin is with a noise
canceller.
18
P00
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller.
11
17
P01/BZ2
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as a buzzer output.
16
10
16
P02/ADST
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as the external activation
pin for the A/D converter.
15
9
15
P03/EC
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as the external clock input
for the 16-bit timer/counter.
14
8
14
P04/PWO
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as the PWM output for
the 8-bit PWM timer.
13,
12
7,
6
13,
12
P05/SI,
P06/SO
D
General-purpose CMOS I/O ports
These port inputs are a hysteresis input, with a built-in
noise canceller. Also serve as serial data outputs for
the 8-bit serial interface.
11
5
11
P07/SCK
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as the serial transfer
clock output for the 8-bit serial interface.
47 to 40
41 to 34
63 to 56
P10 to P17
G
P-ch high-voltage open-drain output ports for large
current
*1: DIP-48P-M01
*2: FPT-48P-M15
*3: MDP-64C-P02
8
Pin name
SHDIP*1
(Continued)
MB89910 Series
(Continued)
Pin no.
SHDIP*1
QFP*2
38 to 31
32 to 25
10 to 7
MDIP*3
Pin name
Circuit
type
Function
54 to 47 P20 to P27
G
P-ch high-voltage open-drain output ports for small
current
4 to 1
10 to 7
P30/AN0 to
P33/AN3
H
General-purpose N-ch open-drain I/O ports
These port inputs are a hysteresis input, each with a
built-in noise canceller. Although the pins are also
serve as an analog inputs, an analog input does not
pass through their noise cancellers.
6 to 3
48 to 45
6 to 3
P34/AN4 to
P37/AN7
F
General-purpose CMOS I/O ports
These port inputs are a hysteresis input, each with a
built-in noise canceller. Although the pins are also serve
as an analog inputs, an analog input does not pass
through their noise cancellers.
23
17
23
P40/INT0
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in noise
canceller. Also serves as an external interrupt. External
interrupt input passes through the noise canceller.
22
16
22
P41/INT1
E
General-purpose N-ch open-drain I/O port
This port input is a hysteresis input, with a built-in noise
canceller. Also serves as an external interrupt. External
interrupt input passes through the noise canceller.
21
15
21
P42
E
General-purpose N-ch open-drain I/O port
This port input is a hysteresis input, with a built-in noise
canceller.
30
24
46
P50
G
P-ch high-voltage open-drain output ports for small
current
29
23
45
P51/BZ1
G
P-ch high-voltage open-drain output port for small
current
Also serves as a buzzer output.
28
22
44
TEST
B
Operating mode selection pin
Usually, connect to VSS directly. On the product with an
EPROM, the pin is the VPP pin.
39
33
55
VFDP
—
Voltage supply pin connected to a pull-down resistor for
ports 1, 2, and 5 In products without a pull-down
resistor, in the MB89P915, and in the MB89PV910, this
pin should be left open.
(Continued)
*1: IP-48P-M01
*2: FPT-48P-M15
*3: MDP-64C-P02
9
MB89910 Series
(Continued)
Pin no.
Circuit
type
Function
QFP*2
MDIP*3
48
42
64
VCC
—
Power supply pin
25
19
32,41
VSS
—
Power supply (GND) pin
1
43
1
AVSS
—
A/D converter power supply pin
Use this pin at the same voltage as VSS.
2
44
2
AVR
—
A/D converter reference voltage input pin
*1: IP-48P-M01
*2: FPT-48P-M15
*3: MDP-64C-P02
10
Pin name
SHDIP*1
MB89910 Series
• External EPROM pins (MDIP only)
Pin no.
MDIP*
Pin name
I/O
Function
65
VPP
O
“H” level output pin
66
67
68
69
70
71
72
73
74
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
75
76
77
O1
O2
O3
I
Data input pins
78
VSS
O
Power supply (GND) pin
79
80
81
82
83
O4
O5
O6
O7
O8
I
Data input pins
84
CE
O
ROM chip enable pin
Outputs “H” during standby.
85
A10
O
Address output pin
86
OE
O
ROM output enable pin
Outputs “L” at all times.
87
88
89
A11
A9
A8
O
Address output pin
90
A13
O
91
A14
O
92
VCC
O
EPROM power supply pin
* : MDP-64C-P02
11
MB89910 Series
■ I/O CIRCUIT TYPE
Type
Circuit
A
• Main clock
At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
N-ch
Remarks
P-ch
X0
Main clock control signal
B
C
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
• CMOS hysteresis input (with a noise canceller)
R
P-ch
N-ch
Hysteresis input (with a noise canceller)
D
P-ch
• CMOS I/O
• CMOS hysteresis input (with a noise canceller)
N-ch
Hysteresis input (with a noise canceller)
E
• N-ch open-drain I/O
• CMOS hysteresis input (with a noise canceller)
N-ch
Hysteresis input (with a noise canceller)
(Continued)
12
MB89910 Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
• CMOS hysteresis input (with a noise canceller
excluding analog inputs)
P-ch
N-ch
Port
Hysteresis input (with a noise canceller)
Analog input
G
• P-ch high-voltage open-drain output
• At an output pull-down resistor of approximately
100 kΩ/5.0 V
P-ch
VFDP
H
• N-ch open-drain output
• CMOS hysteresis input (with a noise canceller
excluding analog inputs)
N-ch
Hysteresis input (with a noise canceller)
Analog input
I
Port
X1A
Hysteresis input (with a noise canceller)
N-ch
P-ch
• Subclock
The oscillation feedback resistor is built only in the
MB89PV910.
• CMOS hysteresis input (with a noise canceller)
when no subclock is being used
X0A
Subclock control signal
Port
Hysteresis input (with a noise canceller)
13
MB89910 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and
wake-up from stop mode.
14
MB89910 Series
■ PROGRAMMING TO EPROM ON THE MB89P915
The MB89P915 is an OTPROM version of the MP89910 series.
1. Features
• 16-Kbyte PROM on chip
2. Memory Space
Memory space in each mode such as 16-Kbyte PROM mode is diagrammed below.
MB89P915
EPROM mode
(Corresponding addresses on the EPROM programmer)
0000H
I/O
0080H
RAM
0280H
Not available
8000H
0000H
Not available
(Read value FFH)
Free space
(Read value FFH)
4000H
C000H
Program area
(PROM)
16 KB
FFFFH
Program area
(PROM)
16 KB
7FFFH
3. Programming to the EPROM
Since the MB89P915 requires a special method for programming to its PROM, the types of general-purpose
EPROM programmers applicable to the MB89P915 are limited. Programming to the PROM on the MB89P915
requires an EPROM programmer applicable to the MB89P915 and a dedicated adapter.
When the operating ROM area for a single chip is 16 Kbytes (C000H to FFFFH) the PROM can be programmed
as follows:
• Programming procedure
(1) Set the EPROM programmer to the MB89P195.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH. (note that addresses 0C000H to 0FFFFH
in the operation mode correspond to 4000H to 7FFFH in EPROM mode.)
(3) Program with the EPROM programmer.
15
MB89910 Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Recommended programmer manufacturer
and programmer name
Part no.
Package
Compatible socket adapter
Sun Hayato Co., Ltd.
Data I/O Co., Ltd.
UNISITE
(ver.5.0 or
later)
MB89P915P-SH
SH-DIP-48 ROM-48QF2-28DP-8L
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444
EUROPE (49)-8-985-8580
16
3900
(ver.2.8 or
later)
Recommended
2900
(ver.3.8 or
later)
MB89910 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20CZ
2. Programming Socket Adapter
Any special programming adapter is not required since the package for the EPROM to be used is DIP-28.
3. Memory Space
EPROM memory space and the memory space on the MB89PV910 are diagrammed below.
MB89PV910
0000H
I/O
0080H
RAM
0480H
Not available
MBM27C256A-20CZ
0000H
8000H
Program area
(EPROM)
32 KB
Program area
32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A-20CZ.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH. (note that addresses 08000H to 0FFFFH
in the operation mode correspond to 0000H to 7FFFH in the EPROM mode.)
(3) Program with the EPROM programmer.
17
MB89910 Series
■ BLOCK DIAGRAM
Timebase timer
Main clock
oscillator
X0
X1
Reset circuit
(Watchdog timer)
RST
VFDP
X0A/P60
X1A/P61
Subclock oscillator
(32.768 kHz)
CMOS input port
Internal bus
Port 6
Clock controller
High-voltage output
port 1
8
High-voltage output
port 2
8
High-voltage output
port 5
P10 to P17
P20 to P27
P50
P51/BZ1
Watch prescaler
Buzzer output
P01/BZ2
4
P00
N-ch open-drain I/O port
8-bit serial I/O
8-bit A/D
converter
8-bit PWM timer
CMOS I/O port
P04/PWO
16-bit timer/counter
P03/EC
N-ch open-drain output port
Port 4
RAM
External interrupt
ROM
CMOS I/O port
Other pins
VCC, VSS, TEST
P42
P41/INT1
Port 4
F2MC-8L
CPU
18
P07/SCK
P06/SO
P05/SI
Port 3
AVR
AVSS
P34/AN4 to 4
P37/AN7
P02/ADST
CMOS I/O port
Port 0
P30/AN0 to
P33/AN3
Port 3
Low-voltage
detection reset
P40/INT0
MB89910 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89910 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/
O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area.
• Memory Space
MB89P915
MB89915
MB89PV910
0000 H
I/O
I/O
0080 H
0080 H
0080 H
0100 H
Register
0200 H
I/O
RAM
512 B
RAM
1 KB
0100 H
MB89913
0000 H
0000 H
0100 H
Register
Register
0180 H
0200 H
0280 H
0480 H
Not available
Not available
Not available
8000 H
C000 H
External ROM
32 KB
FFFF H
E000 H
ROM*
16 KB
FFFF H
ROM
8 KB
FFFF H
*: This is an internal PROM on the MB89P915.
19
MB89910 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
16 bits
Initial value
: Program counter
PC
FFFDH
A
: Accumulator
T
: Temporary accumulator Indeterminate
IX
: Index register
Indeterminate
EP
: Extra pointer
Indeterminate
SP
: Stack pointer
Indeterminate
PS
: Program status
Indeterminate
I-flag = 0, IL1, 0 = 11
The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
• Structure of the Program Status Register
15
PS
14
13
12
RP
10
9
8
Vacancy Vacancy Vacancy
RP
20
11
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
MB89910 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
Lower OP codes
RP
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared
to ‘0’ at the reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low
N-flag: Set to ‘1’ if the MSB becomes to ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit
is cleared to ‘0’.
Z-flag:
Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.
V-flag:
Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to to ‘0’ if the
overflow does not occur.
C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.
21
MB89910 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit resister for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89915. The bank currently in use is indicated
by the register bank pointer (RP).
• Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
22
MB89910 Series
■ I/O MAP
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
Vacancy
03H
Vacancy
04H
Vacancy
05H
Vacancy
06H
Vacancy
07H
(R/W)
SYCC
System clock control register
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBCR
Time-base timer control register
0BH
(R/W)
WPCR
Watch prescaler control register
0CH
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 direction register
0EH
(R/W)
BUZR
Buzzer register
0FH
(R/W)
EIC
10H
(R/W)
PDR1
Port 1 data register
11H
(R/W)
PDR2
Port 2 data register
12H
(R/W)
PDR5
Port 5 data register
13H
(R)
PDR6
Port 6 data register
14H
(R/W)
PDR4
Port 4 data register
15H
(W)
DDR4
Port 4 direction register
16H
(W)
COMR
PWM compare register
17H
(R/W)
CNTR
PWM control register
18H
(R/W)
TMCR
16-bit timer control register
19H
(R/W)
TCHR
16-bit timer control register (H)
1AH
(R/W)
TCLR
16-bit timer control register (L)
External interrupt control register
Vacancy
1BH
1CH
(R/W)
SMR
Serial mode register
1DH
(R/W)
SDR
Serial data register
1EH
(R/W)
ADC1
A/D converter control register 1
1FH
(R/W)
ADC2
A/D converter control register 2
(Continued)
23
MB89910 Series
(Continued)
Address
Read/write
Register name
20H
(R/W)
ADCD
21H
A/D converter data register
Vacancy
22H
(W)
PCR
Port input control register
23H
(R/W)
LVRC
Low-voltage detection reset control register
24H to 7BH
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Note: Do not use vacancies.
24
Register description
Vacancy
MB89910 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
AVR
VSS – 0.3
VSS + 7.0
V
VPP
– 0.6
13.0
V
VFDP
VCC – 40
VCC + 0.3
V
VI1
VSS – 0.3
VCC + 0.3
V
Except P41*2
VI2
VSS – 0.3
7.0
V
P41
VO1
VSS – 0.3
VCC + 0.3
V
Except P10 to P17,
P20 to P27, P50, P51*2
VO2
VCC – 40.0
VCC + 0.3
V
P10 to P17, P20 to P27
P50, P51
“H” level total maximum output
current
∑IOH

–120
mA
“H” level total average output
current
∑IOHAV

–90
mA
Average value (operating
current × operating rate)

–12
mA
P00 to P07, P34 to P37, P40

–20
mA
P20 to P27, P50, P51

–36
mA
P10 to P17

–6
mA
P00 to P07, P34 to P37, P40
Average value (operating
current × operating rate)

–10
mA
P20 to P27, P50, P51
Average value (operating
current × operating rate)

–20
mA
P10 to P17
Average value (operating
current × operating rate)
Power supply voltage
Input voltage
Output voltage
“H” level maximum output current
“H” level average output current
IOH
IOHAV
“L” level total maximum output
current
∑IOL

36
mA
“L” level total average output
current
∑IOLAV

20
mA
“L” level maximum output current
IOL

10
mA
“L” level average output current
IOLAV

4
mA
AVR ≤ VCC + 0.3*1
Average value (operating
current × operating rate)
P00 to P07, P30 to P37,
P40 to P47
(Continued)
25
MB89910 Series
(Continued)
(AVSS = VSS = 0.0 V)
Symbol
Parameter
Value
Unit
Remarks
440
mW
SH-DIP: DIP-48-M01
—
360
mW
QFP: FPT-48-M15
Min.
Max.
—
Power consumption
PD
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
*1: Take care so that AVR does not exceed VCC + 0.3 V and VCC does not exceed VCC, such as when power is turned
on.
*2: VI and VO must not exceed VCC + 0.3 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Symbol
VCC
A/D converter reference
input voltage
AVR
High-voltage pull-down
resistor supply voltage
VFDP
Operating temperature
TA
Value
Unit
Remarks
Min.
Max.
4.5*
5.5*
V
Normal operation assurance
range*(MB89PV910)
3.8*
5.5*
V
Normal operation assurance
range*(MB89P915/915/913)
2.7
5.5
V
Watch mode, sub-RUN mode
1.5
5.5
V
Retains the RAM state in stop
mode
0.0
VCC
V
VCC – 35.0
VCC + 0.3
V
–40
+85
°C
* : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1
and “5. A/D Converter Electrical Characteristics.”
26
MB89910 Series
Figure 1
Operating Voltage vs. Main Clock Operating Frequency
6
5
Operating voltage (V)
Operation assurance range
4
3
2
1
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
2.0
1.3
1.0
0.8
0.66 0.57
0.5
0.44
0.4 (µs)
Minimum execution time (instruction cycle)
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
27
MB89910 Series
3. DC Characteristics
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
“H” level
input voltage
“L” level
input voltage
Open-drain
output pin
application
voltage
Symbol
Pin name
Condition
VIHS
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
X0, RST
X1, TEST
Input leakage
current
Pull-down
resistance
Remarks
Typ.
Max.
—
0.8 VCC
—
VCC +
0.3
V
VILS
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
X0, RST
X1, TEST
—
VSS −
0.3
—
0.2 VCC
V
VD1
P30 to P33,
P42
—
VSS −
0.3
—
VCC +
0.3
V
VD2
P41
—
VSS −
0.3
—
7.0
V
VOH1
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
IOH = –2.0 mA
2.4
—
—
V
VOH2
P20 to P27,
P50, P51
IOH = –10 mA
3.0
—
—
V
VOH3
P10 to P17
IOH = –20 mA
3.0
—
—
V
VOL1
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
IOL = 1.8 mA
—
—
0.4
V
VOL2
RST,
IOL = 4.0 mA
—
—
0.6
V
ILI1
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
0 < VI < VCC
—
—
±5
µA
ILO1
P20 to P27,
P50, P51
VI = VFDP
—
—
–10
µA
VFDP = VCC –
35.0 V
ILO2
P10 to P17
VI = VFDP
—
—
–20
µA
VFDP = VCC –
35.0 V
RPULL
RST,
VIN = 0.0 V
25
50
100
kΩ
RPD
P10 to P17,
P20 to P27,
P50, P51
Output leakage
current
Pull-up
resistance
Unit
Min.
“H” level
output voltage
“L” level
output voltage
Value
VIN = 5.0 V
50
100
150
kΩ
Excluding
P30 to P33 and
P41, P42
Assuming the
pull-down
resistor option
selected
(Continued)
28
MB89910 Series
(Continued)
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Sleep mode
ICS1
Power supply
current*1
VCC
Unit
Remarks
Typ.
Max.
—
10.0
18.0
—
9
15
mA
—
3.0
6.0
mA MB89P915
—
1.8
2.4
mA
FCH = 8 MHz
VCC = 5.0 V
tinst*2 = 0.5 µs
when A/D
conversion is
stopped
—
3
7
mA
FCH = 8 MHz
VCC = 3.8 V
tinst*2 = 8.0 µs
when A/D
conversion is
stopped
—
1.2
1.8
mA
—
1.2
3.6
mA MB89P915
—
60
180
µA
FCH = 8 MHz
VCC = 3.8 V
tinst*2 = 8.0 µs
when A/D conversion
is stopped
ICC2
Value
Min.
FCH = 8 MHz
VCC = 5.0 V
tinst*2 = 0.5 µs
when A/D conversion
is stopped
ICC1
When lowICS2
voltage
detection reset
operation is
enabled, ILVD is
added to each
ICSB
power supply
current.
Condition
FCL = 32 kHz
VCC = 3.0 V
Subclock mode
mA MB89P915
ICS3
FCL = 32 kHz
VCC = 3.0 V
Subclock sleep mode
—
32
64
µA
ICCT
FCL = 32 kHz
VCC = 3.0 V
• Watch mode
• Main clock stop
mode at dual- clock
system
—
4
20
µA
ICCA
FCH = 8 MHz
TA = +25°C
VCC = 5.0 V
tinst*2 = 0.5 µs
when A/D conversion
is activated
—
12.5
22.5
mA
MB89913/
915/PV910
MB89913/
915/PV910
MB89913/
915/PV910
(Continued)
29
MB89910 Series
(Continued)
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
ICCH
Power supply
current*1
VCC
FCL = 32.678 kHz,
VCC = 3.0 V
TA = +25°C,
• Subclock stop
mode
• Main clock stop
mode at single
clock system
Value
Min.
Typ.
Max.
—
—
10
60
120
µA
AVR
FCH = 8 MHz,
TA = +25°C,
when A/D conversion
is activated
—
200
—
µA
IRH
AVR
FCH = 8 MHz,
TA = +25°C,
when A/D conversion
is stopped
—
—
10
µA
CIN
Other than
AVSS, AVR, f = 1 MHz
VCC, and VSS
—
10
—
pF
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
Remarks
µA
—
*1: The power supply current is measured at external clock.
30
Unit
VCC = 5.0 V
TA = +25°C,
• Subclock stop
mode
• Main clock stop
mode at single
clock system
When lowvoltage
detection reset ILVD
operation is
enabled, ILVD is
added to each
power supply
current.
IR
Input
capacitance
Condition
Power
consumption
of low-voltage
detection
reset
MB89910 Series
4. AC Characteristics
(1) Reset Timing
(AVR = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Parameter
Value
Condition
Min.
Typ.
Max.
Unit
RST “L” pulse width
tZLZH
—
48 tXCYL
—
—
ns
RST noise limit width
tZLNC
—
30
50
80
ns
Remarks
Note: tXCYL is the oscillation period (1/FCH) to input to the X0.
tZLZH
tZLNC
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Condition
Value
Min.
Max.
Unit
Remarks
Power supply rising time
tR
—
—
50
ms
Power-on reset function only
Power supply cut-off time
tOFF
—
1
—
ms
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tOFF
tR
2.0 V
VCC
0.2 V
0.2 V
0.2 V
31
MB89910 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Symbol Pin name Condition
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rising/falling time
Value
Min.
Typ.
Max.
Unit
FCH
X0, X1
—
2
—
8
MHz
FCL
X0A, X1A
—
—
32.768
—
kHz
tXCYL
X0, X1
—
125
—
500
ns
tLXCYL
X0A, X1A
—
—
30.5
—
µs
PWH
PWL
X0
—
30
—
—
ns
PWHL
PWLL
X0A
—
—
15.2
—
µs
tCR
tCF
X0, X0A
—
—
—
10
ns
External clock
• X0 and X1 Timing and Conditions
tXCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Main Clock Conditions
When a crystal
or
ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
Open
C0
32
C1
Remarks
External clock
MB89910 Series
• X0A and X1A Timing and Conditions
tLXCYL
PWLL
PWHL
tCR
tCF
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Subclock Conditions
When a crystal
or
ceramic resonator is used
When a crystal
or
ceramic resonator is used
MB89PV910
MB89913/915/P915
X0A
X1A
X0A
When an external clock is used
X1A
X0A
X1A
Open
RF
RD
C0
C1
C0
C1
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
Symbol
Value (typical)
Unit
4/FCH, 8/FCH, 16/FCH, 32/FCH
µs
Operation at FCH = 8 MHz;
(4/FCH)tinst = 0.5 µs
2/FCL
µs
Operation at FCL = 32.768 kHz;
(4/FCH)tinst = 61.036 µs
tinst
Remarks
Note: When operating at 8 MHz, the cycle varies with the execution time.
33
MB89910 Series
(5) Low-voltage Detection Reset
(AVSS = VSS 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Condition
VDL1
Value
Max.
—
3.00
3.60
V
VDL2
—
3.30
3.90
V
VDL3
—
3.70
4.40
V
VDH1
—
3.10
3.80
V
VDH2
—
3.40
4.10
V
VDH3
—
3.80
4.60
V
∆V
—
0.10
—
V
Reset insensitive time
tL
—
0.3
—
µs
Reset sensitive width
tLW
—
16 tXCYL
—
ns
Reset detection delay time
tD
—
—
2.0
µs
Voltage regulation (V∆/t∆)
VCR
—
—
0.10
V/µs
Detection voltage at power
supply voltage fall
Detection voltage at power
supply voltage rise
Hysteresis width
Power supply voltage
VCC
VDH
∆V
VDL
VDH and VDL are set for
the MB89913/915 by
mask options and for
the MB89P915 by a
register.
V∆
tOSC
tD
tD
tOSC
RESET
tOSC oscillation stabilization time 218 = 32.8 ms (FCH = 8 MHz)
Power supply voltage
VCC
Remarks
t∆
RUN
t LW or less
t L or less
VDH
VDL
t
RUN
RESET
Reset not applied
34
Unit
Min.
Reset applied
t
MB89910 Series
(6) Serial I/O Timing
(AVR = VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
SCK
Serial clock “L” pulse width
tSLSH
SCK
Condition
Internal shift
clock mode
External shift
clock mode
Value
Unit
Min.
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
1/2 tinst*
—
µs
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
1/2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
35
MB89910 Series
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
SO
2.4 V
0.8 V
tIVSH
tSHIX
SI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
SI
36
MB89910 Series
(7) Peripheral Input Timing
(AVR = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Peripheral input “H” level pulse
width
Peripheral input “L” level pulse
width
Symbol
Pin name
EC, ADST
INT0, INT1
EC, ADST
INT0, INT1
tILIH
tIHIL
Value
Min.
Max.
Condition
Unit
2 tinst*
—
µs
2 tinst*
—
µs
Remarks
—
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL
tILIH
INT0, INT1
EC
ADST
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
(8) Peripheral input noise limit width
(AVR = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Peripheral input “H” level
noise limit width 1
tIHNC1
Peripheral input “L” level
noise limit width 1
tILNC1
Peripheral input “H” level
noise limit width 2
tIHNC2
Peripheral input “L” level
noise limit width 2
tILNC2
Pin name
Min.
Value
Typ.
Max.
7
15
30
ns
15
30
60
ns
7
15
30
ns
15
30
60
ns
30
50
100
ns
50
100
250
ns
30
50
100
ns
50
100
250
ns
All inputs excluding
INT1 and INT0
All inputs excluding
INT1 and INT0
Unit
INT1, INT0
INT1, INT0
Remarks
MB89PV910
MB89P915
MB89913/
915
MB89PV910
MB89P915
MB89913/
915
MB89PV910
MB89P915
MB89913/
915
MB89PV910
MB89P915
MB89913/
915
Note: The minimum rating is always cancelled, while values equal to or greater than maximum ratings are not
cancelled.
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61,
SCK, SI, EC
INT0, INT1
ADST
tIHNC1
tIHNC2
tILNC1
tILNC2
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
37
MB89910 Series
5. A/D Converter Electrical Characteristics
(VCC = +3.8 V to +5.5 V, F = 8 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Sym- Pin name
bol
Condition
Resolution
Total error
Linearity error
—
—
Differential linearity
error
Zero transition voltage
Full-scale transition
voltage
VOT
VFST
AN0 to
AN7
—
AN0 to
AN7
Interchannel disparity
A/D mode conversion
time
—
—
Sense mode
conversion time
Analog port input
current
Analog input voltage
IAIN
—
AN0 to
AN7
AVR = VCC = 5.0
V
AN0 to
AN7
—
AVR
IR
AVR
AVR = 5.0 V
Unit Remar
ks
Min.
Typ.
Max.
—
—
8
bit
—
—
±3.0
LSB
—
—
±1.0
LSB
—
—
±0.9
LSB
AVSS – 1.5
LSB
AVSS +0.5
LSB
AVR – 3.5
LSB
AVR – 1.5
LSB
AVSS + 2.5
LSB
mV
AVR +0.5
LSB
mV
—
—
1.0
LSB
—
44 tinst*
—
µs
12 tinst*
—
µs
—
—
10
µA
0.0
—
AVR
V
3.4
—
AVCC
V
—
200
—
µA
—
Reference voltage
Reference voltage
supply current
Value
* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
When the number of bits is 8, analog voltage can be divided into 28 = 256.
• Linearity error (unit: LSB)
The deviation of the straight line drawn connecting the zero transition point (“0000 0000 ” ↔ “0000 0001”) with
the full-scale transition point (“1111 1111 ” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values
38
MB89910 Series
Digital output
1111
1111
0000
0000
0000
Actual conversion value
1111
1110
•
•
•
•
•
•
•
•
•
•
•
•
•
Theoretical conversion value
(1 LSB × N + VOT)
1 LSB =
AVR
256
Linearity error =
Linearity error
Differential linearity error =
Total error =
VNT – (1 LSB × N + VOT)
1 LSB
V( N + 1 ) T – VNT – 1
1 LSB
VNT – (1 LSB × N + 0.5 LSB)
1 LSB
0010
0001
0000
VOT
VNT V(N + 1)T
VFST
Analog input
7. Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter used for the MB89910 series contains a sample hold circuit as illustrated below to fetch
analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low. If a higher accurancy is required, set the output impedance in this series
to 2 kΩ or less.
Note that if the impedance cannot be kept low output impedance, it is recommended either to use the software
to continuously activate the A/D converter for simulating longer sampling time or to connect an external
capacitor of approx. 0.1 µF to the analog input pin.
• Analog Input Equivalent Circuit
Sample hold circuit
.
C =. 33 pF
Analog input pin
Comparator
If the output
impedance of external
circuit is high, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R =. 6 kΩ
Close for 8 instruction cycles after activating
A/D conversion.
Analog channel selector
• Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
39
MB89910 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
(2) “H” Level Output Voltage
VOL vs. IOL
VCC – VOH vs. IOH
VOL (V)
VCC = 2.5 V
TA = +25°C
VCC – VOH (V)
1.0
0.9
0.5
0.7
0.4
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.6
VCC = 3.0 V
0.5
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
0.2
0.3
0.2
0.1
0.0
VCC = 2.5 V
0.8
VCC = 3.0 V
0.3
TA = +25°C
0.1
0
1
2
3
4
5
6
7
8
9
0.0
0.0
10
IOL (mA)
–0.5
–1.0
–1.5
–2.0
–2.5
(3) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)
CMOS hysteresis input
VIN (V)
5.0
4.5
TA = +25°C
4.0
3.5
VIHS
3.0
2.5
VILS
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level
40
–3.0
IOH (mA)
MB89910 Series
(4) Power Supply Current (External Clock)
ICC1 vs. VCC, ICC2 vs. VCC
ICS1 vs. VCC, ICS2 vs. VCC
ICC1,ICC2 (mA)
ICS, ICS2 (mA)
FCH = 8 MHz
TA = +25°C
16
FCH = 8 MHz
TA = +25°C
4.0
14
Divide by 4 (ICC1)
12
Divide by 4 (ICS1)
3.0
10
8
2.0
Divide by 64 (ICS2)
6
Divide by 64 (ICC2)
4
1.0
2
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
VCC (V)
ICSB vs. VCC
ICSB (µA)
200
VCC (V)
ICS3 vs. VCC
ICS3 (µA)
TA = +25°C
7.0
50
TA = +25°C
180
40
160
140
30
120
100
80
20
60
40
10
20
0
0
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
(Continued)
41
MB89910 Series
(Continued)
ICCT vs. VCC
ICCT (µA)
ICCH vs. VCC
ICCH (µA)
36
1.8
TA = +25°C
32
TA = +25°C
1.6
28
1.4
24
1.2
20
1.0
16
0.8
12
0.6
8
0.4
4
0.2
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
VCC (V)
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
50
TA = +85°C
TA = +25°C
TA = –40°C
10
42
2
3
6.0
7.0
VCC (V)
(5) Pull-up Resistance
1
5.0
4
5
6
7
VCC (V)
MB89910 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation of instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
(Continued)
43
MB89910 Series
(Continued)
Symbol
Meaning
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
Number of instructions
#:
Number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
44
MB89910 Series
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
45
MB89910 Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
(Continued)
46
MB89910 Series
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
47
48
B
C
D
E
F
MOV
CMP
ADDC SUBC
A,#d8
A,#d8
A,#d8
A,#d8
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW MOVW MOVW XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir dir,#d8 dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
5
ADDC
A
SUBC
A
XCH
XOR
AND
OR
A, T
A
A
A
MOV
MOV
CLRB
BBC
INCW
DECW MOVW MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
CLRB
BBC
INCW
DECW MOVW MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNZ
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4 R4,#d8 R4,#d8
dir: 4 dir: 4,rel
R4
R4
#4
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BZ
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5 R5,#d8 R5,#d8
dir: 5 dir: 5,rel
R5
R5
#5
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BGE
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6 R6,#d8 R6,#d8
dir: 6 dir: 6,rel
R6
R6
#6
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BLT
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7 R7,#d8 R7,#d8
dir: 7 dir: 7,rel
R7
R7
#7
rel
C
D
E
F
rel
rel
rel
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BN
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3 R3,#d8 R3,#d8
dir: 3 dir: 3,rel
R3
R3
#3
MOVW XCHW
IX,#d16
A,IX
B
MOVW
MOVW
A,@IX +d @IX +d,A
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BP
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2 R2,#d8 R2,#d8
dir: 2 dir: 2,rel
R2
R2
#2
CLRB
BBC
dir: 6 dir: 6,rel
A
MOV
CMP
@IX +d,#d8 @IX +d,#d8
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1 R1,#d8 R1,#d8
dir: 1 dir: 1,rel
R1
R1
#1
OR
A,@IX +d
9
XOR
AND
@A,IX +d A,@IX +d
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0 R0,#d8 R0,#d8
dir: 0 dir: 0,rel
R0
R0
#0
rel
MOV @IX
+d,A
8
SUBC
A,@IX +d
MOV
CMP
CLRB
BBC
MOVW MOVW MOVW XCHW
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16
A,EP
A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8
ADDC
A,@IX +d
CLRB
BBC
MOVW MOVW MOVW XCHW
dir: 4 dir: 4,rel
A,ext
ext,A A,#d16
A,PC
7
CMP
A,@IX +d
DAS
MOV
A,@IX +d
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
MOVW MOVW CLRB
BBC
INCW
DECW MOVW MOVW
CMPW ADDCW SUBCW XCHW XORW ANDW ORW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
A
A
SETC
4
A
CMP
PUSHW POPW MOV
MOVW CLRC
JMP
CALL
IX
IX
ext,A
PS,A
addr16 addr16
RORC
A
DIVU
3
CLRB
BBC
INCW
DECW JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
A
ROLC
A
SETI
7
PUSHW POPW MOV
MOVW CLRI
A
A
A,ext
A,PS
6
9
5
8
4
2
A
RETI
3
MULU
RET
2
1
SWAP
1
NOP
0
0
H
6
L
MB89910 Series
■ INSTRUCTION MAP
MB89910 Series
■ MASK OPTIONS
Part number
No.
Specifying procedure
MB89PV910
–101
–102
MB89913
MB89915
MB89P915
–101
–102
Setting not Setting not
Specify when
Setting not Setting not
possible
possible ordering masking possible
possible
1
Selection either single or
dual clock
Single-clock mode
Dual-clock mode
Single clock Dual clock
Selectable
Single clock Dual clock
2
Pull-down resistors
P17 to P10
P27 to P20
P51, P50
All pins fixed to without
pull-down resistor
Can be selected
per pin.
All pins fixed to without
pull-down resistor
3
Voltage to be detected for lowvoltage detection reset
3.3 ± 0.3 V
Cannot be used.
3.6 ± 0.3 V
4.0 ± 0.3 V
Selectable
Can be set by register.
■ ORDERING INFORMATION
Part number
MB89913P-SH
MB89915P-SH
MB89P915P-101-SH
MB89P915P-102-SH
MB89913PF
MB89915PF
MB89P915PF-101
MB89P915PF-102
MB89PV910C-101-ES-SH
MB89PV910C-102-ES-SH
Package
Remarks
48-pin Plastic SH-DIP
(DIP-48P-M01)
48-pin Plastic QFP
(FPT-48P-M15)
64-pin Ceramic MDIP
(MDP-64C-P02)
49
MB89910 Series
■ PACKAGE DIMENSIONS
48-pin Plastic SH-DIP
(DIP-48P-M01)
+0.20
43.69 –0.30
+.008
1.720 –.012
INDEX-1
13.80±0.25
(.543±.010)
INDEX-2
0.51(.020)MIN
5.25(.207)
MAX
0.25±0.05
(.010±.002)
3.00(.118)
MIN
+0.50
1.00 –0
+.020
.039 –0
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
50
1994 FUJITSU LIMITED D48002S-3C-3
0.45±0.10
(.018±.004)
15.24(.600)
TYP
15°MAX
40.894(1.610)REF
Dimensions in mm (inches)
MB89910 Series
(Continued)
48-pin Plastic QFP
(FPT-48P-M15)
36
15.30±0.40 SQ
(.602±.016)
+0.30
12.00 –0.10 SQ
+.012
.472 –.004
2.70(.106)MAX
0.05(.002)MIN
(STAND OFF)
25
37
Details of "A" part
24
0.15(.006)
8.80
(.346)
REF
13.60±0.40
(.535±.016)
0.20(.008)
0.15(.006)MAX
INDEX
0.50(.020)MAX
48
13
"A"
Details of "B" part
LEAD No.
1
0.80(.0315)TYP
12
+0.05
0.30±0.06
(.012±.002)
0.16(.006)
"B"
M
0.15 –0.01
+.002
.006 –.0004
0~10°
0.85±0.30
(.033±.012)
0.10(.004)
C
1994 FUJITSU LIMITED F48025S-1C-1
Dimensions in mm (inches)
51
MB89910 Series
(Continued)
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
2.54±0.25
(.100±.010)
33.02(1.300)REF
INDEX AREA
0.25±0.05
(.010±.002)
1.27±0.25
(.050±.010)
10.16(.400)MAX
1.778±0.25
(.070±.010)
C
52
19.05±0.30
(.750±.012)
1994 FUJITSU LIMITED M64002SC-1-4
+0.13
0.46 –0.08
+.005
.018 –.003
55.12(2.170)REF
0.90±0.13
(.035±.005)
3.43±0.38
(.135±.015)
Dimensions in mm (inches)
MB89910 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
 FUJITSU LIMITED Printed in Japan
53