FUJITSU SEMICONDUCTOR DATA SHEET DS07-16803-1E 32-bit Microcontroller CMOS FR60Lite MB91245/S Series MB91247/247S/248/248S/F248/F248S/MB91V245A ■ OVERVIEW MB91245/S series is Fujitsu’s general-purpose 32-bit RISC microcontroller, which is designed for embedded control applications that require high-speed real-time processing of consumer appliances. This microcontroller uses FR60Lite as its CPU, compatible with other products in the FR* family. This series incorporates an LCD controller and stepping motor controller. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. ■ FEATURES • FR60Lite CPU • 32-bit RISC, load/store architecture, 5-stage pipeline • Maximum operating frequency : 32 MHz (Source oscillation is 4 MHz with x8 multiplier – PLL clock multiplier system) • 16-bit fixed-length instructions (basic instructions) • Instruction execution speed : 1 instruction per cycle • Instruction set optimized for embedded application : Memory-to-memory transfer, bit manipulation, barrel shift instructions etc. • Instructions adapted for programming C language : Function entry/exit instructions, multiple-register load/store instructions. • Register interlock function : Easier assembler coding enabled • Built-in multiplier supported at the instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles (Continued) Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2006 FUJITSU LIMITED All rights reserved MB91245/S Series (Continued) • Interrupt (PC/PS save) : 6 cycles (16 priority levels) • Harvard architecture allowing program access and data access to be executed simultaneously. • Instruction set compatible with FR family • Internal Peripheral Functions • Internal ROM size & ROM type MASK ROM : 256 Kbytes (MB91248/S) / 128 Kbytes (MB91247/S) Flash Memory : 256 Kbytes • Internal RAM size : 16 Kbytes (MB91248/S, MB91F248/S) / 8 Kbytes (MB91247/S) / 32 Kbytes (MB91V245A) • General-purpose ports : up to 120 ports (includes 4 input-only ports) • 8/10-bit A/D converter (Sequential comparison type) 8/10-bit resolution : 32 channels Conversion time : 3 µs (16/32 MHz) Set the PLL multiplier and the division ratio of peripheral circuit clocks so that the above conversion time is achieved. 32 MHz : Source oscillation (4 MHz) with x8 multiplier, divided by 1 16 MHz : Source oscillation with x8 multiplier, divided by 2 • External interrupt input : 8 channels • Bit search module (for REALOS) Search function to locate the position of the first bit that changes from “1” to “0” in one word, from the MSB (Most Significant Bit) • UART (full duplex double buffer type) : 1 channel Parity enable/disable selectable Asynchronous clock operation (start-stop synchronization) and synchronous clock operation selectable Dedicated baud-rate timer (U-Timer) embedded in each channel External clock can be used as transfer clock Parity, frame, overrun error detection functions provided • LIN-UART (full duplex double buffer type) : 3 channels Synchronous/asynchronous clock operations selectable Sync-break detection Dedicated built-in baud-rate generator • Stepping motor controller (SMC) : 6 channels 8-bit PWM with 4 high-current outputs for each channel • 8/16-bit PPG timer : 8/4 channels • 16-bit reload timer : 3 channels • 16-bit free-run timer : 2 channels (ICU/OCU linkage) • 16-bit pulse width counter : 1 channel • Input capture : 4 channels (linked to ch.0 and ch.1 of free-run timer) ch.0 linked to PWC • Output compare : 2 channels (linked to ch.0 of free-run timer) • LCD controller : SEG00 to SEG31/COM0 to COM3 (shared with port) • 16-bit timebase/watch dog timer • Sound generator • Real-time clock • 32 kHz sub clock (not supported in single clock products) • C-CAN : 2 channels • Low power consumption modes : sleep mode, stop mode, watch mode • Package : LQFP-144 (FPT-144P-M08) • CMOS technology : 0.35 µm • Power supply voltage : 5 V (Internal logic : 3.3 V, I/O : 5.0 V (step-down circuit used)) 2 MB91245/S Series ■ PRODUCT LINEUP A table below shows the product lineup of the MB91245/S series. Embedded peripheral functions which are not listed are common functions. MB91V245A MB91247/S MB91248/S MB91F248/S ROM/Flash size RAM size External SRAM 128 Kbytes 256 Kbytes 256 Kbytes 32 Kbytes 8 Kbytes 16 Kbytes 16 Kbytes External interrupt 8 channels DMA Controller 5 channels A/D Converter 32 channels UART 1 channel LIN-UART 3 channels Stepping Motor Controller 6 channels 8 /16-bit PPG 8 channels/4 channels 16-bit Reload Timer 3 channels 16-bit Free Run Timer 2 channels 16-bit Pulse Width Counter 1 channel Input Capture Unit 4 channels Output Compare Unit 2 channels LCD Controller 4 COM, 32 SEG Sound Generator 1 channel Real Time Clock Yes 32 kHz Sub Clock Yes On Chip Debug Support Unit C-CAN unit Yes/No (S series) Yes/No (S series) Addr 16 bits Data 16 bits External bus Others Yes/No (S series) EVA device MASK ROM product MASK ROM product Flash memory product ⎯ DSU4 2 channels 32-message buffer 3 MB91245/S Series ■ PIN ASSIGNMENT 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P23/SEG03/A03 P22/SEG02/A02 P21/SEG01/A01 P20/SEG00/A00 PD7/COM3/PPG7 PD6/COM2/PPG5 PD5/COM1/PPG3 PD4/COM0/PPG1 PD3/IN3 PD2/TIN2/IN2 PD1/TIN1/IN1 PD0/TIN0/IN0/PWC0 PG3/TOT2/PPG6 PG2/TOT1/PPG4 PG1/TOT0/PPG2 X0 X1 VSS VCC PG0/PPG0 P47/SGO/SYSCLK P46/SGA/AS P57/OUT1/RDY P56/OUT0/WR1 P55/SCK5/WR0 P54/SOT5/RD P53/SIN5/CK1/CS3 P52/SCK4/CS2 P51/SOT4/CS1 P50/SIN4/CK0/CS0 P45/SCK3 P44/SOT3 P43/SIN3 P42/SCK0 P41/SOT0 P40/SIN0 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P73/TX1 DVCC DVSS PB0/PWM1P0 PB1/PWM1M0 PB2/PWM2P0 PB3/PWM2M0 PB4/PWM1P1 PB5/PWM1M1 PB6/PWM2P1 PB7/PWM2M1 PC0/PWM1P2 PC1/PWM1M2 PC2/PWM2P2 PC3/PWM2M2 DVCC DVSS P97/AN31 P96/AN30 P95/AN29 P94/AN28 P93/AN27 P92/AN26 P91/AN25 P90/AN24 P87/AN23 P86/AN22 P85/AN21 P84/AN20 P83/AN19 P82/AN18 P81/AN17 P80/AN16 AVCC AVRH AVSS/AVRL 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A04/SEG04/P24 A05/SEG05/P25 A06/SEG06/P26 A07/SEG07/P27 A08/SEG08/P30 A09/SEG09/P31 A10/SEG10/P32 A11/SEG11/P33 A12/SEG12/P34 A13/SEG13/P35 A14/SEG14/P36 A15/SEG15/P37 D08/SEG16/P10 D09/SEG17/P11 D10/SEG18/P12 X0A X1A VCC VSS VCC3C D11/SEG19/P13 D12/SEG20/P14 D13/SEG21/P15 D14/SEG22/P16 D15/SEG23/P17 D00/INT0/SEG24/P00 D01/INT1/SEG25/P01 D02/INT2/SEG26/P02 D03/INT3/SEG27/P03 D04/INT4/SEG28/P04 D05/INT5/SEG29/P05 D06/SEG30/P06 D07/ATG/SEG31/P07 RX0/INT6/P70 TX0/P71 RX1/INT7/P72 (FPT-144P-M08) 4 INIT MOD0 MOD1 MOD2 DVSS DVCC PE7/PWM2M5 PE6/PWM2P5 PE5/PWM1M5 PE4/PWM1P5 PE3/PWM2M4 PE2/PWM2P4 PE1/PWM1M4 PE0/PWM1P4 PA3/PWM2M3 PA2/PWM2P3 PA1/PWM1M3 PA0/PWM1P3 DVSS DVCC PF7/AN15 PF6/AN14 PF5/AN13 PF4/AN12 PF3/AN11 PF2/AN10 PF1/AN9 PF0/AN8 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 MB91245/S Series ■ PIN DESCRIPTIONS Pin no. Pin name I/O circuit type* P24 to P27 1 to 4 5 to 12 13 to 15 SEG04 to SEG07 Function General purpose I/O port pins F SEG output pin for LCDC A04 to A07 Bits 04 to 07 pins of external address bus P30 to P37 General purpose I/O port pins SEG08 to SEG15 F SEG output pins for LCDC A08 to A15 Bits 08 to 15 pins of external address bus P10 to P12 General purpose I/O port pins SEG16 to SEG18 G D08 to D10 SEG output pins for LCDC Bits 08 to 10 pins of external data bus 16 X0A B Sub clock (oscillation) input 17 X1A B Sub clock (oscillation) output 18 VCC ⎯ Power supply pins 19 VSS ⎯ GND pins 20 VCC3C ⎯ Capacitor connection pin for internal regulator P13 to P17 21 to 25 26 to 31 SEG19 to SEG23 General purpose I/O port pins G D11 to D15 Bits 11 to 15 pins of external data bus P00 to P05 General purpose I/O port pins SEG24 to SEG29 INT0 to INT5 G D00 to D05 33 34 SEG30 External interrupt input pins General purpose I/O port pin G SEG output pins for LCDC D06 Bit 06 pin of external data bus P07 General purpose I/O port pin SEG31 ATG G SEG output pin for LCDC External trigger input pin at using of A/D converter D07 Bit 07 pin of external data bus P70 General purpose I/O port pin INT6 I RX0 35 SEG output pins for LCDC Bits 00 to 05 pins of external data bus P06 32 SEG output pins for LCDC P71 TX0 External interrupt input pin RX0 input pin of CAN0 I General purpose I/O port pin TX0 output pin of CAN0 (Continued) 5 MB91245/S Series Pin no. Pin name I/O circuit type* P72 36 INT7 General purpose I/O port pin I RX1 37 P73 TX1 Function External interrupt input pin RX1 input pin of CAN1 I General purpose I/O port pin TX1 output pin of CAN1 38 DVCC ⎯ Power supply input pins for SMC 39 DVSS ⎯ GND pins for SMC 40 41 42 43 44 45 46 47 48 49 50 51 PB0 PWM1P0 PB1 PWM1M0 PB2 PWM2P0 PB3 PWM2M0 PB4 PWM1P1 PB5 PWM1M1 PB6 PWM2P1 PB7 PWM2M1 PC0 PWM1P2 PC1 PWM1M2 PC2 PWM2P2 PC3 PWM2M2 H H H H H H H H H H H H General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller 52 DVCC ⎯ Power supply input pins for SMC 53 DVSS ⎯ GND pins for SMC (Continued) 6 MB91245/S Series Pin no. Pin name I/O circuit type* P97 to P90 54 to 61 E Function General-purpose I/O port pins : Valid when analog input is prohibited AN31 to AN24 Analog input pins of A/D converter : Valid when ADER register is set to analog input P87 to P80 General-purpose I/O port pins : Valid when analog input is prohibited 62 to 69 E AN23 to AN16 Analog input pins of A/D converter : Valid when ADER register is set to analog input 70 AVCC ⎯ Analog power supply input pin for A/D converter 71 AVRH ⎯ Analog base voltage input pin for A/D converter 72 AVSS/AVRL ⎯ Analog GND/analog base low voltage input pin for A/D converter P60 to P67 73 to 80 E General-purpose I/O port pins : Valid when analog input is prohibited AN0 to AN7 Analog input pins of A/D converter : Valid when ADER register is set to analog input PF0 to PF7 General-purpose I/O port pins : Valid when analog input is prohibited 81 to 88 E AN8 to AN15 Analog input pins of A/D converter : Valid when ADER register is set to analog input 89 DVCC ⎯ Power supply input pins for SMC 90 DVSS ⎯ GND pins for SMC 91 92 93 94 95 96 97 98 PA0 PWM1P3 PA1 PWM1M3 PA2 PWM2P3 PA3 PWM2M3 PE0 PWM1P4 PE1 PWM1M4 PE2 PWM2P4 PE3 PWM2M4 H H H H H H H H General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller (Continued) 7 MB91245/S Series Pin no. 99 100 101 102 Pin name PE4 PWM1P5 PE5 PWM1M5 PE6 PWM2P5 PE7 PWM2M5 I/O circuit type* H H H H Function General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller General purpose I/O port pin PWM output pin of stepping motor controller 103 DVCC ⎯ Power supply input pins for SMC 104 DVSS ⎯ GND pins for SMC 105 MOD2 D Mode pin 2 : Used to set basic operating mode and required to be connected to VCC or VSS 106 MOD1 D Mode pin 1 : Used to set basic operating mode and required to be connected to VCC or VSS 107 MOD0 D Mode pin 0 : Used to set basic operating mode and required to be connected to VCC or VSS 108 INIT C External reset input pin General-purpose I/O port pin : Valid when UART0 data input is prohibited P40 109 I SIN0 UART0 serial data input pin, requiring output by ports to be stopped while UART0 is performing input operation, except when executed intentionally, as this input is always in use P41 General-purpose I/O port pin : Valid when UART0 data output is prohibited 110 I SOT0 P42 111 I UART0 serial data output pin : Valid when UART0 data output is permitted General-purpose I/O port pin : Valid when clock output of UART0 is prohibited SCK0 UART0 clock input and output pin for serial communication : Valid when clock output of UART0 is permitted P43 General-purpose I/O port pin : Valid when LIN-UART0 data input is prohibited 112 I SIN3 LIN-UART0 serial data input pin, requiring output by ports to be stopped while LIN-UART0 is performing input operation, except when executed intentionally, as this input is always in use P44 General-purpose I/O port pin : Valid when LIN-UART0 data output is prohibited 113 I SOT3 LIN-UART0 serial data output pin : Valid when data output of LIN-UART0 is permitted (Continued) 8 MB91245/S Series Pin no. Pin name I/O circuit type* P45 114 I SCK3 117 120 LIN-UART0 clock input and output pin for serial communication : Valid when clock output of LIN-UART0 is permitted General-purpose I/O port pin SIN4 Serial data input pin of LIN-UART1 : LIN-UART1, requiring output by ports to be stopped while LIN-UART1 is performing input operation, except when executed intentionally, as this input is always in use I CK0 External clock input pin of free-run timer 0 CS0 Output pin of chip select 0 : Valid when external bus mode is selected P51 General-purpose I/O port pin SOT4 I LIN-UART1 serial data output pin : Valid when data output of LIN-UART1 is permitted CS1 Output pin of chip select 1 : Valid when output of chip select 1 is permitted P52 General-purpose I/O port pin SCK4 I LIN-UART1 clock input and output pin for serial communication : Valid when clock output of LIN-UART1 is permitted CS2 Output pin of chip select 2 : Valid when output of chip select 2 is permitted P53 General-purpose I/O port pin SIN5 Serial data input pin of LIN-UART2 : LIN-UART2, requiring output by ports to be stopped while LIN-UART2 is performing input operation, except when executed intentionally, as this input is always in use 118 119 General-purpose I/O port pin : Valid when clock output of LIN-UART0 is prohibited P50 115 116 Function I CK1 External clock input pin of free-run timer 1 CS3 Output of chip select 3 : Valid when output of chip select 3 is permitted P54 General-purpose I/O port pin SOT5 I Serial data output pin of LIN-UART2 : Valid when data output of LIN-UART2 is permitted RD Read strobe output pin of external bus : Valid when external bus mode is selected P55 General-purpose I/O port pin SCK5 WR0 I LIN-UART2 clock input and output pin for serial communication : Valid when clock output of LIN-UART2 is permitted Write strobe output pin of external bus : Valid when WR0 output is permitted in external bus mode (Continued) 9 MB91245/S Series Pin no. Pin name I/O circuit type* P56 121 122 123 OUT0 General-purpose I/O port pin I Output compare output pin WR1 Write strobe output pin of external bus : Valid when WR1 output is permitted in external bus mode P57 General-purpose I/O port pin OUT1 J Output compare output pin RDY External ready input pin : Valid when external ready input is permitted P46 General-purpose I/O port pin SGA I Sound generator pin AS External address strobe output pin : Valid when address strobe output is permitted P47 General-purpose I/O port pin SGO 124 Sound generator pin I SYSCLK PG0 125 Function PPG0 System clock output pin : Valid when system clock output is permitted and outputs the same clock as the operating frequency of external bus (Output is stopped in STOP mode) General-purpose I/O port pin I Output of PPG timer 0 : Valid when output of PPG timer 0 is permitted 126 VCC ⎯ Power supply pins 127 VSS ⎯ GND pins 128 X1 A Main clock (oscillation) output pin 129 X0 A Main clock (oscillation) input pin PG1 130 TOT0 General-purpose I/O port pin I Output pin of PPG timer 2 : Valid when output of PPG timer 2 is permitted PPG2 PG2 131 TOT1 General-purpose I/O port pin I PG3 TOT2 PPG6 Output pin for reload timer Output pin of PPG timer 4 : Valid when output of PPG timer 4 is permitted PPG4 132 Output pin for reload timer General-purpose I/O port pin I Output pin for reload timer Output pin of PPG timer 6 : Valid when output of PPG timer 6 is permitted (Continued) 10 MB91245/S Series (Continued) Pin no. 133 Pin name I/O circuit type* PD0 General-purpose I/O port pin TIN0 Event input pin for reload timer IN0 K PD1 General-purpose I/O port pin TIN1 Event input pin for reload timer IN1 Trigger input pin of input capture 1 : This sets input capture to trigger input and is enabled when input port is set up. When set as input capture input, it requires output by ports to be stopped, except when executed intentionally, as this input is always used. PD2 General-purpose I/O port pin TIN2 Event input pin for reload timer 134 K IN2 Trigger input pin of input capture 2 : This sets input capture to trigger input and is enabled when input port is set up. When set as input capture input, it requires output by ports to be stopped, except when executed intentionally, as this input is always used. PD3 General-purpose I/O port pin IN3 Trigger input pin of input capture 3 : This sets input capture to trigger input and is enabled when input port is set up. When set as input capture input, it requires output by ports to be stopped, except when executed intentionally, as this input is always used. 135 K K PD4 to PD7 137 to 140 COM0 to COM3 General-purpose I/O port pin F PPG1, PPG3, PPG5, PPG7 SEG00 to SEG03 A00 to A03 Output pin of COM0 to COM3 of LCDC Output pin of PPG timer 1, 3, 5 and 7 : Valid when output of PPG timer 1, 3, 5 and 7 is permitted P20 to P23 141 to 144 Trigger input pin of input capture 0 : This sets input capture to trigger input and is enabled when input port is set up. When set as input capture input, it requires output by ports to be stopped, except when executed intentionally, as this input is always used. Input pin of pulse width counter 0 of PWC0 : Valid when input of pulse width counter 0 of PWC0 is permitted PWC0 136 Function General purpose I/O port pins F SEG output pins for LCDC Bits 00 to 03 pins of external address bus * : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. 11 MB91245/S Series ■ I/O CIRCUIT TYPE Group Circuit Type Remarks Clock input For high speed (source oscillation of main clock) • Oscillation circuit • Feedback resistance X0 : approx. 1 MΩ Clock input For low speed (source oscillation of sub clock) • Oscillation circuit • Feedback resistance X0A : approx. 7 MΩ X1 A X0 Standby control X1A B X0A Standby control P-ch • CMOS hysteresis input • Pull-up resistor provided • No standby control P-ch N-ch C R Digital input (Continued) 12 MB91245/S Series Group Circuit Type MASK ROM product Hysteresis input R N-ch D Flash memory product N-ch • MASK ROM product Hysteresis input Pull-down resistor provided only for MOD2 & MOD1 • Flash memory product Hysteresis input High-voltage control for Flash test provided Control N-ch N-ch R N-ch Mode input Diffused resistor P-ch Digital output N-ch E Remarks Digital output • CMOS output (4 mA) • Hysteresis (Automotive level) input (Standby control provided) • Analog input (Analog input is valid when the corresponding ADER bit is set to 1.) R Digital input Standby control Analog input • CMOS output (4 mA) • LCDC output • Hysteresis (Automotive level) input (Standby control provided) P-ch N-ch F R LCDC output R Hysteresis input Standby control (Continued) 13 MB91245/S Series Group Circuit Type • CMOS output (4 mA) • LCDC output • Hysteresis (Automotive level) input (Standby control provided) • Hysteresis (CMOS level) input (Standby control provided) P-ch N-ch R G Remarks LCDC output Hysteresis input (Automotive level) R R Hysteresis input (CMOS level) Standby control P-ch Digital output • CMOS output High current output for PWM (30 mA) • Hysteresis (Automotive level) input (Standby control provided) N-ch Digital output H R Digital input Standby control P-ch Digital output • CMOS output (4 mA) • Hysteresis (Automotive level) input (Standby control provided) N-ch I Digital output R Digital input Standby control (Continued) 14 MB91245/S Series (Continued) Group Circuit Type Remarks • CMOS output (4 mA) • Hysteresis (Automotive level) input (Standby control provided) • Hysteresis (CMOS level) input (Standby control provided) P-ch N-ch R J Hysteresis input (Automotive level) Hysteresis input (CMOS level) Standby control R • Hysteresis (Automotive level) input (Standby control provided) P-ch N-ch K R Digital input Standby control 15 MB91245/S Series ■ HANDLING DEVICES • Preventing Latch-up Latch-up may occur in a CMOS IC, if a voltage greater than VCC pin or less than VSS pin is applied to input and output pin, or if an above-rating voltage is applied between VCC and VSS. When latch-up occurs, it may significantly increase the power supply current, and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. • Treatment of Unused Input Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by performing a pull-up or pull-down with a resistance of 2 kΩ or more. An unused I/O pin should be set to the output status and left open. When set to the input status, it should be handled in the same way as an input pin. • About power supply pins If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. This device incorporates a regulator. When using the device with 5V power supply, apply that power supply to the VCC pin and always connect a 1 µF or greater capacitor to the VCC3C for the regulator. Example of power supply connection 5V VCC 5V AVCC AVRH AVSS VCC3C VSS 1 µF GND 16 MB91245/S Series • Crystal oscillator circuit Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the PC board such that X0/X1 pins, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to the ground are placed as near one another as possible. When routing the X0 and X1 signals, they should be shielded for use on the board. Caution must be taken especially when using a pin next to the X0. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout. In addition, a sub clock is required even when a dual clock product is used as a single clock product. When using MB91F248S/248S/247S, connect the X0A pin to GND and leave the X1A pin open. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. • Mode pins (MOD0 to MOD2) These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to test mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS pins is as short as possible and the connection impedance is now. • Operation at start-up Always use the INIT pin to perform a setting initialization reset (INIT) after power-on. Immediately after poweron, hold the low level input to the INIT pin for the stabilization wait time required for the oscillator circuit, to take the oscillation stabilization wait time for the oscillator circuit. For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value. • Source oscillation input upon power-on When power-on, always input the clock for the duration of the oscillation stabilization delay time. • Treatment of power supply pins on A/D converter Connect to ensure “AVCC = AVRH = VCC and AVSS = VSS” even if the A/D converter is not in use. • Power-on sequence for power supply analog input of A/D converter Always supply power to the A/D converter (AVCC and AVRH) and apply analog input (AN0 to AN 31) after turning on the digital power supply (VCC). Also, turn off the power supply for the A/D converter and analog input before turning off the digital power supply (VCC). In so doing, the power supply must be turn on and off so that AVRH does not exceed AVCC. Even when using a pin shared with analog input as an input port, ensure that the input voltage does not exceed AVCC (There is no problem in turning on or off the analog and digital power supplies at the same time). • Handling of power supply for high-current output buffer pin (DVCC, DVSS) Always apply power to high-current output buffer pins (DVCC) after turning on the digital power supply (VCC). In addition, turn off the power supply for the high-current output buffer pins before turning off the digital power supply (VCC). Apply the same power as for high-current output buffer pins even when using such pins as general-purpose ports. (There is no problem in turning on or off the power supply for the high-current output buffer pins and the digital power supply at the same time.) Always use the GND pin (DVSS) for the high-current output buffer pin at the same potential as the digital GND (VSS). 17 MB91245/S Series • About switching from main clock mode to sub clock mode or stop mode Always stop the main clock after switching the main clock mode to the sub clock mode or stop mode. Also secure the oscillation stabilization wait time when returning from the sub clock mode or stop mode to the main clock mode. • About Flash write Note that Flash write is not possible in the sub mode. 18 MB91245/S Series ■ BLOCK DIAGRAM FR 60Lite CPU core 32 32 DMAC 5 channels Bit search 32 ROM 256 Kbytes/ 128 Kbytes/ Flash 256 Kbytes Bus converter RAM 16 Kbytes/8 Kbytes X0, X1 X0A, X1A* MOD0 to MOD2 INIT 32 16 adapters Clock control 16 Interrupt controller INT0 to INT7 SIN0 SOT0 SCK0 external interrupt 8 channels UART 1 channel U-TIMER 1 channel IN0 to IN3 ICU2 ICU 4 channels ICU3 ICU0 ICU1 OUT0, OUT1 OCU OCU0 2 channels OCU1 CK0, CK1 FRT FRT0 2 channels FRT1 SGA SGO ATG AVCC/AVSS AVRH AN0 to AN31 SIN3 to SIN5 SOT3 to SOT5 SCK3 to SCK5 Sound Generator C-CAN 2 channels RX0, RX1 TX0, TX1 Port I/F PORT Reload timer 3 channels TIN0 to TIN2 TOT0 to TOT2 PWC timer 1 channel PWC0 4 channels (when set to 16 bits) 8/16-bit PPG timer PPG0 to PPG7 Real Time Clock CPU Detect Reset 6 channels Stepper Motor Controller PWM1P0 to PWM1P5 PWM1M0 to PWM1M5 PWM2P0 to PWM2P5 PWM2M0 to PWM2M5 8/10-bit 32 channels input A/D converter LIN-UART 3 channels LCD controller 32 SEG × 4 COM COM0 to COM3 SEG00 to SEG31 * : The sub clock is not supported in single clock products. 19 MB91245/S Series ■ MEMORY SPACE • Memory space The FR family has of 4 Gbytes logical address space (232 addresses) linearly accessible to the CPU space. • Direct addressing area The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during on instruction. The direct area varies depending on the size of data to be accessed as follows. → Byte data access : 000H to 0FFH → Halfword data access : 000H to 1FFH → Word data access : 000H to 3FFH 20 MB91245/S Series ■ MEMORY MAP MB91V245A Single chip mode Internal ROM External ROM external bus mode external bus mode I/O I/O I/O addressing area I/O I/O I/O Refer to “■ I/O MAP”. Access prohibited Access prohibited Access prohibited I/O (C-CAN) I/O (C-CAN) I/O (C-CAN) 0003 8000H 0004 0000H Access prohibited Access prohibited Access prohibited Internal RAM 32 KB Internal RAM 32 KB Internal RAM 32 KB 0005 0000H Access prohibited Access prohibited Emulation SRAM area Emulation SRAM area Access prohibited External area 0000 0000H Direct 0000 0400H 0001 0000H 0002 0000H 0002 01B4H Access prohibited 0008 0000H External area 0010 0000H FFFF FFFFH 21 MB91245/S Series MB91F248/S Single chip mode Internal ROM External ROM external bus mode external bus mode 0000 0000H Direct I/O I/O I/O addressing area I/O I/O I/O Refer to “■ I/O MAP”. Access prohibited Access prohibited Access prohibited I/O (C-CAN) I/O (C-CAN) I/O (C-CAN) 0003 C000H 0004 0000H Access prohibited Access prohibited Access prohibited Internal RAM 16 KB Internal RAM 16 KB Internal RAM 16 KB 0005 0000H Access prohibited Access prohibited Flash memory area 256 Kbytes Flash memory area 256 Kbytes Access prohibited External area 0000 0400H 0001 0000H 0002 0000H 0002 01B4H Access prohibited 000C 0000H 0010 0000H External area FFFF FFFFH MB91248/S Single chip mode Internal ROM External ROM external bus mode external bus mode 0000 0000H Direct I/O I/O I/O addressing area I/O I/O I/O Refer to “■ I/O MAP”. Access prohibited Access prohibited Access prohibited I/O (C-CAN) I/O (C-CAN) I/O (C-CAN) Access prohibited Access prohibited Access prohibited Internal RAM 16 KB Internal RAM 16 KB Internal RAM 16 KB Access prohibited Access prohibited MASK ROM area 256 Kbytes MASK ROM area 256 Kbytes Access prohibited External area 0000 0400H 0001 0000H 0002 0000H 0002 01B4H 0003 C000H 0004 0000H Access prohibited 0005 0000H 000C 0000H 0010 0000H External area FFFF FFFFH Note : Each mode is set depending on the mode vector fetch after INIT is negated (For mode settings, refer to “■ MODE SETTINGS”). 22 MB91245/S Series MB91247/S Single chip mode Internal ROM External ROM external bus mode external bus mode 0000 0000H Direct I/O I/O I/O addressing area I/O I/O I/O Refer to “■ I/O MAP”. Access prohibited Access prohibited Access prohibited 0000 0400H 0001 0000H 0002 0000H 0002 01B4H 0003 E000H 0004 0000H I/O (C-CAN) I/O (C-CAN) I/O (C-CAN) Access prohibited Access prohibited Access prohibited Internal RAM 8 KB Internal RAM 8 KB Internal RAM 8 KB Access prohibited Access prohibited MASK ROM area 128 Kbytes MASK ROM area 128 Kbytes Access prohibited External area Access prohibited 0005 0000H 000E 0000H 0010 0000H External area FFFF FFFFH Note : Each mode is set depending on the mode vector fetch after INIT is negated (For mode settings, refer to “■ MODE SETTINGS”). 23 MB91245/S Series ■ MODE SETTINGS The FR family, sets the operation mode using mode pins (MOD2 to MOD0) and mode data. • Mode pins The mode pins (MOD2 to MOD0) specify how the mode vector fetch and reset vector fetch is performed. Other settings than these in the table are prohibited. Mode pin Mode name MOD2 MOD1 MOD0 Reset vector access area 0 0 0 Internal ROM mode vector Internal 0 0 1 External ROM mode vector External • Mode data Data written to the internal mode register (MODR) by mode vector fetch is called mode data. After an operating mode has been set in the mode register the device operates in that operating mode. The mode data is set by all reset sources. User programs cannot set data to the mode register. Detailed description of mode data bit 31 30 29 28 27 26 25 24 0 0 0 0 0 1 1 1 Operating mode setting bits Bit 31 to bit 24 are reserved. Always set the value to “00000111B”. Normal operation is not guaranteed when a value other than “00000111B” is set. Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8H. Place the data in the most significant byte from bit 31 to bit 24 as the FR family uses the big endian system for byte endian. bit Incorrect Correct 24 23 16 15 8 7 0 0x000FFFF8H XXXXXXXX XXXXXXXX XXXXXXXX Mode Data 0x000FFFF8H Mode Data XXXXXXXX XXXXXXXX XXXXXXXX 0x000FFFFCH 24 31 Reset vector MB91245/S Series ■ I/O MAP The following table shows the correspondence between the memory space area and each register of the peripheral resource. [How to read the map] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B XXXXXXXX PDR1 [R/W] B XXXXXXXX PDR2 [R/W] B XXXXXXXX PDR3 [R/W] B XXXXXXXX Block T-unit Port data register Read/Write attribute, Access unit (B : byte, H : halfword, W : word) Initial value after reset Register name (First-column register at address 4n; second-column register at 4n + 1, etc.) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : “ 1 ” : Initial value “1” “ 0 ” : Initial value “0” “ X ” : Initial value “undefined” “-” : No physical register present at this location Access by any undescribed data access attribute is prohibited. 25 MB91245/S Series Address Register +0 +1 +2 +3 00000000H PDR0 [R/W] B, H XXXXXXXX PDR1 [R/W] B, H XXXXXXXX PDR2 [R/W] B, H 00000000 PDR3 [R/W] B, H XXXX0000 00000004H PDR4 [R/W] B, H XXXXXXXX PDR5 [R/W] B, H XXXXXXXX PDR6 [R/W] B, H XXXXXXXX PDR7 [R/W] B, H ----XXXX 00000008H PDR8 [R/W] B, H XXXXXXXX PDR9 [R/W] B, H XXXXXXXX PDRA [R/W] B, H ----XXXX PDRB [R/W] B, H XXXXXXXX 0000000CH PDRC [R/W] B, H ----XXXX PDRD [R/W] B, H 0000XXXX PDRE [R/W] B, H XXXXXXXX PDRF [R/W] B, H XXXXXXXX 00000010H PDRG [R/W] B, H ----XXXX ⎯ 00000040H EIRR0 [R/W] B, H, W ENIR0 [R/W] B, H, W 00000000 00000000 00000044H DICR [R/W] B, H, W -------0 Reserved ELVR0 [R/W] B, H, W 00000000 00000000 External Interrupt Control (INT0 to INT7) ⎯ Delay Interrupt Module HRCL [R/W] B 0--11111 TMRLR0 [W] H, W XXXXXXXX XXXXXXXX TMR0 [R] H, W XXXXXXXX XXXXXXXX 0000004CH ⎯ TMCSR0 [R/W] B, H, W ----0000 00000000 00000050H TMRLR1 [W] H, W XXXXXXXX XXXXXXXX TMR1 [R] H, W XXXXXXXX XXXXXXXX 00000054H ⎯ TMCSR1 [R/W] B, H, W ----0000 00000000 00000058H TMRLR2 [W] H, W XXXXXXXX XXXXXXXX TMR2 [R] H, W XXXXXXXX XXXXXXXX ⎯ TMCSR2 [R/W] B, H, W ----0000 00000000 0000005CH 00000060H 00000064H SSR [R/W] B, H, W 00001000 00001000 SIDR [R/W] B, H, W XXXXXXXX UTIM [R] H (UTIMR [W] H) 00000000 00000000 00000068H to 0000008CH 00000090H 00000094H SGDBL [R/W] B -------0 Reload Timer 0 Reload Timer 1 Reload Timer 2 SCR [R/W] B, H, W 00000100 SMR [R/W] B, H, W 00--0-0- UART0 DRCL [W] B -------- UTIMC [R/W] B 0--00001 U-TIMER0 ⎯ ⎯ Port Data Register ⎯ 00000014H to 0000003CH 00000048H Block Reserved SGCR [R/W] B, H, W 0-----00 000--000 SGAR [R/W] B, H, W SGFR [R/W] B, H, W SGTR [R/W] B, H, W SGDR [R/W] B, H, W 00000000 XXXXXXXX XXXXXXXX XXXXXXXX Sound Generator (Continued) 26 MB91245/S Series Address Register +0 +1 +2 +3 00000098H LCDCMR [R/W] B, H, W ----0000 ⎯ LCR0 [R/W] B, H, W 00010000 LCR1 [R/W] B, H, W 00000000 0000009CH VRAM0 [R/W] B, H, W XXXXXXXX VRAM1 [R/W] B, H, W XXXXXXXX VRAM2 [R/W] B, H, W XXXXXXXX VRAM3 [R/W] B, H, W XXXXXXXX 000000A0H VRAM4 [R/W] B, H, W XXXXXXXX VRAM5 [R/W] B, H, W XXXXXXXX VRAM6 [R/W] B, H, W XXXXXXXX VRAM7 [R/W] B, H, W XXXXXXXX 000000A4H VRAM8 [R/W] B, H, W XXXXXXXX VRAM9 [R/W] B, H, W XXXXXXXX VRAM10 [R/W] B, H, W XXXXXXXX VRAM11 [R/W] B, H, W XXXXXXXX 000000A8H VRAM12 [R/W] B, H, W XXXXXXXX VRAM13 [R/W] B, H, W XXXXXXXX VRAM14 [R/W] B, H, W XXXXXXXX VRAM15 [R/W] B, H, W XXXXXXXX 000000A8H to 000000AFH 000000B0H 000000B4H 000000B8H 000000BCH 000000C0H 000000C4H ⎯ ECCR3 [R/W] B, H, W 000000XX BGR13 [R/W] B, H, W XXXXXXXX SCR4 [R/W] B, H, W SMR4 [R/W] B, H, W SSR4 [R/W] B, H, W 00000000 00000000 00001000 ESCR4 [R/W] B, H, W 00000X00 ECCR4 [R/W] B, H, W 000000XX BGR14 [R/W] B, H, W XXXXXXXX SCR5 [R/W] B, H, W SMR5 [R/W] B, H, W SSR5 [R/W] B, H, W 00000000 00000000 00001000 ESCR5 [R/W] B, H, W 00000X00 ECCR5 [R/W] B, H, W 000000XX 000000C8H to 000000D0H LCD Controller Driver Reserved SCR3 [R/W] B, H, W SMR3 [R/W] B, H, W SSR3 [R/W] B, H, W 00000000 00000000 00001000 ESCR3 [R/W] B, H, W 00000X00 Block BGR15 [R/W] B, H, W XXXXXXXX RDR3/TDR3 [R/W] B, H, W -------BGR03 [R/W] B, H, W XXXXXXXX RDR4/TDR4 [R/W] B, H, W -------BGR04 [R/W] B, H, W XXXXXXXX RDR5/TDR5 [R/W] B, H, W -------BGR05 [R/W] B, H, W XXXXXXXX ⎯ LIN-UART0 LIN-UART1 LIN-UART2 Reserved 000000D4H TCDT0 [R/W] H, W 00000000 00000000 ⎯ TCCS0 [R/W] B, H, W 00000000 16-bit Free Run Timer0 000000D8H TCDT1 [R/W] H, W 00000000 00000000 ⎯ TCCS1 [R/W] B, H, W 00000000 16-bit Free Run Timer1 (Continued) 27 MB91245/S Series Address Register +0 +1 +2 000000DCH to 000000E0H 000000E4H ⎯ IPCP1 [R] H, W XXXXXXXX XXXXXXXX 000000E8H ⎯ 000000ECH IPCP3 [R] H, W XXXXXXXX XXXXXXXX IPCP0 [R] H, W XXXXXXXX XXXXXXXX ICS01 [R/W] B, H, W 00000000 IPCP2 [R] H, W XXXXXXXX XXXXXXXX ICS23 [R/W] B, H, W 00000000 000000F4H to 00000104H ⎯ OCCP1 [R/W] H, W XXXXXXXX XXXXXXXX ⎯ PWCSR0 [R/W] B, H, W 0000000X 00000000 ⎯ ⎯ 16-bit PWC PDIVR0 [R/W] B, H, W -----000 ⎯ ⎯ 00000144H ⎯ 00000148H ⎯ 0000014CH WTHR [R/W] B, H ---XXXXX 00000154H Reserved PWCR0 [R] H, W 00000000 00000000 0000013CH to 00000140H 00000150H 16-bit Output Compare OCS01 [R/W] B, H, W 11101100 00001100 ⎯ 00000134H 00000138H WTDBL [R/W] B -------0 Reserved WTCR [R/W] B, H 00000000 000-00-0 Real Time Clock WTBR [R/W] B ---XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] B, H --XXXXXX ADERH [R/W] B, H, W 00000000 00000000 ADCS1 [R/W] B, H, W 00000000 16-bit Input Capture 2, 3 Reserved ⎯ 00000114H to 0000012CH 00000130H 16-bit Input Capture 0, 1 OCCP0 [R/W] H, W XXXXXXXX XXXXXXXX 0000010CH 00000110H Block Reserved ⎯ 000000F0H 00000108H +3 ADCS0 [R/W] B, H, W 00000000 WTSR [R/W] B --XXXXXX ⎯ ADERL [R/W] B, H, W 00000000 00000000 ADCR1 [R] B, H, W ------XX ADCR0 [R] B, H, W XXXXXXXX A/D Converter (Continued) 28 MB91245/S Series Address 00000158H Register +0 +1 +2 +3 ADCT1 [R/W] B, H, W 00010000 ADCT0 [R/W] B, H, W 00101100 ADSCH [R/W] B, H, W ---00000 ADECH [R/W] B, H, W ---00000 0000015CH CUCR [R/W] B, H, W -------- ---0--00 CUTD [R/W] B, H, W 10000000 00000000 00000160H CUTR1 [R] B, H, W -------- 00000000 CUTR2 [R] B, H, W 00000000 00000000 00000164H PWC20 [R/W] B, H, W XXXXXXXX PWC10 [R/W] B, H, W XXXXXXXX ⎯ Reserved 00000168H ⎯ PWC0 [R/W] B -0000--0 PWS20 [R/W] B, H, W -0000000 PWS10 [R/W] B, H, W --000000 0000016CH PWC21 [R/W] B, H, W XXXXXXXX PWC11 [R/W] B, H, W XXXXXXXX 00000170H ⎯ PWC1 [R/W] B -0000--0 00000174H PWC22 [R/W] B, H, W XXXXXXXX PWC12 [R/W] B, H, W XXXXXXXX 00000178H ⎯ PWC2 [R/W] B -0000--0 0000017CH PWC23 [R/W] B, H, W XXXXXXXX PWC13 [R/W] B, H, W XXXXXXXX 00000180H ⎯ PWC3 [R/W] B -0000--0 00000184H PWC24 [R/W] B, H, W XXXXXXXX PWC14 [R/W] B, H, W XXXXXXXX 00000188H ⎯ PWC4 [R/W] B -0000--0 0000018CH PWC25 [R/W] B, H, W XXXXXXXX PWC15 [R/W] B, H, W XXXXXXXX 00000190H ⎯ PWC5 [R/W] B -0000--0 Block A/D Converter Clock Caliblator ⎯ PWS11 [R/W] B, H, W --000000 PWS21 [R/W] B, H, W -0000000 ⎯ PWS22 [R/W] B, H, W -0000000 PWS12 [R/W] B, H, W --000000 Stepping Motor Controller ⎯ PWS13 [R/W] B, H, W --000000 PWS23 [R/W] B, H, W -0000000 ⎯ PWS24 [R/W] B, H, W -0000000 PWS14 [R/W] B, H, W --000000 ⎯ PWS25 [R/W] B, H, W -0000000 PWS15 [R/W] B, H, W --000000 (Continued) 29 MB91245/S Series Address Register +0 +1 00000194H to 000001A4H 000001A8H +2 +3 ⎯ CANPRE [R/W] B, H, W 00000000 Reserved CAN Prescaler ⎯ Reserved ⎯ 000001ACH Block Reserved 000001B0H ⎯ TRG [R/W] B, H, W 00000000 ⎯ REVC [R/W] B, H, W 00000000 000001B4H PRLH0 [R/W] B, H, W XXXXXXXX PRLL0 [R/W] B, H, W XXXXXXXX PRLH1 [R/W] B, H, W XXXXXXXX PRLL1 [R/W] B, H, W XXXXXXXX 000001B8H PRLH2 [R/W] B, H, W XXXXXXXX PRLL2 [R/W] B, H, W XXXXXXXX PRLH3 [R/W] B, H, W XXXXXXXX PRLL3 [R/W] B, H, W XXXXXXXX 000001BCH PPGC0 [R/W] B, H, W 0000000X PPGC1 [R/W] B, H, W 0000000X PPGC2 [R/W] B, H, W 0000000X PPGC3 [R/W] B, H, W 0000000X 000001C0H PRLH4 [R/W] B, H, W XXXXXXXX PRLL4 [R/W] B, H, W XXXXXXXX PRLH5 [R/W] B, H, W XXXXXXXX PRLL5 [R/W] B, H, W XXXXXXXX 000001C4H PRLH6 [R/W] B, H, W XXXXXXXX PRLL6 [R/W] B, H, W XXXXXXXX PRLH7 [R/W] B, H, W XXXXXXXX PRLL7 [R/W] B, H, W XXXXXXXX 000001C8H PPGC4 [R/W] B, H, W 0000000X PPGC5 [R/W] B, H, W 0000000X PPGC6 [R/W] B, H, W 0000000X PPGC7 [R/W] B, H, W 0000000X 000001CCH to 000001FCH ⎯ 00000200H DMACA0 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX 00000204H DMACB0 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX 00000208H DMACA1 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX 0000020CH DMACB1 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX 00000210H DMACA2 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX 00000214H DMACB2 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX PPG0 PPG0 Reserved DMAC (Continued) 30 MB91245/S Series Address Register +0 +1 +2 +3 Block 00000218H DMACA3 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX 0000021CH DMACB3 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX 00000220H DMACA4 [R/W] B, H, W *1 00000000 0000XXXX XXXXXXXX XXXXXXXX 00000224H DMACB4 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX 00000228H to 0000023CH ⎯ 00000240H DMACR [R/W] B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX 00000244H to 000003ECH ⎯ 000003F0H BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000003F4H BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000003F8H BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000003FCH BSRR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000400H DDR0 [R/W] B, H, W DDR1 [R/W] B, H, W DDR2 [R/W] B, H, W DDR3 [R/W] B, H, W 00000000 00000000 11111111 00001111 00000404H DDR4 [R/W] B, H, W DDR5 [R/W] B, H, W DDR6 [R/W] B, H, W DDR7 [R/W] B, H, W 00000000 00000000 00000000 ----0000 00000408H DDR8 [R/W] B, H, W DDR9 [R/W] B, H, W DDRA [R/W] B, H, W DDRB [R/W] B, H, W Port Direction Register 00000000 00000000 ----0000 00000000 0000040CH DDRC [R/W] B, H, W DDRD [R/W] B, H, W DDRE [R/W] B, H, W DDRF [R/W] B, H, W ----0000 1111---00000000 00000000 00000410H DDRG [R/W] B, H, W ----0000 DMAC Reserved Bit Search Module ⎯ 00000414H to 0000041CH ⎯ 00000420H PFR0 [R/W] B, H, W PFR1 [R/W] B, H, W PFR2 [R/W] B, H, W PFR3 [R/W] B, H, W 00000000 00000000 00000000 00000000 00000424H PFR4 [R/W] B, H, W PFR5 [R/W] B, H, W 00000000 00000000 Reserved ⎯ PFR7 [R/W] B, H, W ----0000 Port Function Register (Continued) 31 MB91245/S Series Address Register +0 +1 ⎯ 00000428H +2 +3 PFRA [R/W] B, H, W PFRB [R/W] B, H, W ----0000 00000000 0000042CH PFRC [R/W] B, H, W PFRD [R/W] B, H, W PFRE [R/W] B, H, W ----0000 00000000 00000000 00000430H PFRG [R/W] B, H, W ----0000 ⎯ ⎯ 00000440H ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000444H ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000448H ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 0000044CH ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000450H ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000454H ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000458H ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 0000045CH ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000460H ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000464H ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000468H ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 0000046CH ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W ---11111 ---11111 ---11111 ---11111 00000470H to 0000047CH ⎯ 00000484H 00000488H Reserved CTBR [W] B, H, W XXXXXXXX WPR [R/W] B, H, W DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W XXXXXXXX 00000011 00000000 ⎯ Interrupt Control Unit Reserved RSRR [R/W] B, H, W STCR [R/W] B, H, W TBCR [R/W] B, H, W 10000000 00110011 00XXXX11 CLKR [W] B, H, W 00000000 Port Function Register ⎯ 00000434H to 0000043CH 00000480H Block OSCCR [R/W] B X000XXX0 Clock Control Unit ⎯ (Continued) 32 MB91245/S Series Address Register +0 +1 OSCR [R/W] B 000--001 ⎯ PSCR [W] B XXXXXXXX 00000540H 00000544H ⎯ PILR5 [R/W] B, H, W 0------- ⎯ ⎯ 00000554H to 00000578H ⎯ Reserved LVRC [R/W] B, H, W 00011000 00000580H to 000005FCH Port Input Level Select Register Reserved Reserved Reserved ⎯ EPFR4 [R/W] B, H, W 00000000 CPU Detection of operation Reserved EPFR2 [R/W] B, H, W 00000000 ⎯ 00000600H EPFR5 [R/W] B, H, W 00000000 EPFR3 [R/W] B, H, W 00000000 ⎯ Extended Port Function Register ⎯ 00000608H 0000060CH ⎯ 00000610H EPFRG [R/W] B, H, W ----0000 00000614H to 0000063CH Reserved PILR0 [R/W] B, H, W PILR1 [R/W] B, H, W 00000000 00000000 ⎯ 00000604H Port Input Level Select Register ⎯ 00000548H to 00000550H 0000057CH Reserved ⎯ 00000500H to 0000053CH Block Clock Control Unit ⎯ 00000494H to 000004F8H 000004FCH +3 ⎯ 0000048CH 00000490H +2 EPFRD [R/W] B, H, W 00000000 ⎯ ⎯ ⎯ Extended Port Function Register Reserved (Continued) 33 MB91245/S Series Address Register +0 +1 +2 +3 00000640H ASR0 [R/W] B, H, W 00000000 00000000 ACR0 [R/W] B, H, W 1111XX00 00000000 00000644H ASR1 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR1 [R/W] B, H, W XXXXXXXX XXXXXXXX 00000648H ASR2 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR2 [R/W] B, H, W XXXXXXXX XXXXXXXX 0000064CH ASR3 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR3 [R/W] B, H, W XXXXXXXX XXXXXXXX 00000650H to 0000065CH AWR0 [R/W] B, H, W 01110000 01011011 AWR1 [R/W] B, H, W XXXX0000 XX0X1XXX 00000664H AWR2 [R/W] B, H, W 0XXX0000 XX0X1XXX AWR3 [R/W] B, H, W 0XXX0000 0X0X1XXX 00000668H to 0000067CH ⎯ CSER [R/W] B, H, W XXXX0001 Reserved External Bus Control Unit ⎯ 00000684H to 000007F8H 000007FCH External Bus Control Unit ⎯ 00000660H 00000680H Block ⎯ ⎯ Reserved ⎯ MODR *2 00000800H to 00000FFCH ⎯ 00001000H DMASA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001004H DMADA0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001008H DMASA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000100CH DMADA1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001010H DMASA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001014H DMADA2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001018H DMASA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Mode register Reserved DMAC (Continued) 34 MB91245/S Series Address Register +0 +1 +2 +3 0000101CH DMADA3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001020H DMASA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001024H DMADA4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001028H to 00006FFCH ⎯ DMAC Reserved 00007000H FLCR [R/W] 01XX1000 ⎯ 00007004H FLWC [R/W] 00000011 ⎯ 00007008H to 0000FFFCH Block Flash I/F (Only Mass Production Product) ⎯ Reserved 00020000H CTRLR0 STATR0 00020004H ERRCNT0 BTR0 00020008H INTR0 TESTR0 0002000CH BRPER0 ⎯ 00020010H IF1CREQ0 IF1CMSK0 00020014H IF1MSK20 IF1MSK10 00020018H IF1ARB20 IF1ARB10 0002001CH IF1MCTR0 ⎯ 00020020H IF1DTA10 IF1DTA20 00020024H IF1DTB10 IF1DTB20 00020028H, 0002002CH ⎯ 00020030H Reserved (IF1 data A mirror, little endian byte ordering) 00020034H Reserved (IF1 data B mirror, little endian byte ordering) 00020038H, 0002003CH ⎯ CAN0 00020040H IF2CREQ0 IF2CMSK0 00020044H IF2MSK20 IF2MSK10 00020048H IF2ARB20 IF2ARB10 0002004CH IF2MCTR0 ⎯ 00020050H IF2DTA10 IF2DTA20 00020054H IF2DTB10 IF2DTB20 (Continued) 35 MB91245/S Series Address Register +0 +1 +2 +3 00020058H, 0002005CH ⎯ 00020060H Reserved (IF2 data A mirror, little endian byte ordering) 00020064H Reserved (IF2 data B mirror, little endian byte ordering) 00020068H, 0002007CH ⎯ 00020080H TREQR20 TREQR10 00020084H Reserved ( > 32..128 Message buffer) 00020088H, 0002008CH ⎯ 00020090H NEWDT20 NEWDT10 00020094H Reserved ( > 32..128 Message buffer) 00020098H, 0002009CH ⎯ 000200A0H INTPEND20 CAN0 INTPEND10 000200A4H Reserved ( > 32..128 Message buffer) 000200A8H, 000200ACH ⎯ 000200B0H Block MESVAL20 MESVAL10 000200B4H Reserved ( > 32..128 Message buffer) 000200B8H, 000200FCH ⎯ 00020100H CTRLR1 STATR1 00020104H ERRCNT1 BTR1 00020108H INTR1 TESTR1 0002010CH BRPER1 ⎯ 00020110H IF1CREQ1 IF1CMSK1 00020114H IF1MSK21 IF1MSK11 00020118H IF1ARB21 IF1ARB11 0002011CH IF1MCTR1 ⎯ 00020120H IF1DTA11 IF1DTA21 00020124H IF1DTB11 IF1DTB21 00020128H, 0002012CH ⎯ 00020130H Reserved (IF1 data A mirror, little endian byte ordering) 00020134H Reserved (IF1 data B mirror, little endian byte ordering) 00020138H, 0002013CH ⎯ CAN1 (Continued) 36 MB91245/S Series (Continued) Address Register +0 +1 +2 +3 00020140H IF2CREQ1 IF2CMSK1 00020144H IF2MSK21 IF2MSK11 00020148H IF2ARB21 IF2ARB11 0002014CH IF2MCTR1 ⎯ 00020150H IF2DTA11 IF2DTA21 00020154H IF2DTB11 IF2DTB21 00020158H, 0002015CH ⎯ 00020160H Reserved (IF2 data A mirror, little endian byte ordering) 00020164H Reserved (IF2 data B mirror, little endian byte ordering) 00020168H, 0002017CH ⎯ 00020180H TREQR21 TREQR11 00020184H Reserved ( > 32..128 Message buffer) 00020188H, 0002018CH ⎯ 00020190H NEWDT21 Reserved ( > 32..128 Message buffer) 00020198H, 0002019CH ⎯ INTPND21 INTPND11 000201A4H Reserved ( > 32..128 Message buffer) 000201A8H, 000201ACH ⎯ 000201B0H CAN1 NEWDT11 00020194H 000201A0H Block MESVAL21 MESVAL11 000201B4H Reserved ( > 32..128 Message buffer) 000201B8H, 000201FCH ⎯ 00038000H to 003FFFFCH ⎯ F-bus RAM 32 Kbytes 0003C000H to 003FFFFCH ⎯ F-bus RAM 16 Kbytes 0003E000H to 003FFFFCH ⎯ F-bus RAM 8 Kbytes *1 : The lower 16 bits (DTC [15 : 0]) of DMACA0 to DMACA4 cannot be accessed in bytes. *2 : This register is set by a mode vector fetch and cannot be accessed by the user. 37 MB91245/S Series Address Register +0 +1 000C0000H to 000FFFFCH Address 000E0000H to 000FFFFCH 38 +2 +3 User ROM 256 Kbytes (Only Mass Production Product) ⎯ Register +0 +1 +2 ⎯ Block +3 Block User ROM 128 Kbytes (MB91247) MB91245/S Series ■ VECTOR TABLE Interrupt number Interrupt source Interrupt level Offset TBR default address DMA start source Decimal Hexadecimal Reset 0 00 ⎯ 3FCH 000FFFFCH ⎯ Mode vector 1 01 ⎯ 3F8H 000FFFF8H ⎯ System reserved 2 02 ⎯ 3F4H 000FFFF4H ⎯ System reserved 3 03 ⎯ 3F0H 000FFFF0H ⎯ System reserved 4 04 ⎯ 3ECH 000FFFECH ⎯ System reserved 5 05 ⎯ 3E8H 000FFFE8H ⎯ System reserved 6 06 ⎯ 3E4H 000FFFE4H ⎯ Coprocessor absent trap 7 07 ⎯ 3E0H 000FFFE0H ⎯ Coprocessor error trap 8 08 ⎯ 3DCH 000FFFDCH ⎯ INTE instruction 9 09 ⎯ 3D8H 000FFFD8H ⎯ System reserved 10 0A ⎯ 3D4H 000FFFD4H ⎯ System reserved 11 0B ⎯ 3D0H 000FFFD0H ⎯ Step trace trap 12 0C ⎯ 3CCH 000FFFCCH ⎯ NMI request (ICE) 13 0D ⎯ 3C8H 000FFFC8H ⎯ Undefined instruction exception 14 0E ⎯ 3C4H 000FFFC4H ⎯ NMI instruction 15 0F 15 (FH) Fixed 3C0H 000FFFC0H ⎯ External interrupt 0 16 10 ICR00 3BCH 000FFFBCH 6 External interrupt 1 17 11 ICR01 3B8H 000FFFB8H 7 External interrupt 2 18 12 ICR02 3B4H 000FFFB4H ⎯ External interrupt 3 19 13 ICR03 3B0H 000FFFB0H ⎯ External interrupt 4 20 14 ICR04 3ACH 000FFFACH ⎯ External interrupt 5 21 15 ICR05 3A8H 000FFFA8H ⎯ External interrupt 6 22 16 ICR06 3A4H 000FFFA4H ⎯ External interrupt 7 23 17 ICR07 3A0H 000FFFA0H ⎯ Reload timer 0 (Underflow) 24 18 ICR08 39CH 000FFF9CH ⎯ Reload timer 1 (Underflow) 25 19 ICR09 398H 000FFF98H 9 Reload timer 2 (Underflow) 26 1A ICR10 394H 000FFF94H 10 UART0 (Reception completed/error) 27 1B ICR11 390H 000FFF90H 0 UART0 (Transmission completed) 28 1C ICR12 38CH 000FFF8CH 3 LIN-UART0 (Reception completed/ error, LIN Sync break, bus idle) 29 1D ICR13 388H 000FFF88H 1 (Continued) 39 MB91245/S Series Interrupt number Interrupt source Interrupt level Offset TBR default address DMA start source Decimal Hexadecimal LIN-UART0 (Transmission completed) 30 1E ICR14 384H 000FFF84H 4 LIN-UART1 (Reception completed/ error, LIN Sync break, bus idle) 31 1F ICR15 380H 000FFF80H 2 LIN-UART1 (Transmission completed) 32 20 ICR16 37CH 000FFF7CH 5 LIN-UART2 (Reception completed/ error, LIN Sync break, bus idle) 33 21 ICR17 378H 000FFF78H ⎯ LIN-UART2 (Transmission completed) 34 22 ICR18 374H 000FFF74H ⎯ CAN0 Reception/Transmission completed Node status transition 35 23 ICR19 370H 000FFF70H ⎯ CAN1 Reception/Transmission completed Node status transition 36 24 ICR20 36CH 000FFF6CH ⎯ System reserved 37 25 ICR21 368H 000FFF68H ⎯ System reserved 38 26 ICR22 364H 000FFF64H ⎯ System reserved 39 27 ICR23 360H 000FFF60H ⎯ PWC (Measurement completed) 40 28 ICR24 35CH 000FFF5CH ⎯ PWC (Overflow) 41 29 ICR25 358H 000FFF58H ⎯ DMAC transfer completed/error 42 2A ICR26 354H 000FFF54H ⎯ A/D converter 43 2B ICR27 350H 000FFF50H 14 Real-time clock Hour/minute/second overflow, corrected 44 2C ICR28 34CH 000FFF4CH ⎯ System reserved 45 2D ICR29 348H 000FFF48H ⎯ Main oscillation stabilization wait timer 46 2E ICR30 344H 000FFF44H ⎯ Timebase timer overflow 47 2F ICR31 340H 000FFF40H ⎯ PPG0/1 underflow 48 30 ICR32 33CH 000FFF3CH ⎯ PPG2/3 underflow 49 31 ICR33 338H 000FFF38H ⎯ PPG4/5 underflow 50 32 ICR34 334H 000FFF34H ⎯ PPG6/7 underflow 51 33 ICR35 330H 000FFF30H ⎯ 16-bit free-run timer 0 Overflow & OCU0 Compare match clear 52 34 ICR36 32CH 000FFF2CH ⎯ (Continued) 40 MB91245/S Series (Continued) Interrupt number Interrupt source Interrupt level Offset TBR default address DMA start source Decimal Hexadecimal 16-bit free-run timer 1 Overflow 53 35 ICR37 328H 000FFF28H ⎯ ICU0 (Capture) 54 36 ICR38 324H 000FFF24H ⎯ ICU1 (Capture) 55 37 ICR39 320H 000FFF20H ⎯ ICU2 (Capture) 56 38 ICR40 31CH 000FFF1CH ⎯ ICU3 (Capture) 57 39 ICR41 318H 000FFF18H ⎯ OCU0 (Match) 58 3A ICR42 314H 000FFF14H ⎯ OCU1 (Match) 59 3B ICR43 310H 000FFF10H ⎯ System reserved 60 3C ICR44 30CH 000FFF0CH ⎯ System reserved 61 3D ICR45 308H 000FFF08H ⎯ Sound generator setup count completed 62 3E ICR46 304H 000FFF04H ⎯ Delay interrupt source bit 63 3F ICR47 300H 000FFF00H ⎯ System reserved (Used by REALOS) 64 40 ⎯ 2FCH 000FFEFCH ⎯ System reserved (Used by REALOS) 65 41 ⎯ 2F8H 000FFEF8H ⎯ System reserved 66 to 79 42 to 4F ⎯ 2F4H to 2C0H 000FFEF4H to 000FFEC0H ⎯ Used by INT instruction 80 to 255 50 to FF ⎯ 2BCH to 000H 000FFEBCH to 000FFC00H ⎯ 41 MB91245/S Series ■ TABLE OF PIN STATUS IN EACH MODE • Single chip mode Initial value Function name INIT INIT X0 X0 Hi-Z or input enabled X1 X1 ”H” output or ”H” output or input enabled input enabled X0A X0A X1A X1A MOD0 MOD0 MOD1 MOD1 MOD2 MOD2 P00 P00/SEG24/INT0/D00 P01 P01/SEG25/INT1/D01 P02 P02/SEG26/INT2/D02 P03 P03/SEG27/INT3/D03 P04 P04/SEG28/INT4/D04 P05 P05/SEG29/INT5/D05 P06 P06/SEG30/D06 P07 P07/SEG31/ATG/D07 P10 to P17 P10 to P17/ SEG16 to SEG23/ D08 to D15 P20 to P27 P20 to P27/ SEG00 to SEG07/ A00 to A07 P30 to P33 P30 to P33/ SEG08 to SEG11/ A08 to A11 P34 to P37 P34 to P37/ SEG12 to SEG15/ A12 to A15 INIT = “L” INIT = “H” In sleep state In stop state Pin name HIZ = 0 HIZ = 1 Input enabled Input enabled Input enabled Input enabled Input enabled Hi-Z or input enabled Hi-Z or input enabled Hi-Z or input enabled ”H” output or ”H” output or input enabled input enabled Input enabled Input enabled Output Hi-Z input enabled Output Hi-Z input enabled “L” output “L” output Output Hi-Z input enabled Output Hi-Z input enabled P: Immediately preceding status held F: Normal operation performed P: Immediately preceding status held F: Operation or output held during LCDC output; INT0 to INT5 input enabled when PFR0 register is set to “0” Operation or output held during LCDC output, otherwise output Hi-Z / INT0 to INT5 input enabled when PFR0 register is set to “0” P: Immediately preceding status held F: Operation or output held during LCDC output; Otherwise Hi-Z Operation or output held during LCDC output; Otherwise output Hi-Z/ Input fixed to “0” (Continued) 42 MB91245/S Series Pin name Function name P40 P40/SIN0 P41 P41/SOT0 P42 P42/SCK0 P43 P43/SIN3 P44 P44/SOT3 P45 P45/SCK3 P46 P46/SGA/AS P47 P47/SGO/SYSCLK P50 P50/SIN4/CK0/CS0 P51 P51/SOT4/CS1 P52 P52/SCK4/CS2 P53 P53/SIN5/CK1/CS3 P54 P54/SOT5/RD P55 P55/SCK5/WR0 P56 P56/OUT0/WR1 P57 P57/OUT1/RDY P60 to P67 P60 to P67/AN0 to AN7 P70 P71 P72 Initial value INIT = “L” INIT = “H” In sleep state In stop state HIZ = 0 HIZ = 1 P: Immediately preceding Output Hi-Z / status held Input fixed to F: “0” Output held or Hi-Z Output Hi-Z input enabled P: Immediately preceding Output Hi-Z status held input F: enabled Normal operation performed P70/RX0/INT6 P: Immediately preceding status held F: Output held, INT6 input enabled Output Hi-Z / INT6 input enabled when PFR7 register is set to “1” P71/TX0 P: Immediately preceding status held, F : Hi-Z Output Hi-Z / Input fixed to “0” P72/RX1/INT7 P: Immediately preceding status held F: Output held, INT7 input enabled Output Hi-Z / INT7 input enabled when PFR7 register is set to “1” (Continued) 43 MB91245/S Series (Continued) 44 Pin name Function name P73 P73/TX0 P80 to P87 P80 to P87/AN16 to AN23 P90 to P97 P90 to P97/AN24 to AN31 PA0 to PA3 PA0 to PA3/ PWMxxx to PWMxxx PB0 to PB7 PB0 to PB7/ PWMxxx to PWMxxx PC0 to PC3 PC0 to PC3/ PWMxxx to PWMxxx PD0 PD0/TIN0/IN0/PWC0 PD1 PD1/TIN1/IN1 PD2 PD2/TIN2/IN2 PD3 PD3/IN3 PD4 PD4/COM0/PPG1 PD5 PD5/COM1/PPG3 PD6 PD6/COM2/PPG5 PD7 PD7/COM3/PPG7 PE0 to PE7 PE0 to PE7/ PWMxxx to PWMxxx PF0 to PF7 PF0 to PF7/AN8 to AN15 PG0 PG0/ (WOT) /PPG0 PG1 PG1/TOT0/PPG2 PG2 PG2/TOT1/PPG4 PG3 PG3/TOT2/PPG6 Initial value In sleep state INIT = “L” INIT = “H” Output Hi-Z input enabled P: Immediately preceding Output Hi-Z status held input F: enabled Normal operation performed Input enabled “L” output Output Hi-Z Input enabled Input enabled Input enabled “L” output P: Immediately preceding status held F: Normal operation Output Hi-Z performed Input enabled In stop state HIZ = 0 HIZ = 1 P: Immediately preceding Output Hi-Z / status held Input fixed to F: “0” Output held or Hi-Z Hi-Z P: Input fixed to Immediately “0” preceding status held LCDC : Output or hold PPG : Output held P: Immediately preceding Output Hi-Z / status held Input fixed to F: “0” Output held or Hi-Z MB91245/S Series • External bus mode (8-bit) Pin name Function name INIT Initial value HIZ = 1 INIT Input enabled Input enabled X0 X0 Hi-Z or input enabled Hi-Z or input enabled X1 X1 ”H” output or input enabled ”H” output or input enabled X0A X0A Hi-Z or input enabled Hi-Z or input enabled X1A X1A ”H” output or input enabled ”H” output or input enabled MOD0 MOD0 MOD1 MOD1 Input enabled Input enabled MOD2 MOD2 P00 P00/SEG24/ INT0 P01 P01/SEG25/ INT1 P02 P02/SEG26/ INT2 P03 P03/SEG27/ INT3 P04 P04/SEG28/ INT4 P: Immediately preceding status held F: Operation or output held during LCDC output; INT0 to INT5 input enabled when PFR0 register is set to “0” Operation or output held during LCDC output, otherwise output Hi-Z / INT0 to INT5 input enabled when PFR0 register is set to “0” P05 P05/SEG29/ INT5 P06 P06/SEG30 P: Immediately preceding status held F: Operation or output held during LCDC output, otherwise Hi-Z Operation or output held during LCDC output, otherwise output Hi-Z / Input fixed to “0” Hi-Z Output Hi-Z / Input fixed to “0” P07/SEG31/ ATG P10 to P17 D08 to D15 P20 to P27 A00 to A07 P30 to P33 A08 to A11 Input enabled Output Hi-Z input enabled INIT = “H” In stop mode HIZ = 0 P07 INIT = “L” In sleep mode Input enabled Input enabled P: Immediately preceding status held Output F: Hi-Z input Normal operation enabled performed Hi-Z “L” output “H” output F : Address output F : Address output Output Hi-Z / Input fixed to “0” (Continued) 45 MB91245/S Series Pin name Function name P34 to P37 A12 to A15 P40 P40/SIN0 P41 P41/SOT0 P42 P42/SCK0 P43 P43/SIN3 P44 P44/SOT3 P45 P45/SCK3 Initial value INIT = “L” INIT = “H” Output Hi-Z input enabled In sleep mode In stop mode HIZ = 0 “H” output F : Address output F : Address output P: Immediately preceding Output status held Hi-Z input F: enabled Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z P46/SGA/ AS P: Immediately preceding status held, “H” output AS : “H” output, F: Normal operation performed P: Immediately preceding status held, AS : “H” output, F : Output held P47 P47/SGO/ SYSCLK P: Immediately preceding status held, CLK : CLK output, F: Normal operation performed P50 P50/SIN4/ CK0/CS0 P51 P51/SOT4/ CS1 P52 P52/SCK4/ CS2 P53 P53/SIN5/ CK1/CS3 P54 P54/SOT5/ RD P55 P55/SCK5/ WR0 P46 Output Hi-Z input enabled CLK output Bus control : “H” output P: Immediately preceding “H” output status held F: Normal operation performed HIZ = 1 P: Output Hi-Z / Immediately preceding Input fixed to “0” status held, CLK : “H” or “L” output, F : Output held Bus control : “H” output P: Immediately preceding status held F: Output held or Hi-Z (Continued) 46 MB91245/S Series Pin name P56 Function name Initial value INIT = “L” P56/OUT0 Output Hi-Z input enabled P57 P60 to P67 P70 P71 P72 P57/OUT1/ RDY INIT = “H” In sleep mode P71/TX0 P72/RX1/ INT7 HIZ = 0 P: Immediately preceding status held F: “H” output Normal operation performed; “H” output when EPFR is set to “0” P: Immediately preceding status held F: Output held; “H” output when EPFR is set to “0” P: Immediately preceding status held RDY input F: Normal status, RDY input P: Immediately preceding status held F: Output held, RDY input HIZ = 1 Output Hi-Z / Input fixed to “0” P: Immediately preceding Output Hi-Z / status held Input fixed to “0” F: Output held or Hi-Z P60 to P77/ AN0 to AN7 P70/RX0/ INT6 In stop mode P: Immediately Output Hi-Z Output Hi-Z preceding status held input input F: enabled enabled Normal operation performed P: Immediately preceding status held F: Output held, INT6 input enabled Output Hi-Z / INT6 input enabled when PFR7 register is set to “1” P: Immediately preceding Output Hi-Z / status held, Input fixed to “0” F : Hi-Z P: Immediately preceding status held F: Output held, INT7 input enabled Output Hi-Z / INT7 input enabled when PFR7 register is set to “1” (Continued) 47 MB91245/S Series (Continued) Pin name Function name P80 to P87 P80 to P87/ AN16 to AN23 P90 to P97 P90 to P97/ AN24 to AN31 PA0 to PA3 PA0 to PA3/ PWMxxx to PWMxxx PB0 to PB7 PB0 to PB7/ PWMxxx to PWMxxx PC0 to PC3 PC0 to PC3/ PWMxxx to PWMxxx PD0 PD0/TIN0/ IN0/PWC0 PD1 PD1/TIN1 PD2 PD2/TIN2 PD3 PD3/IN3 PD4 PD4/COM0/ PPG1 PD5 PD5/COM1/ PPG3 PD6 PD6/COM2/ PPG5 PD7 PD7/COM3/ PPG7 PE0 to PE7 PE0 to PE7/ PWMxxx to PWMxxx PF0 to PF7 PF0 to PF7/ AN8 to AN15 PG0 PG1 48 Initial value INIT = “L” INIT = “H” P: Immediately Output Hi-Z Output Hi-Z preceding status input input held enabled enabled F : Normal operation performed Input enabled Input enabled PG2/TOT1/ PPG4 PG3 PG3/TOT2/ PPG6 Input enabled In stop mode HIZ = 0 P: Immediately preceding status held F: Normal operation performed HIZ = 1 Output Hi-Z / Input fixed to “0” Hi-Z Input fixed to “0” “L” output P: Immediately preceding status held LCDC : Output or hold PPG : Output held “L” output PG0/ (WOT) / Output Hi-Z Output Hi-Z Input Input PPG0 enabled enabled PG1/TOT0/ PPG2 PG2 In sleep mode P: Immediately preceding status held F: Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z Output Hi-Z / Input fixed to “0” MB91245/S Series • External bus mode (16-bit) Initial value Pin Function name name INIT = “L” INIT = “H” In sleep mode In stop mode HIZ = 0 HIZ = 1 INIT INIT Input enabled Input enabled X0 X0 Hi-Z or input enabled Hi-Z or input enabled X1 X1 ”H” output or input enabled ”H” output or input enabled X0A X0A Hi-Z or input enabled Hi-Z or input enabled X1A X1A ”H” output or input enabled ”H” output or input enabled MOD0 MOD0 MOD1 MOD1 Input enabled Input enabled MOD2 MOD2 P00 D00 P01 D01 P02 D02 P03 D03 P04 D04 P05 D05 P06 D06 P07 D07 P10 to P17 D08 to D15 P20 to P27 A00 to A07 P30 to P33 A08 to A11 P34 to P37 A12 to A15 P40 P40/SIN0 P41 P41/SOT0 P42 P42/SCK0 P43 P43/SIN3 P44 P44/SOT3 P45 P45/SCK3 Input enabled Output Hi-Z input enabled Input enabled Output Hi-Z input enabled Input enabled Hi-Z Hi-Z Output Hi-Z Input fixed to “0” “L” output Output Hi-Z input enabled “H” output F : Address output F : Address output Output Hi-Z input enabled P: Immediately preceding status held F: Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z (Continued) 49 MB91245/S Series Pin name P46 Function name In stop mode HIZ = 0 HIZ = 1 P: Immediately preceding status held, AS : “H” output, F : Output held P: Immediately preceding status held, CLK : CLK output, F: Normal operation performed P: Immediately preceding status held, CLK : “H” or “L” output, F : Output held Bus control : “H” output P: Immediately preceding “H” output status held F: Normal operation performed Bus control : “H” output P: Immediately preceding status held F: Output held or Hi-Z Bus control : “H” output P: Immediately preceding “H” output status held F: Normal operation performed Bus control : “H” output P: Immediately preceding status held F: Output held or Hi-Z P57/OUT1/ RDY P: Immediately preceding status held RDY input F: Normal status, RDY input P: Immediately preceding status held F : Output held, RDY input P60 to P77/ AN0 to AN7 P: Immediately Output preceding status held Hi-Z input F: enabled Normal operation performed P: Immediately preceding status held Output Hi-Z / F: Input fixed to “0” Output held or Hi-Z P46/SGA/AS P47/SGO/ SYSCLK P50 P50/SIN4/ CK0/CS0 P51 P51/SOT4/ CS1 P52 P52/SCK4/ CS2 P53 P53/SIN5/ CK1/CS3 P54 P54/SOT5/ RD P55 P55/SCK5/ WR0 P56 P56/OUT0/ WR1 P60 to P67 INIT = “L” INIT = “H” In sleep mode P: Immediately preceding status held, “H” output AS : “H” output, F: Normal operation performed P47 P57 Initial value Output Hi-Z input enabled Output Hi-Z input enabled Output Hi-Z input enabled CLK output Output Hi-Z Input fixed to “0” Output Hi-Z / Input fixed to “0” (Continued) 50 MB91245/S Series Pin name P70 P71 Function name P71/TX0 P72/RX1/ INT7 P80 to P87 P80 to P87/ AN16 to AN23 P90 to P97 P90 to P97/ AN24 to AN31 PB0 to PB7 INIT = “L” INIT = “H” In sleep mode P70/RX0/ INT6 P72 PA0 to PA3 Initial value P: Immediately Output Hi-Z Output Hi-Z preceding status held input input F: enabled enabled Normal operation performed P: Immediately PA0 to PA3/ Output Hi-Z Output Hi-Z preceding status held PWMxxx to input input F: PWMxxx enabled enabled Normal operation PB0 to PB7/ performed PWMxxx to PWMxxx In stop mode HIZ = 0 HIZ = 1 P: Immediately preceding status held F: Output held, INT6 input enabled Output Hi-Z / INT6 input enabled when PFR7 register is set to “1” P: Immediately preceding Output Hi-Z / status held, Input fixed to “0” F : Hi-Z P: Immediately preceding status held F: Output held, INT7 input enabled P: Immediately preceding status held F: Normal operation performed Output Hi-Z / INT7 input enabled when PFR7 register is set to “1” Output Hi-Z/ Input fixed to “0” PC0 PC0 to PC3/ to PWMxxx to PC3 PWMxxx PD0 PD0/TIN0/ IN0/PWC0 PD1 PD1/TIN1 PD2 PD2/TIN2 PD3 PD3/IN3 Input enabled Input enabled Input enabled Hi-Z Input fixed to “0” (Continued) 51 MB91245/S Series (Continued) Pin name Function name PD4 PD4/COM0/ PPG1 PD5 PD5/COM1/ PPG3 PD6 PD6/COM2/ PPG5 PD7 PD7/COM3/ PPG7 PE0 to PE7 PE0 to PE7/ PWMxxx to PWMxxx PF0 to PF7 PF0 to PF7/ AN8 to AN15 PG0 PG1 52 Initial value INIT = “L” “L” output INIT = “H” “L” output PG0/ (WOT) / Output Hi-Z Output Hi-Z Input Input PPG0 enabled enabled PG1/TOT0/ PPG2 PG2 PG2/TOT1/ PPG4 PG3 PG3/TOT2/ PPG6 In sleep mode P: Immediately preceding status held F: Normal operation performed In stop mode HIZ = 0 HIZ = 1 P: Immediately preceding status held LCDC : Output or hold PPG : Output held Input fixed to “0” P: Immediately preceding status held F: Output held or Hi-Z Output Hi-Z / Input fixed to “0” MB91245/S Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*2 VAVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ VAVRH DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC*2 Input voltage*1 VI VSS − 0.3 VCC + 0.3 V Output voltage*1 VO VSS − 0.3 VCC + 0.3 V “L” level maximum output current*3 IOL1 ⎯ 15 mA *5 IOL2 ⎯ 40 mA *6 IOLAV1 ⎯ 4 mA *5 IOLAV2 ⎯ 30 mA *6 ΣIOL1 ⎯ 120 mA *5 ΣIOL2 ⎯ 330 mA *6 ΣIOLAV1 ⎯ 50 mA *5 ΣIOLAV2 ⎯ 240 mA *6 I OH1 3 ⎯ −15 mA *5 I OH2 3 ⎯ −40 mA *6 “H” level average output current IOHAV1*4 ⎯ −4 mA *5 IOHAV2*4 ⎯ −30 mA *6 “H” level total maximum output current ΣIOH1 ⎯ −120 mA *5 ΣIOH2 ⎯ −330 mA *6 ΣIOHAV1*7 ⎯ −50 mA *5 ΣIOHAV2*7 ⎯ −240 mA *6 PD ⎯ 660 mW −40 +105 °C MASK ROM product (in single chip operation) −40 +105 °C Flash memory product (in single chip operation) −40 +85 °C MASK ROM/Flash memory product (in external bus operation) Tstg −55 +150 °C +B input standard (Maximum clamp current) IIHH ⎯ 2 mA +B input standard (Total maximum clamp current) ΣIIHH ⎯ 20 mA Power supply voltage*1 “L” level average output current*4 “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature * * TA Exclusive of dedicated input pins*8 (Continued) 53 MB91245/S Series (Continued) *1 : The parameter is base on VSS = AVSS = DVSS = 0.0 V. *2 : Caution must be taken that AVCC and DVCC do not exceed VCC upon power-on and under other circumstances. *3 : The maximum output current defines the peak current value of each of the corresponding pins. *4 : The average output current defines the average value of the current (100 ms) which passes through each of the corresponding pins. The average value represents a value calculated by multiplying the operating current by the operating rate. *5 : Output other than PA0 to PA3 pins, PB0 to PB7 pins, PC0 to PC3 pins, and PE0 to PE7 pins *6 : (PA0 to PA3 pins, PE0 to PE7 pins) + (PB0 to PB7 pins, PC0 to PC3 pins) The SMC pins are divided into two groups (12 pins each) and the value is calculated as the total current per group. *7 : The total average output current defines the average value of the current (100 ms) which passes through all the corresponding pins. The average value represents a value calculated by multiplying the operating current by the operating rate. *8 : +B input standard defines the current value for each of the corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 54 MB91245/S Series 2. Recommended Operating Conditions (VSS = DVSS = AVSS = 0.0 V) Parameter Power supply voltage Smoothing capacitor*3 Operating temperature Symbol VCC AVCC DVCC Rating Unit Remarks 5.5 V Recommended guaranteed operating range (MB91F248, MB91248) 3.5 5.5 V Guaranteed operating range*1 (MB91F248, MB91248) 2.0 5.5 V Guaranteed operating range for holding stop operation status*2 (MB91F248, MB91248) µF Use a ceramic capacitor or a capacitor with similar frequency characteristics. Min Max 4.5 CS TA 1 −40 +105 °C MASK ROM product (in single chip operation) −40 +105 °C Flash memory product (in single chip operation) −40 +85 °C MASK ROM/Flash memory product (in external bus operation) *1 : Exclusive of A/D operation *2 : Internal voltage held in RAM : 1.8 V (Min) /3.6 V (Max) *3 : For how to connect the smoothing capacitor CS, refer to the figure below. • C Pin Connection Diagram C CS VSS DVSS AVSS < + B input (12 V to 16 V) conditions> • Do not connect +B potential directly to a microcontroller pin. • Always connect a resistor between the microcontroller pin and +B signal to limit the current. lIHH = 2 mA per pin (Max.) [In the steady state and transient state between power-on and power-off, etc.] It can be connected to any general-purpose input port except the output pin for LCDC. • The protection diode in the microcontroller turns the potential upon +B input between the limiting resistor and microcontroller pin into “VCC + protection diode ON voltage”. Configure the circuit so that these are not interfered and the potential is not exceeded. 55 MB91245/S Series Recommended example circuit MB91245/S series Protection diode lIHH +B Input (12 V to 16 V) Current limiting resistor WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 56 MB91245/S Series 3. DC Specifications (TA : Recommended operating conditions; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin name Condition VIHS ⎯ VIH Value Unit Remarks Min Typ Max ⎯ 0.8 VCC ⎯ VCC + 0.3 V Automotive level input pins*1 P00 to P07, P10 to P17, P57 ⎯ 0.7 VCC ⎯ VCC + 0.3 V CMOS hysteresis input pins*2 VIHM ⎯ ⎯ VCC − 0.3 ⎯ VCC + 0.3 V MOD pins*3 VIHX X0, X1, X0A, X1A, INIT ⎯ 0.8 VCC ⎯ ⎯ V VILS ⎯ ⎯ VSS − 0.3 ⎯ 0.5 VCC V Automotive level input pins*1 VIL P00-P07, P10-P17, P57 ⎯ VSS − 0.3 ⎯ 0.3 VCC V CMOS hysteresis input pins*2 VILM ⎯ ⎯ VSS − 0.3 ⎯ Vss + 0.3 V MOD pins*3 VILX X0, X1, X0A, X1A, INIT ⎯ ⎯ ⎯ 0.2 VCC V ⎯ 55 85 mA ⎯ 55 85 mA MASK ROM product ⎯ 100 150 mA In Flash-Write mode Operating frequency : FCP = 32 kHz, TA = +25 °C in sub mode ⎯ 290 450 µA ICCH TA = +25 °C, Vcc = 5V in stop mode (oscillation stopped) ⎯ 95 150 µA ICTS TA = +25 °C, Vcc = 5V in stop mode (RTC in use) ⎯ 390 500 µA VCC = DVCC = AVCC = 5.5 V VSS < VI < VCC −5 ⎯ +5 µA CIN1 Other than Vcc, VSS, DVcc, DVSS, AVcc, AVSS, PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 ⎯ ⎯ 5 15 pF Input capacity 2 CIN2 PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 ⎯ ⎯ 15 45 pF Pull-up resistance RUP INIT ⎯ 25 50 100 kΩ “H” level input voltage “L” level input voltage Operating frequency : FCP = 32 MHz in main mode ICC Power supply current*4 Input leak current Input capacity 1 ICCL IIL VCC All input pins Flash memory product At 4 MHz (Continued) 57 MB91245/S Series (Continued) Parameter (TA : Recommended operating conditions; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V) Symbol Remarks 100 kΩ MASK ROM products only ⎯ ⎯ V VCC − 0.5 ⎯ ⎯ V Vcc = 4.5 V IOL = 4.0 mA ⎯ ⎯ 0.4 V Vcc = 4.5 V IOL = 30.0 mA ⎯ ⎯ 0.55 V PWM1Pn, High current output PWM1Mn, Drive capacity ∆VOH2 PWM2Pn, Phase-to-phase PWM2Mn, deviation 1 n = 0 to 5 Vcc = 4.5 V IOH = 30.0 mA Maximum deviation of VOH2 0 ⎯ 90 mV *5 Vcc = 4.5 V IOL = 30.0 mA Maximum deviation of VOL2 0 ⎯ 90 mV *5 Output “H” voltage 1 Output “H” voltage 2 Output “L” voltage 1 Output “L” voltage 2 Condition Value Unit Pull-down resistance Pin name Min Typ Max ⎯ 25 50 VOH1 Other than PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 Vcc = 4.5 V IOH = −4.0 mA VCC − 0.5 VOH2 PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 Vcc = 4.5 V IOH = −30.0 mA VOL1 Other than PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 VOL2 PA0 to PA3, PB0 to PB7, PC0 to PC3, PE0 to PE7 RDOWN MOD1, MOD2 High current output Drive capacity Phase-to-phase deviation 2 ∆VOL2 PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 5 COM0 to COM3 Output impedance RVCOM COMm (m = 0 to 3) ⎯ ⎯ ⎯ 2.5 kΩ SEG00 to SEG31 Output impedance RVSEG SEGn (n = 00 to 31) ⎯ ⎯ 15 30 kΩ ILCDC COMm (m = 0 to 3) , SEGn, (n = 00 to 31) TA = +25 °C −0.5 ⎯ +0.5 µA LCDC leak current *1 : All input pins except X0, X1, X0A, X1A, MOD0, MOD1, MOD2 and INIT pins *2 : Can be selected by the input level select register (PILR). *3 : MOD0, MOD1 and MOD2 *4 : They represent current values used when supplying power to the external clock from pin X1. *5 : Defined by the maximum deviation of VOH2/VOL2 of each pin, when PWM1P0, PWM1M0, PWM2P0 and PWM2M0 in ch.0 are simultaneously turned on. The same applies to other channels. 58 MB91245/S Series 4. Flash Memory Write/Erase Characteristics Parameter Condition Value Min Typ Max Unit Remarks Sector erase time TA = +25 °C, Vcc = 5.0 V ⎯ 1 15 s Exclusive of internal write time prior to erase Chip erase time TA = +25 °C, Vcc = 5.0 V ⎯ 5 ⎯ s Exclusive of internal write time prior to erase Halfword write time TA = +25 °C, Vcc = 5.0 V ⎯ 16 3600 µs Exclusive of overhead time at system level Chip write time TA = +25 °C, Vcc = 5.0 V ⎯ 2.1 ⎯ s Exclusive of overhead time at system level ⎯ 10000 ⎯ ⎯ cycle TA = +85 °C (average) 10 ⎯ ⎯ year Erase/write cycle Flash memory data retain time * * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) . 59 MB91245/S Series 5. AC Specifications (1) Clock timing (TA : Recommended operating conditions; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V) Parameter Symbol Pin name FC Value Condition Unit Remarks Min Typ Max X0, X1 ⎯ 4 ⎯ MHz Fca X0A, X1A ⎯ 32 ⎯ kHz Source oscillation clock Cycle time tCYL X0, X1 ⎯ 250 ⎯ ns Input clock pulse width PWH , PWL X0 100 ⎯ ⎯ ns 0.0312 ⎯ 32 MHz CPU based (CLKB) 0.0312 ⎯ 16 MHz External bus based (CLKT) fCPP 0.0312 ⎯ 32 MHz Peripheral based (CLKP) tCPB 31.25 ⎯ 32000 ns CPU based (CLKB) 62.5 ⎯ 32000 ns External bus based (CLKT) 31.25 ⎯ 32000 ns Peripheral based (CLKP) ⎯ ⎯ 5 ns When external clock is used ⎯ ⎯ 32 31.25 ⎯ ⎯ Frequency of source oscillation clock ⎯ fCPB Frequency of internal operating clock Internal operating clock cycle fCPT tCPT ⎯ ⎯ ⎯ ⎯ tCPP Input clock Rise/fall time tcr tcf X0 ⎯ Frequency of internal base clock FCP ⎯ Internal base clock Cycle time tCP ⎯ ⎯ The duty ratio normally ranges from 40% to 60%. When main oscillation MHz is at 4 MHz and PLL multiplied by 8 is used ns When main oscillation is at 4 MHz and PLL multiplied by 8 is used • X0/X1 Clock Timing tCYL 0.8 VCC X0 0.2 VCC PWH 60 tcf PWL tcr MB91245/S Series • Operations Oscillation should be performed as described below : [Source oscillation] : X0/X1 : 4 MHz, PLL : multiplied by 8, Internal frequency : 32 MHz : X0A/X1A : 32 kHz, PLL : no multiplied, Internal frequency : 32 kHz Note that the PLL oscillation stabilization wait time should be set to 500 µs or more. Example oscillation circuit X0 X1 R C1 C2 AC specifications are defined by the following measurement standard voltage values : • Input signal waveform Hysteresis input pin • Output signal waveform Output pin 0.8 VCC 2.4 V 0.5 VCC 0.8 V 61 MB91245/S Series (2) Reset input (TA : Recommended operating conditions; Vcc = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V) Symbol Parameter INIT input time Pin name tINTL INIT Value Condition Unit Remarks Min Max 500 ⎯ ns Flash memory product 10 tCP ⎯ ns MASK ROM product Oscillation time of oscillator* + 10 tcp + 12 µs ⎯ ms In stop mode ⎯ * : The oscillation time of the oscillator refers to the time when the amplitude has reached 90%. The oscillation time of the crystal oscillator ranges from several ms to tens of ms. The oscillation time of the ceramic oscillator ranges from several hundreds to several ms, while that of the external clock is 0 ms. tINTL INIT 0.2 VCC 0.2 VCC • In stop mode tINTL INIT 0.2 VCC X0 0.2 VCC 90% of amplitude Internal operation clock 10 tcp + 12 µs Oscillation time of oscillator Oscillation stabilization wait time Instruction executed Internal reset 62 MB91245/S Series [External reset input specifications (INIT) and internal reset signal cancellation timing] • When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the internal reset signal to transmit all reset signals to the internal logic. (Max 8 µs at 32 MHz) • The following chart shows how to set the timing for instruction execution start (start of application operation) after external reset input. Time from external reset input to instruction start = Max 256 tcp + 61 tcp • Timing Chart INIT Min Internal reset input timing 10 tcp Internal reset 61 tcp Max 256 tcp Internal reset cancellation timing [Pin state in external bus mode] In the external bus mode, it is not guaranteed to hold the RAM value upon external reset (INIT = “0”) input. In the external bus mode, the value of the internal bus is output to each pin during the time from the internal reset input to its cancellation as well as the RAM value is not guaranteed to be held. • Timing Chart (Pin State for External Bus Mode : 1) INIT Min 10 tcp Internal reset 61 tcp Max 256 tcp Pin state of external bus Hi-Z Value immediately before reset Initial value at reset 63 MB91245/S Series It can be avoided by the following external reset input to continue Hi-Z. • Timing Chart (Pin State for External Bus Mode : 2) INIT 256 tcp Internal reset 61 tcp Max 256 tcp Pin state of external bus 64 Hi-Z Initial value at reset MB91245/S Series (3) Power-on Conditions (TA : Recommended operating conditions; VSS = 0.0 V) Parameter Symbol Pin name Condition Value Min Max Unit Power supply rising time tR 0.05 30 ms Power supply start voltage VOFF ⎯ 0.2 V Power supply peak voltage VON 3.5 ⎯ V Power supply cut-off time tOFF 50 ⎯ ms Remarks ⎯ Vcc Due to repetitive operation tR 4.5 V Vcc 0.2 V 0.2 V 0.2 V tOFF Power supply drop time, power supply voltages and external reset input to retain RAM data in MB91245/S Satisfy the following reset input standard to retain the RAM data used in the single chip mode. Vcc (V) Voltage drop time External reset input standard (INIT) 4.0 V → 3.5 V dropped Vcc Min 256 tcp Min 256 tcp 4V 4V 3.5 V 3.5 V INIT 256 tcp To retain RAM data, enter 256 tcp of INIT or more before dropping VCC to 3.5 V or lower. 65 MB91245/S Series (4) Clock Output Timing (VCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Pin name Cycle time tCYC SYSCLK SYSCLK↑→SYSCLK↓ tCHCL SYSCLK SYSCLK↓→SYSCLK↑ tCLCH SYSCLK Value Condition ⎯ Min Max tCPT ⎯ Unit Remarks ns *1 tCYC / 2 − 10 tCYC / 2 + 10 ns *2 tCYC / 2 − 10 tCYC / 2 + 10 ns *3 tCYC tCHCL tCLCH VOH SYSCLK VOH VOL *1 : tCYC is the frequency of one clock cycle including the gear cycle. *2 : The ratings are based on conditions with “gear cycle × 1”. When the gear cycle is set to 1/2, 1/4 or 1/8, perform calculation by substituting 1/2, 1/4 or 1/8 for “n” in the following formula, respectively. ( 1 / 2 × 1 / n ) × tCYC − 10 *3 : This is the value for the gear cycle × 1. 66 MB91245/S Series (5) Normal Bus Access : Read/Write Operation (VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, TA = 0 °C to + 70 °C) Parameter Symbol Pin name tCSLCH CS0 to CS3 setup tCSDLCH CS0 to CS3 hold SYSCLK CS0 to CS3 Condition Value Unit Min Max AWRxL : W02 = 0 3 ⎯ ns AWRxL : W02 = 1 −8 ⎯ ns 3 tCYC / 2 + 25 ns tCHCSH tASCH SYSCLK A00 to A15 3 ⎯ ns tASWL WR0, WR1 A00 to A15 3 ⎯ ns tASRL RD A00 to A15 3 ⎯ ns tCHAX SYSCLK A00 to A15 3 tCYC / 2 + 25 ns tWHAX WR0, WR1 A00 to A15 3 ⎯ ns tRHAX RD A00 to A15 3 ⎯ ns Valid address → valid data input time tAVDV A00 to A15 D00 to D15 ⎯ 3 / 2 × tCYC + 45 ns WR0, WR1 delay time tCHWL ⎯ 8 ns WR0, WR1 delay time tCHWH SYSCLK WR0, WR1 ⎯ 8 ns WR0, WR1 minimum pulse width tWLWH WR0, WR1 tCYC − 5 ⎯ ns WR0, WR1↑→ data hold time tWHDX D00 to D15 3 ⎯ ns RD delay time tCHRL ⎯ 6 ns RD delay time tCHRH SYSCLK RD ⎯ 6 ns RD ↓ → valid data input time tRLDV ⎯ tCYC − 30 ns Data setup → RD ↑ time tDSRH 20 ⎯ ns RD ↑ → data hold time tRHDX 0 ⎯ ns RD minimum pulse width tRLRH RD tCYC − 5 ⎯ ns AS setup tASLCH 3 ⎯ ns AS hold tCHASH SYSCLK AS 3 tCYC / 2 + 25 ns Address setup Address hold RD D00 to D15 ⎯ Remarks *1, *2 *1 *1 : If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated value. *2 : The ratings are based on conditions with “gear cycle × 1”. If the gear cycle is set to 1/2 to 1/16, perform calculation by substituting the corresponding value for “n” in the following formula. Formula : 3/ (2n) × tCYC + 45 67 MB91245/S Series tCYC VOH VOH VOH VOH SYSCLK tASLCH AS tCHASH VOH VOL tCSLCH tCSDLCH CS0 to CS3 tCHCSH VOH VOL tASCH A00 to A15 tCHAX VOH VOL VOH VOL tCHRL tCHRH tRLRH RD VOL tRHAX tASRL tRLDV tDSRH tRHDX tAVDV D00 to D15 VOH VOH VOL VOL tCHWH tCHWL tWLWH VOL WR0, WR1 tASWL VOH tWHAX tWHDX D00 to D15 68 VOH VOL VOH VOL MB91245/S Series (6) Ready Input Timing (VCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Pin name RDY setup time →SYSCLK↓ tRDYS SYSCLK RDY SYSCLK↑→ RDY hold time tRDYH SYSCLK RDY Value Condition Unit Min Max 10 ⎯ ns 0 ⎯ ns Remarks ⎯ tcyc VoH SYSCLK VoL tRDYS With RDY wait Without RDY wait VoH VoL tRDYH tRDYS VoH tRDYH VoH VoL VoL VoH VoH VoL VoL 69 MB91245/S Series (7) UART Timing (TA : Recommended operating conditions; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Symbol Pin name Serial clock Cycle time tSCYC SCK↓→ SOT delay time tSLOV Valid SIN→ SCK↑ tIVSH SCK↑→ Valid SIN hold time Condition Value Max SCK0 8 tCP ⎯ ns SCK0, SOT0 −80 +80 ns 100 ⎯ ns tSHIX 60 ⎯ ns Serial clock “H” pulse width tSHSL 4 tCP ⎯ ns Serial clock “L” pulse width tSLSH 4 tCP ⎯ ns SCK↓→ SOT delay time tSLOV ⎯ 150 ns Valid SIN→ SCK↑ tIVSH 60 ⎯ ns SCK↑→ Valid SIN hold time tSHIX 60 ⎯ ns ⎯ Remarks For internal shift clock mode output pin, CL = 80 pF+1⋅TTL SCK0, SIN0 SCK0 SCK0, SOT0 ⎯ SCK0, SIN0 Notes : • The above ratings are the values for clock synchronous mode. • CL is a load capacitance connected to pins during testing. 70 Unit Min For external shift clock mode output pin, CL = 80 pF+1⋅TTL MB91245/S Series • Internal Shift Clock Mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 Vcc 0.8 Vcc 0.5 Vcc 0.5 Vcc • External Shift clock Mode tSLSH tSHSL 0.8 Vcc SCK 0.6 Vcc 0.8 Vcc 0.6 Vcc tSLOV SOT 2.4 V 0.8 V tIVSH SIN tSHIX 0.8 Vcc 0.8 Vcc 0.5 Vcc 0.5 Vcc 71 MB91245/S Series (8) Timer Input Timing (TA : Recommended operating conditions; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol Pin name Condition tTIWH tTIWL TIN0 to TIN2, PWC IN0 to IN3 ⎯ Value Min Max 4 tCP ⎯ Unit Remarks ns • Timer Input Timing tTIWL tTIWH TINx INx 0.8 Vcc 0.8 Vcc 0.5 Vcc 0.5 Vcc (9) External Interrupt Timing (TA : Recommended operating conditions; VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol Pin name Condition tINTH, INTL INT0 to INT7 ⎯ Value Min Max 3 tCP ⎯ Unit Remarks ns • External interrupt input timing tINTH 0.8 Vcc INTx tINTL 0.8 Vcc 0.5 Vcc 0.5 Vcc Note : For INTx level detection time required to recover from the stop mode, add the stabilization time for the internal step-down circuit (12 µs). 72 MB91245/S Series 6. A/D Converter Electrical Characteristics (1) Electrical Characteristics (TA : Recommended operating conditions; VCC = AVCC = 5.0 V ±10%, VSS = AVSS = 0.0 V) Symbol Pin name Resolution ⎯ Total error Parameter Value Unit Min Typ Max ⎯ ⎯ ⎯ 10 bit ⎯ ⎯ ⎯ ⎯ ±3.0 LSB Non-linearity error ⎯ ⎯ ⎯ ⎯ ±2.5 LSB Differential linearity error ⎯ ⎯ ⎯ ⎯ ±1.9 LSB Zero transition voltage VOT AN0 to AN31 AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB V AVRH − 1.5 LSB AVRH + 0.5 LSB V Remarks 1 LSB = (AVRH − AVSS) / 1024 Full-scale transition voltage VFST AN0 to AN31 AVRH − 3.5 LSB Sampling time tSMP ⎯ 1.375 ⎯ ⎯ µs *1 Compare time tCMP ⎯ 1.375 ⎯ ⎯ µs *2 A/D conversion time tCNV ⎯ 2.750 ⎯ ⎯ µs *3 Analog port input current IAIN AN0 to AN31 ⎯ ⎯ 10 µA VAVSS ≤ VAIN ≤ VAVCC Analog input voltage VAIN AN0 to AN31 0 ⎯ AVRH V AVR + AVRH 4.0 ⎯ AVcc V ⎯ 2.4 4.7 mA ⎯ ⎯ 5 µA *5 Standard voltage Power supply current*4 IA IAH AVCC Standard voltage supply current IR AVRH ⎯ 500 900 µA VAVRH = 5.0 V IRH AVRH ⎯ ⎯ 5 µA *5 Variation between channels ⎯ AN0 to AN31 ⎯ ⎯ 5 LSB *1 : *2 : *3 : *4 : *5 : When FCP is 32 MHz : tSMP = (Rext + Rin) × Cin × 7 = ST × CLKP cycle = 2 channels × 31.25 ns = 1.375 µs When FCP is 32 MHz : tCMP = CKIN × 11 = CT × CLKP cycle × 11 = 4 h × 31.25 ns × 11 = 1.375 µs This represents the conversion time per channel when tSMP and tCMP are selected while FCP is 32 MHz. The current values are targeted temporary ratings. This defines the power supply current when the A/D converter is not in operation and the CPU is stopped (at “Vcc = AVcc = AVRH = 5.0 V”) Notes : • As AVRH becomes smaller, the error becomes greater. • Use the output impedance rS of the external circuit for analog input under the following conditions : Output impedance rS of the external circuit = 5 kΩ (Max) • If the output impedance of the external circuit is too high, the sampling time of the analog voltage may not be sufficient. When placing a DC blocking capacitor between the external circuit and input pin, set the capacitance to the value calculated by multiplying CSH by several thousands as a guideline in order to minimize the impact from dividing voltage capacitance with CSH. 73 MB91245/S Series • Analog Input Equivalent Circuit Circuit in microcontroller Input pin AN0 RSH rs CSH Comparator Input pin AN7 Vs S/H circuit External circuit Analog channel selector <Recommended parameter values and tentative guideline for each element> rS = 5 kΩ or less RSH = approx. 2.5 kΩ CSH = approx. 10 pF Note : These element parameters should be regarded as tentative values used only for design purposes. They are not guaranteed values. 74 MB91245/S Series (2) Term Definitions • Resolution Level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, the analog voltage can be resolved into 210 = 1024. • Total error Difference between actual and theoretical values, which is a total value derived from an offset error, gain error, non-linearity error and noise. • Linearity error Deviation between the value along a straight line connecting the zero transition point (“00 0000 0000”←→ “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1110”←→“11 1111 1111”) compared with the actual conversion values obtained. • Differential linearity error Deviation of input voltage, which is required for changing output code by1 LSB, from an ideal value. 75 MB91245/S Series • 10-bit A/D Converter- Conversion Characteristics 11 1111 1111B 11 1111 1110B 11 1111 1101B 11 1111 1100B . . . 1 LSB x N + VOT . Digital output . . . . . . Linearity error . . . 00 0000 0011B 00 0000 0010B 00 0000 0001B 00 0000 0000B VNT V(N + 1)T VOT Analog input 1 LSB = Linearity error = Differential linearity error = N VOT VFST VNT 76 VFST− VOT 1022 VNT− (1 LSB × N + VOT) 1 LSB V (N + 1) T − VNT −1 1 LSB [LSB] [LSB] : A/D converter digital output value. : Voltage at which digital output transits from 000H to 001H. : Voltage at which digital output transits from 3FEH to 3FFH. : A voltage at which digital output transits from (N − 1) to N. VFST MB91245/S Series ■ EXAMPLE CHARACTERISTICS (1) Power supply current (at main RUN) ICC - VCC 500 90 450 80 400 70 350 60 300 50 40 200 150 20 100 10 50 4 4.5 VCC (V) 5 (3) Power supply current (at stop : when oscillation stops) ICCH - VCC 4 4.5 VCC (V) 5 5.5 (4) Power supply current (at stop : when using RTC 4 MHz) ICTS - VCC TA = + 25 °C 500 TA = + 25 °C 450 400 350 ICTS (µA) 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 3.5 0 3.5 5.5 TA = + 25 °C 250 30 0 3.5 ICCH (µA) ICCL - VCC TA = + 25 °C ICCL (µA) ICC (mA) 100 (2) Power supply current (at sub RUN) 300 250 200 150 100 50 4 4.5 VCC (V) 5 5.5 0 3.5 4 4.5 VCC (V) 5 5.5 (Continued) 77 MB91245/S Series (5) A/D power supply current IA - VCC VCC = AVCC = AVRH TA = + 25 °C 5 900 4 800 3.5 700 3 600 2.5 2 500 400 1.5 300 1 200 0.5 100 0 3.5 4 5 4.5 VCC (V) IR - VCC VCC = AVCC = AVRH TA = + 25 °C 1000 4.5 IR (µA) IA (mA) (6) A/D reference voltage supply current 0 3.5 5.5 4 4.5 VCC (V) 5 5.5 (7) “H” level input voltage/“L” level input voltage (8) “H” level input voltage/“L” level input voltage (Automotive input) (CMOS hysteresis input) VIN - VCC VIN - VCC TA = + 25 °C 5 5 4.5 4.5 4 VIHS 3.5 3 3 VIN (V) VIN (V) 4 3.5 VILS 2.5 2 2 1.5 1 1 0.5 0.5 4 4.5 VCC (V) 5 5.5 VIH 2.5 1.5 0 3.5 TA = + 25 °C 0 3.5 VIL 4 4.5 VCC (V) 5 5.5 (Continued) 78 MB91245/S Series (Continued) (9) “H” level output voltage (10) “H” level output voltage VOH2 - IOH VOH1 - IOH VCC = DVCC = 5.0 V TA = + 25 °C 0.7 0.7 0.6 0.6 VCC - VOH2 (V) VCC - VOH1 (V) 0.8 0.5 0.4 0.3 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 0 −1 −2 −3 IOH (mA) −4 VCC = DVCC = 5.0 V TA = + 25 °C 0.8 0 −5 (11) “L” level output voltage 0 −10 VOL1 - IOL −40 VOL2 - IOL 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.3 VCC = DVCC = 5.0 V TA = + 25 °C 0.8 VOL2 (V) VOL1 (V) −30 (12) “L” level output voltage VCC = DVCC = 5.0 V TA = + 25 °C 0.8 −20 IOH (mA) 0.4 0.3 0.2 0.2 0.1 0.1 0 0 0 1 2 3 IOL (mA) 4 5 0 10 20 IOL (mA) 30 40 79 MB91245/S Series ■ ORDERING INFORMATION Part number 80 Package Remarks MB91V245ACR-ES 401-pin ceramic PGA (PGA-401C-A02) Evaluation product MB91F248PFV-GSE1 144-pin plastic LQFP (FPT-144P-M08) Dual clock product MB91F248SPFV-GSE1 144-pin plastic LQFP (FPT-144P-M08) Single clock product MB91247PFV-GSE1 144-pin plastic LQFP (FPT-144P-M08) Dual clock product MB91247SPFV-GSE1 144-pin plastic LQFP (FPT-144P-M08) Single clock product MB91248PFV-GSE1 144-pin plastic LQFP (FPT-144P-M08) Dual clock product MB91248SPFV-GSE1 144-pin plastic LQFP (FPT-144P-M08) Single clock product MB91245/S Series ■ PACKAGE DIMENSION 144-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 20.0 × 20.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 1.20g Code (Reference) P-LFQFP144-20×20-0.50 (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 22.00±0.20(.866±.008)SQ * 20.00±0.10(.787±.004)SQ 108 0.145±0.055 (.006±.002) 73 109 72 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 0˚~8˚ INDEX 144 37 "A" LEAD No. 1 36 0.50(.020) C 0.22±0.05 (.009±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) M 2003 FUJITSU LIMITED F144019S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 81 MB91245/S Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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