FUJITSU MB91305

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16703-1E
32-bit Microcontroller
CMOS
FR60 MB91305
MB91305
■ DESCRIPTION
MB91305 is a single-chip microcontroller that has a 32-bit high-performance RISC CPU as well as built-in I/O
resources for embedded controllers requiring high-performance and high-speed CPU processing.
The FR family is the most suitable for embedded applications, for example, DVD player, printer, TV, and PDP
control, that require a high level of CPU processing power.
MB91305 is an FR60 model that is based on the FR30/40 of CPUs. It has enhanced bus access and is optimized
for high-speed use.
■ FEATURES
1. FR CPU
• 32-bit RISC, load/store architecture, 5 stages pipeline
• With USB function (MOD = 0000B) : operating frequency of 64 MHz [original oscillation at 48 MHz] 48 MHz /
3-divided × 4 multiplication
(Continued)
■ PACKAGE
176-pin plastic LQFP
(FPT-176P-M07)
Copyright©2006 FUJITSU LIMITED All rights reserved
MB91305
(Continued)
• With no USB function (MOD = 0010B) : operating frequency of 64 MHz [original oscillation at 16 MHz]
16 MHz × 4 multiplication
• 16-bit fixed-length instructions (basic instructions) , one instruction per cycle
• Memory-to-memory transfer, bit processing, instructions including barrel shift, etc. : instructions appropriate
for embedded applications
• Function entry and exit instructions, multi load/store instructions of register contents : instructions compatible
with high-level languages
• Register interlock function to facilitate assembly-language coding
• Built-in multiplier/instruction-level support
- Signed 32-bit multiplication : 5 cycles
- Signed 16-bit multiplication : 3 cycles
• Interrupts (saving of PC and PS) : 6 cycles, 16 priority levels
• Harvard architecture enabling simultaneous execution of both program access and data access
• 4-word queues in the CPU provided to add an instruction prefetch function
• Instructions compatible with the FR family
2. Bus Interface
This bus interface is used for external bus and internal macro USB function.
• Maximum operating frequency of 32 MHz
• 16-bit data input-output
• Totally independent 8-area chip select outputs that can be defined in the minimum units of 64K bytes. The
CS2 and CS3 areas are reserved as shown below. CS0, CS1, and CS4 to CS7 can be used only.
- CS2 area : USB function
- CS3 area : Unused
• Basic bus cycle (2 cycles)
• Automatic wait cycle generator that can be programmed for each area and can insert waits because CS2 and
CS3 are reserved, the setting is fixed.
• 24-bit address can be fully outputted
• 8- and 16-bit data I/O
• Prefetch buffer installed
• Unused data and address pins can be used as general-purpose I/O and resource function.
• Support of interfaces for various memory modules
Asynchronous SRAM, asynchronous ROM/Flash memory
Page-mode ROM/Flash memory (a page-size of 1, 2, 4, or 8 can be selected)
Burst-mode ROM/Flash memory (MBM29BL160D/161D/162D etc.)
SDRAM (or FCRAM type, CAS Latency1 to Latency8, 2/4 bank product)
Address/data multiplexed bus (8-bit/16-bit width only)
• Basic bus cycle : 2 cycles
• Automatic wait cycle generator (Max 15 cycles) that can be programmed for each area
• External wait cycles due to RDY input
• Endian setting of byte ordering (big/little)
Note : CS0 area is only big endian.
• Write disable setting (read only area)
• Enable/disable set of capturing to the built-in cache
• Enable/disable set of prefetch function
• External bus arbitration using BRQ and BGRNT is enabled
3. Built-in Memory
64K bytes RAM of built-in F-bus
2
MB91305
4. Instruction Cache Memory
•Instruction cache : 4K bytes
•2 way set associative
•128 block/way, 4 entry (4 words) /block
•Lock function allows specific program codes to stay resident in cache.
•Instruction RAM function : A part of the instruction cache not in use can be used as RAM for instruction execution
5. DMAC (DMA Controller)
•5 channels (channels 1 and 2 are connected to the USB function.)
•3 transfer sources (internal peripherals, software)
•Addressing mode with 32-bit full address specifications (increase, decrease, fixed)
•Transfer modes (demand transfer, burst transfer, step transfer, block transfer)
•Transfer data size that can be selected from 8, 16, and 32 bits
6. Bit Search Module (Used by REALOS)
Searches for the position of the first bit varying between 1 and 0 in the MSB of a word
7. 16-bit Reload Timer (Including One Channel for REALOS)
•16-bit timer; 3 channels
•Internal clock that can be selected from those resulting from frequency divided by 2, 8, and 32
8. UART
•Full-duplex double buffer
•5 channels
•Parity or no parity can be selected.
•Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected.
•Built-in timer for dedicated baud rates
•An external clock can be used as the transfer clock.
•Plentiful error detection functions (parity, frame, overrun)
9. I2C Interface*
•4 channels (bridge function and pin function for 5 channels)
•Master/slave transmission and reception
•Clock synchronization function
•Transfer direction detection function
•Bus error detection function
•Supports standard mode (Max 100 Kbps) and high-speed mode (Max 400 Kbps) .
•Built-in FIFO function : each 16-byte sending/receiving
•Arbitration function
•Slave address/general call address detection function
•Start condition repetitious occurrence and detection function
•10-bit/7-bit slave address
10.Interrupt Controller
•Total of 17 external interrupts (one unmaskable interrupt pin (NMI) and 16 regular interrupt pins (INT15 to INT0) )
•Interrupts from internal peripherals
•Priority level can be defined as programmable (16 levels) except for the unmaskable interrupt pin.
•Can be used for wake-up during stop.
11.10-bit A/D Converter
•10-bit resolution, 10 channels
•Sequential comparison and conversion type (conversion time : about 8.18 µs)
•Conversion modes (single conversion mode and scan conversion mode)
•Causes of startup (software and external triggers)
3
MB91305
12. PPG
• 4 channels
• 16-bit data register with 16-bit down counter and cycle setting buffer
• Internal clock : Frequency-divide-by number selectable from 1, 4, 16, and 64
13. PWC
• 1 channel (1 input)
• 16-bit up counter
• Simple Low-pass digital filter
14. 16-bit Free-run Timer
• 16-bit 1channel
• Input capture 4 channels
15. USB Function (Enabling/Disabling Function Can Be Selected by Mode Pin)
• USB2.0 full-speed, double buffer
• Configuration of FIFO for End point
CONTROL IN/OUT, BULK IN/OUT, and INTERRUPT IN
16. Other Interval Timers
Watchdog timer
17. I/O Ports
Maximum of 98 ports
18. Other Features
•
•
•
•
•
•
•
•
•
Has a built-in oscillation circuit as a clock source.
INIT is provided as a reset pin.
Additionally, a watchdog timer reset and software resets are provided.
Stop mode and sleep mode supported as low-power consumption modes
Gear function
Built-in timebase timer
Package : LQFP-176, 0.5 mm pitch, and 24 mm × 24 mm
CMOS technology : 0.18 µm
Power supply voltage : two sources (0.18 µm) of 3.3 V (−0.3 V to +0.3 V) and 1.8 V (−0.15 V to +0.15 V)
* : LICENSE
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
4
MB91305
■ PIN ASSIGNMENT
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
D23/P27
D22/P26
D21/P25
D20/P24
D19/P23
D18/P22
D17/P21
D16/P20
VDDI
VSS
VDDE
PE2/DEOP2/TRG3
PE1/DACK2/TRG2
PE0/DREQ2/TRG1
PD5/DEOP1/TIN2
PD4/DACK1/TIN1
PD3/DREQ1/TIN0
PD2/DEOP0
PD1/DACK0
PD0/DREQ0
PC7/RIN/IORD
PC6/TOUT2/IOWR
PC5/TOUT1
PC4/TOUT0/TRG0
PC3/PPG3
PC2/PPG2
PC1/PPG1
PC0/PPG0
VDDI
VSS
UDM
UDP
VDDE
PB7/INT15/ICU3
PB6/INT14/ICU2
PB5/INT13/ICU1
PB4/INT12/ICU0
PB3/INT11/FRCK
PB2/INT10/ATRG
PB1/INT9
PB0/INT8
PA7/INT7
PA6/INT6
PA5/INT5
(TOP VIEW)
VDDE
VSS
VDDI
D24
D25
D26
D27
D28
D29
D30
D31
VDDE
VSS
VDDI
RD
WR0/DQMUU
WR1/DQMUL/P30
CS0/P31
CS1/P32
CS4/P33
CS5/P34
CS6/P35
CS7/P36
RDY/P37
P40/BGRNT
P41/BRQ
SYSCLK/P42
MCLKE/P43
MCLK/P44
P45/SRAS/LBA/AS
P46/SCAS/BAA
P47/SWE/WR
VDDE
VSS
VDDI
A0
A1
A2
A3
A4
A5
A6
A7
A8
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PA4/INT4
PA3/INT3
PA2/INT2
PA1/INT1
PA0/INT0
NMI
VDDI
VSS
VDDE
P97/SDA4
P96/SCL4
P95/SDA3
P94/SCL3
P93/SDA2
P92/SCL2
P91/SDA1
P90/SCL1
P84/SDA0
P83/SCL0
P82/SCK4
P81/SOUT4
P80/SIN4
P75/SCK3
P74/SOUT3
P73/SIN3
P72/SCK2
P71/SOUT2
P70/SIN2
P65/SCK1
P64/SOUT1
P63/SIN1
P62/SCK0
P61/SOUT0
P60/SIN0
VDDI
VSS
VDDE
TRST
ICLK
IBREAK
ICD3
ICD2
ICD1
ICD0
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
ICS2
ICS1
ICS0
AN9/PF7
AN8/PF6
AN7/PF5
AN6/PF4
AN5/PF3
AN4/PF2
AN3/PF1
AN2/PF0
AN1
AN0
AVSS
AVRH
AVCC
MD3
MD2
MD1
MD0
INIT
VDDI
X1
VSS
X0
VDDE
A23/P57
A22/P56
A21/P55
A20/P54
A19/P53
A18/P52
A17/P51
A16/P50
VDDI
VSS
VDDE
A15
A14
A13
A12
A11
A10
A9
(FPT-176P-M07)
5
MB91305
■ PIN DESCRIPTION
• Function pins
Pin no.
169 to 176
Pin name
D16 to D23
P20 to P27
I/O
Type*
C
Function
External data bus bit16 to bit23. It is available in the external bus mode.
Can be used as ports in 8-bit external bus mode.
4 to 11
D24 to D31
C
External data bus bit24 to bit31.
It is available in the external bus mode.
15
RD
H
External bus read strobe output. This pin is enabled at external bus mode.
16
WR0
/DQMUU
H
External bus write strobe output. This pin is enabled at external bus mode.
When WR is used as the write strobe, this becomes the byte-enable pin
(DQMUU) .
17
18
WR1
/DQMUL
D
External bus write strobe output. The pin is enabled when WR1 output is
enabled in the external bus mode. When WR is used as the write strobe, this
becomes the byte-enable pin (DQMUL) .
P30
General-purpose input/output port. The pin is enabled when the external bus
write-enable output is disabled.
CS0
Chip select 0 output. This pin is enabled at external bus mode.
P31
D
CS1
19
D
General-purpose input/output port. This pin is enabled in the single-chip
mode.
Chip select 1 output. This function is enabled when chip select 1 output is
enabled.
P32
General-purpose input/output port. This function is enabled when chip select
1 output is disabled.
CS4
Chip select 4 output. This function is enabled when chip select 4 output is
enabled.
D
20
P33
General-purpose input/output port. This function is enabled when chip select
4 output is disabled.
CS5
Chip select 5 output. This function is enabled when chip select 5 output is
enabled.
21
D
P34
General-purpose input/output port. This function is enabled when chip select
5 output is disabled.
CS6
Chip select 6 output. This function is enabled when chip select 6 output is
enabled.
22
D
P35
General-purpose input/output port. This function is enabled when chip select
6 output is disabled.
CS7
Chip select 7 output. This function is enabled when chip select 7 output is
enabled.
23
D
P36
General-purpose input/output port. This function is enabled when chip select
7 output is disabled.
(Continued)
6
MB91305
Pin no.
Pin name
I/O
Type*
RDY
24
D
P37
BGRNT
25
D
Acceptance output for external bus release.
Outputs “L” when the external bus is released. This function is enabled when
output is enabled.
BRQ
External bus release request input. Input "1" to request release of the external
bus. The function is enabled when input is enabled.
D
P41
General-purpose input/output port. This function is enabled when the external
bus release request is disabled.
SYSCLK
System clock output. This function is enabled when system clock output is
enabled. This outputs the same clock as the external bus operating frequency.
(Output halts in stop mode.)
D
General-purpose input/output port. This function is enabled when system clock
output is disabled.
P42
MCLKE
P43
Clock enable signal for SDRAM.
D
MCLK
29
D
General-purpose input/output port. This function is enabled when memory
clock output is disabled.
Memory clock output. This function is enabled when memory clock output is
enabled. This outputs the same clock as the external bus operating frequency.
(Output halts in sleep mode.)
P44
General-purpose input/output port. This function is enabled when memory
clock output is disabled.
AS
Address strobe output. This function is enabled when address strobe output is
enabled.
LBA
Address load output for burst flash memory. This function is enabled when
address load output is enabled.
D
SRAS
31
General-purpose input/output port. This function is enabled when external
ready input is disabled.
General-purpose input/output port. This function is enabled when external bus
release acceptance is disabled.
27
30
External ready input. This function is enabled when external ready input is
enabled.
P40
26
28
Function
RAS strobe single for SDRAM.
P45
General-purpose input/output port. This function is enabled when address load
output is disabled.
BAA
Address advance output for burst flash memory. This function is enabled when
address advance output is enabled.
SCAS
P46
D
CAS strobe signal for SDRAM.
General-purpose input/output port. This function is enabled when address
advance output is disabled.
(Continued)
7
MB91305
Pin no.
Pin name
I/O
Type*
Memory write strobe output. This function is enabled when write strobe output is enabled.
WR
32
SWE
D
55 to 62
A0 to A15
A16 to A23
P50 to P57
Write output for SDRAM.
General-purpose input/output port. This function is enabled when write
strobe output is disabled.
P47
36 to 51
Function
H
D
External address bus bit0 to bit15.
External address bus bit16 to bit23.
Can be used as ports when external address bus is not used.
64
X0
66
X1
68
INIT
B
External reset input (Reset to initialize settings)
69 to 71
MD0 to
MD2
I
These pins set the basic operating mode. Connect VCC or VSS.
72
MD3
J
These pins set the basic operating mode. Connect VCC or VSS.
76, 77
AN0, AN1
M
Analog input pin.
78 to 85
AN2 to
AN9
F
A
PF0 to PF7
Clock (oscillation) input.
Clock (oscillation) output.
Analog input pin.
Can be used as ports when analog input pin is not used.
86 to 88
ICS0 to
ICS2
C
Status output pin for development tool.
89 to 92
ICD0 to
ICD3
L
Data input/output pin for development tool.
93
IBREAK
J
Break pin for development tool.
94
ICLK
D
Clock pin for development tool.
95
TRST
B
Reset pin for development tool.
D
UART0 data input pin. This input is used continuously when UART0 is
performing input. In this case, do not output to this port unless doing so
intentionally.
99
SIN0
P60
100
SOUT0
General-purpose input/output port.
D
P61
101
SCK0
P62
UART0 data output pin. This function is enabled when UART0 data output is
enabled.
General-purpose input/output port.
D
UART0 clock input/output pin. This function is enabled when UART0 clock
output is enabled.
General-purpose input/output port.
(Continued)
8
MB91305
Pin no.
102
Pin name
SIN1
I/O
Type*
D
P63
103
SOUT1
104
105
D
D
108
General-purpose input/output port.
SIN2
UART2 data input pin. This input is used continuously when UART2 is
performing input. In this case, do not output to this port unless doing so
intentionally.
D
SOUT2
General-purpose input/output port.
D
SCK2
D
111
General-purpose input/output port.
SIN3
UART3 data input pin. This input is used continuously when UART3 is
performing input. In this case, do not output to this port unless doing so
intentionally.
D
SOUT3
General-purpose input/output port.
D
SCK3
UART3 data output pin. This function is enabled when UART3 data output is
enabled.
General-purpose input/output port.
D
UART3 clock input/output pin. This function is enabled when UART3 clock
output is enabled.
P75
General-purpose input/output port.
SIN4
UART4 data input pin. This input is used continuously when UART4 is
performing input. In this case, do not output to this port unless doing so
intentionally.
D
P80
112
UART2 clock input/output pin. This function is enabled when UART2 clock
output is enabled.
P72
P74
110
UART2 data output pin. This function is enabled when UART2 data output is
enabled.
General-purpose input/output port.
P73
109
UART1 clock input/output pin. This function is enabled when UART1 clock
output is enabled.
P65
P71
107
UART1 data output pin. This function is enabled when UART1 data output is
enabled.
General-purpose input/output port.
P70
106
UART1 data input pin. This input is used continuously when UART1 is
performing input. In this case, do not output to this port unless doing so
intentionally.
General-purpose input/output port.
P64
SCK1
Function
SOUT4
P81
General-purpose input/output port.
D
UART4 data output pin. This function is enabled when UART4 data output is
enabled.
General-purpose input/output port.
(Continued)
9
MB91305
Pin no.
113
Pin name
SCK4
I/O
Type*
D
P82
114
SCL0
SDA0
D
116
D
SDA1
D
118
D
SDA2
K
120
K
SDA3
K
122
P96
Clock I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
K
P95
SCL4
Data I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
P94
121
Clock I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
P93
SCL3
Data I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
P92
119
Clock I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
P91
SCL2
Data I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
P90
117
Clock I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
P84
SCL1
UART4 clock input/output pin. This function is enabled when UART4 clock
output is enabled.
General-purpose input/output port.
P83
115
Function
Data I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
K
Clock I/O pin for I2C bus. This function is enabled when typical operation of
I2C is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
(Continued)
10
MB91305
Pin no.
123
Pin name
SDA4
I/O
Type*
K
P97
127
NMI
128 to 131
INT0 to
INT3
INT4
B
NMI (Non Maskable Interrupt) input
G
External interrupt inputs. These inputs are used continuously when the
corresponding external interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
General-purpose input/output port.
G
PA4
133 to 135
INT5 to
INT7
136
137
External interrupt input. These inputs are used continuously when the
corresponding external interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally. When USB function is enabled
(MD3, MD2, MD1, MD0 = 0000B) , INT4 function is used only for the USB
interrupt. Therefore, it is not possible to use it as an external interrupt pin.
General-purpose input/output port.
G
PA5 to PA7
INT8
Data I/O pin for I2C bus. This function is enabled when typical operation of I2C
is enabled. The port output must remain off unless intentionally turned on.
(pseudo open drain output)
General-purpose input/output port.
PA0 to PA3
132
Function
External interrupt input. These inputs are used continuously when the
corresponding external interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
General-purpose input/output port.
G
External interrupt input. These inputs are used continuously when the
corresponding external interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
PB0
General-purpose input/output port.
INT9
External interrupt input. These inputs are used continuously when the
corresponding external interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
G
PB1
General-purpose input/output port.
External interrupt input. These inputs are used continuously when the
corresponding external interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
INT10
138
G
ATRG
PB2
General-purpose input/output port.
External interrupt input. These inputs are used continuously when the
corresponding external interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
INT11
139
G
FRCK
PB3
A/D converter external trigger input. These inputs are used continuously
when using as A/D start trigger. In this case, do not output to these ports
unless doing so intentionally.
External clock input pin of free-run timer. These inputs are used continuously
when using as external clock input pin of free-run timer. In this case, do not
output to these ports unless doing so intentionally.
General-purpose input/output port.
(Continued)
11
MB91305
Pin no.
Pin name
I/O
Type*
External interrupt input. These inputs are used continuously when the
corresponding external interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
INT12 to
INT15
140 to 143
ICU0 to
ICU3
G
PB4 to
PB7
145
UDP
146
UDM
149 to 152
PPG0 to
PPG3
PC0 to
PC3
TRG0
USB
154
General-purpose input/output port.
Data output of reload timer 0. This function is enabled when data output of
reload timer 0 is enabled using port function register.
D
D
Data output of reload timer 1. This function is enabled when data output of
reload timer 1 is enabled using port function register.
General-purpose input/output port.
Data output of reload timer 2. This function is enabled when data output of
reload timer 2 is enabled using port function register.
D
Write strobe output for DMA fly-by transfer. This function is enabled when
outputting a write strobe for DMA fly-by transfer is enabled.
PC6
General-purpose input/output port.
RIN
PWC input. These inputs are used continuously when the corresponding
external interrupt is enabled. In this case, do not output to these ports unless
doing so intentionally.
156
157
External trigger input for PPG0 timer. This input is used continuously when
the corresponding timer input is enabled. In this case, do not output to this
port unless doing so intentionally.
General-purpose input/output port.
TOUT2
IOWR
− pin of USB.
PPG ch.0 to PPG ch.3 timer output.
PC5
155
+ pin of USB.
D
PC4
TOUT1
Input capture input pins. These inputs are used continuously when selected
as input capture inputs. In this case, do not output to these ports unless doing
so intentionally.
General-purpose input/output port.
TOUT0
153
Function
D
IORD
Read strobe output for DMA fly-by transfer. This function is enabled when
outputting a read strobe for DMA fly-by transfer is enabled.
PC7
General-purpose input/output port.
DREQ0
PD0
D
External input for DMA transfer requests. This input is used continuously
when the corresponding external input for DMA transfer requests are
enabled. In this case, do not output to this port unless doing so intentionally.
General-purpose input/output port.
(Continued)
12
MB91305
Pin no.
158
Pin name
DACK0
I/O
Type*
D
PD1
159
DEOP0
DMA external transfer request acceptance output. This function is enabled
when DMA external transfer request acceptance output is enabled.
General-purpose input/output port.
D
PD2
Completion output for DMA external transfer. This function is enabled when
completion output for DMA external transfer is enabled.
General-purpose input/output port.
DREQ1
160
Function
D
External input for DMA transfer requests. This input is used continuously
when external input for DMA transfer request is enabled. In this case, do not
output to this port unless doing so intentionally. When using USB, this
function (DMAC ch.1) cannot be used because it is used as USB data
transfer. DREQ2 input is disabled.
TIN0
Reload timer input. This input is used continuously when the corresponding
timer input is enabled. In this case, do not output to this port unless doing so
intentionally.
PD3
General-purpose input/output port.
DACK1
D
161
DMA external transfer request acceptance output. This function is enabled
when DMA transfer request acceptance output is enabled.
When using USB, this function (DMAC ch.1) cannot be used because it is
used as USB data transfer. External transfer ACK output of DMA should be
disabled.
TIN1
Reload timer input. This input is used continuously when the corresponding
timer input is enabled. In this case, do not output to this port unless doing so
intentionally.
PD4
General-purpose input/output port.
Completion output for DMA external transfer. This function is enabled when
completion output for DMA external transfer is enabled. When using USB, this
function (DMAC ch.1) cannot be used because it is used as USB data
transfer. External transfer EOP output of DMA should be disabled.
DEOP1
162
D
TIN2
Reload timer input. This input is used continuously when the corresponding
timer input is enabled. In this case, do not output to this port unless doing so
intentionally.
PD5
General-purpose input/output port.
DREQ2
163
D
TRG1
PE0
External input for DMA transfer requests. This input is used continuously
when external input for DMA transfer request is enabled. In this case, do not
output to this port unless doing so intentionally.
When using USB, this function (DMAC ch.2) cannot be used because it is
used as USB data transfer. DREQ2 input is disabled.
External trigger input for PPG1 timer. This input is used continuously when
the corresponding timer input is enabled. In this case, do not output to this
port unless doing so intentionally.
General-purpose input/output port.
(Continued)
13
MB91305
(Continued)
Pin no.
Pin name
I/O
Type*
DMA external transfer request acceptance output. This function is enabled
when DMA transfer request acceptance output is enabled.
When using USB, this function (DMAC ch.2) cannot be used because it is
used as USB data transfer. External transfer ACK output of DMA should be
disabled.
DACK2
164
D
External trigger input for PPG2 timer. This input is used continuously when the
corresponding timer input is enabled. In this case, do not output to this port
unless doing so intentionally.
TRG2
PE1
General-purpose input/output port.
Completion output for DMA external transfer. This function is enabled when
completion output for DMA external transfer is enabled.
When using USB, this function (DMAC ch.2) cannot be used because it is
used as USB data transfer. External transfer EOP output of DMA should be
disabled.
DEOP2
165
Function
D
External trigger input for PPG3 timer. This input is used continuously when the
corresponding timer input is enabled. In this case, do not output to this port
unless doing so intentionally.
TRG3
PE2
General-purpose input/output port.
* : For I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
• Power supply and GND pins
14
Pin no.
Pin name
Function
2, 13, 34, 53, 65, 97,
125, 147, 167
VSS
GND pins.
Connect all pins at the same potential.
3, 14, 35, 54, 67, 98,
126, 148, 168
VDDI
1.8 V power supply pins.
Connect all pins at the same potential.
1, 12, 33, 52, 63, 96,
124, 144, 166
VDDE
3.3 V power supply pins.
Connect all pins at the same potential.
73
AVCC
Analog power supply pin for A/D converter
74
AVRH
Reference power supply pin for A/D converter
75
AVSS
Analog GND pin for the A/D converter
MB91305
■ I/O CIRCUIT TYPES
Type
Circuit
Remarks
Oscillation feedback resistance
approx. 1MΩ
X1
Clock input
A
X0
Standby control
P-ch
• With pull-up resistor
• CMOS level hysteresis input
P-ch
B
N-ch
Digital input
• CMOS level I/O
• With standby control
• IOL = 4 mA
P-ch
Digital output
C
Digital output
N-ch
Digital input
Standby control
(Continued)
15
MB91305
Type
Circuit
Remarks
P-ch
Digital output
D
•
•
•
•
CMOS level output
CMOS level hysteresis input
With standby control
IOL = 4 mA
Digital output
N-ch
Digital input
Standby control
• CMOS level input
• No standby control
P-ch
E
N-ch
Digital input
P-ch
Digital output
•
•
•
•
•
CMOS level output
CMOS level hysteresis input
With standby control
With analog input
IOL = 4 mA
Digital output
N-ch
F
Analog input
Digital input
Standby control
(Continued)
16
MB91305
Type
Circuit
Remarks
Pull-up control
P-ch
P-ch
Digital output
•
•
•
•
•
With pull-up control
CMOS level output
CMOS level hysteresis input
No standby control
IOL = 4 mA
G
Digital output
N-ch
Digital input
CMOS level output
P-ch
Digital output
H
Digital output
N-ch
• CMOS level hysteresis input
• No standby control
P-ch
I
N-ch
Digital input
(Continued)
17
MB91305
Type
Circuit
Remarks
• CMOS level hysteresis input
• With pull-down resistor
P-ch
J
N-ch
N-ch
Digital input
P-ch
Open-drain control
•
•
•
•
3 ports for I2C
CMOS level hysteresis input
CMOS level output
With stop control
Digital output
N-ch
Digital input
Control
Digital input
K
Control
Open-drain control
P-ch
Digital output
N-ch
Digital input
P-ch
Open-drain control
Digital output
N-ch
(Continued)
18
MB91305
(Continued)
Type
Circuit
Remarks
Pull-down control
• CMOS I/O
• With pull-down control
P-ch
Digital output
L
Digital output
N-ch
N-ch
Digital input
Analog pin
P-ch
M
N-ch
Analog input
19
MB91305
■ HANDLING DEVICES
• Preventing a Latch-up
A latch-up can occur on a CMOS IC under following conditions. A latch-up, if it occurs, significantly increases
the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very
careful not to exceed the maximum rating.
- When a voltage higher than VDDE or VDDI or a voltage lower than VSS is applied to an input or output pin.
- When a voltage higher than the rating is applied between VDDE or VDDI and VSS.
• Handling of Unused Input Pins
Do not leave an unused input pin open since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor.
• Power Supply Pins
If more than one VDDE or VDDI or VSS pin exists, those that must be kept at the same potential are designed
to be connected to one other inside the device to prevent malfunctions such as latch-up. Be sure to connect the
pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation, prevent
strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating.
Given consideration to connecting the current supply source to VDDE or VDDI and VSS pin of the device at the
lowest impedance possible.
It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VDDE or VDDI and
VSS pin at circuit points close to the device as a bypass capacitor.
• Quartz Oscillation Circuit
Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boards so that X0, X1,
the quartz oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as near to one another
as possible.
It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pins with ground be
used to increase the expectation of stable operation.
Please ask the Oscillation maker to evaluate the oscillational characteristics of the crystal and this device.
• Mode Pins (MD0 to MD3)
In order to prevent mistakes due to noise, and sending them into test mode, connect these pins as close to
VDDE and VSS pins, and at as low an impedance as possible.
• Tool Reset Pins (TRST)
Be sure to input the same signal as the INIT when this pin is not used for the tool. The same processing is
executed for the mass product.
• Power-on
Immediately after power-on, be sure to apply setting initialization reset (INIT) with INIT pin.
Also immediately after power-on, keep the INIT pin at the “L” level until the oscillator has reached the required
oscillation stabilization wait time. (For initialization by INIT from the INIT pin, the oscillation stabilization wait time
is set to the minimum value.)
• Source Oscillation Input at Power-on
At power-on, be sure to input a source clock until the oscillation stabilization wait time is reached.
20
MB91305
• Precautions at Power-On/Power-Off
• Precautions when turning on and off VDDI pin and VDDE pin
To ensure the reliability of LSI devices, do not continuously apply only VDDE pin for about a minute when VDDI
is off.
When VDDE pin is changed from off to on, the power noise may make it impossible to retain the internal state
of the circuit.
Power-on : Supply voltage of VDDI pin → analog → Supply voltage of VDDE pin → signal
Power-off : Signal → Supply voltage of VDDE pin → analog → Supply voltage of VDDI pin
• Indeterminate Output when the Power is Turned On
When turning on the power, the output pin may remain indeterminate until internal power supply becomes stable.
• Clocks
• Notes on using external clock
When the external clock is used, in principle, supply a clock signal to the X0 pin and an opposite-phase clock
signal to the X1 pin at the same time. However, in this case the STOP mode (oscillation stop mode) must not
be used (This is because, in the STOP mode, the X1 pin stops at “H” output).
Example of using an external clock is illustrated in the following figure.
Example of using external clock (normal)
X0
X1
MB91305
The STOP mode (oscillation stop mode) cannot be used.
• Limitations
• Clock controller
Secure the stabilization wait time while “L” is input to INIT pin.
• Bit search module
Only word access is permitted for data register for detection 0 (BSD0), data register for detection 1 (BSD1), and
data register for change point detection (BSDC) .
• I/O port
Only byte access is permitted for ports.
21
MB91305
• Low-power Consumption Mode
To switch to standby mode, use synchronous standby mode (set by the SYNCS bit, that is bit8 of the TBCR,
timebase counter control register) and be sure to use the following sequence :
(LD1 #value_of_stanby, R0)
(LD1 #_STCR, R12)
STB
R0, @R12 : Writing into the standby control register (STCR)
LDUB @R12, R0 : STCR read for synchronous standby
LDUB @R12, R0 : Dummy re-read of STCR
NOP
: NOP × 5 for timing adjustment
NOP
NOP
NOP
NOP
• When using the monitor debugger, do not :
- Set a break point within the above sequence of instructions.
- Step of the instructions within the above sequence of instructions.
• Prefetch
When allowing prefetch in the little endian area, only word access (32-bit) should be used to access the area.
Byte access and halfword access are not working properly.
• Notes on using PS register
PS register is processed by some instructions in advance so that exception operations as stated below may
cause breaks during interruption handling routine when using debugger and may cause updates to the display
contents of PS flags.
In either case, this device is designed to carry out reprocessing properly after returning from such EIT events.
The operations before and after EIT events are performed as prescribed in the specification.
1. The following operations may be performed when the instruction immediately followed by a DIVOV/DIVOS
instruction is acceptance of a user interrupt/NMI, single-stepped, or breaks in response to an emulator menu.
(1) D0 and D1 flags are updated in advance.
(2) EIT handling routine (user interrupt/NMI, or emulator) is executed.
(3) After returning from the EIT, a DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as in (1) .
2. The following operations are performed if each instruction from ORCCR, STILM, MOV Ri, and PS is executed
to allow an interruption while user interrupt/NMI trigger exists.
(1) PS register is updated in advance.
(2) EIT handling routine (user interrupt/NMI) is executed.
(3) After returning from the EIT, the above instructions are executed and the PS register is updated to
the same value as in (1) .
22
MB91305
• Watchdog Timer Function
The watchdog timer equipped in this model operates to monitor programs to ensure that they execute reset
defer function within a certain period of time, and to reset the CPU if the reset defer function is not executed
due to the program runaway. For that reason, once the watchdog timer function is enabled, it keeps its operation
until it is reset.
By way of exception, the watchdog timer automatically defers a reset under the condition where the CPU
program executions are stopped. For more detail, refer to the description section of the watchdog timer function
in “Hardware Manual”.
If the system gets out of control and the situation becomes as mentioned above, watchdog reset may not be
generated. In that case, please reset (INIT) from the external INIT pin.
• Note on using A/D
The MB91305 has a built-in A/D converter. Do not supply a voltage higher than VDDE to the AVCC.
• Software reset in synchronous mode
When software reset in the synchronous mode is used, the following two conditions must be satisfied before
setting the SRST bit of the STCR (standby control register) to 0.
- Set the interrupt enable flag (I-Flag) to the interrupt disabled (I-Flag = 0).
- Do not use NMI.
• Simultaneous occurrences of software break and user interrupt/NMI
If software break and user interrupt/NMI occur together, emulator debugger may:
- Stop at a point other than the programmed break points.
- Not reexecute properly after halting.
If such failures occur, use hardware break instead of software break. When using monitor debugger, do not set
any break points within the corresponding instructions.
• Stepping of the RETI Instruction
In the environment where interruptions occur frequently during stepping, the RETI is executed repeatedly for
the corresponding interrupt process routines after the stepping. As the result of it, the main routine and low
interrupt- level programs are not executed. To avoid this situation, do not step the RETI instruction. Otherwise,
perform debugging by disabling the interruptions when the debug on the corresponding interrupt routines
becomes unnecessary.
• Operand Break
Do not set the access to the areas containing the address of stack pointer as a target of data event break.
• Sample Batch File for Configuration
When a program is downloaded to internal RAM to execute debug, be sure to execute the following batch file
after reset.
#----------------------------------------------------------------------------------------------------------------------------------# Set MODR (0x7fd) = Enable In memory + 16-bit External Bus
set mem/byte 0x7fd = 0x5
#-----------------------------------------------------------------------------------------------------------------------------------
23
MB91305
■ BLOCK DIAGRAM
FR
CPU Core
32
Instruction
cache 4KB
32
Bit search
Module
RAM 64KB
Bus converter
32 ↔ 16
adapter
DMAC
5 channels
External bus
interface
SDRAM
interface
Clock
control
Interrupt
controller
UART
5 channels
I2C
interface
4 channels
10-bit
A/D converter
10channels
16-bit
Free-run timer
1 channel
PWC
1 channel
PPG
4 channels
16-bit
Reload timer
3 channels
16-bit
Input capture
4 channels
External
interrupt
Port
24
USB
function
MB91305
■ CPU AND CONTROL UNIT
Internal Architecture
The FR family is a high-performance core based on RISC architecture and advanced instructions for embedded
applications.
1. Features
• RISC architecture used
Basic instruction : One instruction per cycle
• 32-bit architecture
General-purpose register : 32 bits × 16
• 4G bytes linear memory space
• Multiplier installed
32-bit by 32-bit multiplication : 5 cycles
16-bit by 16-bit multiplication : 3 cycles
• Enhanced interrupt processing function
Quick response speed : 6 cycles
Support of multiple interrupts
Level mask function : 16 levels
• Enhanced instructions for I/O operations
Memory-to-memory transfer instruction
Bit-processing instructions
• Efficient code
Basic instruction word length : 16 bits
• Low-power consumption
Sleep and stop modes
• Gear function
25
MB91305
2. Internal Architecture
The FR family CPU uses the Harvard architecture, which has separate buses for instructions and data. A 32bit↔16-bit bus converter is connected to the 32-bit bus (F-bus) , providing an interface between the CPU and
peripheral resources. A Harvard↔Princeton bus converter is connected to both the I-bus and D-bus, providing
an interface between the CUP and bus controllers.
FRex CPU
D-bus
I-bus
32
I address
32
Harvard
External
address
24
I data
32
D address
32
D data
32-bit
16-bit
Bus converter
Princeton
bus
converter
address
32
data
32
16
F-bus
R-bus
Peripheral resources
26
Internal I/O
Bus controller
F-bus RAM
External date
16
MB91305
3. Programming Model
• Programming Model
32 bits
Initial value
R0
XXXX XXXXH
R1
General-purpose
register
R12
R13
AC
R14
XXXX XXXXH
FP
R15
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply and
divide registers
MDH
0000 0000H
SP
ILM
SCR
CCR
MDL
27
MB91305
4. Registers
• General-purpose Registers
32 bits
Initial value
R0
R1
R12
R13
R14
R15
XXXX XXXXH
AC
FP
SP
XXXX XXXXH
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers are used as an accumulator in an operation
or a pointer in a memory access.
Of these 16 registers, the following are intended for special applications and therefore enhanced instructions
are provided for them :
• R13 :
Virtual accumulator (AC)
• R14 :
Frame pointer (FP)
• R15 :
Stack pointer (SP)
The initial value upon reset is undefined for R0 through R14 and is “00000000H” (SSP value) for R15.
• PS (Program Status)
The program status register (PS : Program Status) holds the program status. The PS register consists of three
parts : ILM, SCR, and CCR. All undefined bits are reserved. During reading, “0” is always read. Writing is
disabled.
bit31
bit20
bit16
ILM
28
bit10 bit8 bit7
SCR
bit0
CCR
MB91305
• CCR (Condition Code Register)
bit7
⎯
bit6
⎯
bit5
bit4
bit3
S
I
N
bit2 bit1
Z
V
bit0
Initial value
C
--00XXXXB
S : Stack flag
• This bit is cleared to “0” by a reset.
• Set this bit to “0” when the RETI instruction is executed.
I : Interrupt enable flag
This bit is cleared to “0” by a reset.
N : Negative flag
The initial state of this bit upon reset is undefined.
Z : Zero flag
The initial state of this bit upon reset is undefined.
V : Overflow flag
The initial state of this bit upon reset is undefined.
C : Carry flag
The initial state of this bit upon reset is undefined.
• SCR (System Condition code Register)
bit10 bit9
D1
bit8
Initial value
T
XX0B
D0
D1, D0 : Step division flag
These bits hold the intermediate data obtained when step division is executed.
T : Step trace trap flag
This bit specifies whether the step trace trap is to be enabled.
The step trace trap function is used by an emulator. When an emulator is used, this function cannot be used in
a user program.
• ILM (Interrupt Level Mask Register)
bit20 bit19 bit18 bit17 bit16
Initial value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
The interrupt level mask (ILM) register holds an interrupt level mask value. The value held in ILM register is
used as a level mask.
This register is initialized to 15 (01111B) by a reset.
29
MB91305
• PC (Program Counter)
bit31
bit0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction being executed.
The initial value upon reset is undefined.
• TBR (Table Base Register)
bit31
bit0
Initial value
000FFC00H
The table base register holds the first address of the vector table to be used during EIT processing.
The initial value upon reset is “000FFC00H”.
• RP (Return Pointer)
bit31
bit0
Initial value
XXXXXXXXH
The return pointer holds the return address from a subroutine.
When the CALL instruction is executed, the value of the PC is transferred to the RP.
When the RET instruction is executed, the contents of the RP are transferred to the PC.
The initial value upon reset is undefined.
• SSP (System Stack Pointer)
bit31
bit0
Initial value
00000000H
The SSP is the system stack pointer.
This register is used as an R15 general-purpose register if the S flag of the condition code register (CCR) is “0”.
The SSP can also be specified explicitly.
This register is also used as a stack pointer that specifies a stack on which the contents of the PS and PC are
to be saved if an EIT occurs.
The initial value upon reset is “00000000H”.
30
MB91305
• USP (User Stack Pointer)
bit31
bit0
Initial value
XXXXXXXXH
The USP is the user stack pointer.
This register is used as an R15 general-purpose register if the S flag of the condition code register (CCR) is “1”.
The USP can also be specified explicitly.
The initial value upon reset is undefined.
This register cannot be used by the RETI instruction.
• MDH/MDL (Multiply & Divide register)
MDH
Initial value
XXXXXXXXH
MDL
XXXXXXXXH
bit31
bit0
MDH and MDL are the multiply and divide registers. Each register is 32 bits long.
The initial value upon reset is undefined.
31
MB91305
■ MODE SETTINGS
For the FR family, set the operating mode using the mode pins (MD3, MD2, MD1 and MD0) and the mode
register (MODR) .
1. Mode pins
Use the four mode pins (MD3, MD2, MD1, and MD0) to specify mode vector fetch.
shows the specification related to the mode vector fetch.
Mode pin
MD3 MD2 MD1 MD0
Mode name
Reset vector access
area
Remarks
0
0
0
0
External ROM
mode vector
External
With USB.
Used at 48 MHz source oscillation.
0
0
1
0
External ROM
mode vector
External
Without USB.
Used at 16 MHz source oscillation.
Note : The setting other than that shown is prohibited. The single-chip mode is not supported.
2. Mode Register (MODR)
• Detailed explanation of the register
MODR
Address
07FDH
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
0
0
0
0
0
ROMA
WTH1
WTH0
Initial value
XXXXXXXXB
Operation mode setting bit
Mode data is data written to the mode register by a mode vector fetch.
After setting to the mode register (MODR) is completed, perform with the operation mode according to this
register.
The mode register is set by all reset sources. Accordingly, user program cannot write data to the mode register.
• Detailed explanation of the mode data.
• In the save way of the reset vector, set the mode vector in the vector area.
• Details of the mode data which sets to the mode vector is shown below.
Address
FFFF8H
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
0
0
0
0
0
ROMA
WTH1
WTH0
Operation mode setting bit
[bit31 to bit27] Reserved bits
Be sure to set “00000B” to these bits.
Operation when value other than “00000B” is set cannot guarantee.
[bit26] ROMA (Internal ROM enable bit)
This bit sets whether to enable internal ROM areas.
32
Initial value
XXXXXXXXB
MB91305
ROMA
0
1
Function
Remarks
External ROM mode * Internal F-bus region (40000H to 100000H) becomes an external region.
Internal F-bus region (40000H to 100000H) becomes access prohibited
(setting disabled) .
Internal ROM mode
* : MB91305 does not contain internal ROM. Use as external ROM mode (setting ROMA = 0) .
[bit25, bit24] WTH1, WTH0 (Bus width specification bit)
Set the bus width specification in external bus mode.
This value is set by DBW1 and DBW0 bits of ACR0 (CS0 area) in the external bus mode.
WTH1
WTH0
Function
Remarks
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
32-bit bus width
External bus mode (setting disabled)
1
1
Single-chip mode *
Single-chip mode (setting disabled)
* : not supported.
Note : Mode data set in mode vector must be allocated to “0x000FFFF8H” as a byte data. In the FR family, since
big endian is used as byte endian, the data must be allocated to the most significant byte in bit31 to bit24
as shown below.
bit31
Address
0x000FFFF8H
0x000FFFFCH
bit24 bit23
Mode Data
bit16 bit15
XXXXXXXX
bit8 bit7
XXXXXXXX
bit0
XXXXXXXX
Reset Vector
33
MB91305
■ MEMORY SPACE
1. Memory Space
The FR family has a logical address space of 4G bytes (232 addresses) , which the CPU accesses linearly.
• Direct addressing area
The areas in the address space listed below are used for input-output.
These areas are called the direct addressing area. The address of an operand can be directly specified in an
instruction.
The size of the direct addressing area varies according to the size of data to be accessed :
• Byte data access
: 000H to 0FFH
• Halfword data access : 000H to 1FFH
• Word data access
: 000H to 3FFH
2. Memory Map
External ROM External bus mode
0000 0000H
I/O
0000 0400H
I/O
0001 0000H
0003 0000H
Direct
addressing area
See "3. I/O MAP"
Access
disallowed
Built-in RAM
0004 0000H
0005 0000H
0006 0000H
0007 0000H
Access
disallowed
External
area
USB
function
Fixed in the CS2 area
External
area
FFFF FFFFH
Note : Internal RAM area of the MB91305 is “0003 0000H” to “0003 FFFFH”.
34
MB91305
■ I/O MAP
Shows the correspondence between the memory space area and the peripheral resource registers.
Reading the table
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
Port Data Register
Read/write attribute
Initial value of register after reset
Register name (column 1 of the register is at address 4n,
column 2 is at address 4n + 2...)
Leftmost register address (For word-length access,
column 1 of the register becomes the MSB of the data.)
Note : The initial value of bits in a register are indicated as follows :
“1” : Initial value “1”
“0” : Initial value “0”
“X” : Initial value “X”
“-” : A physical register does not exist at the location.
35
MB91305
Address
Register
+0
+1
+2
+3
000000H
to
00000FH
⎯
⎯
⎯
⎯
000010H
PDR0[R/W]
XXXXXXXX
PDR1[R/W]
XXXXXXXX
PDR2[R/W]
XXXXXXXX
PDR3[R/W]
XXXXXXXX
000014H
PDR4[R/W]
XXXXXXXX
PDR5[R/W]
XXXXXXXX
PDR6[R/W]
--XXXXXX
PDR7[R/W]
--XXXXXX
000018H
PDR8[R/W]
XXXXXXXX
PDR9[R/W]
XXXXXXXX
PDRA[R/W]
-----XXX
PDRB[R/W]
XXXXXXXX
00001CH
PDRC[R/W]
XXXXXXXX
PDRD[R/W]
--XXXXXX
PDRE[R/W]
-----XXX
PDRF[R/W]
XXXXXXXX
000020H
ADCTH[R/W]
XXXXXX00
ADCTL[R/W]
00000X00
Block
Reserved
R-bus
Port Data
Register
ADCH[R/W]
00000000 00000000
000024H
ADAT0[R]
XXXXXX00 00000000
ADAT1[R]
XXXXXX00 00000000
000028H
ADAT2[R]
XXXXXX00 00000000
ADAT3[R]
XXXXXX00 00000000
00002CH
ADAT4[R]
XXXXXX00 00000000
ADAT5[R]
XXXXXX00 00000000
000030H
ADAT6[R]
XXXXXX00 00000000
ADAT7[R]
XXXXXX00 00000000
000034H
ADAT8[R]
XXXXXX00 00000000
ADAT9[R]
XXXXXX00 00000000
10-bit A/D
converter
000038H
TEST [R/W]
00000000
⎯
⎯
⎯
00003CH
⎯
⎯
⎯
⎯
000040H
HEIRR0 [R/W]
00000000
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000
External interrupt
000044H
DICR [R/W]
-------0
HRCL [R/W]
0--11111
⎯
DLYI/I-unit
000048H
TMRLR0 [W]
XXXXXXXX XXXXXXXX
TMR0 [R]
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR0 [R/W]
----0000 00000000
000050H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
TMR1 [R]
XXXXXXXX XXXXXXXX
⎯
TMCSR1 [R/W]
----0000 00000000
000054H
Reserved
16-bit
Reload Timer 0
16-bit
Reload Timer 1
(Continued)
36
MB91305
Address
Register
+0
+1
+2
+3
000058H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
TMR2 [R]
XXXXXXXX XXXXXXXX
00005CH
⎯
TMCSR2 [R/W]
----0000 00000000
000060H
000064H
000068H
00006CH
000070H
000074H
000078H
00007CH
000080H
SIDR0 [R]/
SODR0 [W]
XXXXXXXX
SSR0 [R/W]
00001000
UTIM0 [R] (UTIMR0 [W])
00000000 00000000
SIDR1 [R]/
SODR1 [W]
XXXXXXXX
SSR1 [R/W]
00001000
UTIM1 [R] (UTIMR1 [W])
00000000 00000000
SIDR2 [R]/
SODR2 [W]
XXXXXXXX
SSR2 [R/W]
00001000
UTIM2 [R] (UTIMR2 [W])
00000000 00000000
SIDR3 [R]/
SODR3 [W]
XXXXXXXX
SSR3 [R/W]
00001000
UTIM3 [R] (UTIMR3 [W])
00000000 00000000
SIDR4 [R]/
SODR4 [W]
XXXXXXXX
SSR4 [R/W]
00001000
SMR0 [R/W]
00--0-0-
UART0
DRCL0 [W]
--------
UTIMC0 [R/W]
0--00001
U-TIMER 0
SCR1 [R/W]
00000100
SMR1 [R/W]
00--0-0-
UART1
DRCL1 [W]
--------
UTIMC1 [R/W]
0--00001
U-TIMER 1
SCR2 [R/W]
00000100
SMR2 [R/W]
00--0-0-
UART2
DRCL2 [W]
--------
UTIMC2 [R/W]
0--00001
U-TIMER 2
SCR3 [R/W]
00000100
SMR3 [R/W]
00--0-0-
UART3
DRCL3 [W]
--------
UTIMC3 [R/W]
0--00001
U-TIMER 3
SCR4 [R/W]
00000100
SMR4 [R/W]
00--0-0-
UART4
DRCL4 [W]
--------
UTIMC4 [R/W]
0--00001
U-TIMER 4
UTIM4 [R] (UTIMR4 [W])
00000000 00000000
000088H
⎯
⎯
00008CH
⎯
⎯
000094H
000098H
00009CH
PWCCL[R/W]
0000--00
PWCCH[R/W]
00-00000
PWCD[R]
XXXXXXXX XXXXXXXX
PWCC2[R/W]
000-----
Reserved
PWCUD[R]
XXXXXXXX XXXXXXXX
16-bit
Reload Timer 2
SCR0 [R/W]
00000100
000084H
000090H
Block
Reserved
⎯
⎯
PWC
⎯
⎯
(Continued)
37
MB91305
Address
Register
+0
+1
+2
+3
0000A0H
⎯
⎯
0000A4H
⎯
⎯
0000A8H
⎯
⎯
0000ACH
⎯
⎯
0000B0H
IFN0 [R]
00000000
IFRN0 [R/W]
00000000
0000B4H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
0000B8H
ITMK0 [R/W]
00111111 11111111
IFCR0 [R/W]
00-00000
Reserved
IFDR0 [R/W]
00000000
ITBA0 [R, R/W]
00000000 00000000
ISMK0 [R/W]
01111111
ISBA0 [R/W]
00000000
0000BCH
⎯
IDAR0 [R/W]
00000000
ICCR0 [R/W]
00011111
⎯
0000C0H
IFN1 [R]
00000000
IFRN1 [R/W]
00000000
IFCR1 [R/W]
00-00000
IFDR1 [R/W]
00000000
0000C4H
IBCR1 [R/W]
00000000
IBSR1 [R]
00000000
0000C8H
ITMK1 [R/W]
00111111 11111111
ITBA1 [R, R/W]
00000000 00000000
ISMK1 [R/W]
01111111
ISBA1 [R/W]
00000000
0000CCH
⎯
IDAR1 [R/W]
00000000
ICCR1 [R/W]
00011111
⎯
0000D0H
IFN2 [R]
00000000
IFRN2 [R/W]
00000000
IFCR2 [R/W]
00-00000
IFDR2 [R/W]
00000000
0000D4H
IBCR2 [R/W]
00000000
IBSR2 [R]
00000000
0000D8H
ITMK2 [R/W]
00111111 11111111
ITBA2 [R, R/W]
00000000 00000000
ISMK2 [R/W]
01111111
ISBA2 [R/W]
00000000
0000DCH
⎯
IDA2R [R/W]
00000000
ICCR2 [R/W]
00011111
⎯
0000E0H
IFN3 [R]
00000000
IFRN3 [R/W]
00000000
IFCR3 [R/W]
00-00000
IFDR3 [R/W]
00000000
0000E4H
IBCR3 [R/W]
00000000
IBSR3 [R]
00000000
0000E8H
ITMK3 [R/W]
00111111 11111111
Block
ITBA3 [R, R/W]
00000000 00000000
ISMK3 [R/W]
01111111
ISBA3 [R/W]
00000000
I2C interface ch.0
I2C interface ch.1
I2C interface ch.2
I2C interface ch.3
0000ECH
⎯
IDAR3 [R/W]
00000000
ICCR3 [R/W]
00011111
⎯
0000F0H
⎯
⎯
⎯
⎯
Reserved
⎯
TCCS [R/W]
00000000
16-bit free-run
timer
0000F4H
TCDT [R/W]
00000000 00000000
(Continued)
38
MB91305
Address
Register
+0
+1
+2
+3
0000F8H
IPCP1 [R]
XXXXXXXX XXXXXXXX
IPCP0 [R]
XXXXXXXX XXXXXXXX
0000FCH
IPCP3 [R]
XXXXXXXX XXXXXXXX
IPCP2 [R]
XXXXXXXX XXXXXXXX
000100H
⎯
ICS23 [R/W]
00000000
⎯
ICS01 [R/W]
00000000
000104H
⎯
⎯
⎯
⎯
000108H
⎯
⎯
⎯
⎯
00010CH
⎯
⎯
⎯
⎯
000110H
EIRR1 [R/W]
00000000
ENIR1 [R/W]
00000000
Block
16-bit input
capture
Reserved
ELVR1 [R/W]
00000000 00000000
External interrupt
Reserved
000114H
to
00011FH
⎯
⎯
000120H
PTMR0 [R]
11111111 11111111
PCSR0 [W]
XXXXXXXX XXXXXXXX
000124H
PDUT0 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR1 [R]
11111111 11111111
00012CH
PDUT1 [W]
XXXXXXXX XXXXXXXX
000130H
PTMR2 [R]
11111111 11111111
00134H
PDUT2 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR3 [R]
11111111 11111111
00013CH
PDUT3 [W]
XXXXXXXX XXXXXXXX
PCNH0 [R/W]
00000000
PCNL0 [R/W]
00000000
PCSR1 [W]
XXXXXXXX XXXXXXXX
PCNH1 [R/W]
00000000
PCNL1 [R/W]
00000000
PCSR2 [W]
XXXXXXXX XXXXXXXX
PCNH2 [R/W]
00000000
PCNL2 [R/W]
00000000
PCSR3[W]
XXXXXXXX XXXXXXXX
PCNH3 [R/W]
00000000
PCNL3 [R/W]
00000000
000140H
to
0001FCH
⎯
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 00000000 00000000
PPG0
PPG1
PPG2
PPG3
Reserved
DMAC
(Continued)
39
MB91305
Address
Register
+0
+1
+2
+3
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 00000000 00000000
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 00000000 00000000
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 00000000 00000000
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000228H
⎯
00022CH
to
00023CH
⎯
000240H
DMACR [R/W]
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
000244H
to
0002FCH
⎯
Block
DMAC
Reserved
000304H
⎯
⎯
⎯
ISIZE[R/W]
------10
I-Cache
000308H
to
0003E0H
⎯
⎯
⎯
⎯
Reserved
0003E4H
⎯
⎯
⎯
ICHCR[R/W]
0-000000
I-Cache
0003E8H
to
0003ECH
⎯
⎯
⎯
⎯
Reserved
(Continued)
40
MB91305
Address
Register
+0
+1
+2
+3
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
⎯
⎯
DDR2 [R/W]
00000000
DDR3 [R/W]
----0000
000404H
DDR4 [R/W]
00000000
DDR5 [R/W]
00000000
DDR6 [R/W]
--000000
DDR7 [R/W]
--000000
000408H
DDR8 [R/W]
---00000
DDR9 [R/W]
00000000
DDRA [R/W]
00000000
DDRB [R/W]
00000000
00040CH
DDRC [R/W]
00000000
DDRD [R/W]
--000000
DDRE [R/W]
------00
DDRF [R/W]
00000000
PFR0 [R/W]
0--00000
PFR1 [R/W]
00000000
PFR2 [R/W]
000---00
PFR3 [R/W]
----0000
000414H
PFR4 [R/W]
-----000
PFR5 [R/W]
11111111
PFR6 [R/W]
00000000
PFR7 [R/W]
-----000
000418H
⎯
PFR9 [R/W]
11111111
⎯
PFRB [R/W]
00011-0-
00041CH
PFRC [R/W]
1111--11
PFRD [R/W]
---101--
PCRA [R/W]
00000000
PCRB [R/W]
00000000
000410H
000420H
to
00043CH
⎯
Block
Bit Search
Module
R-bus
Port Direction
Register
R-bus
Port Function
Register
Reserved
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02[R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
Interrupt
Controller
(Continued)
41
MB91305
Address
Register
+0
+1
+2
+3
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
to
00047CH
⎯
RSRR [R/W]
10000000 *2
STCR [R/W]
00110011 *2
TBCR [R/W]
00XXXX00 *1
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
00000000 *1
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011 *1
DIVR1[R/W]
00000000 *1
000488H
⎯
⎯
⎯
⎯
00048CH
⎯
⎯
⎯
⎯
000490H
⎯
⎯
⎯
⎯
⎯
000600H
to
00063FH
⎯
Interrupt
Controller
Reserved
000480H
000494H
to
0005FCH
Block
Clock Control
Reserved
000640H
ASR0 [R/W]
00000000 00000000 *1
ACR0 [R/W]
1111XX00 00000000 *1
000644H
ASR1 [R/W]
XXXXXXXX XXXXXXXX *1
ACR1 [R/W]
XXXXXXXX XXXXXXXX *1
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX *1
ACR2 [R/W]
XXXXXXXX XXXXXXXX *1
00064CH
ASR3 [R/W]
XXXXXXXX XXXXXXXX *1
ACR3 [R/W]
XXXXXXXX XXXXXXXX *1
000650H
ASR4 [R/W]
XXXXXXXX XXXXXXXX *1
ACR4 [R/W]
XXXXXXXX XXXXXXXX *1
000654H
ASR5 [R/W]
XXXXXXXX XXXXXXXX *1
ACR5 [R/W]
XXXXXXXX XXXXXXXX *1
000658H
ASR6 [R/W]
XXXXXXXX XXXXXXXX *1
ACR6 [R/W]
XXXXXXXX XXXXXXXX *1
T-unit
(Continued)
42
MB91305
Address
Register
+0
+1
+2
+3
00065CH
ASR7 [R/W]
XXXXXXXX XXXXXXXX *1
ACR7 [R/W]
XXXXXXXX XXXXXXXX *1
000660H
AWR0 [R/W]
01111111 11111111 *1
AWR1 [R/W]
XXXXXXXX XXXXXXXX *1
000664H
AWR2 [R/W]
XXXXXXXX XXXXXXXX *1
AWR3 [R/W]
XXXXXXXX XXXXXXXX *1
000668H
AWR4 [R/W]
XXXXXXXX XXXXXXXX *1
AWR5 [R/W]
XXXXXXXX XXXXXXXX *1
00066CH
AWR6 [R/W]
XXXXXXXX XXXXXXXX *1
AWR7 [R/W]
XXXXXXXX XXXXXXXX *1
000670H
MCRA [R/W]
XXXXXXXX
000684H
IOWR0 [R/W]
XXXXXXXX
IOWR1 [R/W]
XXXXXXXX
⎯
IOWR2 [R/W]
XXXXXXXX
⎯
⎯
TCR [R/W]
00000000
⎯
⎯
⎯
CSER [R/W]
00000001
CHER [R/W]
11111111
RCR [R/W]
00XXXXXX XXXX0XXX
000688H
to
0007F8H
0007FCH
⎯
⎯
00067CH
000680H
T-unit
MCRB [R/W]
XXXXXXXX
000674H
000678H
Block
⎯
⎯
MODR [W]
XXXXXXXX
000800H
to
000AFCH
Reserved
⎯
⎯
⎯
⎯
Reserved
000B00H
ESTS0 [R/W]
X0000000
ESTS1 [R/W]
XXXXXXXX
ESTS2 [R]
1XXXXXXX
⎯
000B04H
ECTL0 [R/W]
0X000000
ECTL1 [R/W]
00000000
ECTL2 [W]
000X0000
ECTL3 [R/W]
00X00X11
000B08H
ECNT0 [W]
XXXXXXXX
ECNT1 [W]
XXXXXXXX
EUSA [W]
XXX00000
EDTC [W]
0000XXXX
000B0CH
EWP1 [R]
00000000 00000000
⎯
000B10H
EDTR0 [W]
XXXXXXXX XXXXXXXX
EDTR1 [W]
XXXXXXXX XXXXXXXX
DSU
(Continued)
43
MB91305
Address
Register
+0
+1
+2
000B14H
to
000B1CH
⎯
000B20H
EIA0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B24H
EIA1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B28H
EIA2 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B2CH
EIA3 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B30H
EIA4 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B34H
EIA5 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B38H
EIA6 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B3CH
EIA7 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B40H
EDTA [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B44H
EDTM [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B48H
EOA0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B4CH
EOA1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B50H
EPCR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B54H
EPSR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B58H
EIAM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B5CH
EIAM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B60H
EOAM0/EODM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B64H
EOAM1/EODM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
DSU
(Continued)
44
MB91305
(Continued)
Address
Register
+0
+1
+2
000B68H
EOD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B6CH
EOD1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B70H
to
000FFCH
⎯
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
007104H
⎯
+3
Block
DSU
Reserved
DMAC
Reserved
*1 : Register whose initial value depends on the reset level. The registers at the INIT level are indicated.
*2 : Register whose initial value depends on the reset level. The registers at the INIT level due to the INIT pin are
indicated.
45
MB91305
Address
Register
+0
+1
+2
+3
00060000H
FIFO0o [R]
XXXXXXXX XXXXXXXX
FIFO0i [W]
XXXXXXXX XXXXXXXX
00060004H
FIFO1 [R]
XXXXXXXX XXXXXXXX
FIFO2 [W]
XXXXXXXX XXXXXXXX
00060008H
FIFO3 [R]
XXXXXXXX XXXXXXXX
-⎯
0006000CH
to
0006001FH
⎯
00060020H
⎯
CONT1 [R/W]
000XX0XX XXX00000
00060024H
CONT2 [R/W]
XXXXXXXX XXX00000
CONT3 [R/W]
XXXXXXXX XXX00000
00060028H
CONT4 [R/W]
XXXXXXXX XXX00000
CONT5 [R/W]
XXXXXXXX XXXX00XX
0006002CH
CONT6 [R/W]
XXXXXXXX XXXX00XX
CONT7 [R/W]
XXXXXXXX XXX00000
00060030H
CONT8 [R/W]
XXXXXXXX XXX00000
CONT9 [R/W]
0XX0XXXX 0XXX0000
00060034H
CONT10 [R/W]
00000000 X00000XX
TTSIZE [R/W]
00010001 00010001
00060038H
TRSIZE [R/W]
00010001 00010001
⎯
USB Function
⎯
0006003CH
00060040H
RSIZE0 [R]
XXXXXXXX XXXX0000
⎯
00060044H
RSIZE1 [R]
XXXXXXXX X0000000
⎯
00060048H
to
0006005FH
00060060H
Block
⎯
ST1 [R/W]
XXXXXX00 00000000
⎯
⎯
00060064H
00060068H
ST2 [R]
XXXXXXXX XXX00000
ST3 [R/W]
XXXXXXXX XXX00000
0006006CH
ST4 [R/W]
XXXXX000 00000000
ST5 [R/W]
XXXX0XXX XX000000
(Continued)
46
MB91305
(Continued)
Address
Register
+0
+1
+2
+3
Block
00060070H
to
0006007FH
⎯
USB Function
00060080H
to
0006FFFBH
⎯
Reserved
0006FFFCH
⎯
⎯
USBRST
-0------
⎯
USB reset
47
MB91305
■ INTERRUPT SOURCE TABLE
Interrupt number
Interrupt source
Interrupt
level
Offset
Address of
TBR default
Resource
number
Decimal
Hexadecimal
Reset
0
00
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
3F8H
000FFFF8H
⎯
Reserved for system
2
02
⎯
3F4H
000FFFF4H
⎯
Reserved for system
3
03
⎯
3F0H
000FFFF0H
⎯
Reserved for system
4
04
⎯
3ECH
000FFFECH
⎯
Reserved for system
5
05
⎯
3E8H
000FFFE8H
⎯
Reserved for system
6
06
⎯
3E4H
000FFFE4H
⎯
No-coprocessor trap
7
07
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
3D8H
000FFFD8H
⎯
Instruction break exception
10
0A
⎯
3D4H
000FFFD4H
⎯
Operand break trap
11
0B
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
15 (FH)
fixed
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
⎯
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
⎯
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
⎯
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
⎯
External interrupt 4 (USB-function)
20
14
ICR04
3ACH
000FFFACH
⎯
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
⎯
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
⎯
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
⎯
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1
25
19
ICR09
398H
000FFF98H
9
Reload timer 2
26
1A
ICR10
394H
000FFF94H
10
UART0 (Reception completed)
27
1B
ICR11
390H
000FFF90H
0
UART1 (Reception completed)
28
1C
ICR12
38CH
000FFF8CH
1
UART2 (Reception completed)
29
1D
ICR13
388H
000FFF88H
2
UART0 (Transmission completed)
30
1E
ICR14
384H
000FFF84H
3
UART1 (Transmission completed)
31
1F
ICR15
380H
000FFF80H
4
(Continued)
48
MB91305
Interrupt number
Interrupt source
Interrupt
level
Offset
Address of
TBR default
Resource
number
Decimal
Hexadecimal
UART2 (Transmission completed)
32
20
ICR16
37CH
000FFF7CH
5
DMAC0 (end or error)
33
21
ICR17
378H
000FFF78H
⎯
DMAC1 (end or error)
34
22
ICR18
374H
000FFF74H
⎯
DMAC2 (end or error)
35
23
ICR19
370H
000FFF70H
⎯
DMAC3 (end or error)
36
24
ICR20
36CH
000FFF6CH
⎯
DMAC4 (end or error)
37
25
ICR21
368H
000FFF68H
⎯
A/D
38
26
ICR22
364H
000FFF64H
⎯
PPG0
39
27
ICR23
360H
000FFF60H
⎯
PPG1
40
28
ICR24
35CH
000FFF5CH
⎯
PPG2
41
29
ICR25
358H
000FFF58H
⎯
PPG3
42
2A
ICR26
354H
000FFF54H
⎯
PWC
43
2B
ICR27
350H
000FFF50H
⎯
External interrupt 8/U-TIMER0
44
2C
ICR28
34CH
000FFF4CH
⎯
External interrupt 9/U-TIMER1
45
2D
ICR29
348H
000FFF48H
⎯
External interrupt 10/U-TIMER2
46
2E
ICR30
344H
000FFF44H
⎯
Timebase timer overflow /
U-TIMER3
47
2F
ICR31
340H
000FFF40H
⎯
External interrupt 11/U-TIMER4
48
30
ICR32
33CH
000FFF3CH
⎯
16-bit free-run timer
49
31
ICR33
338H
000FFF38H
⎯
I2C ch.0
50
32
ICR34
334H
000FFF34H
⎯
2
51
33
ICR35
330H
000FFF30H
⎯
2
I C ch.2
52
34
ICR36
32CH
000FFF2CH
⎯
I2C ch.3
53
35
ICR37
328H
000FFF28H
⎯
UART3 (Reception completed)
54
36
ICR38
324H
000FFF24H
⎯
UART4 (Reception completed)
55
37
ICR39
320H
000FFF20H
⎯
UART3 (Transmission completed)
56
38
ICR40
31CH
000FFF1CH
⎯
UART4 (Transmission completed)
57
39
ICR41
318H
000FFF18H
⎯
External interrupt 12/Input capture 0
58
3A
ICR42
314H
000FFF14H
⎯
External interrupt 13/Input capture 1
59
3B
ICR43
310H
000FFF10H
⎯
External interrupt 14/Input capture 2
60
3C
ICR44
30CH
000FFF0CH
⎯
External interrupt 15/Input capture 3
61
3D
ICR45
308H
000FFF08H
⎯
Reserved for system
62
3E
ICR46
304H
000FFF04H
⎯
Delayed interrupt source bit
63
3F
ICR47
300H
000FFF00H
⎯
I C ch.1
(Continued)
49
MB91305
(Continued)
Interrupt number
Interrupt source
50
Interrupt
level
Offset
Address of
TBR default
Resource
number
Decimal
Hexadecimal
Reserved for system
(used by REALOS)
64
40
⎯
2FCH
000FFEFCH
⎯
Reserved for system
(used by REALOS)
65
41
⎯
2F8H
000FFEF8H
⎯
Reserved for system
66
42
⎯
2F4H
000FFEF4H
⎯
Reserved for system
67
43
⎯
2F0H
000FFEF0H
⎯
Reserved for system
68
44
-
2ECH
000FFEECH
⎯
Reserved for system
69
45
⎯
2E8H
000FFEE8H
⎯
Reserved for system
70
46
⎯
2E4H
000FFEE4H
⎯
Reserved for system
71
47
⎯
2E0H
000FFEE0H
⎯
Reserved for system
72
48
⎯
2DCH
000FFEDCH
⎯
Reserved for system
73
49
⎯
2D8H
000FFED8H
⎯
Reserved for system
74
4A
⎯
2D4H
000FFED4H
⎯
Reserved for system
75
4B
⎯
2D0H
000FFED0H
⎯
Reserved for system
76
4C
⎯
2CCH
000FFECCH
⎯
Reserved for system
77
4D
⎯
2C8H
000FFEC8H
⎯
Reserved for system
78
4E
⎯
2C4H
000FFEC4H
⎯
Reserved for system
79
4F
⎯
2C0H
000FFEC0H
⎯
Used in INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
⎯
MB91305
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VDDE
VSS − 0.5
VSS + 4.0
V
*2
VDDI
VSS − 0.5
VSS + 2.2
V
*2
AVCC
VSS − 0.5
VSS + 4.0
V
*3
AVRH
VSS − 0.5
VSS + 4.0
V
*3
VI
VSS − 0.3
VDDE + 0.3
V
VIA
VSS − 0.3
AVCC + 0.3
V
VO
VSS − 0.3
AVCC + 0.3
V
IOL
⎯
10
mA
*4
“L” level average output current
IOLAV
⎯
4
mA
*5
“L” level total maximum output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*6
IOH
⎯
−10
mA
*4
“H” level average output current
IOHAV
⎯
−4
mA
*5
“H” level total maximum output current
ΣIOH
⎯
−50
mA
ΣIOHAV
⎯
−20
mA
Power consumption
PD
⎯
750
mW
Operating temperature
Ta
−10
+70
°C
TSTG
⎯
+150
°C
Power supply voltage*1
Power supply voltage (Internal) *1
Analog power supply voltage*
Analog reference voltage*
1
1
Input voltage*1
Analog pin input voltage*1
Output voltage*
1
“L” level maximum output current
“L” level total average output current
“H” level maximum output current
“H” level total average output current
Storage temperature
*6
*1 : This parameter is based on AVSS = VSS = 0.0 V.
*2 : VDDE must not be lower than VSS − 0.3 V.
*3 : Be careful not to exceed VDDE + 0.3 V, for example, when power is turned on.
*4 : Maximum output current determines the peak value of any one of corresponding pins.
*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the
corresponding pins.
*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the
corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
51
MB91305
2. Recommended Operating Conditions
(VSS = AVSS = 0 V)
Parameter
Symbol
Value
Unit
Min
Max
VDDE
3.0
3.6
V
VDDI
1.65
1.95
V
Analog power supply voltage
AVCC
VSS − 0.3
VSS + 3.6
V
Analog reference voltage
AVRH
AVSS
AVCC
V
Ta
− 10
+70
°C
Power supply voltage
Operating temperature
Remarks
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
52
MB91305
3. DC Characteristics
(1) CPU
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
Conditions
Value
Min
Typ
Max
Unit
VIH
D31 to D16
⎯
0.7 × VDDE
⎯
VDDE + 0.3
V
VHIS
Input ports
except for
D31 to D16
⎯
0.8 × VDDE
⎯
VDDE + 0.3
V
VIL
D31 to D16
⎯
VSS
0.25 × VDDE
V
VILS
Input ports
except for
D31 to D16
⎯
VSS
⎯
0.2 × VDDE
V
“H” level
output voltage
VOH
All output pins
VDDE = 3.0 V
IOH = −4.0 mA
VDDE − 0.5
⎯
VDDE
V
“L” level
output voltage
VOL
All output pins
VDDE = 3.0 V
IOL = 4.0 mA
VSS
⎯
0.4
V
Input leak
current
(High-Z
output Leakage
current)
ILI
All input pins
VDDE = 3.6 V
0.45 V < VI <
VDDE
−5
⎯
+5
µA
Pull-up
resistance
RUP
*1
VDDE = 3.6 V
VI = 0.45 V
12
25
100
kΩ
Pull-down
resistance
RDOWN
*2
VDDE = 3.6 V
VI = 3.3 V
12
25
100
kΩ
“H” level
input voltage
“L” level
input voltage
ICC
Power supply
current
ICCS
VDDE, VDDI
ICCH
Input
capacitance
CIH
Remarks
Hysteresis
input
Hysteresis
input
fC = 16.5 MHz
VDDE = 3.3 V
VDDI = 1.8 V
⎯
120
180
(Multiply by 4)
When
mA
operating at
66 MHz
fC = 16.5 MHz
VDDE = 3.3 V
VDDI = 1.8 V
⎯
60
90
mA at sleep
Ta = +25 °C
VDDE = 3.3 V
VDDI = 1.8 V
⎯
200
1000
µA
⎯
10
⎯
pF
Other than
VDDE, VSS
AVCC and
AVSS
⎯
at stop
*1 : Pins that the I/O circuit type is B and G
*2 : Pins that the I/O circuit type is J
53
MB91305
(2) USB
[1] DC characteristics
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Symbol
Pin
“H” level
output voltage
VOH
⎯
“L” level
output voltage
VOL
Parameter
“H” level
output voltage
Conditions
Value
Unit
Min
Typ
Max
IOH = −100 µA
VDDE − 0.2
⎯
VDDE
V
⎯
IOL = 100 µA
0
⎯
0.2
V
⎯
Full Speed
VOH = VDDE − 0.4 V
−20
⎯
⎯
⎯
Low Speed
VOH = VDDE − 0.4 V
−6
⎯
⎯
⎯
Full Speed
VOL = 0.4 V
20
⎯
⎯
⎯
Low Speed
VOL = 0.4 V
6
⎯
⎯
IOH
Remarks
mA
“L” level
output voltage
IOL
Output ShortCircuit Current
IOS
⎯
⎯
⎯
⎯
300
mA
*1
Input leak
current
ILZ
⎯
⎯
⎯
⎯
±5
µA
*2
mA
*1 : < Output Short Circuit Current IOS >
The output short circuit current IOS is the maximum current that flows when the output pin is connected to VDDE
or VSS pin (within the maximum rating) .
Output Short Circuit Current : The output short circuit current’s value is the short-circuit current value of one
terminal in one side of the differential output terminal. As this USB I/O buffer is
a differential output, consider both of the pins.
“H” level
“H” output
Monitor short circuit current
Short-circuit to GND level
3-State Enable "L"
Short-circuit to VDDE level
“L” level
“L” output
Monitor short circuit current
3-State Enable "L"
54
MB91305
*2 : < Z leak current ILZ measurement >
The leak current when VDDE or VSS potential is impressed to bi-directional pin at high-impedance state of USB
I/O buffer is the input leak current ILZ.
Monitor leak current
Z output
Impressed 0 V, VDDE level to
output pin
3-State Enable "H"
55
MB91305
[2] DC Characteristics
Conform to USB Specification Revision 1.1
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Value
Parameter
Symbol
Unit Remarks
Min
Max
Input Levels
High (driven)
VIH
2.0
⎯
V
*1
Low
VIL
⎯
0.8
V
*1
Differential Input Sensitivity
VDI
0.2
⎯
V
*2
Common Mode Range
VCM
0.8
2.5
V
*2
Low
VOL
0.0
0.3
V
*3
VOH
2.8
3.6
V
*3
Differential Output Signal Voltage
VCRS
1.3
2.0
V
*4
Bus Pull-Up Resistor on Upstream Port
RPU
1.425
1.575
kΩ
1.5 kΩ ± 5%
RPD
1.425
1.575
kΩ
1.5 kΩ ± 5%
VTERM
3.0
3.6
V
Output Levels High (driven)
Terminations Bus Pull-Down Resistor on Downstream Port
Termination Voltage for Upstream Port Pull-Up
*5
*1 : < Input Levels VIH and VIL >
The switching-threshold voltage of the single-end-receiver in USB I/O buffer is set within the following range; VIL
(Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard).
And, to fall the noise sensitivity, a little hysteresis is set.
56
MB91305
*2 : < Input Levels VDI and VCM >
Reception of the USB differential data signal uses the differential-receiver.
The differential input sensitivity of the differential-receiver is 200 mV, when the difference voltage between the
differrential data input and local ground reference level is the following ranges; 0.8 V to 2.5 V.
Minimum differential input sensitivity (V)
The voltage range above is called the common2 mode input voltage range.
1.0
0.2
0.8
2.5
Common mode input voltage (V)
*3 : < Output Levels VOL and VOH >
The driver’s output driving ability is set to following;
- at low state (VOL) : less than 0.3 V (vs. 3.6 V, 1.5 kΩ load)
- at high state (VOH) : more than 2.8 V (vs. ground, 1.5 kΩ load)
*4 : < Output Levels VCRS >
The cross voltage of the external differrencial output signal (D+/D−) in USB buffer is from 1.3 V to 2.0 V.
D+
Max 2.0 V
VCRS standard range
Min 1.3 V
D−
*5 : < Terminations VTERM >
Pull-up voltage for the upstream port is shown.
57
MB91305
4. AC Characteristics
(1) Clock timing ratings
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Clock frequency (1)
Symbol
Pin
fC
X0
X1
Conditions
⎯
Value
Unit
Min
Max
37.5
48
MHz
12.5
16
MHz
⎯
20.8
ns
⎯
62.5
ns
Remarks
Using PLL*1
Clock cycle time
tC
X0
X1
Clock frequency (2)
fC
X0
X1
10
50
MHz
Clock frequency (3)
fC
X0
X1
10
50
MHz
Clock cycle time
tC
X0
X1
40
100
ns
Input clock pulse width
PWH
PWL
X0
X1
16
⎯
ns
Input clock rise time
and fall time
tCR
tCF
X0
X1
⎯
8
ns
3.125*2
64
MHz
CPU
3.125*2
32
MHz
Peripheral
2
32
MHz
External bus
⎯
fCP
Internal operating clock
frequency
fCPP
⎯
⎯
fCPT
3.125*
tCP
Internal operating clock
cycle time
tCPP
⎯
tCPT
⎯
Self-oscillation
(1/2 division input)
At external clock
tCR + tCF
15.6
2
1280*
ns
CPU
31.2
1280*2
ns
Peripheral
31.2
1280*2
ns
External bus
*1 : This value is as follows;
- With USB function (MD pin = 0000B)
: 37.5 MHz to 48 MHz And using USB: fixed to 48 MHz
(operation at a maximum internal speed of 64 MHz by
quadrupling a self-oscillation frequency of 48 MHz via PLL of
divided by 3.)
- Without USB function (MD pin = 0010B) : 12.5 MHz to 16 MHz
(operation at a maximum internal speed of 64 MHz by
quadrupling a self-oscillation frequency of 16 MHz via PLL.)
*2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillation
circuit PLL and a gear ratio of 1/16.
12.5 [MHz] × 4 (multiply) × 1/16 (gear 1/16) = 3.125 [MHz]
58
MB91305
• Conditions for measuring the clock timing ratings
tC
Output pin
0.8 VDDE
C = 30 pF
0.2 VDDE
PWH
PWL
tCF
tCR
• Operation Assurance Range
Power supply
VDDI [V]
Operation Assurance Range (Ta = − 10 °C to + 70 °C)
VDDE = 3.0 V to 3.6 V
fCPP is represented by the shaded area.
1.95
1.65
0 0.3125
33
66
fCP/fCPP
[MHz]
Internal clock
59
MB91305
• External/internal clock setting range
Oscillation input clock
Without USB fc = 16 MHz
WIth USB fc = 48 MHz
[MHz]
fCP ,
fCPT
64
Internal clock
CPU :
Peripheral, External bus :
fCPP
32
16.5
4:4
2:2
1:2
CPU : Division ration
for peripheral
Notes : • When the PLL is used, the external clock input must fall between 12.5 MHz and 16.5 MHz.
• Set the PLL oscillation stabilization wait time longer than 500 µs.
• The internal clock gear setting should not exceed the relevant value in the table in (1) "Clock timing ratings”.
60
MB91305
(2) Clock output timing
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Conditions
Symbol
Pin
Cycle time
tCYC
MCLK
SYSCLK
MCLK (SYSCLK) ↑
→
MCLK (SYSCLK) ↓
tCHCL
MCLK
SYSCLK
MCLK (SYSCLK) ↓
→
MCLK (SYSCLK) ↑
tCLCL
MCLK
SYSCLK
⎯
Value
Unit
Remarks
Min
Max
tCPT
⎯
ns
*1
1/2 × tCYC − 3
1/2 × tCYC + 3
ns
*2
1/2 × tCYC − 3
1/2 × tCYC + 3
ns
*3
tCYC
tCHCL
MCLK
tCLCH
VOH
VOH
SYSCLK
VOL
*1 : tCYC is the frequency of one clock cycle after gearing.
*2 : The following ratings are for the gear ratio set to 1.
For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the
following equation.
tCHCL = (1 / 2 × 1 / n) × tCYC − 10
*3 : The following rating are for the gear ratio set to 1.
61
MB91305
(3) Reset and hardware standby input ratings
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
Conditions
INIT input time
(at power-on)
tINTL
INIT input time
(other than at power-on)
INIT
Value
Max
*
⎯
ns
tCP × 5
⎯
ns
⎯
* : INIT input time (at power-on)
FAR resonator, ceramic oscillator : φ × 215 or greater recommended
Crystal : φ × 221 or greater recommended
φ : Power on → X0/X1 period × 2
tINTL
INIT
0.2 Vcc
62
Unit
Min
Remarks
MB91305
(4-1) Normal bus access read/write operation
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
Conditions
Value
Unit
Min
Max
3
⎯
ns
3
tCYC / 2 + 6
ns
MCLK/SYSCLK
A23 to A0
3
⎯
ns
3
tCYC / 2 + 6
ns
A23 to A0
D31 to D16
⎯
3/2 × tCYC − 15
ns
⎯
6
ns
⎯
6
ns
tCYC − 3
⎯
ns
tCYC
⎯
ns
5
⎯
ns
⎯
6
ns
⎯
6
ns
⎯
tCYC − 15
ns
15
⎯
ns
0
⎯
ns
CS0/CS1/CS4/CS5/
CS6/CS7 setup
tCSLCH
CS0/CS1/CS4/CS5/
CS6/CS7 hold
tCSHCH
Address setup
tASCH
Address hold
tCHAX
Valid address →
Valid data input time
tAVDV
WR0 , WR1 delay time
tCHWL
WR0 , WR1 delay time
tCHWH
MCLK/SYSCLK
WR0, WR1
WR0 , WR1 minimum
pulse width
tWLWH
WR0, WR1
Data setup → WRx ↑
tDSWH
WRx ↑ → Data hold
time
tWHDX
RD delay time
tCHRL
RD delay time
tCHRH
RD ↓ →
Valid data input time
tRLDV
Data setup
→ RD ↑ Time
tDSRH
RD ↑ → Data hold time
tRHDX
RD minimum pulse
width
tRLRH
RD
tCYC − 3
⎯
ns
AS setup
tASLCH
3
⎯
ns
AS hold
tASHCH
MCLK/SYSCLK
AS
3
⎯
ns
MCLK/SYSCLK
CS0 to CS7
WR0, WR1
D31 to D16
MCLK/SYSCLK
RD
RD
D31 to D16
⎯
Remarks
*1
*2
*1
*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of
cycles added for the delay) to this rating.
*2 : The following ratings are for the gear ratio set to 1.
For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 and 1/8 for n in the
following equation.
tAVDV : 3 / (2n) × tCYC − 15
63
MB91305
tCYC
BA1
MCLK
VOH
VOH
VOH
tASLCH
tASHCH
VOH
SYSCLK
VOH
AS
VOL
LBA
tCSLCH
CS0 to CS7
tCSHCH
VOH
VOL
tASCH
A23 to A00
tCHAX
VOH
VOL
VOH
VOL
tCHRH
tCHRL
tRLRH
VOL
RD
VOH
tRHDX
tRLDV
tDSRH
tAVDV
D31 to D16
VOH
VOH
VOL
VOL
tCHWL
tCHWH
tWLWH
VOL
WR0, WR1
VOH
tWHDX
tDSWH
D31 to D16
64
VOH
VOL
VOH
write
VOL
MB91305
(4-2) Multiplex bus access read/write operation
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Value
CondiParameter
Symbol
Pin
Unit Remarks
tions
Min
Max
D31 to D16 address
setup time
→ MCLK (SYSCLK) ↑
tASCH
MCLK (SYSCLK) ↑ →
D31 to D16 address
hold time
tCHAX
D31 to D16 address
setup time → AS ↑
tASASH
AS ↑ →
D31 to D16 address
hold time
tASHAX
MCLK/SYSCLK
D31 to D16
(address)
3
⎯
ns
3
tCYC / 2 + 6
ns
12
⎯
ns
*
tCYC − 3
tCYC + 3
ns
*
⎯
AS
D31 to D16
(address)
* : At CS → RD/WR setup extension = 1
Note : Use the same rating as normal bus interface except for this rating.
65
MB91305
• At CS → RD/WR setup extension = 1
tCYC
BA1
MCLK
VOH
BA2
BA1W
VOH
VOH
tASLCH
tASHCH
BA3
VOH
VOH
VOH
SYSCLK
AS
VOH
VOL
tASASH
tASHAX
tCSLCH
CS0 to CS7
VOL
tASCH
D31 to D16
VOH
VOL
tCHAX
Address
VOH
VOL
VIH
VIL
VIH
Read data VIL
tDSRH
tRHDX
tRLDV
VOH
VOL
RD
tRLRH
tCHRH
tCHRL
D31 to D16
VOH
VOL
Address
VOH
VOL
VOH
VOL
tDSWH
tWHDX
VOH
VOL
WR0, WR1
VOH
VOL
Write data
tWLWH
tCHWL
VOH
A23 to A00
66
VOL
Address
tCHWH
MB91305
• At CS → RD/WR setup extension = 0
tCYC
BA1
MCLK
VOH
BA2
BA3
VOH
VOH
VOH
VOH
SYSCLK
VOH
VOL
AS
tASLCH
tASHCH
tCSLCH
CS0 to CS7
D31 to D16
VOL
tASCH
tCHAX
VOH
VOL
Address VOL
VOH
VIH
VIL
VIH
VIL
Read data
tDSRH
tRHDX
tRLDV
VOH
VOL
RD
tRLRH
tCHRH
tCHRL
D31 to D16
VOH
VOL
Address
VOH
VOL
VOH
VOL
Write data
tDSWH
tWHDX
VOH
VOL
WR0, WR1
tWLWH
tCHWL
A23 to A00
VOH
VOL
tCHWH
Address
67
MB91305
(5) Ready input timings
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Value
Symbol
Pin
Conditions
Min
Max
RDY setup time →
MCLK (SYSCLK) ↓
tRDYS
MCLK
SYSCLK
RDY
⎯
10
⎯
ns
MCLK (SYSCLK) ↓ →
RDY hold time
tRDYH
MCLK
SYSCLK
RDY
⎯
0
⎯
ns
Parameter
tCYC
MCLK
VOH
VOH
SYSCLK
VOL
VOL
tRDYS
RDY
with wait
tRDYH
tRDYS
VOH
VOH
VOL
VOL
RDY
without wait
VOH
VOH
VOL
68
tRDYH
VOL
Unit
Remarks
MB91305
(6) Hold timing
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
BGRNT delay time
tCHBGL
BGRNT delay time
tCHBGH
MCLK
SYSCLK
BGRNT
Pin floating
→ BGRNT ↓ time
tXHAL
BGRNT ↑ →
Pin valid time
tHAHV
Conditions
⎯
Value
Unit
Min
Max
tCYC / 2 − 6
tCYC / 2 + 6
ns
tCYC / 2 − 6
tCYC / 2 + 6
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
Remarks
BGRNT
Note : It takes one cycle or more from when BRQ is captured until BGRNT changes.
tCYC
VOH
VOH
VOH
VOH
MCLK
SYSCLK
BRQ
tCHBGL
tCHBGH
VOH
BGRNT
VOL
tXHAL
Each pin
tHAHV
VOH
VOL
VOH
High-impedance
VOL
69
MB91305
(7) UART timing
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCLK ↓ →
SOUT delay time
Value
Unit
Min
Max
SCK0 to SCK4
8 tCYCP
⎯
ns
tSLOV
SCK0 to SCK4
SOUT0 to SOUT4
−80
+80
ns
Valid SIN →
SCLK ↑
tIVSH
SCK0 to SCK4
SIN0 to SIN4
100
⎯
ns
SCLK ↑ →
valid SIN hold time
tSHIX
SCK0 to SCK4
SIN0 to SIN4
60
⎯
ns
Serial clock
“H” Pulse Width
tSHSL
SCK0 to SCK4
4 tCYCP
⎯
ns
Serial clock
“L” Pulse Width
tSLSH
SCK0 to SCK4
4 tCYCP
⎯
ns
SCLK ↓ →
SOUT delay time
tSLOV
SCK0 to SCK4
SOUT0 to SOUT4
⎯
150
ns
Valid SIN →
SCLK ↑
tIVSH
SCK0 to SCK4
SIN0 to SIN4
60
⎯
ns
SCLK ↑ →
valid SIN hold time
tSHIX
SCK0 to SCK4
SIN0 to SIN4
60
⎯
ns
Notes : • Above rating is for CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
70
Conditions
Internal shift
clock mode
External
shift clock
mode
Remarks
MB91305
• Internal shift clock mode
tSCYC
SCK0 to SCK4
VOL
VOH
VOL
tSLOV
VOH
VOL
SOUT0 to SOUT4
tIVSH
tSHIX
VOH
VOL
SIN0 to SIN4
VOH
VOL
• External shift clock mode
tSLSH
SCK0 to SCK4
VOL
tSHSL
VOL
VOH
VOL
tSLOV
SOUT0 to SOUT4
VOH
VOL
tIVSH
SIN0 to SIN4
VOH
VOL
VOH
VOL
71
MB91305
(8) Timer clock Input Timing
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
Conditions
tTIWH
tTIWL
TIN0 to TIN2
⎯
Input pulse width
Value
Min
Max
2 tCYCP
⎯
Unit
Remarks
ns
Note : tCYCP indicates the peripheral clock cycle time.
VIH
VIH
VIL
tTIWH
VIL
tTIWL
(9) Trigger Input Timing
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
Conditions
A/D activation trigger input
time
tATG
ATRG
⎯
Value
Min
Max
5 tCYCP
⎯
Unit
ns
Note : tCYCP indicates the peripheral clock cycle time.
tATG
ATRG
72
VIH
VIH
Remarks
MB91305
(10) DMA controller timing
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
DREQ Input pulse width
tDRWH
tCLDL
DACK delay time
DEOP delay time
IORD delay time
IOWR delay time
tCLDH
tCLEL
tCLEH
tCLIRL
tCLIRH
tCLIWL
tCLIWH
Conditions
Value
Min
Max
DREQ0 to DREQ2
5 tCYC
⎯
MCLK/SYSCLK
DACK0 to DACK2
⎯
6
⎯
6
MCLK/SYSCLK
DEOP0 to DEOP2
⎯
6
⎯
6
⎯
6
⎯
6
⎯
6
⎯
6
MCLK/SYSCLK
MCLK/SYSCLK
⎯
Unit
Remarks
ns
ns
ns
ns
ns
73
MB91305
tCYC
BA1
MCLK
BA2
VOH
VOH
VOL
VOL
VOL
SYSCLK
tCLDL
tCLDH
VOH
VOL
DACK0 to DACK2
tCLEL
tCLEH
VOL
DEOP0 to DEOP2
VOH
tCLIRL
tCLIRH
VOL
IORD
VOH
tCLIWL
IOWR
tCLIWH
VOL
VOH
tDRWH
DREQ0 to DREQ2
VOL
VOH
Note : The waveform of DACKx and DEOPx is the waveforms when the PFR register is set to FR30 compatible
timing.
When the setting is chip selection timing, The delay starts from the falling edge of MCLK/SYSCLK.
74
MB91305
(11) USB interface
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Input clock
Tucyc
Pin
Conditions
X0
X1
⎯
X0
⎯
Value
Min
Typ
Max
Unit
⎯
48*1
⎯
MHz
Remarks
Self oscillation
2500 ppm accuracy*1
External input
2500 ppm accuracy*1
Rise Time
Tutfr
UDP/
UDM
Full Speed
4
⎯
20
ns
*2
Fall Time
Tutff
UDP/
UDM
Full Speed
4
⎯
20
ns
*2
Differential Rise and
Fall Timing Matching
Tutfrfm
UDP/
UDM
Full Speed
90
⎯
111.11
%
*2
Driver Output
Resistance
Tuzdrv
UDP
UDM
⎯
28
⎯
44
Ω
*3
Tucyc
VIH
VIH
X0
UDP
90%
90%
10%
10%
UDM
Tutfr
Tutff
*1 : AC characteristics for USB interface conform to USB Specification Revision 1.1.
*2 : < Driver Characteristics Tutfr, Tutff and Tutfrfm >
These are regulations of the rising / falling time of the differential data signal.
This time is defined at the time between 10% to 90% of the output signal voltage.
For full-speed buffer, Tutfr/Tutff is specified such that the Tutfr/Tutff ratio falls within ±10% to minimize RFI radiation.
75
MB91305
*3 : < Driver Characteristics ZDRV >
The USB Full-speed connection is done by 90 Ω ± 15% of characteristic impedance (Z0).
It is connected through the shielded twist 2-pair cable.
In this USB standard, both following conditions must be satisfied.
- The output impedance of USB Driver is from 28 Ω to 44 Ω.
- To balance, discrete series resistor (Rs) is added.
The output impedance of USB I/O Buffer of this LSI is about 3 Ω to 19 Ω.
Therefore, it is necessary to add the series resistance Rs of 25 Ω to 30 Ω (recommended value 27 Ω).
Rs
28 Ω to 44 Ω Equiv. Imped.
TxD+
Rs
TxD−
28 Ω to 44 Ω Equiv. Imped.
3-State
Driver output impedance 3 Ω to 19 Ω
Rs series resistance 25 Ω to 30 Ω
Resistance Rs of recommended value 27 Ω should be added.
76
MB91305
(12) I2C Timing
In the master mode operation
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*3
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
“L” width of the SCL clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” width of the SCL clock
tHIGH
4.0
⎯
0.6
⎯
µs
Bus free time between a
STOP and START condition
tBUS
4.7
⎯
1.3
⎯
µs
SCL ↓ → SDA
output delay time
tDLDAT
⎯
5 × M*1
⎯
5 × M*1
ns
Set-up time for a repeated
START condition
SCL↑ → SDA↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Hold time (repeated)
START condition
SDA↓ → SCL↓
tHDSTA
4.0
⎯
0.6
⎯
µs
Set-up time for STOP
condition
SCL↑ → SDA↑
tSUSTO
4.0
⎯
0.6
⎯
µs
Data input hold time
(vs.SCL↓)
tHDDAT
2 × M*1
⎯
2 × M*1
⎯
µs
Data input set-up time
(vs.SCL↑)
tSUDAT
250
⎯
100*2
⎯
ns
R = 1 kΩ,
C = 50 pF*4
Remarks
The first clock
pulse is generated afterword.
*1 : M = Resource clock cycle (ns)
*2 : To use high-speed mode I2C bus device for standard mode I2C bus system, it must satisfy the request condition
(tSUDAT = 250 ns). If a device does not extend "L" period of the SCL signal, the following data must be output to
the SDA line before 1250 ns (SCL line is opened, equal to SDA, SCL rise Max time + tSUDATA).
*3 : To use it exceeding 100kHz, the resource clock is set to 6MHz or more.
*4 : R and C is the pull-up resistor and the load capacity for SCL and SDA output lines respectively.
77
MB91305
In the slave mode operation
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*3
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
“L” width of the SCL clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” width of the SCL clock
tHIGH
4.0
⎯
0.6
⎯
µs
SCL ↓ → SDA
output delay time
tDLDAT
⎯
5 × M*1
⎯
5 × M*1
ns
tBUS
4.7
⎯
1.3
⎯
µs
2 × M*1
⎯
2 × M*1
⎯
µs
250
⎯
100*2
⎯
ns
Bus free time between a
STOP and START
condition
Data input hold time
(vs.SCL↓)
tHDDAT
Data input set-up time
(vs.SCL↑)
tSUDAT
Set-up time for a repeated
START condition
SCL↑ → SDA↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Hold time for a repeated
START condition
SDA↓ → SCL↓
tHDSTA
4.0
⎯
0.6
⎯
µs
Set-up time for STOP
condition
SCL↑ → SDA↑
tSUSTO
4.0
⎯
0.6
⎯
µs
R = 1 kΩ,
C = 50 pF*4
Remarks
The first clock
pulse is generated afterword.
*1 : M = Resource clock cycle (ns)
*2 : To use high-speed mode I2C bus device for standard mode I2C bus system, it must satisfy the request condition
(tSUDAT = 250 ns). If a device does not extend "L" period of the SCL signal, the following data must be output
to the SDA line before 1250 ns (SCL line is opened, equal to SDA, SCL rise Max time + tSUDATA).
*3 : To use it exceeding 100kHz, the resource clock is set to 6MHz or more.
*4 : R and C is the pull-up resistor and the load capacity for SCL and SDA output lines respectively.
78
MB91305
(13) SDRAM Timing
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Output clock cycle time
tCYCSD
“H” level clock pulse width
tCHSD
“L” level clock pulse width
tCLSD
MCLK ↑ → output delay time
tODSDCKE
Output hold time
tOHSDCKE
MCLK ↑ → output delay time
tODSDRAS
Output hold time
tOHSDRAS
MCLK ↑ → output delay time
tODSDCAS
Output hold time
tOHSDCAS
MCLK ↑ → output delay time
tODSDWE
Output hold time
tOHSDWE
MCLK ↑ → output delay time
tODSDCS
Output hold time
tOHSDCS
MCLK ↑ → output delay time
tODSDA
Output hold time
tOHSDA
MCLK ↑ → output delay time
tODSDDQM
Output hold time
tOHSDDQM
MCLK ↑ → output delay time
tODSDD
Output hold time
tOHSDD
Data input setup time
tISSDD
Data input hold time
tIHSDD
Pin
MCLK
Conditions
⎯
MCLKE
SRAS
SCAS
SWR
CS6
CS7
⎯
A00 to A15
DQMUU
DQMUL
D16 to D31
D16 to D31
⎯
Value
Unit
Min
Max
⎯
32
MHz
12
⎯
ns
12
⎯
ns
⎯
15
ns
2
⎯
ns
⎯
15
ns
2
⎯
ns
⎯
15
ns
2
⎯
ns
⎯
15
ns
2
⎯
ns
⎯
15
ns
2
⎯
ns
⎯
15
ns
2
⎯
ns
⎯
15
ns
2
⎯
ns
⎯
15
ns
2
⎯
ns
15
⎯
ns
2
⎯
ns
Remarks
79
MB91305
tCYCSD
MCLK
VOH
VOH
VOH
VOL
tCHSD
VOL
tCLSD
VOH
MCLK
VOH
tODSDCKE
tODSDRAS
tODSDCAS
tODSDWE
tODSDCS
tODSDA
tODSDDQM
MCLKE
SRAS
SCAS
SWR
CS6
CS7
A00 to A15
DQMUU
DQMUL
VOH
VOH
tOHSDCKE
tOHSDRAS
tOHSDCAS
tOHSDWE
tOHSDCS
tOHSDA
tOHSDDQM
tODSDD
VOH
VOL
D16 to D31
tOHSDD
D16 to D31
VIH
VIL
VIH
VIL
tISSDD
80
tIHSDD
VOH
VOL
MB91305
5. Electrical Characteristics for the A/D Converter
(VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = −10 °C to +70 °C)
Parameter
Symbol
Pin
Resolution
⎯
Total error
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
BIT
⎯
⎯
⎯
⎯
± 5.5
LSB
Nonlinear error
⎯
⎯
⎯
⎯
± 3.5
LSB
Differential linear error
⎯
⎯
⎯
⎯
± 2.0
LSB
Zero transition voltage
VOT
AN0 to
AN9
−4.0
⎯
+6.0
LSB
Full-transition voltage
VFST
AN0 to
AN9
AVRH − 5.5
⎯
AVRH+3.0
LSB
Conversion time
⎯
⎯
8.18*1
⎯
⎯
µs
Analog port input current
IAIN
AN0 to
AN9
⎯
0.1
10
µA
Analog input voltage
VAIN
AN0 to
AN9
AVSS
⎯
AVRH
V
⎯
AVRH
AVSS
⎯
AVCC
V
⎯
3.6
⎯
mA
⎯
⎯
10*2
µA
⎯
600
⎯
µA
⎯
⎯
10*
µA
⎯
⎯
5
LSB
Reference voltage
Power supply current
Reference voltage supply current
Variation between channels
IA
IAH
IR
IRH
⎯
AVCC
AVRH
AN0 to
AN9
2
*1 : For VDDI = 1.8 V ± 0.15 V, VDDE = AVCC = 3.3 V ± 0.3 V, machine clock = 32 MHz
*2 : Current when A/D converter not operating (VDDE = AVCC = AVRH = 3.6 V, VDDI = 1.95 V)
Notes : • The relative error increases as AVRH becomes smaller.
• If the output impedance of the external circuit is too high, the analog voltage sampling time may be too
short.
81
MB91305
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the operating frequency or
decrease the external impedance so that the sampling time is longer than the minimum value.
And if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R
4.9 kΩ (Max)
C
27 pF (Max)
Note : The values are reference values.
.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
100
20
90
18
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
80
70
60
50
40
30
20
10
16
14
12
10
8
6
4
2
0
0
5
10
15
20
25
30
35
0
0
Minimum sampling time [µs]
• About the error
The accuracy gets worse as | AVRH−AVSS | becomes smaller.
82
1
2
3
4
5
6
Minimum sampling time [µs]
7
8
MB91305
• Definition of A/D Converter Terms
• Resolution
Analog variation that is recognized by an A/D converter.
• Linearity error
The deviation between the actual conversion characteristics and a straight line connecting the device's zero
transition point (“0000000000” ←→“0000000001”) and full scale transition point (“1111111110” ←→
“1111111111”).
• Differential linear error
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Linearity error
Differential linear error
Ideal characteristics
Actual conversion characteristic
3FFH
N-1
Actual conversion
characteristic
3FDH
{1 LSB × (N-1) + VTO
VFST
(measurement value)
VNT
004H
(measurement value)
003H
Actual conversion
characteristic
Ideal characteristics
002H
001H
N-2
V (N-1) T
N-1
(measurement value)
VNT
(measurement
value)
N-2
VTO(measurement value)
AVRL
Digital output
Digital output
3FEH
AVRH
Actual conversion characteristic
AVRL
Analog input
Linear error in digital output N =
VNT − { 1LSB × (N − 1) + VOT}
1LSB
Differential linear error in digital output N =
1LSB =
VFST − VOT
1022
1LSB’ =
AVRH − AVRL
1024
N
VOT
VFST
VNT
AVRH
Analog input
[LSB]
V (N + 1) T − VNT
[LSB]
1LSB
[V]
[V] (Ideal value)
: A/D converter digital output value
: A voltage at which digital output transitions from (000)H to (001)H.
: A voltage at which digital output transitions from (3FE)H to (3FF)H.
: A voltage at which digital output transitions from (N − 1) to N.
83
MB91305
• Total error
This error indicates the difference between actual and ideal values, including the zero transition error/full-scale
transition error/linearity error.
Total error
3FFH
Actual conversion characteristic
1.5 LSB''
3FEH
{1 LSB'' × (N−1) + 0.5 LSB''
Digital output
3FDH
VNT
004H
(measurement value)
003H
Actual conversion
characteristic
002H
001H
Ideal
0.5 LSB'' characteristics
AVRL
AVRH
Analog input
Total error of digital output N =
VNT − {1 LSB” × (N − 1) + 0.5 LSB”}
[LSB]
1 LSB”
N : A/D converter digital output value
VOT” (Ideal value) = AVRL + 0.5 LSB" [V]
VFST” (Ideal value) = AVRH − 1.5 LSB" [V]
VNT: A voltage at which digital output transitions from (N − 1) to N.
84
MB91305
■ EXAMPLE CHARACTERISTICS
ICC-VDDI example characteristics
Ta = + 25 °C, fcp = 68 MHz
fcpp = 34 MHz, fcpt = 34 MHz
ICC-fCP example characteristics
Ta = + 25 °C, VDDE = 3.3 V
VDDI = 1.8 V
100
100
ICC [mA]
120
ICC [mA]
120
80
60
80
60
40
40
20
20
0
1.5
0
1.7
1.9
VDDI [V]
0
2.1
10
20
30
40
50
fcp [MHz]
60
70
80
(fcp : fcpp : fcpt = 2 : 1 : 1, PLL 4 multiplication)
ICCS-VDDI example characteristics
Ta = + 25 °C
ICCH-VDDI example characteristics
Ta = + 25 °C
50
ICCH [µA]
ICCS [mA]
60
40
30
20
10
0
0
1.7
1.9
VDDI [V]
2.1
140
120
100
80
60
40
20
0
1.5
VOH-VDDE example characteristics
Ta = + 25 °C
1.9
VDDI [V]
2.1
VOL-VDDE example characteristics
Ta = + 25 °C
0.6
4
VOL [V]
3
VOH [V]
1.7
2
1
0
2
3
VDDE [V]
4
0.4
0.2
0
2
3
VDDE [V]
4
Note : Not including USB I/O
(Continued)
85
MB91305
Pull-down resistor example characteristics
Ta = + 25 °C
120
120
80
80
R [kΩ]
R [kΩ]
Pull-up resistor example characteristics
Ta = + 25 °C
40
40
0
0
2
3
2
4
3
VDDE [V]
ICC-fCP example characteristics
Ta = + 25 °C, VDDE = 3.3 V
VDDI = 1.8 V
120
120
100
100
ICC [mA]
ICC [mA]
ICC-VDDI example characteristics
Ta = + 25 °C, fcp = 68 MHz
fcpp = 34 MHz, fcpt = 34 MHz
80
60
80
60
40
40
20
20
0
1.5
4
VDDE [V]
0
1.7
1.9
VDDI [V]
2.1
0
10
20
30
40
50
fcp [MHz]
60
70
80
(fcp : fcpp : fcpt = 2 : 1 : 1, PLL 4 multiplication)
ICCS-VDDI example characteristics
Ta = + 25 °C
ICCH-VDDI example characteristics
Ta = + 25 °C
50
ICCH [µA]
ICCS [mA]
60
40
30
20
10
0
0
1.7
1.9
VDDI [V]
2.1
140
120
100
80
60
40
20
0
1.5
1.7
1.9
VDDI [V]
2.1
Note : Not including USB I/O
(Continued)
86
MB91305
(Continued)
VOH-VDDE example characteristics
Ta = + 25 °C
VOL-VDDE example characteristics
Ta = + 25 °C
4
0.6
VOL [V]
VOH [V]
3
2
1
0.4
0.2
0
2
3
VDDE [V]
0
4
2
120
120
80
80
40
0
2
3
4
VDDE [V]
VDDE [V]
4
Pull-down resistor example characteristics
Ta = + 25 °C
R [kΩ]
R [kΩ]
Pull-up resistor example characteristics
Ta = + 25 °C
3
40
0
2
3
VDDE [V]
4
Note : Not including USB I/O
87
MB91305
■ ORDERING INFORMATION
Part number
MB91305PMC
88
Package
176-pin plastic LQFP
(FPT-176P-M07)
Remarks
MB91305
■ PACKAGE DIMENSION
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25 (.010) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
176-pin plastic LQFP
(FPT-176P-M07)
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0˚~8˚
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
89
MB91305
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
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device based on such information, you must assume any
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function and schematic diagrams, shall not be construed as license
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Please note that Fujitsu will not be liable against you and/or any
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Edited
Business Promotion Dept.
F0604