The following document contains information on Cypress products. FUJITSU MICROELECTRONICS DATA SHEET DS07-16507-3E 32-bit Proprietary Microcontrollers CMOS FR60Lite MB91260B Series MB91263B/MB91264B/MB91F264B ■ DESCRIPTION The MB91260B series is a 32-bit RISC microcontroller designed by Fujitsu microelectronics for embedded control applications which require high-speed processing. The CPU is used the FR family and the compatibility of FR60Lite. ■ FEATURES • FR60Lite CPU • 32-bit RISC, load/store architecture with a five-stage pipeline • Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier (PLL clock multiplication method) • 16-bit fixed length instructions (basic instructions) • Execution speed of instructions : 1 instruction per cycle • Memory-to-memory transfer, bit handling, barrel shift instructions, etc. : Instructions suitable for embedded applications • Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language (Continued) For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ Copyright©2005-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2008.10 MB91260B Series (Continued) • Register interlock function : Facilitates coding in assembler. • Built-in multiplier with instruction-level support • 32 bit multiplication with sign : 5 cycles • 16 bit multiplication with sign : 3 cycles • Interrupt (PC, PS save) : 6 cycles, 16 priority levels • Harvard architecture allowing program access and data access to be executed simultaneously • FR family instruction compatible • Internal peripheral functions • Capacity of internal ROM and ROM type MASK ROM : 128 Kbytes (MB91263B)/256 Kbytes (MB91264B) FLASH ROM : 256 Kbytes (MB91F264B) • Capacity of internal RAM : 8 Kbytes • A/D converter (sequential comparison type) • Resolution : 10 bits : 2 channels × 2 units, 8 channels × 1 unit • Conversion time : 1.2 µs (Minimum conversion time system clock at 33 MHz) 1.35 µs (Minimum conversion time system clock at 20 MHz) • External interrupt input : 10 channels • Bit search module (for REALOS) Function for searching the MSB in each word for the first 1-to-0 inverted bit position • UART (Full-duplex double buffer) : 3 channels Selectable parity On/Off Asynchronous (start-stop synchronized) or clock-synchronous communications selectable Internal timer for dedicated baud rate (U-Timer) on each channel External clock can be used as transfer clock Error detection function for parity, frame and overrun errors • 8/16-bit PPG timer : 16 channels (at 8-bit) / 8 channels (at 16-bit) • 16-bit reload timer : 3 channels (with cascade mode, without output of reload timer 0) • 16-bit free-run timer : 1 channel • 16-bit PWC timer : 2 channels • Input capture : 4 channels (interface with free-run timer) • Output compare : 6 channels (interface with free-run timer) • Waveform generator Various waveforms which are generated by using output compare, 16-bit PPG timer 0 and 16-bit dead timer • MAC RAM : instruction RAM 256 × 16-bit XRAM 64 × 16-bit YRAM 64 × 16-bit Execution of 1 cycle product addition (16-bit × 16-bit + 40 bits) Operation results are extracted rounded from 40 to 16 bits • DMAC (DMA Controller) : 5 channels Operation of transfer and activation by internal peripheral interrupts and software • Watchdog timer • Low Power Consumption Mode Sleep/stop function • Other • Package : QFP-100, LQFP-100 • Technology : CMOS 0.35 µm • Power supply : 1-power supply [Vcc = 4.0 V to 5.5 V] 2 DS07-16507-3E MB91260B Series ■ PIN ASSIGNMENT 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P22/SCK0 P21/SOT0 P20/SIN0 P17 P16/PPG15 X0 X1 VSS VCC P15/PPG14 P14/PPG13 P13/PPG12 P12/PPG11 P11/PPG10 P10/PPG9 P07/PPG8 P06/PPG7 P05/PPG6 P04/PPG5 P03/PPG4 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P02/PPG3 P01/PPG2 P00/PPG1 INIT MD0 MD1 MD2 NMI P77/ADTG2 P76/ADTG1 P75/ADTG0 P74/PWI1 VSS VCC P73/PWI0 P72/DTTI P71/TOT2 P70/TOT1 P63/INT9 P62/INT8 P61/IC3 P60/IC2 P37/IC1 P36/IC0 P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2 P31/RTO1 P30/RTO0 PE1/AN11 PE0/AN10 AVRH2 ACC AVCC AVRH1 AVSS PD1/AN9 PD0/AN8 AVRH0 PC7/AN7 PC6/AN6 PC5/AN5 PC4/AN4 PC3/AN3 PC2/AN2 PC1/AN1 PC0/AN0 VCC VSS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P23/SIN1 P24/SOT1 P25/SCK1 P26/INT6 P27/INT7 P50 P51/TIN0 P52/TIN1 P53/TIN2 P54/INT0 P55/INT1 P56/INT2 P57/INT3 PG0/CKI/INT4 PG1/PPG0/INT5 PG2 VCC VSS C PG3/SIN2 PG4/SOT2 PG5/SCK2 P40 P41 P42 P43 P44 P45 P46 P47 (FPT-100-M06) (Continued) DS07-16507-3E 3 MB91260B Series (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P24/SOT1 P23/SIN1 P22/SCK0 P21/SOT0 P20/SIN0 P17 P16/PPG15 X0 X1 VSS VCC P15/PPG14 P14/PPG13 P13/PPG12 P12/PPG11 P11/PPG10 P10/PPG9 P07/PPG8 P06/PPG7 P05/PPG6 P04/PPG5 P03/PPG4 P02/PPG3 P01/PPG2 P00/PPG1 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 INIT MD0 MD1 MD2 NMI P77/ADTG2 P76/ADTG1 P75/ADTG0 P74/PWI1 VSS VCC P73/PWI0 P72/DTTI P71/TOT2 P70/TOT1 P63/INT9 P62/INT8 P61/IC3 P60/IC2 P37/IC1 P36/IC0 P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2 P45 P46 P47 PE1/AN11 PE0/AN10 AVRH2 ACC AVCC AVRH1 AVSS PD1/AN9 PD0/AN8 AVRH0 PC7/AN7 PC6/AN6 PC5/AN5 PC4/AN4 PC3/AN3 PC2/AN2 PC1/AN1 PC0/AN0 VCC VSS P30/RTO0 P31/RTO1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P25/SCK1 P26/INT6 P27/INT7 P50 P51/TIN0 P52/TIN1 P53/TIN2 P54/INT0 P55/INT1 P56/INT2 P57/INT3 PG0/CKI/INT4 PG1/PPG0/INT5 PG2 VCC VSS C PG3/SIN2 PG4/SOT2 PG5/SCK2 P40 P41 P42 P43 P44 (FPT-100-M20) 4 DS07-16507-3E MB91260B Series ■ PIN DESCRIPTION Pin no. QFP LQFP Pin name Circuit type SIN1 1 2 3 4 5 99 D General-purpose I/O port. This port is enabled when UART1 data input is disabled. SOT1 UART1 data output pin. This function is enabled when UART1 data output is enabled. 100 D P24 General-purpose I/O port. This function is enabled when UART1 data output is disabled. SCK1 UART1 clock input/output pin. This function is enabled when UART1 clock output is enabled. 1 D P25 General-purpose I/O port. This function is enabled when UART1 clock output is disabled. INT6 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. 2 E P26 General-purpose I/O port. This function is enabled when external interrupt input is disabled. INT7 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. 3 4 E General-purpose I/O port. This function is enabled when external interrupt input is disabled. P50 C General-purpose I/O port. This port is enabled in single-chip mode. C Reload timer 0 external trigger input pin. Since this input is used as required when trigger input is enabled, the port output must remain off unless used intentionally. TIN0 7 8 9 UART1 data input pin. Since this input is used as required when UART1 is performing input operation, the port output must remain off unless used intentionally. P23 P27 6 Description 5 P51 General-purpose I/O port. This function is enabled when reload timer 0 external clock input is disabled. TIN1 Reload timer 1 external trigger input pin. Since this input is used as required when trigger input is enabled, the port output must remain off unless used intentionally. 6 C P52 General-purpose I/O port. This function is enabled when reload timer 1 external clock input is disabled. TIN2 Reload timer 2 external trigger input pin. Since this input is used as required when trigger input is enabled, the port output must remain off unless used intentionally. 7 C P53 General-purpose I/O port. This function is enabled when reload timer 2 external clock input is disabled. (Continued) DS07-16507-3E 5 MB91260B Series Pin no. QFP LQFP Pin name Circuit type INT0 10 11 12 13 14 15 8 E General-purpose I/O port. This function is enabled when external interrupt input is disabled. INT1 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. E P55 General-purpose I/O port. This function is enabled when external interrupt input is disabled. INT2 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. 10 E P56 General-purpose I/O port. This function is enabled when external interrupt input is disabled. INT3 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. 11 13 E P57 General-purpose I/O port. This function is enabled when external interrupt input is disabled. CKI Free-running timer external clock input pin. Since this input is used as required when selected as the external clock input for the free-running timer, the port output must remain off unless used intentionally. INT4 E 14 General-purpose I/O port. This port is enabled when free-running timer external clock input and external interrupt input are disabled. PPG0 PPG timer 0 output pin. This function is enabled when PPG timer 0 output is enabled. INT5 E PG2 18 PG3 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. General-purpose I/O port. This port is enabled when PPG timer 0 output and external interrupt input are disabled. C General-purpose I/O port. D UART2 data input pin. Since this input is used as required when UART2 is performing input operation, the port output must remain off unless used intentionally. SIN2 20 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. PG0 PG1 16 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. P54 9 12 Description General-purpose I/O port. This port is enabled when UART2 data input is disabled. (Continued) 6 DS07-16507-3E MB91260B Series Pin no. QFP LQFP Pin name Circuit type SOT2 21 22 19 D Description UART2 data output pin. This function is enabled when UART2 data output is enabled. PG4 General-purpose I/O port. This port is enabled when UART2 data output is disabled. SCK2 UART2 clock input/output pin. This function is enabled when UART2 clock output is enabled. 20 D PG5 General-purpose I/O port. This function is enabled when UART2 clock output is disabled. 23 21 P40 C General-purpose I/O port. 24 22 P41 C General-purpose I/O port. 25 23 P42 C General-purpose I/O port. 26 24 P43 C General-purpose I/O port. 27 25 P44 C General-purpose I/O port. 28 26 P45 C General-purpose I/O port. 29 27 P46 C General-purpose I/O port. 30 28 P47 C General-purpose I/O port. AN11 31 32 38 39 41 29 G A/D converter analog input pin. This function is enabled when the AICR2 register specifies analog input. PE1 General-purpose I/O port. This function is enabled when analog input is disabled. AN10 A/D converter analog input pin. This function is enabled when the AICR2 register specifies analog input. 30 G PE0 General-purpose I/O port. This function is enabled when analog input is disabled. AN9 A/D converter analog input pin. This function is enabled when the AICR1 register specifies analog input. 36 G PD1 General-purpose I/O port. This function is enabled when analog input is disabled. AN8 A/D converter analog input pin. This function is enabled when the AICR1 register specifies analog input. 37 G PD0 General-purpose I/O port. This function is enabled when analog input is disabled. AN7 A/D converter analog input pin. This function is enabled when the AICR0 register specifies analog input. 39 G PC7 General-purpose I/O port. This function is enabled when analog input is disabled. (Continued) DS07-16507-3E 7 MB91260B Series Pin no. QFP LQFP Pin name Circuit type AN6 42 43 44 45 46 47 48 40 G General-purpose I/O port. This function is enabled when analog input is disabled. AN5 A/D converter analog input pin. This function is enabled when the AICR0 register specifies analog input. 41 G PC5 General-purpose I/O port. This function is enabled when analog input is disabled. AN4 A/D converter analog input pin. This function is enabled when the AICR0 register specifies analog input. 42 G PC4 General-purpose I/O port. This function is enabled when analog input is disabled. AN3 A/D converter analog input pin. This function is enabled when the AICR0 register specifies analog input. 43 G PC3 General-purpose I/O port. This function is enabled when analog input is disabled. AN2 A/D converter analog input pin. This function is enabled when the AICR0 register specifies analog input. 44 G PC2 General-purpose I/O port. This function is enabled when analog input is disabled. AN1 A/D converter analog input pin. This function is enabled when the AICR0 register specifies analog input. 45 G PC1 General-purpose I/O port. This function is enabled when analog input is disabled. AN0 A/D converter analog input pin. This function is enabled when the AICR0 register specifies analog input. 46 G RTO0 52 A/D converter analog input pin. This function is enabled when the AICR0 register specifies analog input. PC6 PC0 51 Description 49 J General-purpose I/O port. This function is enabled when analog input is disabled. Multifunction timer waveform generator output pin. This pin outputs a specified waveform to the waveform generator. The waveform output is enabled when waveform generator output is enabled. P30 General-purpose I/O port. This function is enabled when waveform generator output is disabled. RTO1 Multifunction timer waveform generator output pin. This pin outputs a specified waveform to the waveform generator. The waveform output is enabled when waveform generator output is enabled. 50 J P31 General-purpose I/O port. This function is enabled when waveform generator output is disabled. (Continued) 8 DS07-16507-3E MB91260B Series Pin no. QFP LQFP Pin name Circuit type RTO2 53 54 55 56 57 58 59 51 J Description Multifunction timer waveform generator output pin. This pin outputs a specified waveform to the waveform generator. The waveform output is enabled when waveform generator output is enabled. P32 General-purpose I/O port. This function is enabled when waveform generator output is disabled. RTO3 Multifunction timer waveform generator output pin. This pin outputs a specified waveform to the waveform generator. The waveform output is enabled when waveform generator output is enabled. 52 J P33 General-purpose I/O port. This function is enabled when waveform generator output is disabled. RTO4 Multifunction timer waveform generator output pin. This pin outputs a specified waveform to the waveform generator. The waveform output is enabled when waveform generator output is enabled. 53 J P34 General-purpose I/O port. This function is enabled when waveform generator output is disabled. RTO5 Multifunction timer waveform generator output pin. This pin outputs a specified waveform to the waveform generator. The waveform output is enabled when waveform generator output is enabled. 54 J P35 General-purpose I/O port. This function is enabled when waveform generator output is disabled. IC0 Input capture 0 trigger input pin. The trigger can be input when the input capture trigger input and input port are set. Since this input is used as required when selected as the input capture input, the port output must remain off unless used intentionally. 55 D P36 General-purpose I/O port. This function is enabled when input capture trigger input is disabled. IC1 Input capture 1 trigger input pin. The trigger can be input when the input capture trigger input and input port are set. Since this input is used as required when selected as the input capture input, the port output must remain off unless used intentionally. 56 D P37 General-purpose I/O port. This function is enabled when input capture trigger input is disabled. IC2 Input capture 2 trigger input pin. The trigger can be input when the input capture trigger input and input port are set. Since this input is used as required when selected as the input capture input, the port output must remain off unless used intentionally. 57 D P60 General-purpose I/O port. This function is enabled when input capture trigger input is disabled. (Continued) DS07-16507-3E 9 MB91260B Series Pin no. QFP LQFP Pin name Circuit type IC3 60 61 62 63 64 65 66 58 D General-purpose I/O port. This function is enabled when input capture trigger input is disabled. INT8 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. 59 E P62 General-purpose I/O port. This function is enabled when external interrupt input is disabled. INT9 External interrupt input pin. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. 60 E P63 General-purpose I/O port. This function is enabled when external interrupt input is disabled. TOT1 Reload timer 1 output pin. This function is enabled when reload timer output is enabled. 61 C P70 General-purpose I/O port. This function is enabled when reload timer output is disabled. TOT2 Reload timer 2 output pin. This function is enabled when reload timer output is enabled. 62 C P71 General-purpose I/O port. This function is enabled when reload timer output is disabled. DTTI Input signal for controlling multifunction timer waveform generator output pins RTO0 to RTO5. This function is enabled when DTTI input is enabled. 63 D P72 General-purpose I/O port. This function is enabled when DTTI input is disabled. PWI0 PWC timer 0 pulse width counter input pin. This function is enabled when PWC timer 0 pulse width counter input is enabled. 64 D PWI1 67 D P74 ADTG0 70 Input capture 3 trigger input pin. The trigger can be input when the input capture trigger input and input port are set. Since this input is used as required when selected as the input capture input, the port output must remain off unless used intentionally. P61 P73 69 Description 68 C P75 General-purpose I/O port. This function is enabled when PWC timer 0 pulse width counter input is disabled. PWC timer 1 pulse width counter input pin. This function is enabled when PWC timer 1 pulse width counter input is enabled. General-purpose I/O port. This function is enabled when PWC timer 1 pulse width counter input is disabled. A/D converter 0 external trigger input pin. Since this input is used as required when selected as the A/D converter trigger source, the port output must remain off unless used intentionally. General-purpose I/O port. This function is enabled when A/D converter 0 external trigger input is disabled. (Continued) 10 DS07-16507-3E MB91260B Series Pin no. QFP LQFP Pin name Circuit type ADTG1 71 72 69 C Description A/D converter 1 external trigger input pin. Since this input is used as required when selected as the A/D converter trigger source, the port output must remain off unless used intentionally. P76 General-purpose I/O port. This function is enabled when A/D converter 1 external trigger input is disabled. ADTG2 A/D converter 2 external trigger input pin. Since this input is used as required when selected as the A/D converter trigger source, the port output must remain off unless used intentionally. 70 C General-purpose I/O port. This function is enabled when A/D converter 2 external trigger input is disabled. P77 73 71 NMI H NMI (Non Maskable Interrupt) input pin. 74 72 MD2 K Mode pin 2. The setting of this pin determines the basic operation mode. Connect the pin to Vcc or Vss. 75 73 MD1 K Mode pin 1. The setting of this pin determines the basic operation mode. Connect the pin to Vcc or Vss. 76 74 MD0 K Mode pin 0. The setting of this pin determines the basic operation mode. Connect the pin to Vcc or Vss. 77 75 INIT I External reset input pin. PPG1 78 79 80 81 82 76 C PPG timer 1 output pin. This function is enabled when PPG timer 1 output is enabled. P00 General-purpose I/O port. This function is enabled when PPG timer 1 output is disabled. PPG2 PPG timer 2 output pin. This function is enabled when PPG timer 2 output is enabled. 77 C P01 General-purpose I/O port. This function is enabled when PPG timer 2 output is disabled. PPG3 PPG timer 3 output pin. This function is enabled when PPG timer 3 output is enabled. 78 C P02 General-purpose I/O port. This function is enabled when PPG timer 3 output is disabled. PPG4 PPG timer 4 output pin. This function is enabled when PPG timer 4 output is enabled. 79 C P03 General-purpose I/O port. This function is enabled when PPG timer 4 output is disabled. PPG5 PPG timer 5 output pin. This function is enabled when PPG timer 5 output is enabled. 80 C P04 General-purpose I/O port. This function is enabled when PPG timer 5 output is disabled. (Continued) DS07-16507-3E 11 MB91260B Series Pin no. QFP LQFP Pin name Circuit type PPG6 83 84 85 86 87 88 89 90 91 81 C Description PPG timer 6 output pin. This function is enabled when PPG timer 6 output is enabled. P05 General-purpose I/O port. This function is enabled when PPG timer 6 output is disabled. PPG7 PPG timer 7 output pin. This function is enabled when PPG timer 7 output is enabled. 82 C P06 General-purpose I/O port. This function is enabled when PPG timer 7 output is disabled. PPG8 PPG timer 8 output pin. This function is enabled when PPG timer 8 output is enabled. 83 C P07 General-purpose I/O port. This function is enabled when PPG timer 8 output is disabled. PPG9 PPG timer 9 output pin. This function is enabled when PPG timer 9 output is enabled. 84 C P10 General-purpose I/O port. This function is enabled when PPG timer 9 output is disabled. PPG10 PPG timer 10 output pin. This function is enabled when PPG timer 10 output is enabled. 85 C P11 General-purpose I/O port. This function is enabled when PPG timer 10 output is disabled. PPG11 PPG timer 11 output pin. This function is enabled when PPG timer 11 output is enabled. 86 C P12 General-purpose I/O port. This function is enabled when PPG timer 11 output is disabled. PPG12 PPG timer 12 output pin. This function is enabled when PPG timer 12 output is enabled. C 87 P13 General-purpose I/O port. This function is enabled when PPG timer 12 output is disabled. PPG13 PPG timer 13 output pin. This function is enabled when PPG timer 13 output is enabled. 88 C P14 General-purpose I/O port. This function is enabled when PPG timer 13 output is disabled. PPG14 PPG timer 14 output pin. This function is enabled when PPG timer 14 output is enabled. 89 C P15 General-purpose I/O port. This function is enabled when PPG timer 14 output is disabled. 94 92 X1 A Clock (oscillation) output pin. 95 93 X0 A Clock (oscillation) input pin. (Continued) 12 DS07-16507-3E MB91260B Series (Continued) Pin no. QFP LQFP Pin name Circuit type PPG15 96 94 C P16 97 95 P17 96 99 General-purpose I/O port. D UART0 data input pin. Since this input is used as required when UART0 is performing input operation, the port output must remain off unless used intentionally. General-purpose I/O port. This port is enabled when UART0 data input is disabled. SOT0 UART0 data output pin. This function is enabled when UART0 data output is enabled. D P21 General-purpose I/O port. This port is enabled when UART0 data output is disabled. SCK0 UART0 clock input/output pin. This function is enabled when UART0 clock output is enabled. 98 D P22 • Power supply and GND pins Pin no. QFP General-purpose I/O port. This function is enabled when PPG timer 15 output is disabled. P20 97 100 PPG timer 15 output pin. This function is enabled when PPG timer 15 output is enabled. C SIN0 98 Description LQFP General-purpose I/O port. This function is enabled when UART0 clock output is disabled. Pin name Description 18, 50, 68, 93 16, 48, 66, 91 Vss GND pins. Use all of these pins at equal potential. 17, 49, 67, 92 15, 47, 65, 90 Vcc Power-supply pins. Use all of these pins at equal potential. 35 33 AVcc 33 31 AVRH2 Analog reference power-supply pin for A/D converter 2 36 34 AVRH1 Analog reference power-supply pin for A/D converter 1 40 38 AVRH0 Analog reference power-supply pin for A/D converter 0 37 35 AVss 19 17 C 34 32 ACC DS07-16507-3E Analog power-supply pin for A/D converter Analog GND pin for A/D converter Capacitor coupling pin for internal regulator Analog capacitor coupling pin 13 MB91260B Series ■ I/O CIRCUIT TYPE Type Circuit type Remarks X1 Clock input A • Oscillation circuit • Oscillation feedback resistance : approx. 1 MΩ X0 Standby control P-ch Pull-up control • CMOS level output • CMOS level input. Digital output • With standby control • With Pull-up control P-ch C Digital output • IOL = 4 mA N-ch Digital input Standby control P-ch Pull-up control • CMOS level output • CMOS hysteresis input. Digital output • With standby control • With Pull-up control P-ch D Digital output • IOL = 4 mA N-ch Digital input Standby control (Continued) 14 DS07-16507-3E MB91260B Series Type Circuit type P-ch Remarks Pull-up control • CMOS level output • CMOS hysteresis input. Digital output • Without standby control • With Pull-up control P-ch E Digital output • IOL = 4 mA N-ch Digital input Digital output P-ch Digital output G N-ch Digital input Standby control Analog input • Analog/CMOS level input/output pin • CMOS level output • CMOS level input. (attached with standby control) • Analog input (Analog input is enabled when AICR register’s corresponding bit is set to “1”.) • IOL = 4 mA • CMOS hysteresis input. • Without standby control P-ch H N-ch Digital input (Continued) DS07-16507-3E 15 MB91260B Series (Continued) Type Circuit type Remarks • CMOS hysteresis input. P-ch • With pull-up resistor • Without standby control P-ch I N-ch Digital input • CMOS level output • CMOS hysteresis input. Digital output • With standby control P-ch Digital output J • IOL = 12 mA N-ch Digital input Standby control • CMOS level input. • Without standby control P-ch K N-ch Digital input 16 DS07-16507-3E MB91260B Series ■ HANDLING DEVICES Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC and VSS. A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating. Treatment of Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. About Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. About Crystal Oscillator Circuit Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, X0A and X1A the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. About Mode Pins (MD0 to MD2) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. Operation at Start-up Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up. Also, in order to provide the oscillation stabilization wait time for the oscillation circuit immediately after start-up, hold the “L” level input to the INIT pin for the required stabilization wait time. (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value) . About Oscillation Input at Power On When turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state. DS07-16507-3E 17 MB91260B Series Caution operation during PLL clock mode Even if the oscillator comes off or the clock input stops with the PLL clock selected for this device, the device may continue to operate at the free-run frequency of the PLL’s internal self-oscillating oscillator circuit. Performance of this operation, however, cannot be guaranteed. External clock When external clock is selected, the opposite phase clock to X0 pin must be supplied to X1 pin simultaneously. If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H" output. So, when STOP mode is specified, approximately 1 kΩ of resistance should be added externally to avoid the conflict of output. The following figure shows using an external clock. X0 X1 MB91260B series Using an external clock C pin A bypass capacitor of approximately 0.1 µF should be connected the C pin for built-in regulator. C MB91260B series 0.1 µF VSS GND ACC pin A capacitor should be inserted between the ACC pin and the AVcc pin as this product has built-in regulator for A/D converter. ACC MB91260B series 0.1 µF AVSS 18 DS07-16507-3E MB91260B Series Clock Control Block Input the “L” signal to the INIT pin to assure the clock oscillation stabilization wait time. Switch Shared Port Function To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR) . Low Power Consumption Mode To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR : timebase counter control register) and be sure to use the following sequence (LDI #value_of_standby, R0) : Value_of standby is write data to STCR. (LDI #_STCR, R12) : _STCR is address (481H) of STCR. STB R0, @R12 : Writing to standby control register (STCR) LDUB @R12, R0 : STCR read for synchronous standby LDUB @R12, R0 : Dummy re-read of STCR NOP : NOP × 5 for arrangement of timing NOP NOP NOP NOP In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the standby returns. •Please do not do the following when the monitor debugger is used. • Break point setting for above instruction lines • Step execution for above instruction lines Notes on the PS register As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. • The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event or emulator menu : 1) The D0 and D1 flags are updated in advance. 2) An EIT handling routine (user interrupt or emulator) is executed. 3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed, and the D0 and D1 flags are updated to the same values as in 1). • The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed to allow the interrupt. DS07-16507-3E 19 MB91260B Series 1) The PS register is updated in advance. 2) An EIT handling routine (user interrupt) is executed. 3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the same value as in 1). Watchdog Timer The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on operating programs until it resets the CPU. As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops program execution. For those conditions to which this exception applies, see the function description of watchdog timer. 20 DS07-16507-3E MB91260B Series ■ NOTE ON DEBUGGER • Step execution of RETI command If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed repeatedly after step execution. This will prevent the main routine and low-interrupt-level programs from being executed. Do not execute step of RETI instruction for escape. Disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine no longer needs debugging. • Operand break Do not apply a data event break to access to the area containing the address of a system stack pointer. • Execution in an unused area of FLASH memory Accidentally executing an instruction in an unused area of FLASH memory (with data placed at FFFFH) prevents breaks from being accepted. To prevent this, the code event address mask function of the debugger should be used to cause a break when accessing an instruction in an unused area. • Power-on debugging All of the following three conditions must be satisfied when the power supply is turned off by power-on debugging. (1) The time for the user power to fall from 0.9 VCC to 0.5 VCC is 25 µs or longer. Note : In a dual-power system, VCC indicates the external I/O power supply voltage. (2) CPU operating frequency must be higher than 1 MHz. (3) During execution of user program • Interrupt handler for NMI request (tool) Add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor flag to be set only in response to a break request from the ICE is set, for example, by an adverse effect of noise to the DSU pin while the ICE is not connected. Enable to use the ICE while adding this program. Additional location Next interrupt handler Interrupt source : NMI request (tool) Interrupt number : #13 (decimal) , 0DH (hexa decimal) Offset : 3C8H Address TBR is default : 000FFFC8H Additional program STM (R0, R1) LDI #B00H, R0; LDI #0, R1 STB R1, @R0 LDM (R0, R1) : B00H is the address of DSU break factor register. : Clear the break factor register. RETI DS07-16507-3E 21 MB91260B Series ■ BLOCK DIAGRAM FR60 Lite CPU core 32 32 DMAC 5 channels Bit search MAC ROM 128 Kbytes/ ROM 256 Kbytes/ FLASH 256 Kbytes Bus converter RAM 8 Kbytes X0, X1 MD0 to MD2 INIT 32 32 ↔ 16 Adapter Clock control 16 Interrupt controller INT0 to INT9 NMI 10 channels External interrupt SCK0 to SCK2 3 channels 16-bit reload timer 2 channels 16-bit PWC timer SIN0 to SIN2 SOT0 to SOT2 Port I/F PORT TIN0 to TIN2 TOT1, TOT2 PWI0, PWI1 3 channels UART 16/8 channels 8/16 PPG timer PPG0 to PPG15 3 channels U-TIMER AVCC Multi-function timer ADTG0 AN0 to AN7 AVRH0 8 channels input 8/10-bit A/D converter 0 ADTG1 AVRH1 AN8, AN9 2 channels input 8/10-bit A/D converter 1 ADTG2 AVRH2 AN10, AN11 2 channels input 8/10-bit A/D converter 2 22 Free-run timer 1 channel CKI Input capture 4 channels IC0 to IC3 Output compare 6 channels RTO0 to RTO5 Waveform generator DTTI DS07-16507-3E MB91260B Series ■ MEMORY SPACE 1. Memory space The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. • Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The size of directly addressable areas depends on the data size to be being accessed as follows. → Byte data access → Half word data access → Word data access : 000H to 0FFH : 000H to 1FFH : 000H to 3FFH 2. Memory Map MB91263B MB91F264B/MB91264B Single chip mode Single chip mode 0000 0000H I/O Direct addressing area 0000 0400H I/O Access disallowed 0003 E000H Refer to “■ I/O MAP”. I/O 0001 0000H 0004 0000H 0004 0000H 000C 0000H Access disallowed 000E 0000H Internal RAM 256 Kbytes 0010 0000H Internal RAM 128 Kbytes Access disallowed Access disallowed DS07-16507-3E Access disallowed Internal RAM 8 Kbytes Access disallowed FFFF FFFFH Refer to “■ I/O MAP”. 0003 E000H Internal RAM 8 Kbytes 0010 0000H Direct addressing area 0000 0400H I/O 0001 0000H 0000 0000H FFFF FFFFH 23 MB91260B Series ■ MODE SETTINGS The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode. • Mode Pins The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed. Setting is prohibited other than that shown in the following table. Mode Pins Mode name Reset vector access area 0 Internal ROM mode vector Internal 1 External ROM mode vector External MD2 MD1 MD0 0 0 0 0 Remarks Not supported by this model. • Mode data Data written to the internal mode register (MODR) by a mode vector fetch is called mode data. After an operation mode has been set in the mode register, the device operates in the operation mode. The mode data is set by all reset source. User programs cannot set data to the mode register. Details of mode data description bit 31 30 29 28 27 26 25 24 0 0 0 0 0 1 1 1 Operation mode setting bits Bit31 to bit24 are all reserved bits. Be sure to set this bit to “00000111”. Operation is not guaranteed when any value other than “00000111” is set. Note : Mode data set in the mode vector must be placed as byte data at 000FFFF8H. Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte endian. bit 31 Incorrect Correct 24 24 23 16 15 87 0 000FFFF8H XXXXXXXX XXXXXXXX XXXXXXXX Mode Data 000FFFF8H Mode Data XXXXXXXX XXXXXXXX XXXXXXXX 000FFFFCH Reset Vector DS07-16507-3E MB91260B Series ■ I/O MAP [How to read the table] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block T-unit Port data register Read/write attribute Access unit (B : byte, H : half word, W : word) Initial value of register after reset Register name (column 1 of the register is at address 4n, column 2 is at address 4n + 1...) Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.) Note : Initial values of register bits are represented as follows : “ 1 ” : Initial Value “ 1 ” “ 0 ” : Initial Value “ 0 ” “ X ” : Initial Value “ undefined” “ - ” : No physical register at this location Access is barred with an undefined data access attribute. DS07-16507-3E 25 MB91260B Series Address Register +0 +1 +2 +3 000000H PDR0 [R/W] B XXXXXXXX PDR1 [R/W] B XXXXXXXX PDR2 [R/W] B XXXXXXXX PDR3 [R/W] B XXXXXXXX 000004H PDR4 [R/W] B XXXXXXXX PDR5 [R/W] B XXXXXXXX PDR6 [R/W] B ----XXXX PDR7 [R/W] B XXXXXXXX Port data register ⎯ 000008H 00000CH PDRC [R/W] B XXXXXXXX PDRD [R/W] B ------XX PDRE [R/W] B ------XX ⎯ 000010H PDRG [R/W] B --XXXXXX ⎯ ⎯ ⎯ 000014H to 00003CH ⎯ 000040H EIRR0 [R/W] B, H, W 00000000 ENIR0 [R/W] B, H, W 00000000 000044H DICR [R/W] B, H, W -------0 HRCL [R/W, R] B, H, W 0--11111 Reserved ELVR0 [R/W] B, H, W 00000000 00000000 ⎯ ⎯ TMRLR0 [W] H, W XXXXXXXX XXXXXXXX TMR0 [R] H, W XXXXXXXX XXXXXXXX 00004CH ⎯ TMCSR0 [R/W, R] B, H, W ---00000 00000000 000050H TMRLR1 [W] H, W XXXXXXXX XXXXXXXX TMR1 [R] H, W XXXXXXXX XXXXXXXX 000054H ⎯ TMCSR1 [R/W, R] B, H, W ---00000 00000000 000058H TMRLR2 [W] H, W XXXXXXXX XXXXXXXX TMR2 [R] H, W XXXXXXXX XXXXXXXX ⎯ TMCSR2 [R/W, R] B, H, W ---00000 00000000 000048H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H SSR0 [R/W, R] B, H, W 00001000 SIDR0 [R]/SODR0[W] SCR0 [R/W] B, H, W SMR0 [R/W, W] B, H, W B, H, W 00000100 00--0-0XXXXXXXX UTIM0 [R] H / UTIMR0 [W] H 00000000 00000000 SSR1 [R/W, R] B, H, W 00001000 SSR2 [R/W, R] B, H, W 00001000 DRCL0 [W] B -------- SIDR1, SODR1 [R/W] SCR1 [R/W] B, H, W B, H, W 00000100 XXXXXXXX UTIM1 [R] H / UTIMR1 [W] H 00000000 00000000 DRCL1 [W] B -------- SIDR2, SODR2 [R/W] SCR2 [R/W] B, H, W B, H, W 00000100 XXXXXXXX UTIM2 [R] H / UTIMR2 [W] H 00000000 00000000 Block DRCL2 [W] B -------- External interrupt (INT0 to INT7) Delay interrupt/ Hold request Reload timer 0 Reload timer 1 Reload timer 2 UART0 UTIMC0 [R/W] B 0--00001 U-TIMER 0 SMR1 [R/W] B, H, W 00--0-0- UART1 UTIMC1 [R/W] B 0--00001 U-TIMER 1 SMR2 [R/W] B, H, W 00--0-0- UART2 UTIMC2 [R/W] B 0--00001 U-TIMER 2 (Continued) 26 DS07-16507-3E MB91260B Series Register Address +0 +1 000078H ADCH0 [R/W] B, H, W XX000000 ADMD0 [R/W] B, H, W 00001111 00007CH ADCS0 [R/W, W] B, H, W 00000X00 ⎯ 000080H ADCH1 [R/W] B, H, W XXXX0XX0 ADMD1 [R/W] B, H, W 00001111 000084H ADCS1 [R/W, W] B, H, W 00000X00 ⎯ 000088H ADCH2 [R/W] B, H, W XXXX0XX0 ADMD2 [R/W] B, H, W 00001111 00008CH ADCS2 [R/W, W] B, H, W 00000X00 ⎯ +2 +3 ADCD01 [R] B, H, W ADCD00 [R] B, H, W XXXXXXXX XXXXXXXX AICR0 [R/W] B, H, W 00000000 ⎯ ADCD11 [R] B, H, W ADCD10 [R] B, H, W XXXXXXXX XXXXXXXX AICR1 [R/W] B, H, W ------00 ⎯ ADCD21 [R] B, H, W ADCD20 [R] B, H, W XXXXXXXX XXXXXXXX AICR2 [R/W] B, H, W ------00 ⎯ 000090H OCCPBH0, OCCPBL0[W]/ OCCPH0, OCCPL0[R] H, W 00000000 00000000 OCCPBH1, OCCPBL1[W]/ OCCPH1, OCCPL1 [R] H, W 00000000 00000000 000094H OCCPBH2, OCCPBL2[W]/ OCCPH2, OCCPL2 [R] H, W 00000000 00000000 OCCPBH3, OCCPBL3[W]/ OCCPH3, OCCPL3 [R] H, W 00000000 00000000 000098H OCCPBH4, OCCPBL4[W]/ OCCPH4, OCCPL4 [R] H, W 00000000 00000000 OCCPBH5, OCCPBL5[W]/ OCCPH5, OCCPL5 [R] H, W 00000000 00000000 00009CH OCSH1 [R/W] B, H, W X1100000 OCSL0 [R/W] B, H, W 00001100 OCSH3 [R/W] B, H, W X1100000 OCSL2 [R/W] B, H, W 00001100 0000A0H OCSH5 [R/W] B, H, W X1100000 OCSL4 [R/W] B, H, W 00001100 OCMOD [R/W] B, H, W XX000000 ⎯ CPCLRBH, CPCLRBL[W]/ CPCLRH, CPCLRL[R] H, W 11111111 11111111 0000A4H 0000A8H TCCSH [R/W] B, H, W 00000000 TCCSL [R/W] B, H, W 01000000 TCDTH, TCDTL [R/W] H, W 00000000 00000000 ⎯ ADTRGC [R/W] B, H, W XXXX0000 0000ACH IPCPH0, IPCPL0 [R] H, W XXXXXXXX XXXXXXXX IPCPH1, IPCPL1 [R] H, W XXXXXXXX XXXXXXXX 0000B0H IPCPH2, IPCPL2 [R] H, W XXXXXXXX XXXXXXXX IPCPH3, IPCPL3 [R] H, W XXXXXXXX XXXXXXXX 0000B4H PICSH01 [W] B, H, W 000000-- PICSL01 [R/W] B, H, W 00000000 0000B8H EIRR1 [R/W] B, H, W ------00 ENIR1 [R/W] B, H, W ------00 ICSH23 [R] B, H, W XXXXXX00 ICSL23 [R/W] B, H, W 00000000 ELVR1 [R/W] B, H, W -------- ----0000 Block A/D converter 0/ AICR0 A/D converter 1/ AICR1 A/D converter 2/ AICR2 16-bit output compare 16-bit free-run timer 16-bit input capture External interrupt (INT8, INT9) (Continued) DS07-16507-3E 27 MB91260B Series Address Register +0 +1 0000BCH TMRRH0, TMRRL0 [R/W] H, W XXXXXXXX XXXXXXXX 0000C0H TMRRH2, TMRRL2 [R/W] H, W XXXXXXXX XXXXXXXX +2 Block +3 TMRRH1, TMRRL1 [R/W] H, W XXXXXXXX XXXXXXXX ⎯ ⎯ Waveform generator 0000C4H DTCR0 [R/W] B, H, W 00000000 DTCR1 [R/W] B, H, W 00000000 DTCR2 [R/W] B, H, W 00000000 ⎯ 0000C8H ⎯ SIGCR1 [R/W] B, H, W 10000000 ⎯ SIGCR2 [R/W] B, H, W XXXXXXX1 0000CCH ADCOMP0 [R/W] H, W 00000000 00000000 0000D0H ADCOMP2 [R/W] H, W 00000000 00000000 0000D4H to 0000DCH ADCOMP1 [R/W] H, W 00000000 00000000 ADCOMPC [R/W] B, H, W XXXXX000 ⎯ ⎯ Reserved 0000E0H PWCSR0 [R/W, R] B, H, W 00000000 00000000 PWCR0 [R] H, W 00000000 00000000 0000E4H PWCSR1 [R/W, R] B, H, W 00000000 00000000 PWCR1 [R] H, W 00000000 00000000 0000E8H ⎯ PDIVR0 [R/W] B, H, W XXXXX000 0000ECH to 000FCH A/D COMP ⎯ PWC timer PDIVR1 [R/W] B, H, W XXXXX000 ⎯ Reserved 000100H PRLH0 [R/W] B, H, W XXXXXXXX PRLL0 [R/W] B, H, W XXXXXXXX PRLH1 [R/W] B, H, W XXXXXXXX PRLL1 [R/W] B, H, W XXXXXXXX 000104H PRLH2 [R/W] B, H, W XXXXXXXX PRLL2 [R/W] B, H, W XXXXXXXX PRLH3 [R/W] B, H, W XXXXXXXX PRLL3 [R/W] B, H, W XXXXXXXX 000108H PPGC0 [R/W] B, H, W 0000000X PPGC1 [R/W] B, H, W PPGC2 [R/W] B, H, W 0000000X 0000000X PPGC3 [R/W] B, H, W 0000000X 00010CH PRLH4 [R/W] B, H, W XXXXXXXX PRLL4 [R/W] B, H, W XXXXXXXX PRLH5 [R/W] B, H, W XXXXXXXX PRLL5 [R/W] B, H, W XXXXXXXX 000110H PRLH6 [R/W] B, H, W XXXXXXXX PRLL6 [R/W] B, H, W XXXXXXXX PRLH7 [R/W] B, H, W XXXXXXXX PRLL7 [R/W] B, H, W XXXXXXXX 000114H PPGC4 [R/W] B, H, W 0000000X PPGC5 [R/W] B, H, W 0000000X PPGC6 [R/W] B, H, W0000000X PPGC7 [R/W] B, H, W 0000000X 000118H PRLH8 [R/W] B, H, W XXXXXXXX PRLL8 [R/W] B, H, W XXXXXXXX PRLH9 [R/W] B, H, W XXXXXXXX PRLL9 [R/W] B, H, W XXXXXXXX 00011CH PRLH10 [R/W] B, H, W PRLL10 [R/W] B, H, W XXXXXXXX XXXXXXXX PRLH11 [R/W] B, H, W XXXXXXXX PRLL11 [R/W] B, H, W XXXXXXXX 000120H PPGC8 [R/W] B, H, W 0000000X PPGC9 [R/W] B, H, W PPGC10 [R/W] B, H, W 0000000X 0000000X PPG0 to PPG15 PPGC11 [R/W] B, H, W 0000000X (Continued) 28 DS07-16507-3E MB91260B Series Register Address +0 +1 +2 +3 000124H PRLH12 [R/W] B, H, W PRLL12 [R/W] B, H, W PRLH13 [R/W] B, H, W XXXXXXXX XXXXXXXX XXXXXXXX PRLL13 [R/W] B, H, W XXXXXXXX 000128H PRLH14 [R/W] B, H, W PRLL14 [R/W] B, H, W PRLH15 [R/W] B, H, W XXXXXXXX XXXXXXXX XXXXXXXX PRLL15 [R/W] B, H, W XXXXXXXX 00012CH PPGC12 [R/W] B, H, W PPGC13 [R/W] B, H, W PPGC14 [R/W] B, H, W PPGC15 [R/W] B, H, W 0000000X 0000000X 0000000X 0000000X 000130H TRG [R/W] B, H, W 00000000 00000000 ⎯ GATEC [R/W] B, H, W XXXXXX00 000134H REVC [R/W] B, H, W 00000000 00000000 ⎯ ⎯ Block PPG0 to PPG15 000138H to 0001FCH ⎯ 000200H DMACA0 [R/W] B, H, W *1 00000000 00000000 00000000 00000000 000204H DMACB0 [R/W] B, H, W 00000000 00000000 00000000 00000000 000208H DMACA1 [R/W] B, H, W*1 00000000 00000000 00000000 00000000 00020CH DMACB1 [R/W] B, H, W 00000000 00000000 00000000 00000000 000210H DMACA2 [R/W] B, H, W *1 00000000 00000000 00000000 00000000 000214H DMACB2 [R/W] B, H, W 00000000 00000000 00000000 00000000 000218H DMACA3 [R/W] B, H, W *1 00000000 00000000 00000000 00000000 00021CH DMACB3 [R/W] B, H, W 00000000 00000000 00000000 00000000 000220H DMACA4 [R/W] B, H, W *1 00000000 00000000 00000000 00000000 000224H DMACB4 [R/W] B, H, W 00000000 00000000 00000000 00000000 000228H to 00023CH ⎯ Reserved 000240H DMACR [R/W] B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX DMAC 000244H to 000398H ⎯ Reserved Reserved DMAC (Continued) DS07-16507-3E 29 MB91260B Series Address Register +0 +1 +2 +3 ⎯ ⎯ 00039CH ⎯ ⎯ 0003A0H DSP-PC [R/W] XXXXXXXX DSP-CSR [R/W, R, W] 00000000 DSP-LY [R/W] XXXXXXXX XXXXXXXX 0003A4H DSP-OT0 [R] XXXXXXXX XXXXXXXX DSP-OT1 [R] XXXXXXXX XXXXXXXX 0003A8H DSP-OT2 [R] XXXXXXXX XXXXXXXX DSP-OT3 [R] XXXXXXXX XXXXXXXX 0003ACH ⎯ ⎯ 0003B0H DSP-OT4 [R] XXXXXXXX XXXXXXXX DSP-OT5 [R] XXXXXXXX XXXXXXXX 0003B4H DSP-OT6 [R] XXXXXXXX XXXXXXXX DSP-OT7 [R] XXXXXXXX XXXXXXXX ⎯ 0003B8H to 0003ECH ⎯ 0003F0H BSD0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX MAC ⎯ Reserved Bit search 000400H DDR0 [R/W] B 00000000 DDR1 [R/W] B 00000000 DDR2 [R/W] B 00000000 DDR3 [R/W] B 00000000 000404H DDR4 [R/W] B 00000000 DDR5 [R/W] B 00000000 DDR6 [R/W] B ----0000 DDR7 [R/W] B 00000000 000408H ⎯ ⎯ ⎯ ⎯ 00040CH DDRC [R/W] B 00000000 DDRD [R/W] B ------00 DDRE [R/W] B ------00 ⎯ 000410H DDRG [R/W] B --000000 ⎯ ⎯ ⎯ 000414H to 00041CH Block ⎯ Data direction register Reserved 000420H PFR0 [R/W] B 00000000 PFR1 [R/W] B -0000000 PFR2 [R/W] B --00-00- ⎯ 000424H ⎯ ⎯ ⎯ PFR7 [R/W] B ------00 000428H ⎯ ⎯ ⎯ ⎯ 00042CH ⎯ ⎯ ⎯ ⎯ 000430H PFRG [R/W] B --00--0- ⎯ ⎯ ⎯ Port function register (Continued) 30 DS07-16507-3E MB91260B Series Register Address +0 +1 +2 +3 Block 000434H to 00043CH ⎯ 000440H ICR00 [R/W, R] B, H, W ICR01 [R/W, R] B, H, W ICR02 [R/W, R] B, H, W ICR03 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000444H ICR04 [R/W, R] B, H, W ICR05 [R/W, R] B, H, W ICR06 [R/W, R] B, H, W ICR07 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000448H ICR08 [R/W, R] B, H, W ICR09 [R/W, R] B, H, W ICR10 [R/W, R] B, H, W ICR11 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 00044CH ICR12 [R/W, R] B, H, W ICR13 [R/W, R] B, H, W ICR14 [R/W, R] B, H, W ICR15 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000450H ICR16 [R/W, R] B, H, W ICR17 [R/W, R] B, H, W ICR18 [R/W, R] B, H, W ICR19 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000454H ICR20 [R/W, R] B, H, W ICR21 [R/W, R] B, H, W ICR22 [R/W, R] B, H, W ICR23 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000458H ICR24 [R/W, R] B, H, W ICR25 [R/W, R] B, H, W ICR26 [R/W, R] B, H, W ICR27 [R/W, R] B, H, W controller ----1111 ----1111 ----1111 ----1111 00045CH ICR28 [R/W, R] B, H, W ICR29 [R/W, R] B, H, W ICR30 [R/W, R] B, H, W ICR31 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000460H ICR32 [R/W, R] B, H, W ICR33 [R/W, R] B, H, W ICR34 [R/W, R] B, H, W ICR35 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000464H ICR36 [R/W, R] B, H, W ICR37 [R/W, R] B, H, W ICR38 [R/W, R] B, H, W ICR39 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000468H ICR40 [R/W, R] B, H, W ICR41 [R/W, R] B, H, W ICR42 [R/W, R] B, H, W ICR43 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 00046CH ICR44 [R/W, R] B, H, W ICR45 [R/W, R] B, H, W ICR46 [R/W, R] B, H, W ICR47 [R/W, R] B, H, W ----1111 ----1111 ----1111 ----1111 000470H to 00047CH ⎯ Reserved Reserved 000480H RSRR [R/W] B, H, W 10000000 STCR [R/W] B, H, W 00110011 TBCR [R/W] B, H, W 00XXXX00 CTBR [W] B, H, W XXXXXXXX 000484H CLKR [R/W] B, H, W 00000000 WPR [W] B, H, W XXXXXXXX DIVR0 [R/W] B, H, W 00000011 DIVR1 [R/W] B, H, W 00000000 000488H to 0005FCH Interrupt ⎯ Clock control Reserved 000600H PCR0 [R/W] B 00000000 PCR1 [R/W] B 00000000 PCR2 [R/W] B 00000000 PCR3 [R/W] B 00------ 000604H PCR4 [R/W] B 00000000 PCR5 [R/W] B 00000000 PCR6 [R/W] B ----0000 PCR7 [R/W] B 00000000 000608H ⎯ ⎯ ⎯ ⎯ 00060CH ⎯ ⎯ ⎯ ⎯ Pull-up controller (Continued) DS07-16507-3E 31 MB91260B Series Address 000610H Register +0 +1 +2 +3 PCRG [R/W] B --000000 ⎯ ⎯ ⎯ 000614H to 000FFCH ⎯ 001000H DMASA0 [R/W] W 00000000 00000000 00000000 00000000 001004H DMADA0 [R/W] W 00000000 00000000 00000000 00000000 001008H DMASA1 [R/W] W 00000000 00000000 00000000 00000000 00100CH DMADA1 [R/W] W 00000000 00000000 00000000 00000000 001010H DMASA2 [R/W] W 00000000 00000000 00000000 00000000 001014H DMADA2 [R/W] W 00000000 00000000 00000000 00000000 001018H DMASA3 [R/W] W 00000000 00000000 00000000 00000000 00101CH DMADA3 [R/W] W 00000000 00000000 00000000 00000000 001020H DMASA4 [R/W] W 00000000 00000000 00000000 00000000 001024H DMADA4 [R/W] W 00000000 00000000 00000000 00000000 001028H to 006FFCH ⎯ DMAC Reserved FLCR [R/W] 0110X000 ⎯ ⎯ ⎯ 007004H FLWC [R/W] 00000011*2 ⎯ ⎯ ⎯ 007008H ⎯ ⎯ ⎯ ⎯ 00700CH ⎯ ⎯ ⎯ ⎯ 007010H ⎯ ⎯ ⎯ ⎯ ⎯ Pull-up controller Reserved 007000H 007014H to 00BFFCH Block FLASH Reserved (Continued) 32 DS07-16507-3E MB91260B Series (Continued) Address Register +0 +1 +2 00C000H to 00C07CH X-RAM (coefficient RAM) [R/W] 64 × 16 bits 00C080H to 00C0FCH Y-RAM (variable RAM) [R/W] 64 × 16 bits 00C100H to 00C2FCH I-RAM (instruction RAM) [R/W] 256 × 16 bits 00C300H to 00FFFCH ⎯ +3 Block MAC Reserved *1 : The lower 16 bits (DTC15 to DCT0) of DMACA0 to DMACA4 cannot be accessed in bytes. *2 : The initial value of 1FLWC (7004H) is “00010011B” on EVA tool. Writing “00000011B” on the evaluation model has no effect on its operation. Notes : • Do not execute Read Modify Write instructions on registers having a write-only bit. • Data is undefined in reserved or (-) area. DS07-16507-3E 33 MB91260B Series ■ INTERRUPT VECTOR Interrupt number Offset TBR default address RN 10 16 Interrupt level Reset 0 00 ⎯ 3FCH 000FFFFCH ⎯ Mode vector 1 01 ⎯ 3F8H 000FFFF8H ⎯ System reserved 2 02 ⎯ 3F4H 000FFFF4H ⎯ System reserved 3 03 ⎯ 3F0H 000FFFF0H ⎯ System reserved 4 04 ⎯ 3ECH 000FFFECH ⎯ System reserved 5 05 ⎯ 3E8H 000FFFE8H ⎯ System reserved 6 06 ⎯ 3E4H 000FFFE4H ⎯ Coprocessor absent trap 7 07 ⎯ 3E0H 000FFFE0H ⎯ Coprocessor error trap 8 08 ⎯ 3DCH 000FFFDCH ⎯ INTE instruction 9 09 ⎯ 3D8H 000FFFD8H ⎯ Instruction break exception 10 0A ⎯ 3D4H 000FFFD4H ⎯ Operand break trap 11 0B ⎯ 3D0H 000FFFD0H ⎯ Step trace trap 12 0C ⎯ 3CCH 000FFFCCH ⎯ NMI request (tool) 13 0D ⎯ 3C8H 000FFFC8H ⎯ Undefined instruction exception 14 0E ⎯ 3C4H 000FFFC4H ⎯ NMI request 15 0F 15 (FH) fixed 3C0H 000FFFC0H ⎯ External interrupt 0 16 10 ICR00 3BCH 000FFFBCH 6 External interrupt 1 17 11 ICR01 3B8H 000FFFB8H 7 External interrupt 2 18 12 ICR02 3B4H 000FFFB4H ⎯ External interrupt 3 19 13 ICR03 3B0H 000FFFB0H ⎯ External interrupt 4 20 14 ICR04 3ACH 000FFFACH ⎯ External interrupt 5 21 15 ICR05 3A8H 000FFFA8H ⎯ External interrupt 6 22 16 ICR06 3A4H 000FFFA4H ⎯ External interrupt 7 23 17 ICR07 3A0H 000FFFA0H ⎯ Reload timer 0 24 18 ICR08 39CH 000FFF9CH 8 Reload timer 1 25 19 ICR09 398H 000FFF98H 9 Reload timer 2 26 1A ICR10 394H 000FFF94H 10 UART0(Reception completed) 27 1B ICR11 390H 000FFF90H 0 UART0 (RX completed) 28 1C ICR12 38CH 000FFF8CH 3 DTTI 29 1D ICR13 388H 000FFF88H ⎯ DMAC0 (end, error) 30 1E ICR14 384H 000FFF84H ⎯ DMAC1 (end, error) 31 1F ICR15 380H 000FFF80H ⎯ DMAC2/3/4 (end, error) 32 20 ICR16 37CH 000FFF7CH ⎯ Interrupt source (Continued) 34 DS07-16507-3E MB91260B Series Interrupt number 10 16 Interrupt level Offset TBR default address RN UART1(Reception completed) 33 21 ICR17 378H 000FFF78H 1 UART1 (RX completed) 34 22 ICR18 374H 000FFF74H 4 UART2 (Reception completed) 35 23 ICR19 370H 000FFF70H 2 UART2 (RX completed) 36 24 ICR20 36CH 000FFF6CH 5 MAC 37 25 ICR21 368H 000FFF68H ⎯ PPG0 38 26 ICR22 364H 000FFF64H ⎯ PPG1 39 27 ICR23 360H 000FFF60H ⎯ PPG2/3 40 28 ICR24 35CH 000FFF5CH ⎯ PPG4/5/6/7 41 29 ICR25 358H 000FFF58H ⎯ PPG8/9/10/11/12/13/14/15 42 2A ICR26 354H 000FFF54H ⎯ External interrupt 8/9 43 2B ICR27 350H 000FFF50H ⎯ Waveform0 (under flow) 44 2C ICR28 34CH 000FFF4CH ⎯ Waveform1 (under flow) 45 2D ICR29 348H 000FFF48H ⎯ Waveform2 (under flow) 46 2E ICR30 344H 000FFF44H ⎯ Timebase timer overflow 47 2F ICR31 340H 000FFF40H ⎯ Free-run timer (Compare clear) 48 30 ICR32 33CH 000FFF3CH ⎯ Free-run timer (zero detection) 49 31 ICR33 338H 000FFF38H ⎯ A/D0 50 32 ICR34 334H 000FFF34H ⎯ A/D1 51 33 ICR35 330H 000FFF30H ⎯ A/D2 52 34 ICR36 32CH 000FFF2CH ⎯ PWC0 (measurement completed) 53 35 ICR37 328H 000FFF28H ⎯ PWC1 (measurement completed) 54 36 ICR38 324H 000FFF24H ⎯ PWC0 (overflow) 55 37 ICR39 320H 000FFF20H ⎯ PWC1 (overflow) 56 38 ICR40 31CH 000FFF1CH ⎯ ICU0 (capture) 57 39 ICR41 318H 000FFF18H ⎯ ICU1 (capture) 58 3A ICR42 314H 000FFF14H ⎯ ICU2/3 (capture) 59 3B ICR43 310H 000FFF10H ⎯ OCU0/1 (match) 60 3C ICR44 30CH 000FFF0CH ⎯ OCU2/3 (match) 61 3D ICR45 308H 000FFF08H ⎯ OCU4/5 (match) 62 3E ICR46 304H 000FFF04H ⎯ Delay interrupt source bit 63 3F ICR47 300H 000FFF00H ⎯ System reserved (Used by REALOS) 64 40 ⎯ 2FCH 000FFEFCH ⎯ System reserved (Used by REALOS) 65 41 ⎯ 2F8H 000FFEF8H ⎯ Interrupt source (Continued) DS07-16507-3E 35 MB91260B Series (Continued) Interrupt number 10 16 Interrupt level Offset TBR default address RN System reserved 66 42 ⎯ 2F4H 000FFEF4H ⎯ System reserved 67 43 ⎯ 2F0H 000FFEF0H ⎯ System reserved 68 44 ⎯ 2ECH 000FFEECH ⎯ System reserved 69 45 ⎯ 2E8H 000FFEE8H ⎯ System reserved 70 46 ⎯ 2E4H 000FFEE4H ⎯ System reserved 71 47 ⎯ 2E0H 000FFEE0H ⎯ System reserved 72 48 ⎯ 2DCH 000FFEDCH ⎯ System reserved 73 49 ⎯ 2D8H 000FFED8H ⎯ System reserved 74 4A ⎯ 2D4H 000FFED4H ⎯ System reserved 75 4B ⎯ 2D0H 000FFED0H ⎯ System reserved 76 4C ⎯ 2CCH 000FFECCH ⎯ System reserved 77 4D ⎯ 2C8H 000FFEC8H ⎯ System reserved 78 4E ⎯ 2C4H 000FFEC4H ⎯ System reserved 79 4F ⎯ 2C0H 000FFEC0H ⎯ Used by INT instruction 80 to 255 50 to FF ⎯ 2BCH to 000H 000FFEBCH to 000FFC00H ⎯ Interrupt source 36 DS07-16507-3E MB91260B Series ■ PIN STATUS IN EACH CPU STATE Terms used as the status of pins mean as follows. • Input enabled • Indicates that the input function can be used. • Input 0 fixed • Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released. • Output Hi-Z • Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving. • Output is maintained. • Indicates the output in the output state existing immediately before this mode is established. • If the device enters this mode with an internal output peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. • State existing immediately before is maintained. • When the device serves for output or input immediately before entering this mode, the device maintains the output or is ready for the input, respectively. DS07-16507-3E 37 MB91260B Series • List of pin status (single chip mode) Pin no. Pin name Function QFP LQFP 1 99 P23 SIN1 2 100 P24 SOT1 3 1 P25 SCK1 4, 5 2, 3 P26, P27 INT6, INT7 6 4 P50 Port 7 to 9 5 to 7 P51 to P53 TIN0 to TIN2 10 8 P54 INT0 11 9 P55 INT1 12 10 P56 INT2 13 11 P57 INT3 14 12 PG0 CKI/INT4 15 13 PG1 16 14 PG2 20 18 PG3 21 19 PG4 SOT2 22 20 PG5 SCK2 23 to 30 21 to 28 P40 to P47 INIT = H*2 At Stop mode HIZ = 0 HIZ = 1 Retention Retention of the of the Output Hi-Z/ immediately immediately Input 0 fixed prior state prior state Input enabled Input enabled Input enabled Retention Retention of the of the Output Hi-Z/ immediately immediately Input 0 fixed prior state prior state Input enabled Input enabled Input enabled Ports 29, 30 PE1, PE0 AN11, AN10 38, 39 36, 37 PD1, PD0 AN9, AN8 PC7 to PC0 AN7 to AN0 51 to 56 49 to 54 P30 to P35 INIT = L*1 At sleep mode PPG0/INT5 Output Hi-Z/ Output Hi-Z/ Input Input Ports enabled disabled SIN2 31, 32 41 to 48 39 to 46 At initializing Retention Retention of the Output Hi-Z/ of the immediately immediately Input 0 fixed prior state prior state RTO0 to RTO5 57, 58 55, 56 P36, P37 IC0, IC1 59, 60 57, 58 P60, P61 IC2, IC3 61, 62 59, 60 P62, P63 INT8, INT9 Input enabled Input enabled Input enabled (Continued) 38 DS07-16507-3E MB91260B Series (Continued) P : Selection of general purpose port, F : Selection of specified function At initializing Pin no. At sleep Pin Function mode name QFP LQFP INIT = L*1 INIT = H*2 63, 64 61, 62 P70, P71 At Stop mode HIZ = 0 HIZ = 1 TOT1, TOT2 65 63 P72 DTTI 66 64 P73 PWI0 69 67 P74 PWI1 70 68 P75 ADTG0 71 69 P76 ADTG1 72 70 P77 ADTG2 73 71 NMI NMI 78 76 P00 PPG1 79 77 P01 PPG2 80 78 P02 PPG3 81 79 P03 PPG4 82 80 P04 PPG5 83 81 P05 PPG6 84 82 P06 PPG7 85 83 P07 PPG8 86 84 P10 PPG9 87 85 P11 PPG10 88 86 P12 PPG11 89 87 P13 PPG12 90 88 P14 PPG13 91 89 P15 PPG14 96 94 P16 PPG15 97 95 P17 Ports 98 96 P20 SIN0 99 97 P21 SOT0 100 98 P22 SCK0 Retention Retention Output Hi-Z/ Output Hi-Z/ of the of the Output Hi-Z/ input disabled input enabled immediately immediately Input 0 fixed prior state prior state Input enabled Input enabled Input enabled Input enabled Input enabled Retention Retention Output Hi-Z/ of the of the Output Hi-Z/ output Hi-Z/ input disabled input enabled immediately immediately input 0 fixed prior state prior state *1 : INIT = L : Indicates the pin status with INIT remaining at the “L” level. *2 : INIT = H : Indicates the pin status existing immediately after INIT transition from “L” to “H” level. DS07-16507-3E 39 MB91260B Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max VCC VSS − 0.5 VSS + 6.0 V AVCC VSS − 0.5 VSS + 6.0 V *2 AVRH VSS − 0.5 VSS + 6.0 V *2 VI VSS − 0.3 VCC + 0.3 V VIA VSS − 0.3 AVcc + 0.3 V VO VSS − 0.3 VCC + 0.3 V IOL ⎯ 10 mA *3 "L" level average output current IOLAV ⎯ 8 mA *4 "L" level total maximum output current ΣIOL ⎯ 100 mA ΣIOLAV ⎯ 50 mA *5 IOH ⎯ − 10 mA *3 "H" level average output current IOHAV ⎯ −4 mA *4 "H" level total maximum output current ΣIOH ⎯ − 50 mA ΣIOHAV ⎯ − 20 mA Power supply voltage*1 Analog power supply voltage* 1 Analog reference voltage*1 Input voltage*1 Analog pin input voltage*1 Output voltage* 1 "L" level maximum output current "L" level total average output current "H" level maximum output current "H" level total average output current 600 Power consumption PD ⎯ 600 FLASH product mW Storage temperature − 40 + 105 °C MASK product (at single chip operating) − 40 + 85 °C FLASH product (at single chip operating) − 55 125 °C Ta Tstg MASK product Ta ≤ + 85 °C MASK product Ta ≤ + 105 °C *6 360 Operating temperature *5 *1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : Be careful not to exceed VCC + 0.3 V, for example, when the power is turned on. Be careful not to let AVCC exceed VCC, for example, when the power is turned on. *3 : The maximum output current is the peak value for a single pin. *4 : The average output current is the average current for a single pin over a period of 100 ms. *5 : The total average output current is the average current for all pins over a period of 100 ms. *6 : For use at Ta = +105 °C, lower the operating frequency to reduce power consumption. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 40 DS07-16507-3E MB91260B Series 2. Recommended Operating Conditions (Vss = AVss = 0 V) Parameter Symbol Value Min Max Unit Remarks Power supply voltage VCC 4.0 5.5 V Analog power supply voltage AVCC VSS + 4.0 VSS + 5.5 V AVRH0 AVSS AVCC V For A/D converter 0 AVRH1 AVSS AVCC V For A/D converter 1 AVRH2 AVSS AVCC V For A/D converter 2 − 40 + 105 °C MASK product (at single chip operation) − 40 + 85 °C FLASH product (at single chip operation) Analog reference voltage Operating temperature Ta At normal operating Note : Upon power up, it takes approx. 100 µs for stabilization of internal power supply after the VCC power supply is stabilized. Keep applying “L” to INIT signal during that period. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-16507-3E 41 MB91260B Series 3. DC Characteristics (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Parameter "H" level input voltage Input Low Voltage "H" level output voltage Output Low Voltage Input leak current Pull-up resistance Sym bol Pin Conditions VIH Other than hysteresis input pin VIHS Input capacitance 42 Unit Remarks Min Typ Max ⎯ 0.8 × Vcc ⎯ Vcc V Hysteresis input pin ⎯ Vcc − 0.4 ⎯ Vcc V VIL Other than hysteresis input pin ⎯ Vss ⎯ 0.2 × Vcc V VILS Hysteresis input pin ⎯ Vss ⎯ Vss + 0.4 V VOH Other than P30 to VCC = 5.0 V, P35 IOH = 4.0 mA Vcc − 0.5 ⎯ ⎯ V VCC = 5.0 V, IOH = 8.0 mA Vcc − 0.7 ⎯ ⎯ V Other than P30 to VCC = 5.0 V, P35 IOL = 4.0 mA ⎯ ⎯ 0.4 V VCC = 5.0 V, IOL = 12 mA ⎯ ⎯ 0.6 V VCC = 5.0 V, VSS ≤ VI ≤ VCC −5 ⎯ 5 µA ⎯ ⎯ 50 ⎯ kΩ VCC VCC = 5.0 V, 33 MHz ⎯ 90 100 mA ICCS VCC VCC = 5.0 V, 33 MHz ⎯ 60 80 mA At SLEEP ICCH VCC VCC = 5.0 V, Ta = + 25 °C ⎯ 300 ⎯ µA ⎯ 10 ⎯ pF VOH2 P30 to P35 VOL VOL2 P30 to P35 ⎯ ILI RPULL ICC Power supply current Value CIN INIT, Pull-up pin Other than VCC, VSS, AVCC, AVSS, AVRH0, 1, 2 ⎯ At STOP DS07-16507-3E MB91260B Series 4. FLASH MEMORY write/erase characteristics Parameter Conditions Sector erase time Value Unit Remarks Min Typ Max Ta = + 25 °C, Vcc = 5.0 V ⎯ 1 15 s Not including time for internal writing before deletion. Chip erase time Ta = + 25 °C, Vcc = 5.0 V ⎯ 10 ⎯ s Not including time for internal writing before deletion. Byte write time Ta = + 25 °C, Vcc = 5.0 V ⎯ 8 3,600 µs Not including system-level overhead time. Chip write time Ta = + 25 °C, Vcc = 5.0 V ⎯ 2.1 ⎯ s Not including system-level overhead time. ⎯ 10,000 ⎯ ⎯ cycle 20 ⎯ ⎯ year Erase/write cycle Flash memory data retention time Average Ta = + 85 °C * * : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) DS07-16507-3E 43 MB91260B Series 5. AC Characteristics (1) Clock Timing Ratings (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Sym bol Pin fC X0 X1 Clock cycle time tC X0 X1 Internal operating clock frequency fCP Parameter Clock frequency Internal operating clock cycle time fCPP ⎯ tCP tCPP ⎯ Conditions Value Unit Remarks Min Typ Max 3.6*2 ⎯ 12 MHz 83.3 ⎯ 278*2 ns ⎯ 33 MHz CPU ⎯ 33 MHz Peripheral ⎯ 485*1 ns CPU ⎯ 485*1 ns Peripheral ⎯ When 4.125 MHz is 2.06*1 input as the X0 2.06*1 clock frequency and 30.3 ×8 multiplication is set for the PLL of the oscillator circuit. 30.3 For using the PLL within the self-oscillation enabled range, set the multiplier for the internal clock not to let the operating frequency exceed 33 MHz. *1 : The values assume a gear cycle of 1/16. *2 : When the PLL is used, the lower-limit frequency of the input clock to the X0 and X1 pins determines depending on the PLL multiplication. At × 1 multiplication : more than 8 MHz At × 2 to × 8 multiplication : more than 4 MHz • Conditions for measuring the clock timing ratings tC 0.8 VCC 0.2 VCC C = 50 pF PWL PWH tCF 44 Output pin tCR DS07-16507-3E MB91260B Series • Operation Assurance Range Power supply VCC (V) 5.5 4.0 0 0.25 33 fCP / fCPP (MHz) Internal clock • Internal clock setting range (MHz) CPU (CLKB) : Internal clock 33 Peripheral (CLKP) : 16.5 Oscillation input clock fC = 4.192 MHz (PLL multiplied by 8) 4.125 8:8 4:4 1:1 CPU : Divided ratio for peripherals. Notes : • Oscillation stabilization time of PLL > 600 µs • The internal clock gear setting should be within the value shown in clock timing ratings table. DS07-16507-3E 45 MB91260B Series (2) Reset Input (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Parameter INIT input time (at power-on and STOP mode) INIT input time (other than the above) Symbol tINTL Pin INIT Value Conditions ⎯ Unit Min Max Oscillation time of oscillator + tC × 10 ⎯ ns tC × 10 ⎯ ns Remarks * * : After the power is stable, L level is kept inputting to INIT for the duration of approximately 100 µs until the internal power is stabilized. tINTL INIT 0.2 VCC 46 DS07-16507-3E MB91260B Series (3) UART Timing (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Pin Serial clock cycle time tSCYC SCK ↓ → SOT delay time Conditions Value Unit Remarks Min Max SCK0 to SCK2 8 tCYCP ⎯ ns tSLOV SCK0 to SCK2, SOT0 to SOT2 − 80 80 ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK2, SIN0 to SIN2 100 ⎯ ns SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK2, SIN0 to SIN2 60 ⎯ ns Serial clock H pulse width tSHSL SCK0 to SCK2 4 tCYCP ⎯ ns Serial clock L pulse width tSLSH SCK0 to SCK2 4 tCYCP ⎯ ns SCK ↓ → SOT delay time tSLOV SCK0 to SCK2, SOT0 to SOT2 ⎯ 150 ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK2, SIN0 to SIN2 60 ⎯ ns SCK ↑ → valid SIN hold time tSHIX SCK0 to SCK2, SIN0 to SIN2 60 ⎯ ns Internal shift clock mode External shift clock mode Notes : • There are the AC ratings for CLK synchronous mode. • tCYCP indicates the peripheral clock cycle time. DS07-16507-3E 47 MB91260B Series • Internal shift clock mode tSCYC SCK0 to SCK2 VOH VOL VOL tSLOV VOH VOL SOT0 to SOT2 tIVSH tSHIX VOH VOL SIN0 to SIN2 VOH VOL • External shift clock mode tSLSH tSHSL VOH SCK0 to SCK2 VOL VOL VOL tSLOV SOT0 to SOT2 VOH VOL tIVSH SIN0 to SIN2 48 VOH VOL tSHIX VOH VOL DS07-16507-3E MB91260B Series (4) Free-run Timer Clock, PWC Input and Reload Timer Trigger Timing (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Pin Conditions Input pulse width tTIWH tTIWL CKI PWI0, PWI1 TIN0 to TIN2 ⎯ Value Min Max 4 tCYCP ⎯ Unit Remarks ns Note : tCYCP indicates the peripheral clock cycle time. tTIWH DS07-16507-3E tTIWL 49 MB91260B Series (5) Trigger Input Timing (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V) Parameter Input capture trigger input A/D activation trigger input Symbol Pin Conditions tINP IC0 to IC3 tATGX ADTG0 to ADTG2 Value Unit Min Max ⎯ 5 tCYCP ⎯ ns ⎯ 5 tCYCP ⎯ ns Remarks Note : tCYCP indicates the peripheral clock cycle time. tATGX, tINP IC0 to IC3 ADTG0 to ADTG2 50 DS07-16507-3E MB91260B Series 6. Electrical Characteristics for the A/D Converter (VCC = AVcc = 5.0 V, VSS = AVSS = 0 V) Symbol Pin Resolution ⎯ Total error*1 Parameter Value Unit Min Typ Max ⎯ ⎯ ⎯ 10 bit ⎯ ⎯ −4 ⎯ 4 LSB Linearity error* ⎯ ⎯ − 3.5 ⎯ 3.5 LSB Differential linearity error*1 ⎯ ⎯ −3 ⎯ 3 LSB Zero transition voltage*1 VOT AN0 to AN11 Full transition voltage*1 VFST AN0 to AN11 AVRH − 5.5 LSB AVRH − 1.5 LSB AVRH + 2.5 LSB V Conversion time ⎯ ⎯ 1.2*2 ⎯ ⎯ µs Analog port Input current IAIN AN0 to AN11 ⎯ ⎯ 10 µA Analog input voltage VAIN AN0 to AN11 AVss ⎯ AVRH V Reference voltage ⎯ AVRHn AVss ⎯ AVcc V Analog power supply current (analog + digital) IA ⎯ 2 ⎯ ⎯ ⎯ 100 ⎯ 1 ⎯ ⎯ ⎯ 100 µA reference power supply current (between AVRH and AVSS) IAH*3 AVss − 3.5 AVss + 0.5 AVss + 4.5 LSB LSB LSB AVcc IR AVRHn IRH*3 Remarks At AVRHn*4 = 5.0 V V mA Per 1 unit µA Per 1 unit Per 1 unit mA AVRHn*4 = 5.0 V, at AVss = 0 V Analog input capacitance ⎯ ⎯ ⎯ 10 ⎯ pF Inter-channel disparity ⎯ AN0 to AN11 ⎯ ⎯ 4 LSB per 1 unit at STOP *1 : Measured in the CPU sleep state *2 : Vcc = AVcc = 5.0 V, peripheral clock at 33 MHz *3 : The current when the CPU is in stop mode and the A/D converter is not operating (at Vcc = AVcc = AVRHn = 5.0 V) *4: AVRHn = AVRH0, AVRH1, AVRH2 Notes : • The above does not guarantee the inter-unit accuracy. • Set the output impedance of the external circuit ≤ 2 kΩ. DS07-16507-3E 51 MB91260B Series • About the external impedance of the analog input and its sampling time A/D converter with sample & hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D conversion precision. So, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input circuit model R Comparator Analog input C During sampling : ON MB91263B MB91264B MB91F264B R C 2.0 kΩ (Max) 14.4 pF (Max) 2.0 kΩ (Max) 14.4 pF (Max) 2.0 kΩ (Max) 16.0 pF (Max) Note : The values are reference values. • The relationship between the external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ) 20 90 MB91263B MB91264B 80 External impedance (kΩ) External impedance (kΩ) 100 70 60 MB91F264B 50 40 30 20 10 0 0 2 4 6 8 Minimum sampling time (µs) 10 18 MB91263B MB91264B 16 14 MB91F264B 12 10 8 6 4 2 0 0 1 2 3 Minimum sampling time (µs) • About errors As |AVRH − AVSS| becomes smaller, values of relative errors grow larger. 52 DS07-16507-3E MB91260B Series Definition of A/D Converter Terms • Resolution : Analog variation that is recognized by an A/D converter. • Linearity error : Zero transition point (00 0000 0000 ←→ 00 0000 0001) and full-scale transition point. Difference between the line connected (11 1111 1110 ←→ 11 1111 1111) and actual conversion characteristics. • Differential linearity error : Deviation of input voltage, that is required for changing output code by 1 LSB, from an ideal value. • Total error : This error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error. Total error 3FFH Digital output 1.5 LSB' Actual conversion characteristics 3FEH 3FDH {1 LSB' (N − 1) + 0.5 LSB'} 004H VNT (measurement value) 003H Actual conversion characteristics 002H Ideal characteristics 001H 0.5 LSB' AVSS AVRH Analog input 1LSB’ (Ideal value) = AVRH − AVSS 1024 [V] Total error of digital output N = VNT − {1 LSB’ × (N − 1) + 0.5 LSB’} 1 LSB’ VOT’ (Ideal value) = AVSS + 0.5 LSB’ [V] VFST’ (Ideal value) = AVRH − 1.5 LSB’ [V] VNT : A voltage at which digital output transitions from (N + 1) to N. (Continued) DS07-16507-3E 53 MB91260B Series (Continued) Linearity error 3FFH Actual conversion characteristics 3FEH Actual conversion characteristics N+1 {1 LSB (N − 1) + VOT} 3FDH Ideal characteristics VFST (measurement value) Digital output Digital output Differential linear error 004H VNT 003H (measurement value) 002H Actual conversion characteristics Ideal characteristics N N−1 VFST (measurement value) VNT (measurement value) N−2 001H Actual conversion characteristics V0T (measurement Value) AVSS AVSS AVRH Analog input AVRH Analog input Linearity error in digital output N = Differential linearity error in digital output N = 1 LSB = VNT − { 1 LSB × (N − 1) + VOT } 1 LSB V (N + 1) T − VNT 1 LSB VFST − VOT 1022 −1 [LSB] [LSB] [V] VOT : A voltage at which digital output transitions from 000H to 001H. VFST : A voltage at which digital output transitions from 3FEH to 3FFH . 54 DS07-16507-3E MB91260B Series ■ EXAMPLE CHARACTERISTICS “L” Level Output Voltage vs. “H” Level Output Voltage vs. Power Supply Voltage Power Supply Voltage 6 400 5 350 300 VOL (mV) VOH (V) 4 3 2 250 200 150 1 100 50 0 4.0 4.5 5.0 5.5 0 4.0 VCC (V) 4.5 5.0 5.5 VCC (V) Pull-up Resistor vs. Power Supply Voltage Power Supply Current vs. Power Supply Voltage 80 100 70 90 80 70 50 ICC (mA) R (kΩ) 60 40 30 60 50 40 30 20 20 10 10 0 4.0 4.5 5.0 0 4.0 5.5 VCC (V) 4.5 5.0 5.5 VCC (V) Power Supply Current vs. Internal Operation Frequency (MB91263B) 100 90 80 ICC (mA) 70 Power supply voltage 4.0 V 4.5 V 5.0 V 5.5 V 60 50 40 30 20 10 0 15 20 25 30 35 Internal operation frequency [MHz] (Continued) DS07-16507-3E 55 MB91260B Series (Continued) Power Supply Current (at sleep) vs. Power Supply Voltage Power Supply Current (at stop) vs. Power Supply Voltage 100 80 90 70 80 70 ICCH (µA) ICCS (mA) 60 50 40 60 50 40 30 30 20 20 10 10 0 4.0 4.5 5.0 0 4.0 5.5 4.5 VCC (V) A/D Conversion Block Per 1 Unit (33 MHz) Analog Power Supply Current vs. Power Supply Voltage A/D Conversion Block Per 1 Unit (33 MHz) Reference Power Supply Current vs. Power Supply Voltage 2 1.0 0.8 IR (mA) IA (mA) 1.5 1 0.5 0.6 0.4 0.2 0 4.0 4.5 0.0 4.0 5.5 5.0 4.5 (External impedance = 0 kΩ to 100 kΩ) 20 90 MB91263B MB91264B 80 External impedance (kΩ) External impedance (kΩ) 5.5 (External impedance = 0 kΩ to 20 kΩ) 100 70 60 MB91F264B 50 40 30 20 10 0 2 4 6 8 Minimum sampling time (µs) 56 5.0 VCC (V) VCC (V) 0 5.5 5.0 VCC (V) 10 18 MB91263B MB91264B 16 14 MB91F264B 12 10 8 6 4 2 0 0 1 2 3 Minimum sampling time (µs) DS07-16507-3E MB91260B Series ■ ORDERING INFORMATION Part number Package Remarks MB91F264BPF-GE1 100-pin plastic QFP (FPT-100P-M06) Lead-free Package MB91F264BPMC-GE1 100-pin plastic LQFP (FPT-100P-M20) Lead-free Package MB91264BPF-G-xxxE1 100-pin plastic QFP (FPT-100P-M06) Lead-free Package MB91264BPMC-G-xxxE1 100-pin plastic LQFP (FPT-100P-M20) Lead-free Package MB91263BPF-G-xxxE1 100-pin plastic QFP (FPT-100P-M06) Lead-free Package MB91263BPMC-G-xxxE1 100-pin plastic LQFP (FPT-100P-M20) Lead-free Package DS07-16507-3E 57 MB91260B Series ■ PACKAGE DIMENSIONS 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 50 81 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 31 100 1 30 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M 0.17±0.06 (.007±.002) "A" ©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6 C 2002 FUJITSU LIMITED F100008S-c-5-5 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 58 DS07-16507-3E MB91260B Series (Continued) 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.0 mm × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.65 g Code (Reference) P-LFQFP100-14×14-0.50 (FPT-100P-M20) 100-pin plastic LQFP (FPT-100P-M20) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 26 100 1 25 C 0.20±0.05 (.008±.002) 0.08(.003) M 0.10±0.10 (.004±.004) (Stand off) 0°~8° "A" 0.50(.020) +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.145±0.055 (.0057±.0022) 2005 -2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-3-3 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ DS07-16507-3E 59 MB91260B Series ■ MAIN CHANGES IN THIS EDITION Page Section ⎯ ⎯ 38 ■ PIN STATUS IN EACH CPU STATE • List of pin status (Single chip mode) Corrected the pin name. 6pin(QFP), 4pin(LQFP) : P51 → P50 7pin(QFP), 5pin(LQFP) : P50 → P51 ■ ELECTRICAL CHARACTERISTICS 6. Electrical Characteristics for the A/D Converter Changed the items of “Zero transition voltage” and “Full transition voltage”. Unit : LSB → V Value: AVSS/AVRH ± value → AVSS/AVRH ± value LSB 51 Change Results Changed the package code. FPT-100P-M05 → FPT-100P-M20 Changed the name of operating clock. machine clock → peripheral clock ■ ORDERING INFORMATION Changed the order informations. MB91F264BPFV-GE1 → MB91F264BPMC-GE1 MB91264BPFV-G-xxxE1 → MB91264BPMC-G-xxxE1 MB91263BPFV-G-xxxE1 → MB91263BPMC-G-xxxE1 ■ PACKAGE DIMENSIONS Changed the package figure. FPT-100P-M05 → FPT-100P-M20 57 59 The vertical lines marked in the left side of the page show the changes. 60 DS07-16507-3E MB91260B Series MEMO DS07-16507-3E 61 MB91260B Series MEMO 62 DS07-16507-3E MB91260B Series MEMO DS07-16507-3E 63 MB91260B Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. 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