FUJITSU MB95F118AS

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12602-1E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95110A Series
MB95116A/F118AS/F118AW/FV100A-101
■ DESCRIPTION
The MB95110A series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
■ FEATURES
• F2MC-8FX CPU core
Instruction set that is optimum to the controllers
• Multiplication and division instructions
• 16-bit arithmetic operation
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Subclock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
■ PACKAGES
48-pin plastic BCC
48-pin plastic-LQFP
(LCC-48P-M09)
(FPT-48P-M26)
MB95110A Series
(Continued)
• Timer
• 8/16-bit compound timer × 2 channels
• 8/16-bit PPG × 2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler (for dual clock product)
• LIN-UART
• Full duplex double buffer
• Clock asynchronous or synchronous serial transfer capable
• UART/SIO
• Clock asynchronous or synchronous serial transfer capable
2C*
•I
• Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption modes.
• 10-bit A/D converter
• 10-bit resolution
• Low-power consumption (standby mode)
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
• I/O port: Max 40
• General-purpose I/O ports (Nch open drain) : 2 ports
• General-purpose I/O ports (CMOS)
: 38 ports
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
2
MB95110A Series
■ PRODUCT LINEUP
Part number
Parameter
Type
MB95116A
MASK product
ROM capacity
32 Kbytes
RAM capacity
1 Kbytes
MB95F118AS
Peripheral functions
CPU functions
MB95FV100A-101
FLASH product
EVA product
60 Kbytes
2 Kbytes
Reset output
Option
MB95F118AW
3.75 Kbytes
No
Selectable
single/dual
-system*2
Single-system
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
Dual-system
Selectable
single/dual
-system*1
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 0.1 µs (at internal 10 MHz)
: 0.9 µs (at internal 10 MHz)
Ports
(Max 40 ports)
General-purpose I/O port (Nch open drain)
General-purpose I/O port (CMOS)
: 2 ports
: 38 ports
Timebase timer
Interrupt cycle : 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer
Reset generated cycle
At main oscillation clock 10 MHz
: Minimum 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Minimum 250 ms
Wild register
Capable of replacing 3 bytes of data
I2C bus
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator
Transfer rate : 2400 bps to 125000 bps (at machine clock 10 MHz)
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock synchronous (SIO) or clock asynchronous (UART) data transfer capable
LIN-UART
Dedicated reload timer allowing a wide range of communication speeds to be set.
Capable of data transfer synchronous or asynchronous to clock signal.
LIN functions available as the LIN master or LIN slave.
A/D converter
(8 channels)
8-bit or 10-bit resolution can be selected.
8/16-bit
compound timer
(2 channels)
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer ×
1 channel”.
Built-in timer function, PWC function, PWM function, capture function and square
waveform output
Count clock : 7 internal clocks and external clock can be selected.
(Continued)
3
MB95110A Series
(Continued)
Part number
Peripheral functions
Parameter
MB95116A
MB95F118AW
MB95FV100A-101
16-bit PPG
PWM mode or one-shot mode can be selected.
Counter operating clock : Eight selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×
1 channel”.
Counter operating clock : Eight selectable clock sources
Watch counter
Count clock : Four selectable clock sources (125ms, 250ms, 500ms, or 1s)
(for dual clock product) Counter value can be set from 0 to 63. (Capable of counting for 1 minute)
Watch prescaler
Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
(for dual clock product)
External interrupt
(8 channels)
Standby mode
Interrupt by edge detection (rising, falling, or both edges can be selected)
Can be used to recover from standby modes.
Sleep, stop, watch, and timebase timer
*1 : Change by the switch on MCU board.
*2 : Specify clock mode when ordering MASK ROM.
4
MB95F118AS
MB95110A Series
■ SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK PRODUCT ONLY)
For the MASK product, you can set the mask option when ordering MASK ROM to select the initial value of main
clock oscillation stabilization wait time from among the following four values.
Note that the EVA and FLASH products are fixed their initial value of main clock oscillation stabilization wait time
at the maximum value.
Selection of oscillation stabilization wait time
Remarks
(22 − 2) /FCH
0.5 µs (at main oscillation clock 4 MHz)
(212 − 2) /FCH
Approx. 1.02 ms (at main oscillation clock 4 MHz)
(2 − 2) /FCH
Approx. 2.05 ms (at main oscillation clock 4 MHz)
(2 − 2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
13
14
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95116A
MB95F118AS
MB95F118AW
MB95FV100A-101
Package
LCC-48P-M09
FPT-48P-M26
BGA-224P-M08
: Available
: Unavailable
5
MB95110A Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using EVA Products
The EVA product has not only the functions of the MB95110A series but also those of other products to support
software development for multiple series and products of F2MC-8FX family. The I/O addresses for peripheral
resources not used by the MB95110A series are therefore access-barred. Read/write access to these accessbarred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected
malfunctions of hardware or software.
Take particular care not to use word, long word, or similar access to read or write odd numbered bytes in the
prohibited areas.
Note that the values read from barred addresses are different between the EVA product and the FLASH or MASK
product. Therefore, the data must not be used for software processing.
The EVA product does not support the functions of some bits in single-byte registers. Read/write access to these
bits does not cause hardware malfunctions. Since the EVA, FLASH, and MASK products are designed to behave
completely the same way in terms of hardware and software, you do not have to pay special attention to specific
products.
• Difference of Memory Spaces
If the amount of memory on the EVA product is different from that of the FLASH or MASK product, carefully
check the difference in the amount of memory from the product to be actually used when developing software.
• Current Consumption
• The current consumption of FLASH product is typically greater than for MASK product.
• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage are different among the EVA, FLASH and MASK products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”
• Difference between RST and MOD pins
The RST and MOD pins are hysteresis inputs on the MASK product. A pull-down resistor is provided for the
MOD pin of the MASK product.
6
MB95110A Series
P64/EC1
P63/TO11
P62/TO10
P61/PPG11
P60/PPG10
P15
P14/PPG0
P13/TRG0/ADTG
P12/UCK0
P11/UO0
P10/UI0
P07/INT07
■ PIN ASSIGNMENTS
48
47
46
45
44
43
42
41
40
39
38
37
P65/SCK
1
P66/SOT
2
36
P06/INT06
P67/SIN
3
35
P05/INT05
P37/AN07
4
34
P04/INT04
P36/AN06
5
33
P03/INT03
P35/AN05
6
32
P02/INT02
P34/AN04
7
31
P01/INT01
P33/AN03
8
30
P00/INT00
P32/AN02
9
29
RST
P31/AN01
10
28
PG1/X0A
P30/AN00
11
27
PG2/X1A
AVss
12
26
PG0
25
Vcc
13
14
15
16
17
18
19
20
21
22
23
24
AVcc
P24/EC0
P23/TO01
P22/TO00
P21/PPG01
P20/PPG00
P51/SDA0
P50/SCL0
MOD
X0
X1
Vss
TOP VIEW
(LCC-48P-M09)
7
P07/INT07
P10/UI0
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P15
P60/PPG10
P61/PPG11
P62/TO10
P63/TO11
P64/EC1
MB95110A Series
48 47 46 45 44 43 42 41 40 39 38 37
P65/SCK
1
36
P06/INT06
P66/SOT
2
35
P05/INT05
P67/SIN
3
34
P04/INT04
P37/AN07
4
33
P03/INT03
P36/AN06
5
32
P02/INT02
P35/AN05
6
31
P01/INT01
P34/AN04
7
30
P00/INT00
P33/AN03
8
29
RST
P32/AN02
9
28
PG1/X0A
P31/AN01
10
27
PG2/X1A
P30/AN00
11
26
PG0
AVss
12
25
Vcc
TOP VIEW
(FPT-48P-M26)
8
X1
Vss
X0
MOD
P50/SCL0
P51/SDA0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
AVcc
P24/EC0
13 14 15 16 17 18 19 20 21 22 23 24
MB95110A Series
■ PIN DESCRIPTION
Pin no.
Pin name
1
P65/SCK
2
P66/SOT
3
P67/SIN
4
P37/AN07
5
P36/AN06
6
P35/AN05
7
P34/AN04
8
P33/AN03
9
P32/AN02
10
P31/AN01
11
P30/AN00
12
Circuit type
K
Description
General-purpose I/O port.
The pin is shared with LIN-UART clock I/O.
General-purpose I/O port.
The pin is shared with LIN-UART data output.
L
General-purpose I/O port.
The pin is shared with LIN-UART data input.
J
General-purpose I/O port.
The pins are shared with A/D analog input.
AVss
⎯
A/D power supply pin (GND)
13
AVcc
⎯
A/D power supply pin
14
P24/EC0
15
P23/TO01
16
P22/TO00
17
P21/PPG01
18
P20/PPG00
19
P51/SDA0
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch0 clock input.
H
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch0 output.
I
20
P50/SCL0
21
MOD
22
X0
23
X1
24
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch0 output.
General-purpose I/O port.
The pin is shared with I2C ch0 data I/O.
General-purpose I/O port.
The pin is shared with I2C ch0 clock I/O.
B
Operating mode designation pin
A
Crystal oscillation pin
Vss
⎯
Power supply pin (GND)
25
Vcc
⎯
Power supply pin
26
PG0
H
General-purpose I/O port.
27
PG2/X1A
28
PG1/X0A
29
RST
H/A
B’
Single-system product is general-purpose port.
Dual-system product is Crystal oscillation pin (32 kHz).
Reset pin
(Continued)
9
MB95110A Series
10
(Continued)
Pin no.
Pin name
30
P00/INT00
31
P01/INT01
32
P02/INT02
33
P03/INT03
34
P04/INT04
35
P05/INT05
36
P06/INT06
37
P07/INT07
38
P10/UI0
39
P11/UO0
40
P12/UCK0
41
P13/TRG0/
ADTG
42
P14/PPG0
43
P15
44
P60/PPG10
45
P61/PPG11
46
P62/TO10
47
P63/TO11
48
P64/EC1
Circuit type
Description
C
General-purpose I/O port.
The pins are shared with external interrupt input. Large current port.
G
General-purpose I/O port.
The pin is shared with UART/SIO ch0 data input.
General-purpose I/O port.
The pin is shared with UART/SIO ch0 data output.
General-purpose I/O port.
The pin is shared with UART/SIO ch0 clock I/O.
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch0 trigger input (TRG0) and A/D
trigger input (ADTG).
General-purpose I/O port.
The pin is shared with 16-bit PPG ch0 output.
General-purpose I/O port.
General-purpose I/O port.
The pins are shared with 8/16-bit PPG ch1 output.
K
General-purpose I/O port.
The pins are shared with 8/16-bit compound timer ch1 output.
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch1 clock input.
MB95110A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation circuit
• High-speed side
Feedback resistance value : approx. 1 MΩ
• Low-speed side
Feedback resistance : approx. 24 MΩ
(EVA product : approx. 10 MΩ)
Dumping resistance : approx. 144 kΩ
(EVA product : without dumping resistance)
X1 (X1A)
A
X0 (X0A)
Standby control
B
• Only for input
• Hysteresis input only for MASK product
• With pull-down resistor only for MASK
product
R
• Hysteresis input only for MASK product
B’
• CMOS output
• Hysteresis input
Pch
C
Nch
Standby control
External
interrupt enable
Pull-up control
R
Pch
•
•
•
•
CMOS output
CMOS input
Hysteresis input
With pull-up control
G
Nch
Standby control
(Continued)
11
MB95110A Series
(Continued)
Type
Circuit
R
Remarks
Pull-up control
• CMOS output
• Hysteresis input
• With pull-up control
Pch
H
Nch
Standby control
• Nch open drain output
• CMOS input
• Hysteresis input
Nch
I
Standby control
Pull-up control
R
Pch
J
•
•
•
•
CMOS output
Hysteresis input
Analog input
With pull-up control
Nch
Analog input
A/D control
Standby control
Pch
K
• CMOS output
• Hysteresis input
Nch
Standby control
Pch
Nch
L
Standby control
12
• CMOS output
• CMOS input
• Hysteresis input
MB95110A Series
■ HANDLING DEVICES
• Preventing Latchup
Care must be taken to ensure that maximum voltage ratings are not exceeded when it is used.
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the
digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the Vcc power-supply voltage.
For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range
(50 Hz to 60 Hz) not to exceed 10% of the Vcc value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Treatment of Unused Input Pin
An unused input pin may cause a malfunction if it is left open. It should be connected to a pull-up or pull-down
resistor.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
• Precaution against Noise to the External Reset Pin (RST)
An input of a reset pulse below the specified level to the external reset pin (RST) may cause malfunctions. Be
sure not to allow an input of a reset pulse below the specified level to the external reset pin (RST).
13
MB95110A Series
■ PROGRAMMING FLASH MICROCONTROLLERS USING PARALLEL PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-48P-M26
TEF110-108F37AP
LCC-48P-M09
TEF100-108F41AP
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
Notes: • Set all of the J1 to J3 switches on the adapter to "95F108".
• For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: 053-428-8380
• Sector Configuration
The individual sectors of flash memory correspond to addresses used for CPU access and programming by the
parallel programmer as follows:
Flash memory
CPU address
Writer address*
1000H
71000H
1FFFH
2000H
71FFFH
72000H
2FFFH
3000H
72FFFH
73000H
3FFFH
4000H
73FFFH
74000H
7FFFH
8000H
77FFFH
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA2 (4 Kbytes)
Lower bank
SA1 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
Upper bank
SA5 (16 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs
data into flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in flash memory.
• Programming Method
1) Set the type code of the parallel programmer to 17226.
2) Load program data to programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel programmer
14
MB95110A Series
■ BLOCK DIAGRAM
2
F MC-8FX CPU
RST
X0,X1
PG2/X1A*
PG1/X0A*
PG0
Reset control
ROM
RAM
Clock control
Interrupt control
Watch prescaler
Wild register
Watch counter
P00/INT00 to P07/INT07
External interrupt
8/16-bit PPG ch1
P10/UI0
UART/SIO
P13/TRG0/ADTG
P14/PPG0
16-bit PPG
P15
P20/PPG00
P21/PPG01
8/16-bit PPG ch0
P22/TO00
P23/TO01
P24/EC0
8/16-bit compound
timer ch0
P30/AN00 to P37/AN07
AVCC
P61/PPG11
P62/TO10
Internal bus
P11/UO0
P12/UCK0
P60/PPG10
8/16-bit compound
timer ch1
P63/TO11
LIN-UART
P66/SOT
P67/SIN
P64/EC1
P65/SCK
10-bit A/D
converter
AVSS
P50/SCL0
P51/SDA0
I 2C
Port
Port
Other pins
MOD, VCC, VSS
* : Single-system product is general-purpose port, and dual-system product is subclock oscillation.
15
MB95110A Series
■ CPU CORE
1. Memory space
Memory space of the MB95110A series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95110A series shown in below.
• Memory Map
MB95116A
0000H
MB95F118A
I/O
0080H
0100H
Register
0200H
0480H
0080H
0100H
RAM 2 KB
Register
0F80H
0880H
Access
prohibited
0F80H
I/O
RAM 3.75 KB
Register
0F80H
I/O
I/O
1000H
1000H
1000H
0100H
0200H
0200H
Access
prohibited
I/O
I/O
0080H
RAM 1 KB
MB95FV100A-101
0000H
0000H
Access
prohibited
8000H
FLASH 60 KB
FLASH 60 KB
ROM 32 KB
FFFFH
16
FFFFH
FFFFH
MB95110A Series
2. Register
The MB95110A series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
: A 16-bit register to indicate locations where instructions are stored.
Program counter (PC)
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower one byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower one byte is used.
: A 16-bit register for index modification
Index register (IX)
: A 16-bit pointer to point to a memory address.
Extra pointer (EP)
: A 16-bit register to indicate a stack area.
Stack pointer (SP)
Program status (PS)
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16-bit
: Program counter
FFFDH
A
: Accumulator
0000H
T
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
PC
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
• Structure of the program status
PS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R4
R3
R2
R1
R0
DP2
DP1
DP0
H
I
IL1
IL0
N
Z
V
C
RP
DP
CCR
17
MB95110A Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
OP code lower
RP upper
"0"
Generated address
"0"
"0"
"0"
"0"
"0"
A15 A14 A13 A12 A11 A10
"0"
"1"
R4
A9
A8
A7
R3
A6
R2
A5
R1
A4
R0
b2
b1
A2
A3
A1
b0
A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
Don’t care
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by this bit.
IL1
IL0
Interrupt level
Priority
0
0
0
High
0
1
1
1
0
2
1
1
3
Low = no interruption
N flag
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
Z flag
V flag
: Set to “1” when an arithmetic operation results in 0. Cleared to “0” otherwise.
C flag
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
bit is set to “0”.
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
18
MB95110A Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. One bank contains
eight registers. Up to a total of 32 banks can be used on the MB95110A series. The bank currently in use is
indicated by the register bank pointer (RP).
• Register Bank Configuration
This address = 0100H + 8 x (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
19
MB95110A Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Vacancy)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
⎯
(Vacancy)
⎯
⎯
000EH
PDR2
Port 2 data register
R/W
00000000B
000FH
DDR2
Port 2 direction register
R/W
00000000B
0010H
PDR3
Port 3 data register
R/W
00000000B
0011H
DDR3
Port 3 direction register
R/W
00000000B
⎯
(Vacancy)
⎯
⎯
0014H
PDR5
Port 5 data register
R/W
00000000B
0015H
DDR5
Port 5 direction register
R/W
00000000B
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0029H
⎯
(Vacancy)
⎯
⎯
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
⎯
(Vacancy)
⎯
⎯
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
PUL2
Port 2 pull-up register
R/W
00000000B
002FH
PUL3
Port 3 pull-up register
R/W
00000000B
0030H
to
0034H
⎯
(Vacancy)
⎯
⎯
0012H
0013H
(Continued)
20
MB95110A Series
Address
Register
abbreviation
Register name
R/W
Initial value
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch1
R/W
00000000B
003AH
PC01
8/16-bit PPG1 control register ch0
R/W
00000000B
003BH
PC00
8/16-bit PPG0 control register ch0
R/W
00000000B
003CH
PC11
8/16-bit PPG1 control register ch1
R/W
00000000B
003DH
PC10
8/16-bit PPG0 control register ch1
R/W
00000000B
003EH
to
0041H
⎯
(Vacancy)
⎯
⎯
0042H
PCNTH0
16-bit PPG status control register (Upper byte) ch0
R/W
00000000B
0043H
PCNTL0
16-bit PPG status control register (Lower byte) ch0
R/W
00000000B
0044H
to
0047H
⎯
(Vacancy)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch0/1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch2/3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch4/5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch6/7
R/W
00000000B
004CH
to
004FH
⎯
(Vacancy)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch0
R
00000000B
005BH
to
005FH
⎯
(Vacancy)
⎯
⎯
(Continued)
21
MB95110A Series
Address
Register
abbreviation
Register name
R/W
Initial value
0060H
IBCR00
I2C bus control register 0 ch0
R/W
00000000B
0061H
IBCR10
I2C bus control register 1 ch0
R/W
00000000B
0062H
IBSR0
I2C bus status register ch0
R
00000000B
I C data register ch0
R/W
00000000B
0063H
2
IDDR0
2
0064H
IAAR0
I C address register ch0
R/W
00000000B
0065H
ICCR0
I2C clock control register ch0
R/W
00000000B
0066H
to
006BH
⎯
(Vacancy)
⎯
⎯
006CH
ADC1
A/D control register 1
R/W
00000000B
006DH
ADC2
A/D control register 2
R/W
00000000B
006EH
ADDH
A/D data register (Upper byte)
R/W
00000000B
006FH
ADDL
A/D data register (Lower byte)
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Vacancy)
⎯
⎯
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector writing control register 0
R/W
00000000B
0074H
SWRE1
Flash memory sector writing control register 1
R/W
00000000B
0075H
⎯
(Vacancy)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
⎯
(Mirror of register bank pointer (RP) and direct bank
pointer (DP) )
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Vacancy)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (Upper byte) ch0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (Lower byte) ch0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (Upper byte) ch1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower byte) ch1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch1
R/W
00000000B
(Continued)
22
MB95110A Series
Address
Register
abbreviation
Register name
R/W
Initial value
0F86H
WRARH2
Wild register address setting register (Upper byte) ch2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower byte) ch2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch2
R/W
00000000B
0F89H
to
0F91H
⎯
(Vacancy)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control
register ch0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch1
R/W
00000000B
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch1
R/W
00000000B
0F99H
T11DR
8/16-bit compound timer 11 data register ch1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch1
R/W
00000000B
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control
register ch1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG1 cycle setting buffer register ch1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG0 cycle setting buffer register ch1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG1 duty setting buffer register ch1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG0 duty setting buffer register ch1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG starting register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
to
0FA9H
⎯
(Vacancy)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (Upper byte) ch0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (Lower byte) ch0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (Upper byte) ch0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (Lower byte) ch0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (Upper byte) ch0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (Lower byte) ch0
R/W
11111111B
(Continued)
23
MB95110A Series
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0FB0H
to
0FBBH
⎯
(Vacancy)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO prescaler selection register ch0
R/W
00000000B
0FBFH
BRSR0
UART/SIO baud rate setting register ch0
R/W
00000000B
0FC0H
to
0FC2H
⎯
(Vacancy)
⎯
⎯
0FC3H
AIDRL
A/D input disable register (Lower byte)
R/W
00000000B
0FC4H
to
0FE2H
⎯
(Vacancy)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
to
0FEDH
⎯
(Vacancy)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Vacancy)
⎯
⎯
• Read/write access symbols
R/W : Readable and Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
24
MB95110A Series
■ INTERRUPT SOURCE TABLE
Vector table address
Upper
Lower
Bit name of
interrupt level
setting register
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch0
(Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch0
(Upper)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
8/16-bit PPG ch1 (Lower)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
8/16-bit PPG ch1 (Upper)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
(Unused)
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
8/16-bit compound timer ch1
(Upper)
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
16-bit PPG ch0
Interrupt source
External interrupt ch0
External interrupt ch4
External interrupt ch1
External interrupt ch5
External interrupt ch2
External interrupt ch6
External interrupt ch3
External interrupt ch7
Interrupt
request
number
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
2
I C ch0
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
(Unused)
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch prescaler/counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
(Unused)
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit compound timer ch1
(Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
FLASH
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
Same level
priority order
(at simultaneous
occurrence)
High
Low
25
MB95110A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp current
“L” level maximum
output current
Symbol
Rating
Vcc,
AVcc
Vss − 0.3
Vss + 4.0
AVR
Vss − 0.3
Vss + 4.0
VI1
Vss − 0.3
Vss + 4.0
VI2
Vss − 0.3
Vss + 6.0
VO
Vss − 0.3
Vss + 4.0
V
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*4
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*4
IOL1
IOL2
⎯
V
mA
mA
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH1
IOH2
⎯
− 15
− 15
mA
−4
⎯
“H” level average current
mA
−8
IOHAV2
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
“H” level total average
output current
Storage temperature
*2
*2 MB95FV100A-101 only
12
IOHAV1
“H” level total maximum
output current
15
V
4
IOLAV2
“H” level maximum
output current
15
⎯
“L” level average current
“L” level total average
output current
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Other than P50, P51*3
P50, P51
*3
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(total of pins)
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(total of pins)
Other than MB95FV100A-101
(Continued)
26
MB95110A Series
(Continued)
*1 : The parameter is based on AVCC = VSS = 0.0 V.
*2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V.
*3 : VI1 and VO should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI1 rating.
*4 : •
•
•
•
•
•
•
•
•
•
Applicable to pins : P00 to P07, P10 to P15, P20 to P24, P30 to P37, PG0
Use within recommended operating conditions.
Use at DC voltage (current).
The + B signal should always be applied a limiting resistance placed between the + B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may
affect other devices.
Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the + B input pin open.
Sample recommended circuits :
• Input/Output Equivalent Circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
Pch
Nch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
27
MB95110A Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Operating temperature
Symbol
VCC,
AVCC
TA
Value
Unit
Remarks
Min
Max
1.8*1
3.3*2
At normal operating, FLASH product,
TA = −10 °C to +85 °C
1.8*1
3.6
At normal operating, MASK product,
TA = −10 °C to +85 °C
2.0*1
3.3*2
At normal operating, FLASH product,
TA = −40 °C to +85 °C
V
2.0*1
3.6
At normal operating, MASK product,
TA = −40 °C to +85 °C
2.6
3.6
MB95FV100A-101
1.5
3.3*2
Retain status of stop operation, FLASH product
1.5
3.6
Retain status of stop operation, MASK product
− 40
+ 85
°C
Other than MB95FV100A-101
*1 : The values vary with the operating frequency.
*2 : Consult Fujitsu separately for a guarantee of a maximum value of 3.6 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
28
MB95110A Series
3. DC Characteristics
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C [MB95FV100A-101 is TA = +25 °C])
Parameter
“H” level input
voltage
Sym
bol
Pin name
Value
Conditions
Min
Typ
Max
Unit
VIH1
P10, P67
*1
0.7 Vcc
⎯
Vcc + 0.3
V
At selecting of
CMOS input level
(hysteresis input)
VIH2
P50, P51
*1
0.7 Vcc
⎯
Vss + 5.5
V
At selecting of
CMOS input level
(hysteresis input)
VIHS1
P00 to P07,
P10 to P15,
P20 to P24,
P30 to P37,
P60 to P67, PG0,
PG1*2, PG2*2
*1
0.8 Vcc
⎯
Vcc + 0.3
V
Hysteresis input
*1
0.8 Vcc
⎯
Vss + 5.5
V
Hysteresis input
⎯
0.7 Vcc
⎯
Vcc + 0.3
V
CMOS input
(FLASH product)
⎯
0.8 Vcc
⎯
Vcc + 0.3
V
Hysteresis input
(MASK product)
VIHS2 P50, P51
VIHM RST, MOD
“L” level input
voltage
VIL
P10, P50, P51,
P67
*1
Vss − 0.3
⎯
0.3 Vcc
V
At selecting of
CMOS input level
(hysteresis input)
VILS
P00 to P07,
P10 to P15,
P20 to P24,
P30 to P37, P50,
P51, P60 to P67,
PG0, PG1*2,
PG2*2
*1
Vss − 0.3
⎯
0.2 Vcc
V
Hysteresis input
⎯
Vss − 0.3
⎯
0.3 Vcc
V
CMOS input
(FLASH product)
⎯
Vss − 0.3
⎯
0.2 Vcc
V
Hysteresis input
(MASK product)
⎯
Vss − 0.3
⎯
Vss + 5.5
V
IOH =
− 4.0 mA
2.4
⎯
⎯
V
MB95FV100A-101
a conditional :
IOH = − 2.0 mA
IOH =
− 8.0 mA
2.4
⎯
⎯
V
MB95FV100A-101
a conditional :
IOH = − 5.0 mA
VILM RST, MOD
Open drain
output application
voltage
VD
VOH1
“H” level output
voltage
Remarks
P50, P51
Output pin other
than P00 to P07
VOH2 P00 to P07
(Continued)
29
MB95110A Series
(Continued)
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C [MB95FV100A-101 is TA = +25 °C])
Parameter
Symbol
Pin name
Conditions
Value
Min
Typ
Max
Unit
Remarks
VOL1
Output pin
other than
P00 to P07
IOL =
4.0 mA
⎯
⎯
0.4
V
MB95FV100A101 a conditional :
IOL = 3.0 mA
VOL2
P00 to P07
IOL = 12 mA
⎯
⎯
0.4
V
MB95FV100A101 a conditional :
IOL = 8.0 mA
Input leakage
current (High-Z
output leakage
current)
ILI
Port other
than P50,
P51
0.0 V < VI < Vcc
−5
⎯
+5
µA
When no pull-up
resistor is
specified
Open drain
output leakage
current
ILIOD
P50, P51
0.0 V < VI < Vss +
5.5 V
⎯
⎯
+5
µA
Pull-up resistor
RPULL
P10 to P15,
P20 to P24,
P30 to P37,
PG0, PG1*2,
PG2*2
VI = 0.0 V
25
50
100
When pull-up
kΩ resistor is
specified
Pull-down
resistor
RMOD
MOD
VI = Vcc
50
100
200
kΩ
⎯
11
14
mA FLASH product
⎯
7.3
10
mA MASK product
⎯
30
35
FLASH product
mA (at FLASH writing
and erasing)
FCH = 20 MHz
fmp = 10 MHz
Main Sleep mode
(divided by 2)
⎯
4.5
6
mA
ICCL
FCL = 32 kHz
fmpl = 16 kHz
Subclock mode
(divided by 2) ,
TA = + 25 °C
⎯
25
35
µA
ICCLS
FCL = 32 kHz
fmpl = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
⎯
7
15
µA
“L” level output
voltage
FCH = 20 MHz
fmp = 10 MHz
Main clock mode
(divided by 2)
ICC
ICCS
VCC
(external
clock
operation)
Power supply
current*3
MASK product
only
(Continued)
30
MB95110A Series
(Continued)
(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C [MB95FV100A-101 is TA = +25 °C])
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Typ
Max
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
⎯
2
10
µA FLASH product
⎯
1
5
µA MASK product
FCH = 4 MHz
fmp = 10 MHz
Main PLL mode
(multiplied by 2.5)
⎯
10
14
mA FLASH product
⎯
6.7
10
mA MASK product
FCL = 32 kHz
fmpl = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
⎯
190
250
µA
ICTS
FCH = 10 MHz
Timebase timer mode
TA = + 25 °C
⎯
0.4
0.5
mA
ICCH
Substop mode
TA = + 25 °C
⎯
1
5
µA
FCH = 10 MHz
At A/D converting
⎯
1.3
2.2
mA
FCH = 10 MHz
At A/D converting stop
TA = + 25 °C
⎯
1
5
µA
⎯
⎯
5
15
pF
ICCT
ICCMPLL
ICCSPLL
Power supply
current*3
VCC
(external
clock
operation)
IA
AVcc
IAH
Input
capacitance
Conditions
CIN
Other than
AVcc, AVss,
Vcc, and Vss
*1 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR).
*2 : Single-clock products only
*3 : The power-supply current is determined by the external clock.
• Refer to “4. AC characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for fmp and fmpl.
31
MB95110A Series
4. AC Characteristics
(1) Clock Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
FCH
Pin
Conditions
X0, X1
Clock frequency
FCL
X0A,
X1A
Value
Unit
Remarks
10
MHz
When using Main oscillation circuit
⎯
20
MHz When using external clock
3
⎯
10
MHz Main PLL multiplied by 1
3
⎯
5
MHz Main PLL multiplied by 2
3
⎯
4
MHz Main PLL multiplied by 2.5
⎯
32.768
⎯
kHz
When using Sub oscillation circuit
When using sub PLL
FLASH product :
Vcc = 2.3 V to 3.3 V
MASK product :
Vcc = 2.3 V to 3.6 V
Min
Typ
Max
1
⎯
1
⎯
32.768
⎯
kHz
100
⎯
1000
ns
When using Main oscillation circuit
50
⎯
1000
ns
When using Sub oscillation circuit
⎯
tHCYL
X0, X1
Clock cycle time
Input clock pulse width
Input clock rise time and
fall time
32
tLCYL
X0A,
X1A
⎯
30.5
⎯
µs
Subclock
tWH1
tWL1
X0
10
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
µs
When using external clock
Duty ratio is about 30% to
70%.
tCR
tCF
X0,
X0A
⎯
⎯
5
ns
When using external clock
MB95110A Series
• X0 and X1 Timing and Applying Conditions
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Main Clock Applying Conditions
When using a crystal or
ceramic oscillator
X0
When using external clock
X1
X0
X1
Open
FCH
FCH
• X0A and X1A Timing and Applying Conditions
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Subclock Applying Conditions
When using a crystal or
ceramic oscillator
X0A
X1A
FCL
When using external clock
X0A
X1A
Open
FCL
33
MB95110A Series
(2) Source Clock/Machine Clock
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Source clock*1
(Clock before setting
division)
Source clock frequency
Machine clock*2
(Minimum instruction
execution time)
Machine clock
frequency
Sym- Pin
bol name
SCLK
Value
Unit
Remarks
2000
ns
When using Main clock
Min : FCH = 10 MHz, PLL multiplied by 1
Max : FCH = 1 MHz, divided by 2
⎯
61.0
µs
When using Subclock
Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
10.0
Min
Typ
Max
100
⎯
7.6
⎯
fsp
⎯
0.5
⎯
fspl
⎯
16.384
⎯
100
⎯
32000
ns
When using Main clock
Min : SLCK = 10 MHz, no division
Max : SLCK = 0.5 MHz, divided by 16
7.6
⎯
976.5
µs
When using Subclock
Min : SLCK = 131 kHz, no division
Max : SLCK = 16 kHz, divided by 16
0.031
⎯
10.000
1.024
⎯
131.072 kHz When using Subclock
MCLK
fmp
fmpl
MHz When using Main clock
131.072 kHz When using Subclock
⎯
⎯
MHz When using Main clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes
the machine clock. Further, the source clock can be selected as follow.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5 multiplication)
• Subclock divided by 2
• PLL multiplication of subclock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follow.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
34
MB95110A Series
• Operating voltage − Operating frequency
• MASK product
Sub PLL operation guarantee range
(2.3 V to 3.6 V)
3.6
A/D converter accuracy
guarantee range
Operating voltage (V)
Main PLL operation guarantee range
2.2
2.0
1.8
1.0
0.5 MHz
3 MHz
5 MHz
10 MHz
Source clock frequency (fsp)
• FLASH product
Sub PLL operation guarantee range
A/D converter accuracy
guarantee range
(2.3 V to 3.3 V)
3.3
Operating voltage (V)
Main PLL operation guarantee range
2.2
2.0
1.8
1.0
0.5 MHz
3 MHz
5 MHz
10 MHz
Source clock frequency (fsp)
Note: In operating by 2.0 V or less, only “TA = -10 °C to +85 °C” is guaranteed.
35
MB95110A Series
• Main PLL operation frequency
10 MHz
Source clock frequency (fsp)
× 2.5
9 MHz
8 MHz
7.5 MHz
×2
7 MHz
6 MHz
×1
5 MHz
4 MHz
3 MHz
3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz
Main clock frequency
36
MB95110A Series
(3) Reset Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Value
Symbol
RST “L” level pulse
width
Min
Max
2 MCLK*1
tRSTL
2
Oscillation time of oscillator*
+ 2 MCLK*1
Unit
Remarks
⎯
ns
At normal operating
⎯
ns
At stop mode, subclock mode,
Sub sleep mode, and watch mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for MCLK.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In FAR/ceramic oscillators, the oscillation time is between hundreds
of µs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, subclock mode, sub sleep mode, and watch mode
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
Oscillation time
of oscillator
2 MCLK
Oscillation stabilization wait time
Execute instruction
Internal reset
37
MB95110A Series
(4) Power-on Reset
(AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Power supply rising time
tR
Power supply cutoff time
tOFF
Value
Unit
Min
Max
⎯
⎯
36
ms
⎯
1
⎯
ms
Remarks
Due to repeated
operations
Note : The power supply must be turned on within the selected oscillation stabilization time.
tR
tOFF
1.5 V
VCC
0.2 V
0.2 V
0.2 V
Sudden change of power supply voltage may activate the power-on reset function.
When changing power supply voltages during operation, set the slope of rising within
20 mV/ms as shown below. In this case, do not use PLL clock. However, if voltage
drop is 1V/s or less, use of PLL clock is allowed during operation.
VCC
Limiting the slope of rising within
20 mV/ms is recommended.
1.5 V
RAM data hold period
VSS
38
MB95110A Series
(5) Peripheral Input Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Peripheral input “H” pulse
width
tILIH
Peripheral input “L” pulse
width
tIHIL
Pin name
INT00 to INT07, EC0,
EC1, TRG0/ADTG
Value
Unit
Min
Max
2 MCLK*
⎯
ns
2 MCLK*
⎯
ns
Remarks
* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.
tILIH
INT00 to INT07,
EC0, EC1,
TRG0/ADTG
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
39
MB95110A Series
(6) UART/SIO, Serial I/O Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Serial clock cycle time
Symbol
Pin name
tSCYC
UCK0
Value
Conditions
UCK0, UO0 Internal
clock
UCK0, UI0 operation
UCK0, UI0
Max
4 MCLK*
⎯
ns
− 190
190
ns
2 MCLK*
⎯
ns
2 MCLK*
⎯
ns
UCK ↓ → UO time
tSLOV
Valid UI → UCK ↑
tIVSH
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
tSHSL
UCK0
4 MCLK*
⎯
ns
Serial clock “L” pulse width
tSLSH
UCK0
4 MCLK*
⎯
ns
UCK ↓ → UO time
tSLOV
⎯
190
ns
Valid UI → UCK ↑
tIVSH
External
UCK0, UO0 clock
operation
UCK0, UI0
2 MCLK*
⎯
ns
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
2 MCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
2.4 V
0.8 V
tIVSH
UI0
VIH
VIL
tSHIX
VIH
VIL
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
2.4 V
0.8 V
tIVSH
UI0
40
Unit
Min
VIH
VIL
tSHIX
VIH
VIL
Remarks
MB95110A Series
(7) LIN-UART Timing
ESCR : SCES = 0, ECCR : SCDE = 0
Parameter
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
SymPin name
bol
Conditions
Value
Unit
Min
Max
5 MCLK*
⎯
ns
−95
95
ns
MCLK* +
190
⎯
ns
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSLOVI
SCK, SOT
Valid SIN → SCK ↑
tIVSHI
SCK, SIN
SCK ↑→ valid SIN hold time
tSHIXI
SCK, SIN
0
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
3 MCLK* −
tR
⎯
ns
Serial clock “H” pulse width
tSHSL
SCK
MCLK* + 95
⎯
ns
SCK ↓ → SOT delay time
tSLOVE SCK, SOT
⎯
2 MCLK* +
95
ns
Valid SIN → SCK↑
tIVSHE
SCK, SIN
190
⎯
ns
SCK ↑ → Valid SIN hold time
tSHIXE
SCK, SIN
MCLK* + 95
⎯
ns
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
External clock
operation output pin :
CL = 80 pF + 1 TTL.
* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.
41
MB95110A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
VIH
SIN
VIL
• External shift clock mode
tSLSH
tSHSL
SCK
VIH
VIL
tF
SOT
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
VIH
VIL
42
tSHIXE
MB95110A Series
ESCR : SCES = 1, ECCR : SCDE = 0
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓ → Valid SIN hold time
tSLIXI
Serial clock “H” pulse width
Parameter
Conditions
Value
Unit
Min
Max
5 MCLK*
⎯
ns
−95
95
ns
MCLK* +
190
⎯
ns
SCK, SIN
0
⎯
ns
tSHSL
SCK
3 MCLK* −
tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
MCLK* +
95
⎯
ns
SCK ↑ → SOT delay time
tSHOVE
SCK, SOT
⎯
2 MCLK* +
95
ns
Valid SIN → SCK ↓
tIVSLE
SCK, SIN
190
⎯
ns
SCK ↓ → Valid SIN hold time
tSLIXE
SCK, SIN
MCLK* +
95
⎯
ns
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
External clock
operation output pin :
CL = 80 pF + 1 TTL.
* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.
43
MB95110A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
VIH
SIN
VIL
• External shift clock mode
tSHSL
SCK
tSLSH
VIH
VIL
tR
SOT
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
VIH
VIL
44
tSLIXE
MB95110A Series
ESCR : SCES = 0, ECCR : SCDE = 1
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin
name
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
Parameter
Value
Conditions
Unit
Min
Max
SCK
5 MCLK*
⎯
ns
tSHOVI
SCK,
SOT
−95
95
ns
Valid SIN→SCK↓
tIVSLI
SCK,
SIN
MCLK* +
190
⎯
ns
SCK ↓ → valid SIN hold time
tSLIXI
SCK,
SIN
0
⎯
ns
SOT → SCK ↓ delay time
tSOVLI
SCK,
SOT
⎯
4 MCLK*
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN
VIH
VIL
0.8 V
tSHOVI
tSOVLI
tSLIXI
VIH
VIL
45
MB95110A Series
ESCR : SCES = 1, ECCR : SCDE = 1
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Parameter
Value
Conditions
Max
SCK
5 MCLK*
⎯
ns
SCK, SOT
−95
95
ns
MCLK* +
190
⎯
ns
0
⎯
ns
⎯
4 MCLK*
ns
Valid SIN → SCK ↑
tIVSHI
SCK ↑ →valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
SOT → SCK ↑ delay time
tSOVHI
SCK, SOT
* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
tIVSHI
SIN
46
tSLOVI
2.4 V
0.8 V
VIH
VIL
Unit
Min
tSHIXI
VIH
VIL
MB95110A Series
(8) I2C Timing
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Standardmode
Conditions
Fast-mode
Unit Remarks
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHD;STA
4.0
⎯
0.6
⎯
µs
SCL clock “L” width
tLOW
4.7
⎯
1.3
⎯
µs
SCL clock “H” width
tHIGH
4.0
⎯
0.6
⎯
µs
4.7
⎯
0.6
⎯
µs
SCL clock frequency
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
tSU;STA
Data hold time SCL ↓ → SDA ↓ ↑
tHD;DAT
0
3.45*2
0
0.9*3
µs
Data setup time SDA ↓ ↑ → SCL ↑
tSU;DAT
0.25
⎯
0.1
⎯
µs
Stop condition setup time SCL ↑ →
SDA ↑
tSU;STO
4
⎯
0.6
⎯
µs
tBUF
4.7
⎯
1.3
⎯
µs
Bus free time between stop
condition and start condition
R = 1.7 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
tWAKEUP
SDA0
tLOW
tSU;DAT
tHIGH
tHD;STA
tBUF
SCL0
tHD;STA
tSU;STO
tHD;DAT
tSU;STA
47
MB95110A Series
(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
I/O Timing
Min
Max
Unit
Remarks
SCL clock “L” width
tLOW
(2 + nm*2 / 2)
MCLK*1 − 20
⎯
ns
Master mode
SCL clock “H” width
tHIGH
(nm*2 / 2)
MCLK*1 − 20
(nm*2 / 2 )
MCLK*1 + 20
ns
Master mode
Start condition hold time
tHD;STA
(−1 + nm*2 / 2)
MCLK*1 − 20
(−1 + nm*2)
MCLK*1 + 20
ns
Master mode
Maximum value is applied when
m, n = 1, 8.
Otherwise, the minimum
value is applied.
Stop condition setup time
tSU;STO
(1 + nm*2 / 2)
MCLK*1 − 20
(1 + nm*2 / 2)
MCLK*1 + 20
ns
Master mode
Start condition setup time
tSU;STA
(1 + nm*2 / 2)
MCLK*1 − 20
(1 + nm*2 / 2)
MCLK*1 + 20
ns
Master mode
tBUF
(2 nm*2 + 4)
MCLK*1 − 20
⎯
ns
tHD;DAT
3 MCLK*1 − 20
⎯
ns
Master mode
ns
Master mode
When assuming that “L” of SCL
is not extended,
the minimum value is applied to
first bit of continuous data. Otherwise, the maximum
value is applied.
Bus free time between stop
condition and start condition
Data hold time
(−2 + nm*2 / 2)
MCLK*1 − 20
(−1 + nm*2 / 2)
MCLK*1 + 20
(nm*2 / 2)
MCLK*1 − 20
(1 + nm*2 / 2)
MCLK*1 + 20
ns
Minimum value is applied to interrupt at 9th SCL↓. Maximum
value is applied to interrupt at
8th SCL↓.
tLOW
4 MCLK*1 − 20
⎯
ns
At reception
tHIGH
4 MCLK* − 20
⎯
ns
At reception
Start condition detection
tHD;STA
2 MCLK*1 − 20
⎯
ns
Undetected when 1 MCLK is
used at reception
Stop condition detection
tSU;STO
2 MCLK*1 − 20
⎯
ns
Undetected when 1 MCLK is
used at reception
Restart condition detection
condition
tSU;STA
2 MCLK*1 − 20
⎯
ns
Undetected when 1 MCLK is
used at reception
tBUF
2 MCLK*1 − 20
⎯
ns
At reception
Data hold time
tHD;DAT
2 MCLK* − 20
⎯
ns
At slave transmission mode
Data setup time
tSU;DAT
tLOW − 3 MCLK*1 −
20
⎯
ns
At slave transmission mode
Data hold time
tHD;DAT
0
⎯
ns
At reception
tSU;DAT
MCLK* − 20
⎯
ns
At reception
Data setup time
tSU;DAT
Setup time between clearing
tSU;INT
interrupt and SCL rising
SCL clock “L” width
SCL clock “H” width
Bus free time
Data setup time
1
1
1
(Continued)
48
MB95110A Series
(Continued)
Parameter
SDA↓→SCL↑
(at wakeup function )
Symbol
tWAKEUP
I/O Timing
Min
Max
Oscillation stabilization wait time
+ 2 MCLK*1 − 20
⎯
Unit
Remarks
ns
*1 : Refer to “ (2) Source Clock/Machine Clock” for MCLK.
*2 : •
•
•
•
m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) .
Actual timing of I2C is determined by m and n values set by the machine clock (MCLK) and ICCR [4 : 0].
Standard-mode :
m and n can be set at the range : 0.9 MHz < MCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < MCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < MCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8)
: 0.9 MHz < MCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < MCLK ≤ 10 MHz
• Fast-mode :
m and n can be set at the range : 3.3 MHz < MCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 3.3 MHz < MCLK ≤ 4 MHz
(m, n) = (1, 22) , (5, 4) : 3.3 MHz < MCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < MCLK ≤ 10 MHz
49
MB95110A Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVcc = Vcc = 1.8 V to 3.3 V [FLASH product], AVcc = Vcc = 1.8 V to 3.6 V [MASK product], AVss = Vss = 0.0 V,
TA = − 40 °C to + 85 °C)
Parameter
Symbol
Resolution
Total error
Linearity error
⎯
Differential linear error
Zero transition voltage
Full-scale transition
voltage
Compare time
Sampling time
VFST
⎯
Unit
Remarks
Min
Typ
Max
⎯
⎯
10
bit
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
AVss − 1.5
LSB
AVss + 0.5
LSB
AVss + 2.5
LSB
V
FLASH product :
2.7 V ≤ AVcc ≤ 3.3 V
MASK product :
2.7 V ≤ AVcc ≤ 3.6 V
AVss − 0.5
LSB
AVss + 1.5
LSB
AVss + 3.5
LSB
V
1.8 V ≤ AVcc < 2.7 V
AVcc − 3.5
LSB
AVcc − 1.5
LSB
AVcc + 0.5
LSB
V
FLASH product :
2.7 V ≤ AVcc ≤ 3.3 V
MASK product :
2.7 V ≤ AVcc ≤ 3.6 V
AVcc − 2.5
LSB
AVcc − 0.5
LSB
AVcc + 1.5
LSB
V
1.8 V ≤ AVcc < 2.7 V
0.6
⎯
16,500
µs
FLASH product :
2.7 V ≤ AVcc ≤ 3.3 V
MASK product :
2.7 V ≤ AVcc ≤ 3.6 V
20
⎯
16,500
µs
1.8 V ≤ AVcc < 2.7 V
0.4
⎯
∞
µs
FLASH product :
2.7 V ≤ AVcc ≤ 3.3 V
MASK product :
2.7 V ≤ AVcc ≤ 3.6 V
external impedance <
at 1.8 kΩ
30
⎯
∞
µs
1.8 V ≤ AVcc < 2.7 V
external impedance <
at 14.8 kΩ
⎯
Analog input current
IAIN
−0.3
⎯
0.3
µA
Analog input voltage
range
VAIN
AVss
⎯
AVcc
V
⎯
AVss + 1.8
⎯
AVcc
V
AVcc pin
IR
⎯
400
600
µA
AVcc pin,
During A/D operation
IRH
⎯
⎯
5
µA
AVcc pin,
at stop mode
Reference voltage
Reference voltage
supply current
50
VOT
Value
MB95110A Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sanple and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Analog input pin
Comparator
C
During sampling : ON
2.7 V ≤ AVcc ≤ 3.6 V
1.8 V ≤ AVcc < 2.7 V
R
1.7 kΩ (Max)
84 kΩ (Max)
C
14.5 pF (Max)
25.2 pF (Max)
Note : The values are reference values.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
AVcc ≥ 2.7 V
External impedance [kΩ]
External impedance [kΩ]
AVcc ≥ 2.7 V
100
90
80
70
60
50
40
30
20
10
0
AVcc ≥ 1.8 V
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
40
20
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
51
MB95110A Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ←
→ “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”)
compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
3FEH
1.5 LSB
004H
VOT
003H
002H
3FDH
Digital output
Digital output
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
Actual conversion
characteristic
003H
002H
1 LSB
Ideal characteristics
001H
001H
0.5 LSB
AVSS
AVCC
AVSS
Analog input
Analog input
AVCC
1 LSB = AVCC − AVSS (V)
1024
Total error of digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB} [LSB]
1 LSB
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
52
MB95110A Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
characteristics
004H
3FFH
003H
002H
Ideal
characteristics
Actual conversion
characteristic
Digital output
Digital output
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
VOT (measurement value)
AVSS
AVSS
AVCC
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FFH
Ideal characteristics
N+1
3FEH
Actual conversion
characteristic
VFST
(measurement
value)
VNT
004H
Actual conversion
characteristic
Ideal characteristics
003H
002H
Digital output
{1 LSB × N + VOT}
3FDH
Digital output
AVCC
Analog input
N
N−1
VNT
Actual conversion
characteristic
N−2
001H
V (N + 1) T
VOT (measurement value)
AVSS
AVCC
AVSS
AVCC
Analog input
Analog input
Linear error in digital output N = VNT − {1 LSB × N + VOT}
1 LSB
Differential linear error in digital output N = V (N + 1) T − VNT
1 LSB
−1
VNT : A voltage at which digital output transits from (N − 1) to N.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVCC − 1.5 LSB [V]
53
MB95110A Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
3*2
s
Excludes 00H programming prior erasure
0.5*1
12*2
s
Excludes 00H programming prior erasure
⎯
32
3600
µs
Excludes system-level overhead
10,000
⎯
⎯
cycle
Power supply voltage at
erase/program
2.7
⎯
3.3
V
Flash data retension time
20*3
⎯
⎯
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
⎯
0.2*1
Sector erase time
(16 Kbytes sector)
⎯
Byte programming time
Erase/program cycle
year Average TA = +85 °C
*1 : TA = +25 °C, Vcc = 3.0 V, 10,000 cycles
*2 : TA = +85 °C, Vcc = 2.7 V, 10,000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
54
MB95110A Series
■ MASK OPTIONS
Part number
No
Specifying procedure
MB95116A
MB95F118AS
MB95F118AW
MB95FV100A-101
Setting disabled
Setting disabled
Single-system
clock mode
Dual-system
clock mode
Changing by the
switch on MCU
board
Fixed to oscillation
stabilization wait
time of
(214-2) /FCH
Fixed to oscillation
stabilization wait
time of
(214-2) /FCH
Fixed to oscillation
stabilization wait
time of
(214-2) /FCH
Specify when
Setting disabled
ordering MASK
1
Clock mode select
• Single-system clock mode
• Dual-system clock mode
2
Selection of oscillation
Selectable
stabilization wait time
1 : ( 22 − 2) /FCH
• Selectable the initial value 2 : ( 212 − 2) /FCH
of main clock oscillation
3 : ( 213 − 2) /FCH
stabilization wait time
4 : ( 214 − 2) /FCH
Selectable
■ ORDERING INFORMATION
Part number
Package
MB95116APV
MB95F118ASPV
MB95F118AWPV
48-pin plastic BCC
(LCC-48P-M09)
MB95116APMT
MB95F118ASPMT
MB95F118AWPMT
48-pin plastic LQFP
(FPT-48P-M26)
MB2146-301
(MB95FV100A-101PBT)
(
MCU board
244-pin plastic PFBGA
(BGA-244P-M08)
Remarks
)
55
MB95110A Series
■ PACKAGE DIMENSIONS
48-pin plastic BCC
(LCC-48P-M09)
0.75±0.05
(.030±.002)
(Mount height)
7.00±0.10(.276±.004)
37
0.50(.020)
TYP
25
6.20(.244)TYP
0.50±0.10
(.020±.004)
25
37
0.50(.020)
TYP
7.00±0.10
(.276±.004)
6.20(.244)
TYP
6.15(.242)TYP
6.25(.246)
REF
5.00(.197)
REF
6.15(.242)
TYP
INDEX AREA
0.50±0.10
(.020±.004)
"A"
1
13
0.05(.002)
13 "C"
0.075±0.025
(.003±.001)
(Stand off)
Details of "A" part
8-0.60±0.06
(8-.024±.002)
0.14(.006)
MIN
C
"B"
5.00(.197)REF
1
6.25(.246)REF
Details of "B" part
0.65±0.06
(.026±.002)
0.30±0.06
(.012±.002)
C0.2(.008)
0.55±0.06
(.022±.002)
Details of "C" part
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
2004 FUJITSU LIMITED C48062S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
(Continued)
56
MB95110A Series
(Continued)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic LQFP
(FPT-48P-M26)
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0˚~8˚
LEAD No.
1
0.50(.020)
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
C
2003 FUJITSU LIMITED F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
57
MB95110A Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
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function and schematic diagrams, shall not be construed as license
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and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
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and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
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satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
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must protect against injury, damage or loss from such failures by
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If any products described in this document represent goods or
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F0502
© 2005 FUJITSU LIMITED Printed in Japan