GS71208TP TSOP Commercial Temp Industrial Temp 128K x 8 1Mb Asynchronous SRAM Features 8 ns 3.3 V VDD Center VDD and VSS TSOP-II 128K x 8-Pin Configuration • Fast access time: 8 ns • CMOS low power operation: 150 mA at minimum cycle time • Single 3.3 V ± 0.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40° to 85°C • Package line up TP: 400 mil, 32-pin TSOP Type II package The GS71208 is a high speed CMOS Static RAM organized as 131,072 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTL-compatible. The GS71208 is available in a 400 mil TSOP Type-II package. 32 A4 A2 2 31 A5 A1 3 30 A6 A0 4 29 A7 CE 5 28 OE DQ1 6 27 DQ8 DQ2 7 26 DQ7 VDD 8 25 VSS 32-pin 400 mil TSOP II 9 24 DQ3 10 23 DQ4 11 22 DQ5 WE 12 21 A8 A16 13 20 A9 A15 14 19 A10 A14 15 18 A11 A13 16 17 A12 VDD DQ6 Description A0–A16 Address input DQ1–DQ8 Data input/output CE Chip enable input WE Write enable input OE Output enable input VDD +3.3 V power supply VSS Ground NC No connect Rev: 1.03 10/2001 1 VSS Description Pin Descriptions Symbol A3 1/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP Block Diagram A0 Address Input Buffer Row Decoder Memory Array Column Decoder A16 CE WE OE I/O Buffer Control DQ1 DQ8 Truth Table CE OE WE DQ1 to DQ8 VDD Current H X X Not Selected ISB1, ISB2 L L H Read L X L Write L H H High Z IDD Note: X: “H” or “L” Rev: 1.03 10/2001 2/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD –0.5 to +4.6 V Input Voltage VIN –0.5 to VDD +0.5 (≤ 4.6 V max.) V Output Voltage VOUT –0.5 to VDD +0.5 (≤ 4.6 V max.) V Allowable power dissipation PD 0.7 W Storage temperature TSTG –55 to 150 o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for -8 VDD 3.135 3.3 3.6 V Input High Voltage VIH 2.0 — VDD +0.3 V Input Low Voltage VIL –0.3 — 0.8 V Ambient Temperature, Commercial Range TAc 0 — 70 oC Ambient Temperature, Industrial Range T AI –40 — 85 o C Note: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance CIN VIN = 0 V 5 pF Output Capacitance COUT VOUT = 0 V 7 pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. Rev: 1.03 10/2001 3/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP DC I/O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current IIL VIN = 0 to VDD –1 uA 1 uA Output Leakage Current ILO Output High Z VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –4mA 2.4 — Output Low Voltage VOL ILO = +4mA — 0.4 V Power Supply Currents Parameter Operating Supply Current Standby Current Standby Current Rev: 1.03 10/2001 0 to 70°C –40 to 85°C 8 ns 8 ns IDD (max) CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA 150 mA 160 mA ISB1 (max) CE ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time 55 mA 65 mA ISB2 (max) CE ≥ VDD – 0.2 V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V 15 mA 25 mA Symbol Test Conditions 4/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP AC Test Conditions Output Load 1 Parameter Conditions Input high level VIH = 2.4 V Input low level VIL = 0.4 V 50Ω Input rise time tr = 1 V/ns VT = 1.4 V Input fall time tf = 1 V/ns Input reference level 1.4 V Output Load 2 Output reference level 1.4 V 3.3 V Output load Fig. 1& 2 DQ 30pF1 589Ω DQ Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ 5pF1 434Ω AC Characteristics Read Cycle Parameter Symbol Read cycle time -8 Unit Min Max tRC 8 — ns Address access time tAA — 8 ns Chip enable access time (CE) tAC — 8 ns Output enable to output valid (OE) tOE — 3.5 ns Output hold from address change tOH 3 — ns Chip enable to output in low Z (CE) tLZ* 3 — ns Output enable to output in low Z (OE) tOLZ* 0 — ns Chip disable to output in High Z (CE) tHZ* — 4 ns Output disable to output in High Z (OE) tOHZ* — 3.5 ns * These parameters are sampled and are not 100% tested Rev: 1.03 10/2001 5/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP Read Cycle 1: CE = OE = VIL, WE = VIH tRC Address tAA tOH Data Out Previous Data Data valid Read Cycle 2: WE = VIH tRC Address tAA CE tAC tHZ tLZ OE tOE Data Out Rev: 1.03 10/2001 tOLZ High impedance tOHZ DATA VALID 6/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP Write Cycle Parameter Symbol Write cycle time -8 Unit Min Max tWC 8 — ns Address valid to end of write tAW 5.5 — ns Chip enable to end of write tCW 5.5 — ns Data set up time tDW 4 — ns Data hold time tDH 0 — ns Write pulse width tWP 5.5 — ns Address set up time tAS 0 — ns Write recovery time (WE) tWR 0 — ns Write recovery time (CE) tWR1 0 — ns Output Low Z from end of write tWLZ* 3 — ns Write to output in High Z tWHZ* — 3.5 ns * These parameters are sampled and are not 100% tested Rev: 1.03 10/2001 7/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP Write Cycle 1: WE control tWC Address tAW tWR OE tCW CE tAS tWP WE tDW Data In tDH DATA VALID tWHZ tWLZ Data Out HIGH IMPEDANCE Write Cycle 2: CE control tWC Address tAW tWR1 OE tAS tCW CE tWP WE tDW Data In DATA VALID Data Out Rev: 1.03 10/2001 tDH HIGH IMPEDANCE 8/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP 32-Pin TSOP-II, 400mil 1 e E A b Detail A Q L1 y L A1 A A2 ZD Dimension in inch c E1 32 D Dimension in mm Symbol min nom max min nom max A 0.039 — 0.05 — — 1.27 A1 0.002 — 0.006 0.01 — 0.15 A2 0.037 0.040 0.045 0.90 1.02 1.14 b 0.012 0.016 0.018 0.30 0.40 0.45 c 0.0047 0.0051 0.0062 0.12 0.13 0.16 D 0.820 0.825 0.830 20.82 20.95 21.08 ZD — 0.037 — — 0.95 — E 0.455 0.463 0.471 11.56 11.76 11.96 E1 0.395 0.400 0.405 10.03 10.16 10.29 e — 0.05 — — 1.27 — L 0.017 0.020 0.023 0.40 0.50 0.60 L1 0.024 0.031 0.039 0.60 0.80 1.00 y 0.00 — 0.003 0.00 — 0.76 Q 0o — 5o 0o — 5o Note: 1.Dimension D includes mold flash, protrusions or gate burrs. 2. Dimension E does not include interlead flash. 3. Controlling dimension: mm Rev: 1.03 10/2001 9/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP Ordering Information Part Number* Package Access Time Temp. Range GS71208TP-8 400 mil TSOP-II 8 ns Commercial Status * Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS71208TP-8T Rev: 1.03 10/2001 10/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc. GS71208TP Revision History Rev. Code: Old; New 1.00 12/1999/1.01 12/1999 Types of Changes Format or Content Content GS71208Rev1.01 12/1999KRev 1.01 2/2000L Format/Content 71208_r1_01; 71208_r1_02 Format/Content 71208_r1_02; 71208_r1_03 Content Rev: 1.03 10/2001 Page #/Revisions/Reason 1. Added TP package to 71208 • GSI LogoAdded Dimension D to 32 pin 400 ml TSOP II Package. • Updated format to comply with Technical Publications standard • Specifically noted that numbers in Power Supply Currents table are worst case scenario • Removed all references to other parts except 71208TP-8 11/11 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, Giga Semiconductor, Inc.