GS71108ATP/J/SJ/U SOJ, TSOP, FP-BGA Commercial Temp Industrial Temp 128K x 8 1Mb Asynchronous SRAM Features 7, 8, 10, 12 ns 3.3 V VDD Center VDD and VSS SOJ & TSOP-II 128K x 8-Pin Configuration • Fast access time: 7, 8, 10, 12 ns • CMOS low power operation: 140/120/95/80 mA at minimum cycle time • Single 3.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40° to 85°C • Package line up J: 400 mil, 32-pin SOJ package TP: 400 mil, 32-pin TSOP Type II package SJ: 300 mil, 32-pin SOJ package U: 6 mm x 8 mm Fine Pitch Ball Grid Array package Description The GS71108A is a high speed CMOS Static RAM organized as 131,072 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS71108A is available in a 6 mm x 8 mm Fine Pitch BGA package, as well as in 300 mil and 400 mil SOJ and 400 mil TSOP Type-II packages. A3 1 32 A4 A2 2 31 A5 A1 3 30 A6 A0 4 29 A7 CE 5 28 OE DQ1 6 DQ8 DQ2 7 400 mil SOJ 27 26 DQ7 VDD 8 & 25 VSS VSS 9 32-pin DQ3 10 DQ4 11 WE 12 A16 24 300 mil SOJ & 400 mil TSOP II VDD 23 DQ6 22 DQ5 21 A8 13 20 A9 A15 14 19 A10 A14 15 18 A11 A13 16 17 A12 Packages J, TP, and SJ Fine Pitch BGA 128K x 8-Bump Configuration 1 2 3 4 5 6 A NC OE A2 A6 A7 NC Description B DQ1 NC A1 A5 CE DQ8 A0–A16 Address input C DQ2 NC A0 A4 NC DQ7 DQ1–DQ8 Data input/output D VSS NC NC A3 NC VDD CE Chip enable input WE Write enable input E VDD NC NC NC NC VSS OE Output enable input F DQ3 NC A14 A11 DQ5 DQ6 VDD +3.3 V power supply G DQ4 NC A15 A12 WE A8 VSS Ground H NC A10 A16 A13 A9 NC NC No connect Pin Descriptions Symbol Rev: 1.04a 10/2002 Package U 6 mm x 8 mm, 0.75 mm Bump Pitch Top View 1/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U Block Diagram A0 Address Input Buffer Row Decoder Memory Array Column Decoder A16 CE WE OE I/O Buffer Control DQ1 DQ8 Truth Table CE OE WE DQ1 to DQ8 VDD Current H X X Not Selected ISB1, ISB2 L L H Read L X L Write L H H High Z IDD Note: X: “H” or “L” Rev: 1.04a 10/2002 2/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD –0.5 to +4.6 V Input Voltage VIN –0.5 to VDD +0.5 (≤ 4.6 V max.) V Output Voltage VOUT –0.5 to VDD +0.5 (≤ 4.6 V max.) V Allowable power dissipation PD 0.7 W Storage temperature TSTG –55 to 150 oC Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for -7/-8/-10/-12 VDD 3.0 3.3 3.6 V Input High Voltage VIH 2.0 — VDD +0.3 V Input Low Voltage VIL –0.3 — 0.8 V Ambient Temperature, Commercial Range TAc 0 — 70 o Ambient Temperature, Industrial Range TAI –40 — 85 oC C Notes: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Rev: 1.04a 10/2002 3/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance CIN VIN = 0 V 5 pF Output Capacitance COUT VOUT = 0 V 7 pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. DC I/O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current IIL VIN = 0 to VDD –1 uA 1 uA Output Leakage Current ILO Output High Z VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –4 mA 2.4 — Output Low Voltage VOL ILO = +4 mA — 0.4 V Power Supply Currents Parameter Symbol Test Conditions IDD CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA Standby Current ISB1 CE ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time Standby Current ISB2 CE ≥ VDD – 0.2 V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V Operating Supply Current Rev: 1.04a 10/2002 0 to 70°C 7 ns 8 ns –40 to 85°C 10 ns 12 ns 7 ns 140 mA 120 mA 95 mA 80 mA 25 mA 20 mA 15 mA 20 mA 10 ns 12 ns 145 mA 125 mA 100 mA 85 mA 30 mA 25 mA 20 mA 2 mA 4/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 8 ns 25 mA 5 mA © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U AC Test Conditions Output Load 1 Parameter Conditions Input high level VIH = 2.4 V Input low level VIL = 0.4 V 50Ω Input rise time tr = 1 V/ns VT = 1.4 V Input fall time tf = 1 V/ns Input reference level 1.4 V Output Load 2 Output reference level 1.4 V 3.3 V Output load Fig. 1& 2 DQ 30pF1 589Ω DQ Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ 5pF1 434Ω AC Characteristics Read Cycle Parameter Symbol Read cycle time -8 -7 -10 -12 Unit Min Max Min Max Min Max Min Max tRC 7 — 8 — 10 — 12 — ns Address access time tAA — 7 — 8 — 10 — 12 ns Chip enable access time (CE) tAC — 7 — 8 — 10 — 12 ns Output enable to output valid (OE) tOE — 3 — 3.5 — 4 — 5 ns Output hold from address change tOH 3 — 3 — 3 — 3 — ns Chip enable to output in low Z (CE) tLZ* 3 — 3 — 3 — 3 — ns Output enable to output in low Z (OE) tOLZ* 0 — 0 — 0 — 0 — ns Chip disable to output in High Z (CE) tHZ* — 3.5 — 4 — 5 — 6 ns Output disable to output in High Z (OE) tOHZ* — 3 — 3.5 — 4 — 5 ns * These parameters are sampled and are not 100% tested Rev: 1.04a 10/2002 5/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U Read Cycle 1: CE = OE = VIL, WE = VIH tRC Address tAA tOH Data Out Previous Data Data valid Read Cycle 2: WE = VIH tRC Address tAA CE tAC tHZ tLZ OE tOE Data Out Rev: 1.04a 10/2002 tOLZ High impedance tOHZ DATA VALID 6/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U Write Cycle Parameter Symbol Write cycle time -7 -8 -10 -12 Unit Min Max Min Max Min Max Min Max tWC 7 — 8 — 10 — 12 — ns Address valid to end of write tAW 5 — 5.5 — 7 — 8 — ns Chip enable to end of write tCW 5 — 5.5 — 7 — 8 — ns Data set up time tDW 3 — 4 — 5 — 6 — ns Data hold time tDH 0 — 0 — 0 — 0 — ns Write pulse width tWP 5 — 5.5 — 7 — 8 — ns Address set up time tAS 0 — 0 — 0 — 0 — ns Write recovery time (WE) tWR 0 — 0 — 0 — 0 — ns Write recovery time (CE) tWR1 0 — 0 — 0 — 0 — ns Output Low Z from end of write tWLZ* 3 — 3 — 3 — 3 — ns Write to output in High Z tWHZ* — 3 — 3.5 — 4 — 5 ns * These parameters are sampled and are not 100% tested Rev: 1.04a 10/2002 7/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U Write Cycle 1: WE control tWC Address tAW tWR OE tCW CE tAS tWP WE tDW Data In tDH DATA VALID tWHZ tWLZ Data Out HIGH IMPEDANCE Write Cycle 2: CE control tWC Address tAW tWR1 OE tAS tCW CE tWP WE tDW Data In DATA VALID Data Out Rev: 1.04a 10/2002 tDH HIGH IMPEDANCE 8/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U 32-Pin SOJ, 400 mil Symbol L D e A A1 A A2 1 GE E HE c y B B1 Detail A Q Dimension in inch Dimension in mm min nom max min nom max A — — 0.146 — — 3.70 A1 0.026 — — 0.66 — — A2 0.105 0.110 0.115 2.67 2.80 2.92 B 0.013 0.017 0.021 0.33 0.43 0.53 B1 0.024 0.028 0.032 0.61 0.71 0.81 c 0.006 0.008 0.012 0.15 0.20 0.30 D 0.820 0.824 0.829 20.83 20.93 21.06 E 0.395 0.400 0.405 10.04 10.16 10.28 e — 0.05 — — 1.27 — HE 0.430 0.435 0.440 10.93 11.05 11.17 GE 0.354 0.366 0.378 9.00 9.30 9.60 L 0.082 — — 2.08 — — y — — 0.004 — — 0.10 Q 0o — 10o 0o — 10o Notes: 1. Dimension D& E do not include interlead flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: inches Rev: 1.04a 10/2002 9/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U 32-Pin TSOP-II, 400mil 1 e E A b Detail A Q L1 y L A1 A A2 ZD Symbol c E1 32 D Dimension in inch Dimension in mm min nom max min nom max A 0.039 — 0.05 — — 1.27 A1 0.002 — 0.006 0.01 — 0.15 A2 0.037 0.040 0.045 0.90 1.02 1.14 b 0.012 0.016 0.018 0.30 0.40 0.45 c 0.0047 0.0051 0.0062 0.12 0.13 0.16 D 0.820 0.825 0.830 20.82 20.95 21.08 ZD — 0.037 — — 0.95 — E 0.455 0.463 0.471 11.56 11.76 11.96 E1 0.395 0.400 0.405 10.03 10.16 10.29 e — 0.05 — — 1.27 — L 0.017 0.020 0.023 0.40 0.50 0.60 L1 0.024 0.031 0.039 0.60 0.80 1.00 y 0.00 — 0.003 0.00 — 0.76 Q 0o — 5o 0o — 5o Notes: 1.Dimension D includes mold flash, protrusions or gate burrs. 2. Dimension E does not include interlead flash 3. Controlling dimension: mm Rev: 1.04a 10/2002 10/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U 6 mm x 8 mm Fine Pitch BGA 0.36(typ) D H G F E D C B A 0.22 ± 0.05 1 0.75(typ). 3.75 3 4 5.25 Rev: 1.04a 10/2002 11/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Ball Dia. 0.35 Pitch 0.75 6 5 Bottom View 2 pin A1 index 1.20(max) pin A1 index units: mm Top View 6.00 ± 0.10 8.00 ± 0.10 0.10 © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U Ordering Information Part Number* Package Access Time Temp. Range GS71108ATP-7 400 mil TSOP-II 7 ns Commercial GS71108ATP-8 400 mil TSOP-II 8 ns Commercial GS71108ATP-10 400 mil TSOP-II 10 ns Commercial GS71108ATP-12 400 mil TSOP-II 12 ns Commercial GS71108ATP-7I 400 mil TSOP-II 7 ns Industrial GS71108ATP-8I 400 mil TSOP-II 8 ns Industrial GS71108ATP-10I 400 mil TSOP-II 10 ns Industrial GS71108ATP-12I 400 mil TSOP-II 12 ns Industrial GS71108ASJ-7 300 mil SOJ 7 ns Commercial GS71108ASJ-8 300 mil SOJ 8 ns Commercial GS71108ASJ-10 300 mil SOJ 10 ns Commercial GS71108ASJ-12 300 mil SOJ 12 ns Commercial GS71108ASJ-7I 300 mil SOJ 7 ns Industrial GS71108ASJ-8I 300 mil SOJ 8 ns Industrial GS71108ASJ-10I 300 mil SOJ 10 ns Industrial GS71108ASJ-12I 300 mil SOJ 12 ns Industrial GS71108AJ-7 400 mil SOJ 7 ns Commercial GS71108AJ-8 400 mil SOJ 8 ns Commercial GS71108AJ-10 400 mil SOJ 10 ns Commercial GS71108AJ-12 400 mil SOJ 12 ns Commercial GS71108AJ-7I 400 mil SOJ 7 ns Industrial GS71108AJ-8I 400 mil SOJ 8 ns Industrial GS71108AJ-10I 400 mil SOJ 10 ns Industrial GS71108AJ-12I 400 mil SOJ 12 ns Industrial Rev: 1.04a 10/2002 12/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Status © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U Ordering Information Part Number* Package Access Time Temp. Range GS71108AU-7 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial GS71108AU-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial GS71108AU-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial GS71108AU-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial GS71108AU-7I 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial GS71108AU-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial GS71108AU-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial GS71108AU-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial Status * Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS71108ATP-8T Rev: 1.04a 10/2002 13/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. GS71108ATP/J/SJ/U 1Mb Asynchronous Datasheet Revision History Rev. Code: Old; New Types of Changes Format or Content Page #/Revisions/Reason • Creation of new datasheet 71108A_r1 71108A_r1; 71108A_r1_01 Content • Added 6 ns speed bin to entire document 71108A_r1_01; 71108A _r1_02 Content • Updated all power numbers • Changed 6 mm x 10 mm package designator from U to X 71108A_r1_02; 71108A _r1_03 Content • Updated Recommended Operating Conditions table on page 3 • Updated Power Supply Currents table • Changed FPBGA package from 6 x 10 to 6 x 8 (package U) 71108A_r1_03; 71108A _r1_04 Content • Removed 6 ns speed bin from entire document • Added 7 ns speed bin to entire document Rev: 1.04a 10/2002 14/14 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc.