HTMOSTM High Temperature Products HIGH TEMPERATURE 32K x 8 STATIC RAM HT6256 FEATURES APPLICATONS • Specified Over -55 to +225°C • Down-Hole Oil Well • Fabricated with HTMOS™ IV Silicon on Insulator (SOI) • Avionics • Read/Write Cycle Times ≤ 50 ns Support 20 MHz Clock • Turbine Engine Control • Asynchronous Operation • Industrial Process Control • CMOS Input/Output Buffers • Nuclear Reactor • Single 5 V ± 10% Power Supply • Electric Power Conversion • Hermetic 28-Lead Ceramic DIP • Heavy Duty Internal Combustion Engines GENERAL DESCRIPTION The 32K x 8 High Temperature Static RAM is a high performance 32,768 word x 8-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell’s HTMOS™ technology, and is designed for use in systems operating in severe high temperature environments. The RAM requires only a single 5 V ± 10% power supply and has CMOS compatible I/O. Power consumption is typically less than 30 mW/MHz in operation, and less than 10 mW when de-selected. The RAM read operation is fully asynchronous, with an associated typical access time of 50 ns at 5 V. PACKAGE PINOUT A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 28 27 3 4 5 6 7 8 9 10 11 12 13 14 26 25 24 23 22 21 20 19 18 17 16 15 Top View VDD NWE A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 The RAM provides guaranteed performance over the full -55 to +225°C temperature range. Typically, parts will operate up to +300°C for a year, with derated performance. All parts are burned in at 250°C to eliminate infant mortality. Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com HT6256 FUNCTIONAL DIAGRAM A:0-8,12-13 32,768 x 8 Memory Array • • • Row Decoder 11 CE* NCS • • • 8 Column Decoder Data Input/Output NWE 8 DQ:0-7 WE • CS • CE NOE NWE • CS • CE • OE (0 = high Z) A:9-11, 14 Signal 1 = enabled # Signal All controls must be enabled for a signal to pass. (#: number of buffers, default = 1) 4 SIGNAL DEFINITIONS A: 0-14 Address input pins which select a particular eight-bit word within the memory array. DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all input buffers. If this signal is not used it must be connected to VSS. NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level NWE allows normal read operation. NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS and NWE. If this signal is not used it must be connected to VSS. CE* External control of Chip Enable is an extra feature available only in other package options. Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the NCS input buffer. If this signal is not used it must be connected to VDD. TRUTH TABLE NCS CE* NWE NOE MODE DQ L H H L Read Data Out L H L X Write Data In H X XX XX Deselected High Z X L XX XX Disabled High Z 2 Notes: X: VI=VIH or VIL XX: VSS≤VI≤VDD NOE=H: High Z output state maintained for NCS=X, CE=X, NWE=X HT6256 ABSOLUTE MAXIMUM RATINGS (1) Rating Symbol Parameter Min Max Units VDD Supply Voltage Range (2) -0.5 6.5 V VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V TSTORE Storage Temperature (Zero Bias) -65 325 °C TSOLDER Soldering Temperature (5 Seconds) 355 °C PD Maximum Power Dissipation (3) 2 W IOUT DC or Average Output Current 25 mA VPROT ESD Input Protection Voltage (4) ΘJC Thermal Resistance (Jct-to-Case) 2000 V 28 DIP °C/W 10 (1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab. RECOMMENDED OPERATING CONDITIONS Description Parameter Symbol Min Typ Max Units VDD Supply Voltage (referenced to VSS) 4.5 5.0 5.5 V TA Ambient Temperature -55 25 225 °C VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V CAPACITANCE (1) Symbol Parameter Typical (2) Worst Case Min Max Units Test Conditions CI Input Capacitance 5 7 pF VI=VDD or VSS, f=1 MHz CO Output Capacitance 7 9 pF VIO=VDD or VSS, f=1 MHz (1) This parameter is tested during initial design characterization only (2) Typical operating conditions: TA= 25°C. DATA RETENTION CHARACTERISTICS (1) Symbol Parameter VDR Data Retention Voltage IDR Data Retention Current Typical Worst Case Min Max 2.5 500 330 (1) Operating conditions: TA= -55°C to +125°C. 3 Units Test Conditions V NCS=VDR VI=VDR or VSS µA µA NCS=VDD=2.5V, VI=VDD or VSS NCS=VDD=3.0V, VI=VDD or VSS HT6256 DC ELECTRICAL CHARACTERISTICS Worst Case (2) Symbol Parameter Test Conditions Typ (1) IDDSB1 Static Supply Current VIH=VDD, IO=0 VIL=VSS, f=0MHz 0.2 2.0 IDDSBMF Standby Supply Current—Deselected NCS=VDD, IO=0, f=40 MHz 0.2 2.0 IDDOPW Dynamic Supply Current—Selected (Write) f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (3) 3.4 4.0 IDDOPR Dynamic Supply Current—Selected (Read) f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (3) 2.8 4.0 II Input Leakage Current VSS IOZ Output Leakage Current VSS VIO VDD Output=high Z V IL Low-Level Input voltage March Pattern 1.7 VIH high-Level Input Voltage March Pattern 3.2 VOL Low-Level Output voltage VD =4.5V, IOL=10 mA (CMOS) VDD=4.5V, IO =200 µA VOH High-Level Output Voltage VDD=4.5V, IOH=-5 mA VDD=4.5V, IOH=-200 µA Min VI VDD (1) Typical operating conditions: VDD= 5.0 V,TA=25°C. (2) Worst case operating conditions: VDD= 5.0 V ±10%, TA=-55°C to +225°C. (3) All inputs switching. DC average current. External control of Chip Enable (CE) is available only in other package options. Max mA mA µA -10 +10 µA 0.3xVdd V V 0.4 0.05 4.2 Vdd-0.05 Vref1 mA +5 0.3 0.005 2.9 V mA -5 0.7xVdd 4.3 4.5 Units + - V V V V Valid high output 249Ω Vref2 DUT output + - Valid low output CL >50 pF* *CL = 5 pF for TWLQZ, TSHQZ, and TGHQZ Tester Equivalent Load Circuit Operating Current vs. Frequency @ 225°C Cycle Times vs. Temperature 30 70 Write Read 50 Read Cycle Time (ns) Operating Current (mA) 60 40 30 25 Write 20 20 10 15 -100 0 0 5 10 15 20 25 Frequency (MHz) 0 100 Temperature (°C) 4 200 300 HT6256 READ CYCLE AC TIMING CHARACTERISTICS (1) Worst Case (3) Symbol Parameter Typical (2) Units Min Max TAVAVR Address Read Cycle Time 50 ns TAVQV Address Access Time TAXQX Address Change to Output Invalid Time TSLQV Chip Select Access Time TSLQX Chip Select Output Enable Time TSHQZ Chip Select Output Disable Time 20 ns TGLQV Output Enable Access Time 15 ns TGLQX Output Enable Output Enable Time TGHQZ Output Enable Output Disable Time TEHQV Chip Enable Output Access Time (4) 17 TEHQX Chip Enable Output enable Time (4) 10 TELQZ Chip Enable Output Disable Time (4) 4 50 3 ns ns 50 5 ns ns 0 ns 15 ns 25 ns 5 ns 10 ns (1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent capacitive output loading CL=5 pF for TSHQZ and TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical). (2) Typical operating conditions: VDD=5.0 V, TA=25°C. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 225°C. (4) External control of Chip Enable (CE) is available only in other package options. TAVAVR ADDRESS TAVQV TAXQX TSLQV NCS TSLQX DATA OUT TSHQZ HIGH IMPEDANCE DATA VALID TEHQX TEHQV CE TELQZ TGLQX TGLQV TGHQZ NOE (NWE = high) 5 HT6256 WRITE CYCLE AC TIMING CHARACTERISTICS (1) Worst Case (3) Symbol Parameters Typical (2) Units Min Max TAVAVW Write Cycle Timing (4) 50 ns TWLWH Write Enable Write Pulse Width 45 ns TSLWH Chip Select to End of Write Time 45 ns TDVWH Data Valid to End of Write Time 35 ns TAVWH Address Valid to End of Write Time 45 ns TWHDX Data Hold Time after End of Write Time 0 ns TAVWL Address Valid Setup to Start of Write Time 0 ns TWHAX Address Valid after End of Write Time 0 ns TWLQZ Write Enable to Output Disable Time 0 TWHQX Write Disable to Ouput Enable Time 5 ns TWHWL Write Disable to Write Enable Pulse Width (5) 5 ns TEHWH Chip Enable to End of Write Time (6) 45 ns 15 ns (1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ. (2) Typical operating conditions: VDD=5.0 V, TA=25°C. (3) Worst case operation conditions: VDD=4.5 V to 5.5 V, -55 to 225°C. (4) TAVAVW = TWLWH + TWHWL (5) Guaranteed but not tested. (6) External control of Chip Enable (CE) is available only in other package options. TAVAVW ADDRESS TAVWH TWHAX TAVWL TWHWL TWLWH NWE TWLQZ DATA OUT TWHQX HIGH IMPEDANCE TDVWH DATA IN DATA VALID TSLWH NCS TEHWH CE 6 TWHDX HT6256 DYNAMIC ELECTRICAL CHARACTERISTICS Read Cycle Write Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (NCS), or chip enable (CE) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high. The output drivers can be controlled independently by the NOE signal. Consecutive read cycles can be executed with NCS held continuously low, and with CE held continuously high, and toggling the addresses. The write operation is synchronous with respect to the address bits, and control is governed by write enable (NWE), chip select (NCS), or chip enable (CE) edge transitions (refer to Write Cycle timing diagrams). To perform a write operation, both NWE and NCS must be low, and CE must be high. Consecutive write cycles can be performed with NWE or NCS held continuously low, or CE held continuously high. At least one of the control signals must transition to the opposite state between consecutive write operations. For an address activated read cycle, NCS and CE must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is TAVAV. When the RAM is operated at the minimum address activated read cycle time, the data outputs will remain valid on the RAM I/O until TAXQX time following the next sequential address transition. The write mode can be controlled via three different control signals: NWE, NCS, and CE. All three modes of control are similar except the NCS and CE controlled modes actually disable the RAM during the write recovery pulse. Both CE and NCS fully disable the RAM decode logic and input buffers for power savings. Only the NWE controlled mode is shown in the table and diagram on the previous page for simplicity. However, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. To control a read cycle with NCS, all addresses and CE must be valid prior to or coincident with the enabling NCS edge transition. Address or CE edge transitions can occur later than the specified setup times to NCS, however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NCS is low, will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TSHQZ time following a disabling NCS edge transition. To write data into the RAM, NWE and NCS must be held low and CE must be held high for at least TWLWH/TSLSH/ TEHEL time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. For consecutive write operations, write pulses must be separated by the minimum specified TWHWL/TSHSL/TELEH time. Address inputs must be valid at least TAVWL/TAVSL/TAVEH time before the enabling NWE/NCS/CE edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/TDVEL, and an address valid to end of write time of TAVWH/TAVSH/ TAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS/CE edge transition must be a minimum of TWHAX/TSHAX/TELAX time and TWHDX/ TSHDX/TELDX time, respectively. The minimum write cycle time is TAVAV. To control a read cycle with CE, all addresses and NCS must be valid prior to or coincident with the enabling CE edge transition. Address or NCS edge transitions can occur later than the specified setup times to CE; however, the valid data access time will be delayed. Any address edge transition which occurs during the time when CE is high will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TELQZ time following a disabling CE edge transition. 7 HT6256 QUALITY ASSURANCE nature. Reliability attributes of the HTMOS process were characterized by testing test structures from which specific failure mechanisms were evaluated. These specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure reliable -55 to +225°C specified products. Honeywell maintains a high level of product integrity through process control utilizing statistical process control, a complete “Total Quality Assurance System,” and a computer data base process performance tracking system. This Total Quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and continuing through product qualification and screening. PACKAGING The standard package is a hermetic 28-lead DIP constructed of multilayer ceramic (Al2O3) and features internal power and ground planes. Ceramic chip capacitors can be mounted to the package by the user to maximize supply noise decoupling and increase board packing density. These capacitors connect to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package. For packaging options with surface mount capability or external control of Chip Enable (CE), call Honeywell. SCREENING LEVELS Honeywell offers several levels of device screening to meet your system needs. Hi-Rel Level B devices undergo additional screening per the requirements of MIL-STD-883. RELIABILITY Honeywell understands the stringent reliability requirements for extreme environment systems and has extensive experience in reliability testing on programs of this 28-LEAD DIP PACKAGE C D Z All dimensions in inches Y Right Reading on Lid Ceramic Body E 1 Optional Capacitors X S2 A Q L b2 S1 b (width) e (pitch) eA A b b2 C D E e eA L Q S1 S2 X Y Z 0.175 (max) 0.018 ± 0.002 0.050 (typ) 0.010 to 0.002 1.400 ± 0.014 0.594 ± 0.010 0.100 ±0.005 0.600 ±0.010 0.125 to 0.175 0.050 ±0.010 0.005 (min) 0.005 (min) 0.100 ref 0.050 ref 0.075 ref ORDERING INFORMATION (1) HT6256DC C - Indicates screening level B = High Temperature Class B C = Commercial D - Indicates package type D = 28-Lead DIP For packaging options, call Honeywell (1) Orders may be faxed to 612-954-2257. Please contact our Customer Service Department at 612-954-2888 for further information. To learn more about Honeywell Solid State Electronics Center, visit our web site at http://www.ssec.honeywell.com Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. 900202 Rev. B 4-98 8 Helping You Control Your World