MIC5400 Micrel MIC5400 Dual, 8-Output, 14-Bit LED Video Display Driver General Description Features The MIC5400 consists of 2 banks of 8 LED driver outputs, each output capable of sinking up to 30mA. Each bank is intended to drive 8 LED pixels of the same color. Most applications will use the MIC5400 to drive pixel clusters of 4 LEDs (RRGB.) Typically two red LEDs are used for every one green and blue to compensate for red LED brightness. A single external resistor sets maximum drive current. Use of an external resistor allows different color LED banks to be biased to the same intensity. Brightness control is digitally programmed through the serial interface. Coarse Brightness Control is determined by two 4-bit DACs, one for each driver bank, limiting the full-scale output to a fraction of the maximum value. Additionally, each output has Fine Brightness Control using 10-bit resolution PWM. Groups of drivers can be cascaded in Daisy Chain fashion. Open circuit output faults are detected and can be read back from the internal Status register. • 2 banks of 8 outputs • Output characteristics: • Current sink: 30mA – Programmable brightness control • Coarse: 4-bit resolution DAC • Fine: 10-bit resolution PWM – Resistor sets maximum LED current to compensate variation in LEDs – Current limit on each output • Full protection: – Over-temperature shutdown – Watchdog disables output under fault condition – Power-on reset (all LEDs Off) – Soft-start on power up and watchdog recovery – Output open fault detection with status register readback • Output transitions are staggered to minimize supply transients Applications • Outdoor video screen • Large LED display Ordering Information Part Number Junction Temp. Range Package MIC5400BWM –40°C to +85°C 28-Pin Wide SOIC MIC5400YWM –40°C to +85°C 28-Pin Wide SOIC Typical Application " )*+ MIC5400 ''( "& )*+ % ! "#$# ''( % " Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com January 2005 1 MIC5400 MIC5400 Micrel Pin Configuration A4 1 28 A5 A3 2 27 A6 A2 3 26 A7 A1 4 25 A8 LOAD 5 24 VDDA SHFTCLK 6 23 BD_A VDD 7 22 GND GND 8 21 IREF SHIFTIN 9 20 BD_B SHIFTOUT 10 19 VDDB B1 11 18 B8 B2 12 17 B7 B3 13 16 B6 B4 14 15 B5 28-Lead SOIC Pin Description Pin Number Pin Name Pin Name 1,2,3,4 A4,A3,A2,A1 5 LOAD 6 SHFTCLK Shift-register Clock Input 7 VDD Positive Supply Voltage 8,22 GND Ground 9 SHIFTIN 10 SHIFTOUT 11,12,13,14 B1,B2,B3,B4 Current Sink pins to be connected to LED cathodes 15,16,17,18 B5,B6,B7,B8 Current Sink pins to be connected to LED cathodes 19 VDDB Analog Power source pins which provide current sense points for Channel A and Channel B PNP emitter currents, independently. 20 BD_B Base Drive Outputs for external PNP transistors. Feedback Loop compensation requires one external capacitor at each PNP transistor collector. 21 REF 23 BD_A Base Drive Outputs for external PNP transistors. Feedback Loop compensation requires one external capacitor at each PNP transistor collector. 24 VDDA Analog Power source pins which provide current sense points for Channel A and Channel B PNP emitter currents, independently. 25,26,27,28 A8,A7,A6,A5 MIC5400 Pin Function Function Current Sink pins to be connected to LED cathodes If this pin is Low, the device acts as a shift register. When this pin is High, only the first falling edge of the clock transfers data from the Shift-Register to the Parallel Register. The next rising edge transfers data from the Status Register to the Shift Register Shift-register Data Input Shift-register Data Output Reference current output. Must be connected to an external resistor to set the maximum current for the current sink outputs. Current Sink pins to be connected to LED cathodes 2 January 2005 MIC5400 Micrel Absolute Maximum Ratings (Note 1) Operating Ratings (Note 2) Supply Voltage .............................................................. +7V Input Voltage ....................................... –0.3V to VCC + 0.3V Base Drive Voltage ....................................................... +7V Output Sink Current (per output) ................................ 35mA Lead Temperature (soldering, 5 sec) ........................ 260°C Junction Temperature (TJ)(max) ............................... 125°C Supply Voltage (VCC) ................................ +4.75V to +5.5V Junction Temperature (TJ) ....................... –40°C to +125°C Package Thermal Resistance SOIC (θJC) .......................................................... 28°C/W SOIC (θJA) ......................................................... 100°C/W DC Electrical Characteristics VDD = 4.75V to 5.5 V, TA = 25°C, bold values indicate –40°C ≤ TA ≤ +85°C. RBIAS = 500Ω. Applies to all channels unless noted. Symbol Parameter Condition IOUT Output Sink Current ∆IOUT Output Current Matching IOUT(OFF) Output Off Leakage VOUT = 5V IDD Supply Current IB Min Typ Max Units 35 mA 7 % –1 1 µA VDD = 5.5V 0 2 mA PNP Base Drive Current VBD = 4V 7 50 mA VREF Reference Output Voltage IREF = –4mA 1.9 2.1 V VIH Logic 1 Input Threshold VIL Logic 0 Input Threshold VOH Logic 1 Output Level ILOAD = 1mA VOL Logic 0 Output Level ILOAD = 1mA TSHUTDOWN Thermal Shutdown Temperature 26 2.2 V 0.8 2.4 V V 0.4 165 V °C AC Electrical Characteristics VDD = 4.75V to 5.5V, TA = 25°C, bold values indicate –40°C ≤ TA ≤ +85°C. RBIAS = 500Ω. Applies to all channels unless noted Symbol Parameter Conditions Min Typ Max Units fSHIFT Shift Frequency 15 tSET-DATA Set Up Time for Data In Note 5 7 ns tHOLD-DATA Hold Time for Data In Note 5 13 ns tSET-LOAD Set Up Time for Load Note 5 20 ns tHOLD-LOAD Hold Time for Load Note 5 13 ns IOUT(tr) Rise Time IOUT Note 4, 5 125 ns IOUT(ttf) Fall Time IOUT Note 4, 5 50 ns tD-SHIFT Clock to Shift Out Delay Rise and Fall, 50% CLOAD = 30pF, Note 5 23 ns tr,f-OUT Shift Out Rise and Fall Time 10% to 90%; CLOAD =30pF, Note 5 10 ns tWD-TIMEOUT Watch Dog Timeout Delay No Shiftclock 200 µs tr,f[in] Logic Input Rise and Fall Times 10 ns 25 Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Note 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. Note 4. Test circuit shown in Figure 1. Note 5. Guaranteed by design; not production tested. January 2005 3 MHz MIC5400 MIC5400 Micrel Test Circuit VDD = 5V 75Ω Device Under Test Controller OUTN VOUT to FET Probe (C < 1.5pF) Figure 1. AC Output Test Circuit Timing Diagrams SHFTCLK LOAD Control Register Contents Shifting Shift Register Contents Status Register Contents DN-1 DN DN DN SN SN SN Shifting SN SN+1 Figure 2. MIC5400 Timing Diagram Linearity Typical Global Full Scale Linearity (any output) 45 40 Linear Operating Region (Recommended) IOUT ( mA ) 35 30 Non-Linear Operation 25 20 15 TJ = 25° 10 5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 IREF (mA) Figure 3. Typical Global Full Scale Linearity MIC5400 4 January 2005 MIC5400 Micrel Functional Diagram PWM Select (3 Bits) PWM Select Select 1 of 8 in Bank A/B PWM 1 Out 1A PWM 2 Out 2A PWM Data B (10 Bits) PWM 3 Out 3A Watchdog Enable (1 Bits) PWM 4 Out 4A PWM 5 Out 5A PWM 6 Out 6A PWM 7 Out 7A PWM 8 Out 8A PWM 1 Out 1B PWM 2 Out 2B Mask Rev. (3 Bits) PWM 3 Out 3B Fixed Pattern (15 Bits) PWM 4 Out 4B PWM 5 Out 5B PWM 6 Out 6B PWM 7 Out 7B PWM 8 Out 8B PWM Data A (10 Bits) Data and Control Register (36 bits) Divisor (4 Bits) IREF A DAC A (4 Bits) DAC B (4 Bits) 2X4-bit Brightness DAC IREF B Status A (8 Bits) Status B (8 Bits) Watchdog Status (1 Bits) Status Register (36 bits) SHIFTIN 36 Bit Shift Register SHFTCLK Thermal Status (1 Bits) SHIFTOUT LOAD MIC5400 Functional Diagram January 2005 5 MIC5400 MIC5400 Micrel Address 3 Bits Q1 to Q3 [Q1 = LSB] Data A 10 bits Q4 to Q13 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 MIC5400 Data B 10 Bits Q14 to Q23 Watchdog 1 Bit Q24 Divisor 4 Bits Q25 to Q28 DAC B 4 Bits Q29 to Q32 DAC B 4 Bits Q33 to Q36 Description Address bit 1 Address Bit 2 Address Bit 3 Data A Bit 1 Data A Bit 2 Data A Bit 3 Data A Bit 4 Data A Bit 5 Data A Bit 6 Data A Bit 7 Data A Bit 8 Data A Bit 9 Data A Bit 10 Data B Bit 1 Data B Bit 2 Data B Bit 3 Data B Bit 4 Data B Bit 5 Data B Bit 6 Data B Bit 7 Data B Bit 8 Data B Bit 9 Data B Bit 10 Watchdog Bit [Disable = 1] Divisor Bit 1 Divisor Bit 2 Divisor Bit 3 Divisor Bit 4 DAC A Bit 1 DAC A Bit 2 DAC A Bit 3 DAC A Bit 4 DAC B Bit 1 DAC B Bit 2 DAC B Bit 3 DAC B Bit 4 Table 1. Shift Register Data Format 6 January 2005 MIC5400 Micrel Status A Status B Watchdog Thermal [1 = Open Circuit] [1 = Open Circuit] [1 = Timeout] [1 = Overtemp] 8 Bits D1-D8 8 Bits D9-D16 1 Bit D17 1 Bit D18 Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 January 2005 Mask Revision Alternating Bits 3 Bits D19 to D21 15 Fixed Bits D22 to D36 Description Status A - Bit 1 (Output Open Circuit = 0) Status A - Bit 2 (Output Open Circuit = 0) Status A - Bit 3 (Output Open Circuit = 0) Status A - Bit 4 (Output Open Circuit = 0) Status A - Bit 5 (Output Open Circuit = 0) Status A - Bit 6 (Output Open Circuit = 0) Status A - Bit 7 (Output Open Circuit = 0) Status A - Bit 8 (Output Open Circuit = 0) Status B - Bit 1 (Output Open Circuit = 0) Status B - Bit 2 (Output Open Circuit = 0) Status B - Bit 3 (Output Open Circuit = 0) Status B - Bit 4 (Output Open Circuit = 0) Status B - Bit 5 (Output Open Circuit = 0) Status B - Bit 6 (Output Open Circuit = 0) Status B - Bit 7 (Output Open Circuit = 0) Status B - Bit 8 (Output Open Circuit = 0) Watchdog Status [0 = Normal, 1 = Time Out] Thermal Status [0 = Normal, 1 = Overtemp] Mask Revision Bit 1 Mask Revision Bit 2 Mask Revision Bit 3 0 [Fixed Pattern Filler Bits] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Table 2. Status Word Format 7 MIC5400 MIC5400 Micrel Applications Information Output Current Drive The MIC5400 includes several ways to program LED output current. These output current controls are superimposed and have an additive effect on LED output current as follows: Global Full Scale Current Limit: This function sets the Global Full Scale (GFS) current at each of the outputs. The GFS value current is about 8.1 times ISET. ISET is the current through the single resistor, RBIAS, connected from VREF to Ground. VREF is regulated to 2V (nominal) so: ISET = As a result of the 25 microsecond minimum watchdog timeout delay, the lower limit of clock frequency is 40kHz. The thermal shutdown typically activates if the die temperature exceeds 165°C. Thermal shutdown shuts off all outputs and sets the Thermal status bit to logic 1 if overtemperature is detected. Thermal status is read back from status word bit D18. External PNP Transistors The external PNPs have a dual role. As part of a voltage regulator loop they aid in limiting package power dissipation. Sensing current in the PNP emitters also allows setting an overall limit to the current available to one bank of 8 LEDs. Power dissipation: The regulator loop controls the voltage at the LED drive output to limit power dissipation. The outputs are typically controlled to 1.1V. A 2.2 µF capactor is required at the collector of each PNP for frequency compensation. PNP Current Limit The current limit of the external PNP can be set by conncting a sense resistor RCS from VDD to VDDA and VDDB respectively. The current limit is: VREF ( 2V ) [8.1] × [2V] = and GFS= RBIAS RBIAS RBIAS For RBIAS = 500Ω, GFS = ≈32.4mA The recommended value for ISET is 4mA or less for linear operation. See Figure 3. Brightness Control Brightness contol is provided by two, 4-bit DACs, one DAC for each of the two output banks of 8 outputs. The output current is varied between 0*GFS and (15/16) *GFS in 15 equal steps based on the 4 Bit DAC code from the shift register Data Word; Bits Q29 -Q32 control Output Bank A and Bits QA3336 control Output Bank B. (See Table 1: Data Word Format). Watchdog Status is read back from Status Word Bit Q17. Thermal Status is read from Status Word Bit Q18. Output Intensity Each LED Output intensity is further controlled by a Pulse Width Modulator providing 10-bit resolution intensity variation. One LED output per bank can be set up for each Data Word. A 3-bit address selects 1 of the 8 PWMs for each of the two output banks. Programming bits Q1-Q3 determine the PWM address, bits Q4-Q13 control the PWMs driving Bank A, bits Q14-Q23 control the PWMs driving Bank B. The PWM is created by comparing the count of a 10-bit counter with the 10-bit programming word. If the count output is greater than the programming word, the output is “OFF”. The PWM frequency is also programmable, in ratio to the frequency of the shift register clock. The ratio value is set by the Divisor, loaded into bits Q25-Q28 of the Data Word. See Table 3. Watchdog and Thermal Shutdown The MIC5400 incorporates both a watchdog and thermal shutdown. The watchdog shuts off all outputs and sets watchdog status bit to logic 1 if the shift clock is absent for more than 200 microseconds. Watchdog status remains logic 0 for shift clocks more frequent than 25 microseconds. The watchdog is enabled by data word bit Q24. Watchdog status is read back from status word bit D17. 48mV ILIM = R SC If current limit is not used, short VDDA and VDDB to VDD. Daisy Chains Parts may be cascaded in groups of arbitrary size. The SHIFTOUT pin of one part is connected to the SHIFTIN pin of the following part. Data bit 36 is the first bit data to be shifted in. Status bit 36 is the first status bit to be shifted out. (See Table 1 and Table 2) When loading the 36-bit data words, the user must keep track of the number of SHIFTCLOCK cycles to determine when data is aligned for transfer to the control and PWM registers. For example, if one daisy chains 10 parts, 360 SHIFTCLK cycles are required to clock in all the data words. LOAD and the Data/Control and Status Registers: When LOAD is low, the MIC5400 acts as a 36-bit shift register. When LOAD goes high, the part no longer shifts data. Data is transferred from the Shift Register to the parallel control registers on the first falling edge of SHIFTCLK after LOAD goes high. While LOAD remains high, the next rising edge of SHIFTCLOCK transfers data from the status registers to the shift register. The first status bit to appear on SHIFTOUT is Status Filler Bit 36 (Logic 0). See Table 2 for description and Figure 2 for timing. Status A or Status B = 0 if the output is open circuit, i.e., open LED. After LOAD returns low, normal shift register operation resumes and status data is shifted out as new data words are shifted in on the rising edge of SHIFTCLK. Divisor Code 0 1 2 3 4 5 6 7 8 9 A B C D E F Divide by R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Table 3. PWM Clock Ratio to Shift Clock [PWM Clock Freq. = (Shift Clock Freq)/R] MIC5400 8 January 2005 Micrel (1V/div) (1V/div) (2V/div) MIC5400 TIME (2.5ns/div) TIME (2.5ns/div) Clock to Shiftout Delay Time (1V/div) Output Current Sink Rise Time TIME (2.5ns/div) Output Current Sink Fall Time January 2005 9 MIC5400 MIC5400 Micrel Package Information Rev. 02 28-Pin Wide SOIC MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. MIC5400 10 January 2005