NSC LP5526TLX

LP5526
Lighting Management Unit with High Voltage Boost
Converter with up to 150mA Serial FLASH LED Driver
General Description
Features
LP5526 is a Lighting Management Unit for portable applications. It is used to drive display backlights, keypad LEDs,
RGB LEDs and camera flash LEDs. LP5526 can drive 2
separately connected strings of LEDs with high voltage
boost converter. The RGB driver allows driving either individual color LEDs or RGB LED from separate supply power,
or it can be used to drive series connecter flash LEDs from
high voltage boost converter.
The backlight drivers (MAIN and SUB pins) are both high
resolution constant current mode drivers. The flash outputs
can drive series connected flash LED with up to 150mA of
current. External PWM control can be used for dimming any
selected LED outputs or it can be used to trigger the flash.
The flash has also 1-second safety timer.
The device is controlled through 2-wire low voltage I2C
compatible interface that reduces the number of required
connections.
n High efficiency boost converter with programmable
output voltage up to 20V
n 2 individual drivers for serial display backlight LEDs
n Automatic dimming controller
n Stand alone RGB controller
n Dedicated flash function
n Safety function to avoid prolonged flash
n 3 general purpose IO pins
n 25-bump micro SMD Package: (2.54mm x 2.54mm x
0.6mm)
Applications
n Cellular Phones and PDAs
n MP3 Players
n Digital Cameras
Typical Application
20179770
© 2006 National Semiconductor Corporation
DS201797
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LP5526 Lighting Management Unit with High Voltage Boost Converter with up to 150mA Serial
FLASH LED Driver
March 2006
LP5526
Typical Application
(Continued)
20179701
Connection Diagrams
25-Bump Thin Micro SMD Package, Large Bump
NS Package Number TLA25CCA
20179772
20179771
Bottom View
Top View
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2
LP5526
Pin Descriptions
Pin #
Name
Type
Description
5E
SW
Output
5D
FB
Input
Boost Converter Power Switch
5C
RLED
Output
Red LED Output (Current Sink / Open Drain Switch)
5B
GLED
Output
Green LED Output (Current Sink / Open Drain Switch)
Boost Converter Feedback
5A
BLED
Output
Blue LED Output (Current Sink / Open Drain Switch)
4E
GND_SW
Ground
Power Switch Ground
4D
NRST
Input
4C
SCL
Logic Input
External Reset, Active Low
Clock Input for I2C Compatible Interface
4B
IRGB
Input
4A
GND_RGB
Ground
Ground for RGB LED Currents
External RGB LED Maximum Current Set Resistor
3E
VDD2
Power
Supply Voltage 3.0...5.5 V
3D
VDDIO
Power
3C
SDA
Logic Input/Output
Data Input/Output for I2C Compatible Interface
3B
GPIO[2]
Logic Input/Output
General Purpose Logic Input/Output
3A
GPIO[0] / PWM
Logic Input/Output
General Purpose Logic Input/Output / External PWM Input
2E
GND_WLED
Ground
Ground for White LED Currents (MAIN and SUB Outputs)
2D
GNDT
Ground
Ground
Supply Voltage for Digital Input/Output Buffers and Drivers
2C
VDD1
Power
Supply Voltage 3.0...5.5 V
2B
VREF
Output
Reference Voltage (1.23V)
2A
GPIO[1]
Logic Input/Output
1E
MAIN
Output
MAIN Display White LED Current Output (Current Sink)
1D
SUB
Output
SUB Display White LED Current Output (Current Sink)
1C
VDDA
Output
Internal LDO Output (2.80V)
1B
GND
Ground
Ground for Core Circuitry
1A
IRT
Input
General Purpose Logic Input/Output
Oscillator Frequency Set Resistor
Package Mark
20179796
Ordering Information
Order Number
Package Marking
Supplied As
Spec/Flow
LP5526TL
LP5526TLX
5526
TNR 250
NoPb
5526
TNR 3000
NoPb
3
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LP5526
Absolute Maximum Ratings
Operating Ratings (Notes 1, 2)
(Notes 1,
2)
V (SW, FB, MAIN, SUB)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VDD1,2
3.0 to 5.5V
VDDIO
1.65V to VDD1
V (SW, FB, MAIN, SUB, RLED,
GLED, BLED)
-0.3V to +23V
Recommended Load Current
(RLED, GLED, BLED) CC Mode
VDD1, VDD2, VDDIO, VDDA
-0.3V to +6.0V
Recommended Total Boost
Converter Load Current
Voltage on IRGB, IRT, VREF
Voltage on Logic Pins
I (VREF)
I(RLED, GLED, BLED)
-0.3V to VDD1+0.3V
with 6.0V max
-0.3V to VDDIO +0.3V
with 6.0V max
10µA
Internally Limited
Junction Temperature (TJ-MAX)
125oC
Storage Temperature Range
-65oC to +150oC
Maximum Lead Temperature
(Soldering) (Note 4)
260oC
Machine Model:
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0mA to 150mA
Junction Temperature (TJ) Range
-30oC to +125oC
Ambient Temperature (TA) Range
(Note 6)
-30oC to +85oC
Junction-to-Ambient Thermal
Resistance(θJA), TLA25 Package
(Note 7)
ESD Rating (Note 5)
Human Body Model:
0mA to 50mA/driver
Thermal Properties
100mA
Continuous Power Dissipation
(Note 3)
0 to +21V
2kV
200V
4
60 - 100oC/W
Limits in standard typeface are for TJ = 25o C. Limits in boldface type apply over the operating ambient temperature range
(-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP5526 Block Diagram with: VDD1,2 = 3.0 ... 5.5V,
CVDD = CVDDIO = 100nF, COUT = 2 x 4.7µF, CIN = 10µF, CVDDA = 1µF, CVREF = 100nF, L1 = 10µH, RRGB = 2.4kΩ and RRT =
82kΩ (Note 9).
Symbol
IVDD
VDDA
Typ
Max
Units
Standby supply current
(VDD1, VDD2)
Parameter
NSTBY = L
Register 0DH=08H (Note 10)
Condition
Min
1.7
7
µA
No-boost supply current
(VDD1, VDD2)
NSTBY = H,
EN_BOOST = L
300
800
µA
No-load supply current
(VDD1, VDD2)
NSTBY = H, EN_BOOST = H
Autoload OFF
780
1300
uA
Output voltage of internal LDO
IVDDA = 1mA
+3
%
2.80
-3
VREF
Reference voltage (Note 11)
1.23
V
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150oC (typ.) and disengages at
TJ=130oC (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip Scale
Package
Note 5: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125oC), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Note 10: Boost output voltage set to 8V (08H in register 0DH) to prevent any unneccessary current consumption.
Note 11: No external loading allowed for VREF pin.
5
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LP5526
Electrical Characteristics (Notes 2, 8)
LP5526
Block Diagram
20179774
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6
RESET:
In the RESET mode all the internal registers are reset to the default values. Reset is entered always if input
NRST is LOW or internal Power On Reset is active. Power On Reset (POR) will activate during the chip
startup or when the supply voltages VDD1 and VDD2 fall below 1.5V. Once VDD1 and VDD2 rises above 1.5V,
POR will inactivate and the chip will continue to the STANDBY mode. NSTBY control bit is low after POR
by default.
STANDBY:
The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the low
power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and
the control bits are effective immediately after start up.
STARTUP:
When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal
blocks (VREF, Bias, Oscillator etc.). To ensure the correct oscillator initialization, a 10ms delay is generated
by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables
the chip operation and STARTUP mode is entered until no thermal shutdown event is present.
BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in low
current PWM mode during the 20ms delay generated by the state-machine. All LED outputs are off during
the 20ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if
EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH.
NORMAL:
During NORMAL mode the user controls the chip using the Control Registers. The registers can be written
in any sequence and any number of bits can be altered in a register in one write.
20179775
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LP5526
Modes of Operation
LP5526
excess charge from the output capacitor at very light loads.
Active load can be disabled by writing the EN_AUTOLOAD
bit low. Disabling active load will increase slightly the efficiency at light loads, but the downside is that pulse skipping
will occur. The Boost Converter should be stopped and set to
8V when there is no load to minimize the current consumption.
The topology of the magnetic boost converter is called CPM
control, current programmed mode, where the inductor current is measured and controlled with the feedback. The user
can program the output voltage of the boost converter. The
output voltage control changes the resistor divider in the
feedback loop. The following figure shows the boost topology with the protection circuitry. Four different protection
schemes are implemented:
Power-Up Sequence
When powering up the device, VDD1 and VDD2 should be
greater than VDDIO to prevent any damage to the device.
20179776
Magnetic Boost DC/DC Converter
The LP5526 Boost DC/DC Converter generates an 8…20V
supply voltage for the LEDs from single Li-Ion battery
(3V…4.5V). The output voltage is controlled with an 8-bit
register in 12 steps. The converter is a magnetic switching
PWM mode DC/DC converter with a current limit. Switching
frequency is 1MHz, when timing resistor RT is 82kΩ. Timing
resistor defines the internal oscillator frequency and thus
directly affects boost frequency and RGB timings.
EMI filter (RSW and CSW) on the SW pin can be used to
suppress EMI caused by fast switching. These components
should be as near as possible to the SW pin to ensure
reliable operation. The LP5526 Boost Converter uses pulseskipping elimination to stabilize the noise spectrum. Even
with light load or no load a minimum length current pulse is
fed to the inductor. An active load is used to remove the
1.
Over voltage protection, limits the maximum output voltage
— Keeps the output below breakdown voltage.
— Prevents boost operation if battery voltage is much
higher than desired output.
2.
Over current protection, limits the maximum inductor
current
— Voltage over switching NMOS is monitored; too high
voltages turn the switch off.
3.
Feedback break protection. Prevents uncontrolled operation if FB pin gets disconnected.
4. Duty cycle limiting, done with digital control.
20179777
Boost Converter Topology
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8
LP5526
Magnetic Boost DC/DC Converter
(Continued)
MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
Symbol
ILOAD
Parameter
Maximum Non-Continuous
Load Current
Conditions
3.2V < VIN
VOUT = 20V
150
100
3.0V = VIN
VOUT = 20V
VOUT
Output Voltage Accuracy
(FB Pin)
3.0V ≤ VIN ≤ 5.5V
VOUT = 20V
RDSON
Switch ON Resistance
ISW = 0.5A
fPWM
PWM Mode Switching
Frequency
RT = 82 kΩ
Frequency Accuracy
RT = 82 kΩ
tSTARTUP Startup Time
IMAX
Max
140
Maximum Continuous Load
Current
Switch Pulse Minimum
Width
Typ
3.0V ≤ VIN ≤ 3.2V
VOUT = 20V
ILOAD
tPULSE
Min
Units
mA
−2.3
-1.7
0.15
+2.3
+1.7
%
0.3
Ω
1.0
MHz
−7
+7
−9
+9
%
no load
45
ns
Boost startup from STANDBY to VOUT
= 20V, no load
15
ms
SW Pin Current Limit
1500
1850
mA
Note: Maximum non-continuous currents rates as short pulses (t < 1s). Exposure to maximum rating conditions for extended periods may affect device reliability.
BOOST STANDBY MODE
User can set the Boost Converter to STANDBY mode by
writing the register bit EN_BOOST low. When EN_BOOST is
written high, the converter starts for 20ms in low current
PWM mode and then goes to normal PWM mode. All LED
outputs are off during the 20ms delay to ensure smooth
startup.
BOOST OUTPUT VOLTAGE CONTROL
User can control the boost output voltage by Boost Output
8-bit register.
Boost Output [7:0]
Register 0DH
Bin
Dec
0000 1000
8
Boost Output Voltage Control
Boost Output
Voltage (typical)
8.0V
0000 1001
9
9.0V
0000 1010
10
10.0V
0000 1011
11
11.0V
0000 1100
12
12.0V
0000 1101
13
13.0V
0000 1110
14
14.0V
0000 1111
15
15.0V
0001 0000
16
16.0V
0001 0001
17
17.0V
0001 0010
18
18.0V
0001 0011
19
19.0V
0001 0100
20
20.0V
20179778
If register value is lower than 8, then value of 8 is used
internally.
If register value is higher than 20, then value of 20 is used
internally.
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LP5526
Boost Converter Typical Performance Characteristics
Vin = 3.6V, Vout = 20.0V if not otherwise stated
Boost Converter Efficiency
Boost Typical Waveforms at 150mA Load
20179779
20179780
Battery Current vs Voltage
Boost Output Voltage vs. Current
20179781
20179782
Boost Line Regulation 3.0V - 3.6V, no load
Boost Turn On Time with No Load
20179783
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20179784
10
Boost Load Transient Response 50mA – 150mA
LP5526
Boost Converter Typical Performance Characteristics
(Continued)
Autoload Effect on Input Current, No Load
20179785
20179786
Boost Maximum Current vs. Output Voltage
20179795
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LP5526
Functionality of Color LED
Outputs (RLED, GLED, BLED)
CONTROL REGISTER (00H)
Name
Bit
LP5526 has one RGB/color LED output, consisting of three
individual LED output pins. Output pins can be used in
switch mode or constant current mode. Output mode can be
selected with the control register (address 00H) bit CC_SW.
If the bit is set high, then RGB outputs are in switch mode,
otherwise in constant current mode. These modes are described later in separate chapters.
RGB_PWM
7
0 = Internal PWM control disabled
1 = Internal PWM control enabled
EN_RGB
6
0 = RGB outputs disabled
1 = RGB outputs enabled
CC_SW
5
0 = Constant current sink mode
1 = Switch mode
RGB LED output control can be done in three ways:
1. Defining the expected color and brightness with internal
PWM in RGB register (address 01H)
RSW
3
0 = RLED disabled
1 = RLED enabled
GSW
2
0 = GLED disabled
1 = GLED enabled
BSW
1
0 = BLED disabled
1 = BLED enabled
COLOR[3:0]
7:4
Color for RGB LED output
BRIGHT[2:0]
3:1
Brightness control
OVL
0
2.
Direct setting each LED ON/OFF via RGB Control register (address 00H)
3.
External PWM control
Description
RGB REGISTER (01H)
1. BRIGHTNESS CONTROL WITH RGB REGISTER
If the RGB LED output is used by defining the balance and
brightness in the RGB register, then one needs to set EN_RGB bit high and RGB_PWM bit high in the Control register
(address 00H). RSW, GSW and BSW are used to enable
each LED output, enabled when written high. CC_SW defines the LED output mode. A single register is used for
defining the color and brightness for the RGB LED output.
OVL bit selects overlapping/non-overlapping mode. Overlapping mode is selected when OVL = 1.
0 = Non-overlapping mode
1 = Overlapping mode
Brightness control is logarithmic and is programmed as follows:
Bright[2:0]
Brightness [%]
Ratio to max
brightness
000
0
0
001
1.56
1/64
010
3.12
1/32
011
6.25
1/16
100
12.5
1/8
101
25
1/4
110
50
1/2
111
100
1/1
16 colors can be selected as follows. Please note that exact color depends on RGB LED current and type. Color setting is
valid only in non-overlapping mode.
COLOR[3:0]
RED
active [%]
GREEN
active [%]
BLUE
active [%]
0000
0001
100
0
0
red
0
100
0
green
0010
0
0
100
blue
0011
50
50
0
yellow
0100
0
50
50
cyan
0101
50
0
50
magenta
0110
33
33
33
white
0111
50
25
25
pink
1000
25
50
25
light green
1001
25
50
25
light blue
1010
25
25
50
orange
1011
75
25
0
deep pink
1100
0
75
25
spring green
1101
25
75
0
lawn green
1110
0
25
75
sky blue
1111
25
0
75
indigo
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RGB COLOR
LP5526
Functionality of Color LED Outputs (RLED, GLED, BLED)
(Continued)
Overlapping Mode
In overlapping mode the brightness is controlled using PWM
duty cycle based control method as the following figure
shows.
20179787
Overlapping Mode
Since RGB outputs are on simuneltaneously, the maximum
load peak current is:
IMAX = I(RLED)MAX + I(GLED)MAX + I(BLED)MAX
Non-Overlapping Mode
The timing diagram shows the splitted R, G and B and
brightness control effect to splitted parts. Full brightness is
used in the diagram. If for example 1⁄2 brightness is used, the
frame is still 50µs, but all LED outputs’ ON time is 50%
shorter and at the last 25µs all LED outputs are OFF.
20179788
Non-Overlapping Mode
The non-overlapping mode has 16 programmed colors (different R, G and B ratio - > different color). Since the R, G and
B are split in to non-overlapping slots the output current
through the RGB LED can be calculated with following equation:
IAVG=(CRxIR+CGxIG+CBxIB)xB
where
C = Color [%] (see table of color control)
B = Brightness [%] (see table of brightness control)
2. LED ON/OFF CONTROL WITH RGB CONTROL
REGISTER
Each LED output can be set ON by writing the corresponding
bit high in the Control register (00H). RSW controls RLED,
GSW controls GLED and BSW controls BLED output. Note
that EN_RGB bit must be high and RGB_PWM bit low. In this
mode, the RGB register (01H) does not have any effect.
CC_SW bit in Control register defines the LED output mode.
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LP5526
Functionality of Color LED
Outputs (RLED, GLED, BLED)
Table with example resistance values and corresponding
output currents:
RGB resistor RRGB (kΩ)
Maximum current / output
IMAX (mA)
2.4
50.2
2.7
44.7
3.0
40.3
3.3
36.7
3.6
33.7
3.9
31.1
4.3
28.3
4.7
25.9
5.1
23.9
CONSTANT CURRENT MODE
5.6
21.8
In constant current mode, the maximum output current is
defined with a single external resistor (RRGB) and the maximum current control register (address 02H).
6.2
19.7
(Continued)
Switch Mode / Constant Current Mode
Each RGB LED output can be set to act as a switch or a
constant current sink. Selection of mode is done with the
CC_SW bit in the Control Register. If bit is set high, then the
switch mode is selected. Default is switch mode.
SWITCH MODE
In switch mode, the RGB LED outputs are low ohmic
switches to ground. Resistance is typically 3.2Ω. External
ballast resistors must be used to limit the current
through the LED.
Note that the LED output requires a minimum saturation
voltage in order to act as a true constant current sink. The
saturation voltage minimum is typically 230mV defined with
10% current drop. If the LED output voltage drops below
230mV, then the current will decrease significantly.
RGB MAX CURRENT REGISTER (02H)
Name
Bit
Description
IR[1:0]
5:4
RLED maximum current
IG[1:0]
3:2
GLED maximum current
3. EXTERNAL PWM CONTROL
IB[1:0]
1:0
BLED maximum current
The GPIO[0]/PWM pin can be used to control the RGB
output brightness or set RGB leds on/off. PWM function for
the pin is selected by writing EN_PWM_PIN high in GPIO
control register (address 06H). Note, that EN_RGB bit must
be set high. Each LED output can be enabled with RSW,
GSW and BSW bits. EN_EXT_R_PWM, EN_EXT_G_PWM
and EN_EXT_B_PWM bits are used to select, which LED
outputs are controlled with the external PWM input. Note that
polarity of external PWM control is active high i.e. when pin
is in high state, then LED output is enabled. If RGB_PWM is
set low, then each selected LED output is controlled directly
with external PWM input. If RGB_PWM is set high, then
internal PWM control is modulated by the external PWM
input. In latter case, internal PWM control is passed to LED
when external PWM input is high.
Maximum current for each LED output is adjusted with the
RGB max current register in following way:
IR[1:0], IG[1:0], IB[1:0]
Maximum current / output
00
0.25 x IMAX
01
0.50 x IMAX
10
0.75 x IMAX
11
1.00 x IMAX
External ballast resistors are not needed in this mode. The
maximum current for all RGB LED drivers is set with RRGB.
The equation for calculating the maximum current is:
IMAX = 100 x 1.23V / (RRGB + 50 Ω)
where
IMAX = maximum RGB current in any RGB output (during
constant current mode)
1.23V = reference voltage
100 = internal current mirror multiplier
RRGB = resistor value in Ohms
50 Ω = Internal resistor in the IRGB input
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• Enable external PWM pin by writing EN_PWM_PIN bit
high
• Use EN_EXT_R_PWM, EN_EXT_G_PWM and EN_EXT_B_PWM bits to select, which LED outputs are
controlled by the external PWM control. Output which
external PWM control is not selected will be on constantly
regardless of the state of the external PWM pin.
• Enable RGB constant current mode, if external ballast
resistors are not used (CC_SW = 0)
• Disable internal RGB PWM mode (RGB_PWM = 0)
• Write wanted maximum current values for each output to
RGB max current register (e.g. 11b for maximum current)
• Enable RGB functions (EN_RGB = 1, RSW= 1, GSW= 1,
BSW = 1)
• Use external PWM control pin (GPIO[0]/PWM) to introduce pre-flash and flash.
(Continued)
FLASH LED DRIVING USING RGB DRIVERS
RGB drivers can be connected in parallel and used as a
flash LED driver (see Typical application 2). Flash LEDs can
be powered through the boost converter. Flash LEDs are
controlled basically the same way as RGB LEDs controlling
is previously described. Additional safety mode is introduced
for FLASH LED driving to avoid prolonged flash and damage
to application. FLASH can be done in 3 different ways:
1. Using external PWM control
2.
Controlling RGB max current register values
3.
Using Flash mode
1. Using External PWM control
In this case pre-flash brightness is adjusted by adjusting the
pulse width of PWM signal
20179702
Using External PWM Control for Flash
2. Controlling RGB Max Current Register Values
• Start pre-flash by switching on the LEDs (RSW = 1, GSW
= 1, BSW = 1). Pre-flash brightness can be adjusted also
by setting on only one or two LEDs during the pre-flash
• Start flash by writing each output maximum current values to RGB max current register
• Stop flash by switching off the LEDs (RSW = 0, GSW = 0,
BSW = 0)
In this case pre-flash brightness is adjusted by adjusting the
current values in the RGB max current register. Note that in
this mode flash control speed and timing depends on the I2C
communication speed.
• Enable RGB functions and disable PWM mode (EN_RGB = 1, RGB_PWM = 0)
• Enable RGB constant current mode (CC_SW = 0)
• Write pre-flash values for each output to RGB max current register (e.g. 00b for 25% of maximum current)
15
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LP5526
Functionality of Color LED
Outputs (RLED, GLED, BLED)
LP5526
Functionality of Color LED Outputs (RLED, GLED, BLED)
(Continued)
20179703
Controlling RGB Max Current Values to Introduce Flash
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16
3. Using Flash Mode
In this mode Flash is triggered with external PWM pin and
pre-flash brightness is adjusted by adjusting the RGB max
current values. After flash pulse flash led will be shut down.
(Continued)
• Write the pre-flash current values to RGB max current
register
• Enable RGB functions and disable PWM mode (EN_RGB = 1, RGB_PWM = 0)
• Enable flash mode (EN_FLASH = 1), make sure
GPIO[0]/PWM pin is in low state
• Enable external PWM pin (EN_PWM_PIN = 1)
• Start pre-flash by switching on the LEDs (RSW = 1, GSW
= 1, BSW = 1). Pre-flash brightness can be affected also
by setting on only one or two LEDs
• Use EN_EXT_R_PWM, EN_EXT_G_PWM and EN_EXT_B_PWM bits to select which LED outputs are used
for flash
• Start flash pulse by setting GPIO[0]/PWM pin high and
stop it by setting GPIO[0]/PWM pin low
• During the flash pulse the LED outputs with EN_EXT_x_PWM bit enabled give out maximum current, regardless
of RGB max current register value or XSW values
Note: EN_FLASH bit must be set low, and then high again
before it is possible to make a new flash pulse.
When RLED, GLED and BLED are connected together as in
Typical Application 1, flash current can be adjusted with
8.33% step in constant current mode by changing RGB max
current register values as seen on following table. Note that
0% means that appropriate output is turned off by setting
RSW, GSW or BSW bit to 0.
IR [%]
IG [%]
IB [%]
Total
current [%]
0
0
25
8.33
0
0
50
16.67
0
0
75
25.00
0
0
100
33.33
0
25
100
41.67
0
50
100
50.00
0
75
100
58.33
0
100
100
66.67
25
100
100
75.00
50
100
100
83.33
75
100
100
91.67
100
100
100
100
20179704
Using Flash Mode
17
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LP5526
Functionality of Color LED
Outputs (RLED, GLED, BLED)
LP5526
Functionality of Color LED
Outputs (RLED, GLED, BLED)
1.
EN_FLASH = 0: Safety counter starts counting when at
least one of the EN_SAFETY_X bits is enabled. Safety
counter can be cleared by executing an I2C read or write
sequence to address 02H. If safety counter reaches one
second, the LEDs which have the safety function enabled, are switched off. Also the read-only bit SAFETY_SET is set high.
2. EN_FLASH = 1: Safety counter starts counting when the
external flash trigger pulse starts (GPIO[0]/PWM goes
high) and stops counting when flash pulse stops
(GPIO[0]/PWM goes low). If flash pulse is longer than
one second, the LEDs which have the safety function
enabled, are switched off. Also the read-only bit SAFETY_SET is set high.
In both cases (EN_FLASH = 0/1) after one second is
reached and the LEDs which safety bit has been enabled are
switched off, the LED state can be restored by disabling the
safety function of the corresponding LED. Counter can be
cleared only by disabling all safety bits (EN_SAFETY_R = 0,
EN_SAFETY_G = 0, EN_SAFETY_B = 0), I2C read or write
sequence to address 02H does not clear the counter when
safety function has been activated.
(Continued)
FLASH SAFETY TIMER FUNCTION
Flash safety function can be used to prevent damages due
to possible overheating when flash or RGB LEDs have been
stuck on because of software or user error. Safety function
has two operation modes:
1.
Disabling selected RGB drivers when no writing has
been done to the RGB max current register (address
02H) for 1 second
2.
Disabling selected RGB drivers if the external flash trigger pulse is longer than 1 second
Flash safety function can be individually enabled for all RGB
LED drivers (EN_SAFETY_R, EN_SAFETY_G, EN_SAFETY_B). The safety function operation mode depends on the
state of EN_FLASH bit.
RGB LEDs Driver Performance Characteristics
Symbol
Parameter
ILEAKAGE
RLED, GLED, BLED pin leakage current
Condition
IMAX(RGB)
Maximum recommended sink current
Min
Typ
Max Units
CC mode
SW mode
Accuracy @ 50mA
CC mode
5
Current mirror ratio
CC mode
1:100
1
µA
50
mA
60
mA
12.5
%
RGB current matching error
IRGB set to 50mA, CC mode
RSW
Switch resistance
SW mode
3.2
Ω
ƒRGB
RGB internal PMW switching frequency
Accuracy same as internal clock
frequency accuracy
20
kHz
VSAT
Saturation voltage (current drop 10%)
+25oC, IRGB set to 50mA
-30oC
+85oC
230
2
%
350
300
430
Note: RGB current should be limited as follows:
constant current mode – limited by external RRGB resistor
switch mode – limited by external ballast resistors
Output Current vs Pin Voltage (CC Mode)
Output Current vs RRGB (CC Mode)
20179705
www.national.com
20179706
18
mV
LP5526 has 2 independent backlight drivers. Both drivers are regulated constant current sinks. LED current for both LED strings
are controlled by the 8-bit current mode DACs with 0.1 mA step. MAIN and SUB LEDs can be also controlled with one DAC
(MAIN) for better matching allowing the use of larger displays having up to 8 white LEDs by setting DISPL bit to 1.
20179790
SUB output for 2 LEDs (DISPL = 0)
20179789
MAIN output for 4 LEDs (DISPL = 0)
20179791
MAIN and SUB outputs for 8 LEDs (DISPL = 1)
EXTERNAL PWM CONTROL
The GPIO[0]/PWM pin can be used to control the backlight drivers brightness or set leds on/off. External PWM control is enabled
by writing 1 to EN_MAIN_PWM and/or EN_SUB_PWM bits in register address 2BH. GPIO[0]/PWM pin is used as external PWM
input when EN_PWM_PIN is set high. PWM input is active high, i.e. LED is activated when in high state.
19
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LP5526
Backlight Drivers
LP5526
Backlight Drivers
Adjustment is made with 04H (main current) and with 05H
(sub current) registers:
(Continued)
FADE IN / FADE OUT
LP5526 has an automatic fade in and out for main and sub
backlight. The fade function is enabled with EN_FADE bit.
The slope of the fade curve is set by the SLOPE bit. Fade
control for main and sub display is set by FADE_SEL bit.
Recommended fading sequence:
1. Set SLOPE
2.
3.
Set FADE_SEL
Set EN_FADE = 1
4.
Set EN_MAIN / EN_SUB = 1
5.
6.
Set target WLED value
Fading will be done either within 0.65s or 1.3s based on
SLOPE selection
Fading times apply to full scale change i.e. from 0 to 100% or
vice versa. If the current change does not correspond to full
scale change, the time will be respectively shorter. See
WLED Dimming diagrams for typical fade times.
WLED CONTROL REGISTER (03H)
Name
Bit
SLOPE
5
FADE execution time:
0 = 1.3s (full scale)
1 = 0.65s (full scale)
Description
FADE_SEL
4
FADE selection:
0 = FADE controls MAIN
1 = FADE controls SUB
EN_FADE
3
FADE enable
0 = FADE disabled
1 = FADE enabled
DISPL
2
Display mode:
0 = MAIN and SUB individual control
1 = MAIN and SUB controlled with
MAIN DAC
EN_MAIN
1
MAIN enable:
0 = disable
1 = enable
EN_SUB
0
SUB enable:
0 = disable
1 = enable
Note: if DISPL=1 and FADE_SEL=0 then FADE effects MAIN and SUB
www.national.com
20
MAIN CURRENT [7:0]
SUB CURRENT [7:0]
Driver current,
mA (typical)
0000 0000
0
0000 0001
0.1
0000 0010
0.2
0000 0011
0.3
…
…
…
…
1111 1101
25.3
1111 1110
25.4
1111 1111
25.5
Symbol
Parameter
Conditions
Min
Typical
Max
Units
mA
IMAX
Maximum Sink Current
ILEAKAGE
Leakage Current
VSUB, MAIN =20V
IMAIN
ISUB
MAIN Current tolerance
SUB Current tolerance
IMAIN and ISUB set to 12.8mA (80H)
MatchMAIN-SUB
Sink Current Matching Error
ISINK=12.8mA, DISPL=1
0.2
MatchMAIN-SUB
Sink Current Matching Error
ISINK=12.8mA, DISPL=0
5
VSAT
95% Saturation Voltage
ISINK=25.5mA
11.1
25.5
30
0.003
1
µA
12.8
14.1
mA
%
400
%
%
500
650
mV
Note: Matching is the maximum difference from the average.
WLED Dimming, SLOPE=0
WLED Dimming, SLOPE=1
20179739
20179740
WLED Output Current vs. Voltage
20179792
21
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LP5526
Backlight Driver Electrical Characteristics
LP5526
General Purpose I/O Functionality
GPIO DATA (07H)
LP5526 has three general purpose I/O pins: GPIO[0]/PWM,
GPIO[1] and GPIO[2]. GPIO[0]/PWM can also be used as a
PWM input for the external LED PWM controlling. GPIO
bi-directional drivers are operating from the VDDIO supply
domain.
GPIO CONTROL (06H)
Name
Bit
4
OEN[2:0]
2:0
Bit
2:0
Description
Data bits
GPIO control register is used to set the direction of each
GPIO pin. For example, by setting OEN0 bit high the
GPIO[0]/PWM pin acts as a logic output pin with data defined DATA0 in GPIO data register. Note, that the EN_PWM_PIN bit overrides OEN0 state by forcing GPIO[0]/PWM to
act as PWM input. GPIO[1] and GPIO[2] pins can be selected to be inputs or outputs, defined by OEN1 and OEN2
bit status. PWM functionality is valid only for GPIO[0]/PWM
pin. GPIO data register contains the data of GPIO pins.
When output direction is selected to GPIO pin, then GPIO
data register defines the output pin state. When GPIO data
register is read, it contains the state of the pin despite of the
pin direction.
Registers for GPIO are as follows:
EN_PWM_PIN
Name
DATA[2:0]
Description
Enable PWM pin
0 = disable
1 = enable
GPIO pin direction
0 = input
1 = output
Logic Interface Characteristics
(VDDIO = 1.65V...VDD1,2 unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.2xVDDIO
V
LOGIC INPUT SCL, SDA, GPIO[0:2]
VIL
Input Low Level
VIH
Input High Level
II
Logic Input Current
fSCL
Clock Frequency
0.8xVDDIO
V
−1.0
1.0
µA
400
kHz
LOGIC INPUT NRST
VIL
Input Low Level
VIH
Input High Level
1.2
II
Input Current
-1.0
tNRST
Reset Pulse Width
0.5
V
V
1.0
10
µA
µs
LOGIC OUTPUT SDA
VOL
Output Low Level
ISDA = 3mA
VOH
Output High Level
ISDA = -3mA
IL
Output Leakage Current
VSDA = 2.8V
0.3
VDDIO − 0.5
0.5
V
1.0
µA
0.5
V
1.0
µA
VDDIO − 0.3
LOGIC OUTPUT GPIO[0:2]
VOL
Output Low Level
VOH
Output High Level
IGPIO = -3 mA
IL
Output Leakage Current
VGPIO = 2.8V
www.national.com
IGPIO = 3 mA
0.3
VDDIO − 0.5
22
VDDIO − 0.3
V
LP5526
I2C Compatible Interface
I2C SIGNALS
TRANSFERRING DATA
The SCL pin is used for the I2C clock and the SDA pin is
used for bidirectional data transfer. Both these signals need
a pull-up resistor according to I2C specification.
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate
an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP5526
address is 59H (101 1001b). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. This means that
the first byte is B2H for WRITE and B3H for READ. The
second byte selects the register to which the data will be
written. The third byte contains data to write to the selected
register.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
20179749
I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I2C master always
generates START and STOP bits. The I2C bus is considered
to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
20179751
I2C Chip Address
Register changes take an effect at the SCL rising edge
during the last ACK from slave.
20179750
I2C Start and Stop Conditions
23
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LP5526
I2C Compatible Interface
(Continued)
20179793
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 59H (101 1001b) for LP5526.
I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read
Cycle waveform.
20179794
I2C Read Cycle
www.national.com
24
LP5526
I2C Compatible Interface
(Continued)
20179754
I2C Timing Diagram
I2C TIMING PARAMETERS (VDD1,2 = 3.0 to 4.5V, VDDIO = 1.8V to VDD1,2)
Symbol
Limit
Parameter
Min
Max
Units
1
Hold Time (repeated) START Condition
0.6
µs
2
Clock Low Time
1.3
µs
3
Clock High Time
600
ns
4
Setup Time for a Repeated START Condition
600
ns
5
Data Hold Time (Output direction, delay generated by LP5526)
300
900
ns
5
Data Hold Time (Input direction, delay generated by Master)
0
900
ns
6
Data Setup Time
7
Rise Time of SDA and SCL
20+0.1Cb
300
ns
8
Fall Time of SDA and SCL
15+0.1Cb
300
ns
100
ns
9
Set-up Time for STOP condition
600
ns
10
Bus Free Time between a STOP and a START Condition
1.3
µs
Cb
Capacitive Load for Each Bus Line
10
200
pF
NOTE: Data guaranteed by design
25
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LP5526
Recommended External Components
rent (1500mA) to ensure reliable operation. Schottky diodes
with a low forward drop and fast switching speeds are ideal
for increasing efficiency in portable applications. Choose a
reverse breakdown voltage of the schottky diode significantly larger (~30V) than the output voltage. Do not use
ordinary rectifier diodes, since slow switching speeds and
long recovery times cause the efficiency and the load regulation to suffer. Examples of suitable diodes are: Central
Semiconductor CMMSH1-40, Infineon BAS52-02V.
OUTPUT CAPACITOR, COUT
The output capacitor COUT directly affects the magnitude of
the output ripple voltage. In general, the higher the value of
COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best choice. At the
lighter loads, the low ESR ceramics offer a much lower VOUT
ripple that the higher ESR tantalums of the same value. At
the higher loads, the ceramics offer a slightly lower VOUT
ripple magnitude than the tantalums of the same value.
However, the dv/dt of the VOUT ripple with the ceramics is
much lower that the tantalums under all load conditions.
Capacitor voltage rating must be sufficient, 25V or greater is
recommended. Examples of suitable capacitors are: TDK
C3216X5R1E475K,
Panasonic
ECJ3YB1E475K,
ECJMFB1E475K and ECJ4YB1E475K.
EMI FILTER COMPONENTS CSW, RSW
EMI filter (RSW and CSW) on the SW pin can be used to
suppress EMI caused by fast switching. These components
should be as near as possible to the SW pin to ensure
reliable operation. 50V or greater voltage rating is recommended for capacitor.
Some ceramic capacitors, especially those in small
packages, exhibit a strong capacitance reduction with
the increased applied voltage (DC bias effect). The capacitance value can fall below half of the nominal capacitance. Too low output capacitance can make the
boost converter unstable. Output capacitors DC bias
effect should be better than –50% at 20V.
INDUCTOR, L1
A 10uH shielded inductor is suggested for LP5526 boost
converter. The inductor should have a saturation current
rating higher than the rms current it will experience during
circuit operation (1300mA). Less than 300mΩ ESR is suggested for high efficiency and sufficient output current. Open
core inductors cause flux linkage with circuit components
and interfere with the normal operation of the circuit. This
should be avoided. For high efficiency, choose an inductor
with a high frequency core material such as ferrite to reduce
the core losses. To minimize radiated noise, use a toroid, pot
core or shielded core inductor. The inductor should be connected to the SW pin as close to the IC as possible. Examples of suitable inductors are: TDK SLF6028T-100M1R3,
Coilcraft MSS6122-103MLB.
INPUT CAPACITOR, CIN
The input capacitor CIN directly affects the magnitude of the
input ripple voltage and to a lesser degree the VOUT ripple. A
higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is recommended.
OUTPUT DIODE, D1
A schottky diode should be used for the output diode. Peak
repetitive current should be greater than inductor peak curLIST OF RECOMMENDED EXTERNAL COMPONENTS
Symbol
Value
Unit
CVDD
C between VDD1,2 and GND
100
nF
CVDDIO
C between VDDIO and GND
100
nF
Ceramic, X7R / X5R
CVDDA
C between VDDA and GND
1
µF
Ceramic, X7R / X5R
COUT
CIN
Symbol explanation
2 x 4.7 or 1 x 10
µF
Maximum DC bias effect @ 20V
C between FB and GND
-50
%
C between battery voltage and GND
10
µF
Ceramic, X7R / X5R, tolerance +/-10%
Ceramic, X7R / X5R
10
µH
Saturation current
1300
mA
CVREF
C between VREF and GND
100
nF
Ceramic, X7R / X5R
RRGB
R between IRGB and GND
2.4
kΩ
82
kΩ
± 1%
± 1%
L1
RRT
L between SW and VBAT
Type
Ceramic, X7R / X5R
R between IRT and GND
Rectifying diode (Vf @ maxload)
D1
Reverse voltage
0.3-0.5
V
30
V
Shielded inductor, low ESR
Schottky diode
Repetitive peak current
1500
mA
CSW
C in EMI filter
100
pF
Ceramic, X7R / X5R, 50V
RSW
R in EMI filter
390
Ω
± 1%
LEDs
User Defined
Note: See Application Note AN-1442 "Design and Programming Examples for Lighting Management Unit LP5526" for more
information on how to design with LP5526
www.national.com
26
REGISTER
Control Register
RGB
RGB max current
WLED Control
MAIN Current
SUB Current
GPIO Control
GPIO Data
Enables
Boost Output
PWM Enable
ADDR
(HEX)
00
01
02
03
04
05
06
07
0B
0D
2B
0
0
EN_SAFETY_G
0
EN_SAFETY_R
0
0
EN_SAFETY_B
0
0
0
EN_BOOST
0
0
0
0
0
0
1
0
0
GSW
D2
0
EN_EXT_B_PWM
0
1
EN_AUTOLOAD
0
0
0
0
0
DISPL
0
0
BRIGHT[2:0]
IG[1:0]
EN_EXT_G_PWM
BOOST[7:0]
0
EN_FLASH
SUB[7:0]
EN_EXT_R_PWM
0
0
0
0
0
RSW
D3
EN_FADE
MAIN[7:0]
EN_PWM_PIN
0
0
FADE_SEL
SLOPE
0
0
IR[1:0]
0
D4
0
0
1
NSTBY
0
0
0
0
0
0
SAFETY_SET
D5
CC_SW
COLOR[3:0]
0
0
0
EN_RGB
RGB_PWM
0
D6
D7
LP5526 Control Register Names and Default Values
0
0
0
0
0
0
0
EN_SUB
0
0
OVL
D0
0
EN_SUB_PWM
IB[1:0]
EN_MAIN_PWM
0
0
DATA[2:0]
0
OEN[2:0]
0
0
0
EN_MAIN
0
0
0
BSW
D1
LP5526
27
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LP5526
LP5526 Register Bit Explanations
Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:
Register Bit Accessibility and Initial Condition
Key
Bit Accessibility
RW
Read/write
R
Read only
–0,–1
Condition after POR
CONTROL REGISTER (00H) – RGB LEDS CONTROL REGISTER
D7
D6
D5
RGB_PWM
EN_RGB
CC_SW
RW - 0
RW - 0
RW - 1
D4
R-0
D3
D2
D1
RSW
GSW
BSW
RW - 0
RW - 0
RW - 0
RGB_PWM
Bit 7
0 - Internal RGB PWM control disabled
1 - Internal RGB PWM control enabled
EN_RGB
Bit 6
0 – RGB outputs disabled
1 – RGB outputs enabled
CC_SW
Bit 5
0 – Constant current sink mode
1 – Switch mode
RSW
Bit 3
0 – RLED disabled
1 – RLED enabled
GSW
Bit 2
0 – GLED disabled
1 – GLED enabled
BSW
Bit 1
0 – BLED disabled
1 – BLED enabled
D0
R-0
RGB (01H) – RGB COLOR AND BRIGHTNESS CONTROL REGISTER
D7
D6
D5
D4
D3
COLOR[3:0]
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
COLOR[3:0]
Bits 7-4
BRIGHT[2:0]
Bits 3-1
PWM brightness control for RGB outputs
Bit 0
0 – Overlapping mode disabled
1 – Overlapping mode enabled
OVL
www.national.com
D2
D1
BRIGHT[2:0]
PWM color for RGB outputs
28
D0
OVL
RW - 0
RW - 0
LP5526
LP5526 Register Bit Explanations
(Continued)
RGB MAX CURRENT (02H) – MAXIMUM RGB CURRENT CONTROL REGISTER
D7
D6
D5
D4
SAFETY_SET
R-0
D3
IR[1:0]
R-0
RW - 0
D2
D1
IG[1:0]
RW - 0
RW - 0
D0
IB[1:0]
RW - 0
SAFETY_SET
Bit 7
0 – safety function not activated
1 – safety function activated
IR[1:0]
Bits 5-4
RLED maximum current
IG[1:0]
Bits 3-2
GLED maximum current
IB[1:0]
Bits 1-0
BLED maximum current
RW - 0
RW - 0
Maximum current for RGB driver
IR,IG,IB[1:0]
Maximum output current
00
0.25 x IMAX
01
0.50 x IMAX
10
0.75 x IMAX
11
1.00 x IMAX
WLED CONTROL (03H) – WLED CONTROL REGISTER
D7
R-0
D6
R-0
D5
D4
D3
D2
D1
D0
SLOPE
FADE_SEL
EN_FADE
DISPL
EN_MAIN
EN_SUB
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
SLOPE
Bit 5
0 – fade execution time 0.65 sec (full scale)
1 – fade execution time 1.3 sec (full scale)
FADE_SEL
Bit 4
0 – fade control for MAIN
1 – fade control for SUB
EN_FADE
Bit 3
0 – automatic fade disabled
1 – automatic fade enabled
DISPL
Bit 2
0 - MAIN and SUB individual control
1 - MAIN and SUB controlled with MAIN DAC
EN_MAIN
Bit 1
0 – MAIN output disabled
1 – MAIN output enabled
EN_SUB
Bit 0
0 – SUB output disabled
1 – SUB output enabled
29
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LP5526
LP5526 Register Bit Explanations
(Continued)
MAIN CURRENT (04H) – MAIN CURRENT CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
RW - 0
RW - 0
RW - 0
RW - 0
D3
D2
D1
D0
RW - 0
RW - 0
RW - 0
RW - 0
D1
D0
MAIN[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
SUB CURRENT (05H) – SUB CURRENT CONTROL REGISTER
D7
D6
D5
D4
SUB[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
MAIN, SUB current adjustment
MAIN[7:0],
SUB[7:0]
Typical driver current (mA)
0000 0000
0
0000 0001
0.1
0000 0010
0.2
0000 0011
0.3
0000 0100
0.4
…
…
1111 1101
25.3
1111 1110
25.4
1111 1111
25.5
GPIO CONTROL (06H) – GPIO CONTROL REGISTER
D7
D6
D5
D4
D3
D2
EN_PWM_PIN
R-0
R-0
R-0
OEN[2:0]
RW - 0
R-0
RW - 0
EN_PWM_PIN
Bit 4
0 – External PWM pin disabled
1 – External PWM pin enabled
OEN[2:0]
Bits 2-0
0 – GPIO pin set as a input
1 – GPIO pin set as a output
RW - 0
RW - 0
GPIO DATA (07H) – GPIO DATA REGISTER
D7
D6
D5
D4
D3
D2
R-0
R-0
R-0
R-0
R-0
RW - 0
DATA[2:0]
Bits 2-0
D1
D0
DATA[2:0]
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GPIO data register bits
30
RW - 0
RW - 0
LP5526
LP5526 Register Bit Explanations
(Continued)
ENABLES (0BH) – ENABLES REGISTER
D7
R-0
D6
D5
NSTBY
EN_BOOST
RW - 0
RW - 0
D4
D3
D2
EN_FLASH
EN_AUTOLOAD
RW - 0
RW - 1
R-0
NSTBY
Bit 6
0 – LP5526 standby mode
1 – LP5526 active mode
EN_BOOST
Bit 5
0 – Boost converter disabled
1 – Boost converter enabled
EN_FLASH
Bit 3
0 – Flash function disabled
1 – Flash function enabled
EN_AUTOLOAD
Bit 2
0 – Boost active load disabled
1 – Boost active load enabled
D1
D0
R-0
R-0
BOOST OUTPUT (0DH) – BOOST OUTPUT VOLTAGE CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
RW - 1
RW - 0
RW - 0
RW - 0
BOOST[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
BOOST output voltage adjustment
BOOST[7:0]
Typical boost output voltage (V)
0000 1000
8.00
0000 1001
9.00
0000 1010
10.00
0000 1011
11.00
0000 1100
12.00
0000 1101
13.00
0000 1110
14.00
0000 1111
15.00
0001 0000
16.00
0001 0001
17.00
0001 0010
18.00
0001 0011
19.00
0001 0100
20.00
31
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LP5526
LP5526 Register Bit Explanations
(Continued)
PWM ENABLE (2BH) – EXTERNAL PWM CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
EN_EXT
G_PWM
EN_EXT
B_PWM
EN_MAIN
PWM
EN_SUB
PWM
RW - 0
RW - 0
RW - 0
RW - 0
EN_SAFETY_R
EN_SAFETY_G
EN_SAFETY_B
EN_EXT
R_PWM
RW - 0
RW - 0
RW - 0
RW - 0
EN_SAFETY_R
Bit 7
0 – Safety function for RLED disabled
1 – Safety function for RLED enabled
EN_SAFETY_G
Bit 6
0 – Safety function for GLED disabled
1 – Safety function for GLED enabled
EN_SAFETY_B
Bit 5
0 – Safety function for BLED disabled
1 – Safety function for BLED enabled
EN_EXT_R_PWM
Bit 4
0 – External PWM control for RLED disabled
1 – External PWM control for RLED enabled
EN_EXT_G_PWM
Bit 3
0 – External PWM control for GLED disabled
1 – External PWM control for GLED enabled
EN_EXT_B_PWM
Bit 2
0 – External PWM control for BLED disabled
1 – External PWM control for BLED enabled
EN_EXT_MAIN_PWM
Bit 1
0 – External PWM control for MAIN disabled
1 – External PWM control for MAIN enabled
EN_EXT_SUB_PWM
Bit 0
0 – External PWM control for SUB disabled
1 – External PWM control for SUB enabled
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32
inches (millimeters) unless otherwise noted
The dimension for X1 ,X2 and X3 are as given:
• X1=2.543mm ± 0.03mm
• X2=2.543mm ± 0.03mm
• X3=0.60mm ± 0.075mm
25-bump micro SMD Package, 2.54 x 2.54 x 0.6mm, 0.5mm pitch
NS Package Number TLA25CCA
See Application note AN–1112 for PCB design and assembly instructions.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
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LP5526 Lighting Management Unit with High Voltage Boost Converter with up to 150mA Serial
FLASH LED Driver
Physical Dimensions