CXB1454R VGA/SVGA/XGA 24bit Receiver Description CXB1454R is the 1 chip deserializer for VGA/SVGA/ XGA 24bit color digital RGB, and meet to the Gigabit Video Interface specification. 64 pin LQFP (Plastic) Absolute Maximum Ratings • Supply voltage Vcc • Storage temperature Tstg • Allowable power dissipation PD 4.0 –65 to +150 1710 V °C REXT PANEL0 PANEL1 LOS TESTDT TESTSB SDATAP REFRQP V °C mW Recommended Operating Condition • Supply voltage Vcc 3.3 ± 0.16 • Operating temperature Topr 0 to +60 SDATAN REFRQN VccA VEES VEEA LPFA Block Digagram & Pin out LPFB Structure Bipolar silicon monolithic IC TESTEXN Features • 1 chip receiver for serial transmission of 24-bit color VGA/SVGA/XGA picture • On chip cable equalizer circuit to compensate the cable loss • On chip PLL circuit for data and clock recovery • On chip panel mode automatically selectable circuit • TTL compatible I/O • Support 1 pixel/shiftclock mode with 1 chip and 2 pixel/shiftclock mode with 2 chips • +3.3V single power supply • Low power consumption • 64pin plastic LQFP package with body size 14mm × 14mm 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 CLKPOL CNTL 49 31 R0 DE 50 SFTCLK 51 VEET 52 30 R1 Cable EQ CDR PLL 29 VEET VccT 53 28 VccT VEEG 54 27 VEEG VccG 55 26 VccG Serial to Parallel Converter HSYNC 56 VSYNC 57 B7 58 25 R2 24 R3 23 R4 B6 59 22 R5 VEEG 60 21 VEEG 20 VCCG VccG 61 B5 62 19 Decoder R6 18 R7 B4 63 17 VEET VccT G0 G1 G2 G3 9 10 11 12 13 14 15 16 G4 8 G5 7 VEET 6 VccT B1 5 G6 4 B0 3 G7 2 B2 VEET 1 B3 VccT 64 Fig. 1. Block Diagram & Pin out Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98X24B03 CXB1454R Pin List Tab. 1. Power/Ground Pin Number Pin Name Descriptions VCCT 8, 16, 28, 53, 64 TTL power surpply, should be connected to 3.3V ± 5% VEET 1, 9, 17, 29, 52 TTL ground, connected to 0V VCCG 20, 26, 55, 61 Logical core power surpply, connected to 3.3V ± 5% VEEG 21, 27, 54, 60 Logical core ground, connected to 0V VCCA 44 Analog power surpply, connected to 3.3V ± 5% VEEA 45 Analog ground, connected to 0V VEES 46 Analog substrate, connected to 0V –2– CXB1454R Tab. 2. Digital Signals Pin Name SFTCLK Pin Number 51 Type TTL out Descriptions Shift clock, for the data fetch at falling or rising edge RED (7 to 0) 18, 19, 22, 23, 24, 25, 30, 31, GRN (7 to 0) 6, 7, 10, 11, TTL out 12, 13, 14, 15, BLU (7 to 0) 58, 59, 62, 63, 2, 3, 4, 5 Pixel data HSYNC 56 TTL out Hsync data VSYNC 57 TTL out Vsync data CNTL 49 TTL out Control data DE 50 TTL out Display enable data LOS 36 TTL out Los of signal TTL in Panel mode select switch TTL in Trigger edge select switch TTL in Reserved for TEST under fabrication PANEL (1, 0) 35, 34 CLKPOL 32 TESTEXN TESTDT TESTSB 43, 37, 38 Equivalent circuit VCCT TTL-OUT VEET 6k 6k TTL-IN 300 VEET VCCG SDATAP/N 40, 41 Rx Serial input SDATAP/N REFRQP/N REFRQP/N 39, 42 VCCG VCCT Rx Refclk request VEEG –3– VEEG CXB1454R Tab. 3. Special Pin Name Pin Number Descriptions Equivalent circuit VCCG REXT 33 External Resister REXT VEEG VCCA LPFA LPFB LPFA/B 47, 48 External loop filter VEEA –4– CXB1454R Electrical characteristics Tab. 4. Absolute Maximum Rating Description Symbol Min. Typ. Max. Unit Power supply voltage VCC –0.3 4 V TTL DC input voltage VI_T –0.5 5.5 V TTL output current (High) IOH_T –20 0 TTL output current (Low) IOL_T 0 20 mA ' mA Serial input pin voltage Vsdin –0.5 VCC + 0.5 V REFRQ output pin voltage VRQout 0.5 VCC + 0.5 V Storage temperature Tstg –65 150 °C Comments Tab. 5. Recommended Operating Conditions Description Symbol Min. Typ. Max. Unit 3.3 3.465 V 60 °C Power supply voltage (Include VCCT5) VCC 3.135 Operating temperature Topr 0 Comments Tab. 6. DC Characteristics (Under the recommended conditons. See Tab. 5) Description Symbol Min. Typ. Max. Unit Conditions Input HIGH voltage (TTL) VIH_T 2 5.5 V Input LOW voltage (TTL) VIL_T 0 0.8 V Input HIGH current (TTL) IIH_T 20 µA VIN = VCC Input LOW current (TTL) IIL_T –400 µA VIN = 0 Output HIGH voltage (TTL) VOH_T 2.25 V IOH = –0.2mA Output LOW voltage (TTL) VOL_T 0.5 V IOL = 4mA Output HIGH current (REFRQ) IOH_RQ –0.1 +0.1 mA Output LOW current (REFRQ) IOL_RQ 7.8 11 mA Input dynamic range (SDATA) VIM_SD VCC – 0.4 VCC + 0.2 V Common mode voltage Input dynamic range (SDATA) VID_SD –0.5 +0.5 V Differential voltage 440 mA 65MHz, All low pattern, Outputs open mA 65MHz, Worst case pattern See Fig. 8 Outputs open 0 325 Supply current ICC 350 –5– 465 See Fig. 3, 4 REXT = 1.3kΩ CXB1454R 50Ω VCCA/G/T CXB1454R 37 TESTDT REFRQP 39 VCC A A 150Ω 38 TESTSB 43 TESTEXN 50Ω REFRQN 42 150Ω VEEA/G/T Fig. 2. IOH_RQ and IOL_RQ DC measurement TESTDT TESTSB TESTEXN Fig. 3. IOH_RQ and IOL_RQ DC measurement setting Electrical characteristics Tab. 7. AC Characteristics (Under the recommended conditons. See Tab. 5) Description Symbol Minimum SFTCLK frequency Maximum SFTCLK frequency Fsftclk SFTCLK duty factor Dsftclk Pixel/Sync/Cntl/DE setup to SFTCLK Tsetup Min. Typ. Max. Unit 25.0 MHz MHz 60 % Vth = 1.4V, CL = 10pF 16 10 5 ns ns ns Vth = 1.4V, CL = 10pF 25MHz 40MHz 65MHz 17 11 6 ns ns ns Vth = 1.4V, CL = 10pF 25MHz 40MHz 65MHz 65.0 40 Conditions Pixel/Sync/Cntl/DE hold to SFTCLK Thold SFTCLK rise time Torc 3 ns 0.8 to 2.0V, CL = 10pF SFTCLK fall time Tofc 2.5 ns 2.0 to 0.8V, CL = 10pF Pixel/Sync/Cntl/DE rise time Tofd 4.5 ns 0.8 to 2.0V, CL = 10pF Pixel/Sync/Cntl/DE fall time Tord 2 ns 2.0 to 0.8V, CL = 10pF CLOCK mode assert time TAclk 0.9 µs CLOCK mode deassert time TDclk 50 µs LOS signal assert time TAlos 0.5 µs LOS signal deassert time TDlos 0.1 µs –6– CXB1454R VCCA/G/T TTLout Cprobe CXB1454R VCC CL' oscilloscope VEEA/G/T CL' + Cprobe = 10pF Fig. 4. Pixel/Sync/Cntl/DE waveform measurement Timing Chart 1/Fsftclk 2.0V Vth SFTCLK 0.8V Torc Tofc Dsftclk/Fsftclk Setup/hold time is refered from rising edge in CLKPOL = GND falling edge in CLKPOL = Vcc or OPEN Tsetup Thold Tord REDxx GRNxx BLUxx H/Vsync CNTL DE 2.0V 0.8V Tofd Fig. 5. TTL output timing Pixel Sync/Cntl/DE error Indeterminate SftClk TAclk REFRQP REFRQN Indeterminate TDclk SDATAP SDATAN Fig. 6. Refclk request timing –7– CXB1454R SDATAP SDATAN NRZ data TDlos TAlos LOS Fig. 7. Idle mode timing T T SFTCLK f RGB <7, 5, 3, 1> f/2 RGB <6, 4, 2, 0> f/2 Fig. 8. Worst case test pattern –8– CXB1454R CLKPOL Pin Control The CLKPOL pin is used to select the SFTCLK trigger edge. (See Table 8.) The CLKPOL pin is open High TTL input. Table 8. SFTCLK Polarity CLKPOL Receiver operation trigger L Rising edge H Falling edge PANEL1 and 0 Pin Control The PANEL1 and 0 pins are used to select the panel mode. (See Table 9.) For the normal use, the all frequencies of SFTCLK (25MHz to 65MHz) can be covered by fixing both PANEL1 and 0 to High. The PANEL1 and 0 pins are open High TTL inputs. Table 9. Panel Mode PANEL1 PANEL0 L L L Supporting panel size Shift clock Serial rate VGA (640 × 480) 25MHz 750Mbps H SVGA (800 × 600) 40MHz 1200Mbps H L XGA (1024 × 768) 65MHz 1950Mbps H H VGA to XGA 25MHz to 65MHz 750Mbps to 1950Mbps Test Pin Control The TESTEXN, TESTDT and TESTSB pins are for test only. Select normal mode. (See Table 10.) The TESTEXN, TESTDT and TESTSB pins are open High, TTL inputs. Table 10. Test Mode TESTEXN TESTDT TESTSB Operation mode L X X Test mode H H H Normal mode LOS Pin Output The LOS pin shows the absence of proper level of SDATA signal. The LOS pin is High when the connector is disconnected or the transmitter is idle. The LOS pin is TTL output. –9– CXB1454R Applications CXB1454R GVIF receiver is applied to the digital RGB signal transmission for P/C with LCD monitor Video on demand system Monitoring system Graphical controller Projector Digital TV monitor Car navigation system with GVIF transmitter, CXB1455R. CXB1455R GVIF Transmitter BLU (7 to 0) SYNC/CNTL/DE 8 8 Parallel to Serial Converter Cable Driver 4 PLL SHIFTCLOCK STP or Twin axial 8 Serial to Parallel Converter Cable Equalizer Decoder GRN (7 to 0) 8 Encoder RED (7 to 0) 8 8 4 PLL CXB1454R GVIF Receiver Fig. 9. Block Diagram of GVIF transceiver chip set – 10 – RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/CNTL/DE SHIFTCLOCK CXB1454R Application Cicuit VCC Differential cable 0.1 to 0.4n (3) (1) CHIP RESISTOR (1%) (2) CHIP CAPACITOR (3) FORMED BY THE PRINTED CIRCUIT PATTERN (L = 0.5 to 1.0mm / W = 0.5 to 1.0mm) Connector E 0.1 to 0.4n (3) 0.1 to 0.4n (3) 100 (1) 33µ 16V 150 (1) 470 (1) 150 (1) 0.1µ 470 (1) (2) 1.3k (1) 47p 47p (2) (2) 330 100p (2) Vcc 330 R0 31 51 SFTCLK R1 30 E VEET 29 53 VccT VccT 28 54 VEEG VEEG 27 55 VccG VccG 26 56 HSYNC R2 25 57 VSYNC R3 24 58 B7 R4 23 59 B6 0.1µ (2) E E R5 22 60 VEEG VEEG 21 61 VccG VCCG 20 E 0.1µ (2) R6 19 62 B5 R7 18 63 B4 VEET 17 VccT VEET 7 8 9 10 11 12 13 14 15 16 G0 G6 6 VccT G7 5 G1 B0 4 G2 B1 3 G3 B2 2 G4 B3 1 G5 VEET 64 VccT Vcc 0.1µ (2) Vcc 52 VEET Vcc H: FALLING EDGE TRIGGER L: RISING EDGE TRIGGER CLKPOL 32 50 DE 0.1µ (2) SW1 330 REXT PANEL0 LOS PANEL1 TESTDT TESTSB REFRQP SDATAP SDATAN REFRQN VccA 49 CNTL TESTEXN VEES VEEA LPFA LPFB 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.1µ (2) 0.1µ (2) Vcc Vcc DE VSYNC HSYNC CNTL SFTCLK 0.1µ (2) 7 MSB 6 5 4 3 2 BLUE DATA 1 0 LSB 7 MSB 6 5 4 3 2 1 0 LSB GREEN DATA 7 6 MSB 5 4 3 2 1 0 LSB RED DATA Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Fig. 10. Recommended application circuit – 11 – CXB1454R Recommended Printed Circuit Board Structure AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA L1: I1: L2: I2: L3: I3: L4: Cu plate (18µm) + solder coat Fiber-glass epoxy core (0.3mm) Cu plate (36µm) Fiber-glass epoxy core (0.8mm) Cu plate (36µm) Fiber-glass epoxy core (0.3mm) Cu plate (18µm) + solder coat Fig. 11. Recommended Printed Circuit Board Structure Recommended Printed Circuit Board Pattern POWER and special signal routing example 0.5mm G Through hole to the GND plane (L2) Through hole to the VCCE/VCCG plane (L3) E AA Through hole to the VCCT plane (L3) T A FET Chip resistor AA AA AA AA L2 doesn't have plane in this area AA AA G 6mm PANEL0 REXT PANEL1 LOS TESTSB TESTDT REFRQP SDATAN SDATAP REFRQN TESTEXN VccA VEEA LPFA 33 VEES 48 LPFB 49 Chip capacitor G DE R0 SFTCLK R1 VEET VEET VccT VccT VEEG VccG G G E E VccG HSYNC R2 VSYNC R3 B7 R4 R5 VEEG VccG E 64 T T T T T T T T VEEG G VccG B5 R6 B4 R7 E 17 VEET VccT G0 G1 G2 G3 G4 G5 VEET VccT G6 G7 B0 B1 B2 B3 VEET VccT T G VEEG B6 G T 1 G G 16 T G 32 CLKPOL CNTL Fig. 12. Recommended Printed Circuit Board Pattern – 12 – CXB1454R Micro Strip Line For maximum performance, the impedance between the pins SDDATAP/N of the LSI and the footprint of the connector should be 50Ω using a micro strip line. 50Ω impedance can be reached when using 0.5mm width pattern lines on L1 using this circuit board structure. The length of the lines should be identical and throughhole should not be used. L2 is recommended as the large ground plane. Terminators Terminators (100Ω resistor) should be located as close to the LSI as possible. Filter Devices and Reference Registors Capacitors and resistors which are connected to LPFA/B and REXT are filters and reference resistors. The region of Layer 2 (L2) is under the device and conductive patterns. The ground plane should be taken off in order to reduce parasitic capacitors. Bypass Capacitors Bypass capacitors (0.1µF SMD type) should be located as close to the pins as possible. Refer to the recommendation. – 13 – CXB1454R Recommendation for Cable and Connector Characteristics The GVIF system uses terminators at both ends (transmitter and receiver), a cable equalizer and a small amplitude differential signal. In order to solve the problems of high speed data transmission such as signal reflection, reduce the signal level and EMI. In order to achieve the best solution, note the following: Tx termination 50Ω Rx termination 100Ω Tx LSI Rx LSI Microstrip line (50Ω) Foot print Connector Cable (diff. 100Ω) Connector Foot print Microstrip line (50Ω) It is important to note the following issues for a good data transmission system: • Good impedance matching Differential impedance should be fit to the recommended template on the next page. • Cable loss should be small and the loss curve should be smooth. Maximum loss should be less than 15dB at 1GHz for the CXB1454R which has a built-in cable equalizer. See the next page. • Skew of POS/NEG (differential signal) should be small Less than 12% of 1-bit time or 160ps@VGA, 100ps@SVGA, 60ps@XGA. • Good EMI performance cable and connectors. In order to satisfy these issues, the recommendations are as follows: • Use the differential cable which provides good controlled impedance, low loss and good skew matching. A shielded twisted pair (STP) cable is recommended. • Use a low reflectance connector. • To minimize interference from other signals, high speed signal lengths should be identical. • Use double shielded cable. – 14 – CXB1454R Recommended Transmission Path : Differential impedance template Zo (Ω) 150 110 106 94 90 75 < 500ps Microstrip line Foot print < 500ps Connector Connector Foot print Microstrip line Recommended Transmission Path : Attennation Characteristics Loss < 15dB 2dB Measured curve Fitting curve Frequency 1GHz – 15 – CXB1454R TTL output waveform with CL = 10pF SFTCLK 65MHz TTL output B0 T 65Mb/s TTL output 1.00V/div ∗ ATTEN 40dB 1.00V/div 5ns/div SFTCLK Power spectrum RL 119.2dBµV 10dB/ D R C CENTER 65.000MHz RBW 100kHz ∗ VBW 100kHz SPAN 9.900MHz ∗ SWP 50.0ms – 16 – CXB1454R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 1.7MAX 14.0 ± 0.1 0.1 33 48 32 (15.0) 49 B A 17 64 16 + 0.08 0.37 – 0.07 (0.5) 1 0.8 0.13 M 0.25 0.6 ± 0.2 0° to 10° (0.5) (0.35) DETAIL A (0.125) + 0.08 0.37 – 0.07 0.145 ± 0.04 0.1 ± 0.1 DETAIL B NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L02 LEAD TREATMENT PALLADIUM PLATING EIAJ CODE LQFP064-P-1414 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.7g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 17 – Sony Corporation