MICREL SY88823VMITR

Micrel, Inc.
SY88823V
3.3V/5V 3.2Gbps CML LOW-POWER
LIMITING POST AMPLIFIER w/TTL SD
SY88823V
DESCRIPTION
FEATURES
Multi-rate up to 3.2Gbps operation
Wide gain-bandwidth product
• 38dB differential gain
• 2GHz 3dB bandwidth
Low noise 50Ω CML data outputs
• 800mVpp output swing
• 60ps edge rates
• 5psrms typ. random jitter
• 15pspp typ. deterministic jitter
Chatter-free, Signal-Detect (SD) output
• 4.6dB electrical hysteresis
• OC-TTL output with internal 4.75kΩ pull-up
resistor
Programmable SD sensitivity using single external
resistor
Integrated input bias reference
TTL EN input allows feedback from SD
Wide operating range
• Single 3.3V ±10% or 5V ±10% power supply
• –40°C to +85°C ambient industrial temperature
range
Available in tiny 10-pin EPAD-MSOP and 16-pin
MLF™ packages
The SY88823V low-power, limiting post amplifier is
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88823V
quantizes these signals and outputs typically 800mVPP
voltage-limited waveforms.
The SY88823V operates from a single +3.3V ±10% or
+5V ±10% power supply, over an industrial temperature
range of –40°C to +85°C. With its wide bandwidth and high
gain, signals with data rates up to 3.2Gbps and as small as
10mVpp can be amplified to drive devices with CML inputs
or AC-coupled PECL inputs.
The SY88823V incorporates a signal detect (SD), opencollector TTL output with internal 4.75kΩ pull-up resistor. A
programmable, signal-detect level set pin (SDLVL) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SDLVL
and de-asserts low otherwise. SD can be fed back to the
enable (EN) input to maintain output stability under a lossof-signal condition. EN de-asserts the true output signal
without removing the input signal. Typically 4.6dB SD
hysteresis is provided to prevent chattering.
Please see Micrel’s website at www.micrel.com for a
complete selection of optical module ICs.
The following table summarizes the differences between
devices in Micrel’s latest family of Limiting Amplifiers.
APPLICATIONS
■ 1.25Gbps and 2.5Gbps Gigabit Ethernet
■ 1.062Gbps and 2.125Gbps Fibre Channel
■ 155Mbps, 622Gbps, 1.25Gbps, and 2.5Gbps SONET/
SDH
■ Gigabit interface converter (GBIC)
■ Small form factor (SFF) and small form factor
pluggable (SFP) transceivers
■ Parallel 10G Ethernet
■ High-gain line driver and line receiver
Part Number
Integrated 50Ω
Input Termination
LOS
or SD
Active LOW
or HIGH Enable
SY88773V
No
LOS
LOW
SY88823V
No
SD
HIGH
SY88843V
Yes
SD
HIGH
SY88973V
Yes
LOS
LOW
Table 1. Limiting Amplifiers Selection Guide
TYPICAL PERFORMANCE
Output Swing
(75mV/div.)
3.3V, 25°C, 10mVpp Input
@3.2Gbps 231–1 PRBS, RLOAD = 50Ω to VCC
TIME (50ps/div.)
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
M9999-110905
[email protected] or (408) 955-1690
Rev.: C
1
Amendment: /0
Issue Date: November 2005
Micrel, Inc.
SY88823V
FUNCTIONAL BLOCK DIAGRAM
VCC
DOUT
DIN
Limiting
Amplifer
CML
Buffer
/DOUT
/DIN
REF
TTL
Buffer
REF
Generator
VCC
25kΩ
EN
Level
Detect
2.8kΩ
VCC
4.75kΩ
OC-TTL
Buffer
SDLVL
GND
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SD
Micrel, Inc.
SY88823V
PACKAGE/ORDERING INFORMATION
VCC
EN
SDLVL
VCC
Ordering Information(1)
16
15
14
13
DIN
1
12
/DOUT
GND
2
11
GND
GND
3
10
GND
/DIN
4
9
8
VCC
7
SD
6
REF
VCC
5
/DOUT
16-Pin MLF™ (MLF-16)
EN 1
Part Number
Package
Type
Operating
Range
Package
Marking
Lead
Finish
SY88823VKI
K10-2
Industrial
823V
Sn-Pb
SY88823VKITR(2)
K10-2
Industrial
823V
Sn-Pb
SY88823VMI
MLF-16
Industrial
823V
Sn-Pb
SY88823VMITR(2)
MLF-16
Industrial
823V
Sn-Pb
SY88823VEY(3)
K10-2
Industrial
823V with
Pb-Free bar-line indicator
Pb-Free
Matte-Sn
SY88823VEYTR(2, 3)
K10-2
Industrial
823V with
Pb-Free bar-line indicator
Pb-Free
Matte-Sn
SY88823VMG(3)
MLF-16
Industrial
823V with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
SY88823VMGTR(2, 3)
MLF-16
Industrial
823V with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
10 VCC
DIN 2
9 DOUT
/DIN 3
8 /DOUT
REF 4
7 SD
SDLVL 5
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
6 GND
10-Pin EPAD-MSOP (K10-2)
PIN DESCRIPTION
Pin Number
(MSOP)
Pin Number
(MLF™)
Pin Name
Type
1
15
EN
TTL Input:
Default is high.
2, 3
1, 4
DIN, /DIN
Differential
Data Input
4
6
REF
5
14
SDLVL
Input:
Default is
maximum sensitivity.
6
Exposed Pad
2, 3, 10, 11
Exposed Pad
GND
Ground
7
7
SD
Open Collector
TTL Output with
internal 4.75kΩ
pull-up resistor
8, 9
9, 12
DOUT, /DOUT
Differential
CML Output
10
5, 8, 13, 16
VCC
Power Supply
M9999-110905
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Pin Function
Enable: De-asserts true data output when low.
Incorporates 25kΩ pull-up to VCC.
Differential Data Input. Input must be biased to meet
common mode range.
Reference Voltage: Bypass with 0.01µF low ESR capacitor from REF to VCC to stabilize SDLVL and REF.
Signal-Detect Level Set: A resistor from this pin to VCC
sets the threshold for the data input amplitude at which the
SD output will be asserted.
Device Ground. Exposed pad must be soldered
(or equivalent) to the same potential as the ground pins.
Signal-Detect: asserts high when the data input
amplitude rises above the threshold set by SDLVL.
Differential Data Output.
3
Positive Power Supply. Bypass with 0.1µF0.01µF low
ESR capacitors. 0.01µF capacitors should be as close as
possible to VCC pins.
Micrel, Inc.
SY88823V
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ....................................... 0V to +7.0V
DIN, /DIN, EN, SDLVL Voltage .............................. 0 to VCC
REF Current ............................................................... ±1mA
SD Current ................................................................. ±5mA
DOUT, /DOUT Current ............................................. ±25mA
Storage Temperature (TS) ....................... –65°C to +150°C
Lead Temperature (Soldering, 20 sec.) .................... 260°C
Supply Voltage (VCC) .............................. +3.0V to +3.6V or
............................................................ +4.5V to +5.5V
Ambient Temperature (TA) ......................... –40°C to +85°C
Junction Temperature (TJ) ....................... –40°C to +120°C
Package Thermal Resistance(3)
MLF™
θJA (Still-Air) ..................................................... 61°C/W
ψJB ................................................................................... 38°C/W
EPAD-MSOP
θJA (Still-Air) ..................................................... 38°C/W
ψJB ................................................................................... 22°C/W
DC ELECTRICAL CHARACTERISTICS
VCC = 3.0V to 3.6V or 4.5V to 5.5V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C; typical values at VCC = 3.3V, TA = 25°C.
Symbol
Parameter
Condition
ICC
Power Supply Current
Power Supply Current
Min
Typ
Max
Units
3.3V, Note 4
5V, Note 4
28
30
42
45
mA
mA
3.3V, Note 5
5V, Note 5
45
47
62
65
mA
mA
VREF
Reference Voltage
VCC–1.3
VSDLVL
SDLVL Voltage Range
VOH
DOUT, /DOUT HIGH Voltage
Note 6
VCC–0.020 VCC–0.005
VOL
DOUT, /DOUT LOW Voltage
3.3V, Note 6
5V, Note 6
VCC–0.475 VCC–0.400 VCC–0.350
VCC–0.510 VCC–0.400 VCC–0.350
VOFFSET
Differential Output Offset
Note 6
ZO
Single-Ended Output Impedance
VIHCMR
Input Common Mode Range
VREF
40
Note 7
50
GND+2.15
V
VCC
V
VCC
V
V
V
±80
mV
60
Ω
VCC
V
Max
Units
VCC
V
0.5
V
TTL DC ELECTRICAL CHARACTERISTICS
VCC = 3.0V to 3.6V or 4.5V to 5.5V; TA = –40°C to +85°C.
Symbol
Parameter
Condition
Min
VOH
SD Output HIGH Level
Sourcing 100µA
2.4
VOL
SD Output LOW Level
Sinking 2mA
VIH
EN Input HIGH Voltage
VIL
EN Input LOW Voltage
IIH
EN Input HIGH Current
VIN = 2.7V
VIN = VCC
IIL
EN Input LOW Current
VIN = 0.5V
Typ
2.0
–0.3
V
0.8
V
20
100
µA
µA
mA
Notes:
1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. This is a stress rating only and functional operation is not implied at
conditions other than those detailed in the operational sections of this data sheet. Exposure to Absolute Maximum Ratings conditions for extended periods
may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance assumes the use of 4-layer PCB. Exposed pad must be soldered (or equivalent) to the device's most negative potential on the
PCB.
4. Excludes current of CML output stage. See “Detailed Description.”
5. Total device current with no output load.
6. Output levels are based on a 50Ω to VCC load impedance. If the load impedance is different, the output level will be changed. Amplifier is in a limiting
mode.
7. The VIHCMR range is referenced to the most positive side of the differential input signal.
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Micrel, Inc.
SY88823V
AC ELECTRICAL CHARACTERISTICS
VCC = 3.0V to 3.6V or 4.5V to 5.5V; TA = –40°C to +85°C; RLOAD = 50Ω to VCC; typical values at VCC = 3.3V, TA = 25°C
Symbol
Parameter
Condition
Min
Typ
PSRR
Power Supply Rejection Ratio
t r, t f
Output Rise/Fall Time
(20% to 80%)
Note 8
60
tJITTER
Deterministic
Random
Note 9
15
5
VID
Differential Input Voltage Swing
VOD
Differential Output Voltage Swing
3.3V, Note 8
5V, Note 8
HYS
SD Hysteresis
Note 10
tOFF
Max
35
10
Units
dB
120
ps
psPP
psRMS
1800
mVPP
700
700
800
800
950
1020
mVPP
mVPP
2
4.6
8
dB
SD Release Time
0.1
0.5
µs
tON
SD Assert Time
0.2
0.5
µs
VSR
SD Sensitivity Range
35
mVPP
B–3dB
–3dB Bandwidth
AV(Diff)
Differential Voltage Gain
S21
Single-Ended Small Signal-Gain
Note 11
10
2.0
GHz
32
38
dB
26
32
dB
Notes:
8. Amplifier in limiting mode. Input is a 200MHz square wave, tr < 300ps.
9. Deterministic jitter measured using 2.488Gbps K28.5 pattern, VID = 10mVpp. Random jitter measured using 2.488Gbps K28.7 pattern, VID = 10mVpp.
10. Electrical signal.
11. This is the detectable range of input amplitudes that can de-assert SD. The input amplitude to assert SD is 2–8dB higher than the de-assert amplitude.
See “Typical Operating Characteristics” for graphs showing how to choose a particular RSDLVL or VSDLVL for a particular SD de-assert, and its
associated assert, amplitude. If increased SD sensitivity and hysteresis are required, an application note entitled “Notes on Sensitivity and Hysteresis
in Micrel Post Amplifiers” is available at http://www.micrel.com/product-info/app_hints+notes.shtml.
M9999-110905
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Micrel, Inc.
SY88823V
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, TA = 25°C, RLOAD = 50Ω to VCC, unless otherwise stated.
Output Swing
(75mV/div.)
1.8Vpp Input @3.2Gbps 231–1 PRBS
Output Swing
(75mV/div.)
10mVpp Input @3.2Gbps 231–1 PRBS
TIME (50ps/div.)
TIME (50ps/div.)
VID to Assert/De-assert SD
vs. RSDLVL
VID to Assert/De-assert SD
vs. VSDLVL
100
100
40
Single-Ended Small-Signal
Gain vs. Frequency
35
10
S21 (dB)
VID (mVpp)
VID (mVpp)
30
10
25
20
15
10
5
0
60
0.2
0.4 0.6 0.8 1.0
VCC – VSDLVL (V)
1
0.1
1.2
Power Supply Current
vs. Temperature
900
880
50
45
40
35
30
25
-40
0
100
Differential Output Voltage
Swing vs. Temperature
(Amplifier in Limiting Mode)
800
-15
10
35
60
TEMPERATURE (°C)
M9999-110905
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85
700
840
820
800
780
760
740
720
700
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
FREQUENCY (GHz)
Differential Output Voltage Swing
vs. Differential Input Voltage Swing
900
860
VOD (mVpp)
CURRENT (mA)
55
1
10
RSDLVL(kΩ)
VOD (mVpp)
1
600
500
400
300
200
100
-15
10
35
60
TEMPERATURE (°C)
6
85
0
0 5 10 15 20 25 30 35 40 45 50
VID (mVpp)
Micrel, Inc.
SY88823V
DETAILED DESCRIPTION
Signal Detect-Level Set
A programmable, signal-detect level set pin (SDLVL) sets
the threshold of the input amplitude detection. Connecting
an external resistor between VCC and SDLVL sets the
voltage at SDLVL. This voltage ranges from VCC to VREF.
The external resistor creates a voltage divider between VCC
and REF as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The relationship between VSDLVL and RSDLVL is given by:
The SY88823V low-power, limiting post amplifier operates
from a single +3.3V ±10% or +5V ±10% power supply, over
an industrial temperature range of –40°C to +85°C. Signals
with data rates up to 3.2Gbps and as small as 10mVPP can
be amplified. Figure 1 shows the allowed input voltage swing.
The SY88823V generates an SD output, providing feedback
to EN for output stability. SDLVL sets the sensitivity of the
input amplitude detection.
Input Amplifier/Buffer
The SY88823V’s input is designed for VREF as its nominal
DC-bias point. If AC-coupling to the SY88823V, REF can
be used as the DC-bias point by externally connecting the
inputs through appropriate termination resistors to REF. If
DC-coupling to the SY88823V, ensure the upstream device’s
output swing meets the SY88823V’s common-mode range.
Figure 2 shows a simplified schematic of the input structure.
The high sensitivity of the input amplifier detects and
amplifies signals as small as 10mVPP. The input amplifier
allows input signals as large as 1800mVPP. Input signals
are linearly amplified with a typically 38dB differential voltage
gain. Since it is a limiting amplifier, the SY88823V outputs
typically 800mVPP voltage-limited waveforms for input signals
that are greater than 10mVPP. Applications requiring the
SY88823V to operate with high gain should have the
upstream TIA placed as close as possible to the SY88823V’s
input pins to ensure the device’s best performance.
Output Buffer
The SY88823V’s CML output buffer is designed to drive
50Ω lines. The output buffer requires appropriate termination
for proper operation. An external 50Ω resistor to VCC or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output structure and includes
an appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50Ω to VCC eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs, typically 800mVPP, waveforms across 25Ω total
loads. The output buffer thus switches typically 16mA tailcurrent. Figure 4 shows the power supply current
measurement which excludes the 16mA tail-current.
Signal Detect
The SY88823V incorporates a chatter-free, signal detect
(SD) open-collector TTL output with internal 4.75kΩ pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude large enough to be considered a valid
input. SD asserts high if the input amplitude rises above the
threshold set by SDLVL and de-asserts low otherwise. SD
can be fed back to the enable (EN) input to maintain output
stability under a loss of signal condition. EN de-asserts low
the true output signal without removing the input signals.
Typically, 4.6dB SD hysteresis is provided to prevent
chattering.
M9999-110905
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VSDLVL = VCC – 1.3
RSDLVL
RSDLVL + 2.8
where voltages are in volts and resistances are in kΩ.
The smaller the external resistor, which implies a smaller
voltage difference from SDLVL to VCC, the lower the SD
sensitivity. Hence, larger input amplitude is required to assert
SD. The “Typical Operating Characteristics” section contains
graphs showing the relationship between the input amplitude
detection sensitivity and VSDLVL and RSDLVL.
Hysteresis
The SY88823V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2IN/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and,
hence, the ratios change linearly as well. Therefore, the
optical hysteresis in dB is half the electrical hysteresis in dB
given in the datasheet. The SY88823V provides typically
2.3dB SD optical hysteresis. As the SY88823V is an
electrical device, this datasheet refers to hysteresis in
electrical terms. With 4.6dB SD hysteresis, a voltage factor
of 1.7 is required to assert SD.
Hysteresis and Sensitivity Improvement
If increased SD sensitivity and hysteresis are required,
an application note entitled “Notes on Sensitivity and
Hysteresis in Micrel Post Amplifiers” is available at http://
www.micrel.com/product-info/app_hints+notes.shtml.
7
Micrel, Inc.
SY88823V
DATA+
5mV (Min.)
VIS(mV)
DATA–
900mV (Max.)
(DATA+) – (DATA–)
10mVpp (Min.)
VID(mVpp)
1800mVpp (Max.)
Figure 1. VIS and VID Definition
VCC
VCC
50Ω
VCC
50Ω
50Ω
DOUT Z0 = 50Ω
50Ω
0.1µF
/DOUT
Z0 = 50Ω
DIN
/DIN
16mA
ESD
STRUCTURE
ESD
STRUCTURE
GND
GND
Figure 2. Input Structure
Figure 3. Output Structure
VCC
VCC
ICC
16mA
4.75kΩ
SD
50Ω
50Ω
Figure 5. SD Output Structure
ESD
STRUCTURE
VCC
RSDLVL
SDLVL
16mA
2.8kΩ
REF
GND
Figure 6. SDLVL Setting Circuit
Figure 4. Power Supply Current Measurement
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AC-Coupling
Capacitors
Micrel, Inc.
SY88823V
TYPICAL APPLICATIONS CIRCUIT
VCC
SD
0.1µF
EN
DIN
From
Transimpedance
Amp.
DOUT
SY88823V
/DIN
0.1µF
50Ω
SDLVL
0.1µF
To
CDR
/DOUT
REF
0.1µF
50Ω
GND
VCC
100kΩ
0.1µF
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number
Function
Data Sheet Link
SY88773V
3.3V/5V 3.2Gbps CML Low-Power,
Limiting Post Amplifier w/ TTL LOS
http://www.micrel.com/_PDF/HBW/sy88773v.pdf
SY88823V
3.3V/5V 3.2Gbps CML Low-Power,
Limiting Post Amplifier w/ TTL SD
http://www.micrel.com/_PDF/HBW/sy88823v.pdf
SY88843V
3.3V/5V 3.2Gbps CML Low-Power,
Limiting Post Amplifier w/ TTL SD
http://www.micrel.com/_PDF/HBW/sy88843v.pdf
SY88973V
3.3V/5V 3.2Gbps CML Low-Power,
Limiting Post Amplifier w/ TTL LOS
http://www.micrel.com/_PDF/HBW/sy88973v.pdf
Application Notes
Notes on Sensitivity and Hysteresis
in Micrel Post Amplifiers
http://www.micrel.com/product-info/app_hints+notes.shtml
M9999-110905
[email protected] or (408) 955-1690
9
Micrel, Inc.
SY88823V
10 LEAD EPAD-MSOP (K10-2)
+0.08
-0.08
+0.003
-0.003
+0.05
-0.05
+0.002
-0.002
+0.15
-0.15
+0.004
-0.004
+0.10
-0.10
+0.004
-0.004
+0.008
-0.008
+0.003
-0.003
Rev.01
+0.15
-0.15
+0.006
-0.006
M9999-110905
[email protected] or (408) 955-1690
+0.07
-0.08
+0.003
-0.003
10
Micrel, Inc.
SY88823V
16-PIN MicroLEADFRAME™ (MLF-16)
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
VEE
Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLF™ Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
USA
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
M9999-110905
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