PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 D D D D D D D D D D D D D D D PC 98/99 Compliant PCI Bus Power Management Interface Specification 1.0 Compliant Advanced Configuration and Power Interface (ACPI) 1.0 Compliant Fully Compatible With the Intel 430TX (Mobile Triton II) Chipset PCI Local Bus Specification Revision 2.2 Compliant 1997 PC Card Standard Compliant 3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards Supports a Single PC Card or CardBus Slot With Hot Insertion and Removal Provides Interface to Parallel Single-Slot PC Card Power-Interface Switches like the TI TPS2211 Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and the CardBus Bus Supports Parallel PCI Interrupts, Parallel ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts Pin-to-Pin Compatible with PCI1210 Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID D D D D D D D D D D D D Pipelined Architecture Allows Greater Than 130M-Bytes-Per-Second Throughput From CardBus to PCI and From PCI to CardBus Supports Up to Five General-Purpose I/Os Five PCI Memory Windows and Two I/O Windows Available to the PC Card16 Socket Two I/O Windows and Two Memory Windows Available to the CardBus Socket Exchangeable Card Architecture (ExCA) Compatible Registers Are Mapped in Memory and I/O Space Intel 82365SL-DF Register Compatible Supports Distributed DMA (DDMA) and PC/PCI DMA Supports 16-Bit DMA on the PC Card Socket Supports Ring Indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN Supports PCI Bus Lock (LOCK) LED Activity Pin Advanced Submicron, Low-Power CMOS Technology Choice of Surface-Mount Packaging: – PGE Low-Profile Plastic Quad Flat Package (LQFP) – GGU High Density Ball Grid Array (BGA) Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Name/Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . 6 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Peripheral Component Interconnect (PCI) Interface . . . . . . . . 22 PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . 34 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . 43 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ExCA Compatibility Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . 112 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . 119 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . 121 PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . 122 PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . 123 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 description The Texas Instruments PCI1211 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1995 PC Card Standard. The PCI1211 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1211 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required. The PCI1211 is compliant with the PCI Local Bus Specification, Revision 2.2, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or CardBus PC Card bridging transactions. The PCI1211 is also compliant with the latest PCI Bus Power Management Interface Specification, Revision 1.0. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1211 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1211 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1211 can also be programmed to accept fast posted writes to improve system-bus utilization. Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features are designed into the PCI1211, such as socket activity light-emitting diode (LED) output, that are discussed in detail throughout the design specification. An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption. Unused PCI1211 inputs must be pulled up using a 43 kW resistor. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 system block diagram A simplified system block diagram using the PCI1211 is provided below. The PCI950 IRQ deserializer and the PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that capability. The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When ZV is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Other miscellaneous system interface terminals are available on the PCI1211 that include: D D D Programmable multifunction terminals SUSPEND, RI_OUT/PME (power management control signal) SPKROUT PCI Bus INTA Interrupt Controller Activity LED TPS2211 Power Switch 4 IRQSER PCI1211 PCI950 IRQSER Deserializer IRQ2–15 3 PC Card Socket Zoom Video 68 23 19 VGA Controller PCI930 ZV Switch Zoom Video External ZV Port 4 Audio Sub-System NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In ZV mode 23 pins are used for routing the ZV signals to the VGA controller. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 terminal assignments 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 CCLK CDEVSEL CGNT CSTOP CPERR CBLOCK V CC CPAR RSVD CC/BE1 CAD16 CAD14 CAD15 CAD12 GND CAD13 CAD11 CAD10 VCCCB CAD9 CC/BE0 CAD8 V CC CAD7 RSVD CAD5 CAD6 CAD3 CAD4 CAD1 GND CAD2 CAD0 CCD1 VCCD1 VCCD0 PGE LOW-PROFILE QUAD FLAT PACKAGE (BOTTOM VIEW) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 REQ GNT AD31 AD30 AD29 GND AD28 AD27 AD26 AD25 AD24 C/BE3 IDSEL VCC AD23 AD22 AD21 VCCP AD20 RST PCLK GND AD19 AD18 AD17 AD16 C/BE2 FRAME IRDY VCC TRDY DEVSEL STOP PERR SERR PAR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CTRDY CIRDY CFRAME CC/BE2 CAD17 GND CAD18 CAD19 CVS2 CAD20 CRST CAD21 CAD22 VCC CREQ CAD23 CC/BE3 VCCCB CAD24 CAD25 CAD26 GND CVS1 CINT CSERR CAUDIO CSTSCHG CCLKRUN CCD2 VCC CAD27 CAD28 CAD29 CAD30 RSVD CAD31 PCI-to-CardBus Pin Diagram 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VPPD1 VPPD0 SUSPEND MFUNC6 MFUNC5 MFUNC4 VCC MFUNC3 MFUNC2 VCCI SPKROUT MFUNC1 MFUNC0 RI_OUT/PME GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 VCC AD7 C/BE0 AD8 AD9 AD10 VCCP AD11 GND AD12 AD13 AD14 AD15 C/BE1 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 terminal assignments (continued) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 A16 A21 WE A20 A14 A19 V CC A13 A18 A8 A17 A9 IOWR A11 GND IORD OE CE2 VCCCB A10 CE1 D15 V CC D7 D14 D6 D13 D5 D12 D4 GND D11 D3 CD1 VCCD1 VCCD0 PGE LOW-PROFILE QUAD FLAT PACKAGE (BOTTOM VIEW) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 143 144 VPPD1 VPPD0 SUSPEND MFUNC6 MFUNC5 MFUNC4 VCC MFUNC3 MFUNC2 VCCI SPKROUT MFUNC1 MFUNC0 RI_OUT/PME GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 VCC AD7 C/BE0 AD8 AD9 AD10 VCCP AD11 GND AD12 AD13 AD14 AD15 C/BE1 REQ GNT AD31 AD30 AD29 GND AD28 AD27 AD26 AD25 AD24 C/BE3 IDSEL VCC AD23 AD22 AD21 VCCP AD20 RST PCLK GND AD19 AD18 AD17 AD16 C/BE2 FRAME IRDY VCC TRDY DEVSEL STOP PERR SERR PAR A22 A15 A23 A12 A24 GND A7 A25 VS2 A6 RESET A5 A4 VCC INPACK A3 REG VCCCB A2 A1 A0 GND VS1 READY(IREQ) WAIT BVD2(SPKR) BVD1(STSCHG/RI) WP(IOIS16) CD2 VCC D0 D8 D1 D9 D2 D10 PCI-to-PC Card (16-Bit) Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 terminal assignments (continued) GGU BALL GRID ARRAY PACKAGE (BOTTOM VIEW) PCI Signals N P P P M P P P L P P P K P J H G F P ÍÍ ÍÍ ÏÏ ÏÏ Í Í P P P P P P P P P P P P P ÍÍ ÍÍ ÏÏ ÏÏ P C ÎÎÎ ÎÎÎÎ ÎÎ ÍÍ ÍÍ C P P C P P C C P C C P C C C C P P P P P P C B P C C A P C C C P P P P D P P Power Switch P P E ÏÏ ÏÏ ÍÍ ÍÍ Interrupt and Misc. P P C C C C C C C C ÍÍ ÍÍ ÏÏ C C C C C C C C ÍÍ C C C C C C C C ÏÏ ÍÏÏ Í C C C C C C C C C C C C C C C C C C C C CardBus Signals 1 2 3 4 ÎÎ ÍÍ ÎÎ ÍÍ 5 6 7 ÏÏ ÏÏ 8 VCC Power Switch GND Interrupt and Miscellaneous 9 10 Clamping Voltages 11 12 13 C CardBus Signals P PCI Signals PCI-to-CardBus and PCI-to-PC Card (16-Bit) Diagram signal names and terminal assignments Signal names and their terminal assignments are shown in Table 1 through Table 4. Table 1 and Table 2 show the terminal assignments for the CardBus PC Card, and Table 3 and Table 4 show the terminal assignments for the 16-bit PC Card. Table 2 and Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name and its associated terminal number. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 1. CardBus PC Card Signal Names – Sorted by BGA Terminal Number† PIN NO. GGU PGE A1 1 A2 PIN NO. SIGNAL NAME GGU PGE REQ C11 106 143 RSVD C12 105 A3 140 CAD28 C13 104 A4 137 CCD2 D1 8 A5 133 CSERR D2 A6 129 CAD26 A7 126 VCCCB A8 124 CAD23 D5 PIN NO. SIGNAL NAME GGU PGE CGNT G10 92 CSTOP G11 91 CPERR G12 89 AD27 G13 90 7 AD28 H1 D3 6 GND D4 5 AD29 136 CCLKRUN PIN NO. SIGNAL NAME SIGNAL NAME GGU PGE CAD11 L4 42 GND CAD10 L5 46 AD9 CAD9 L6 50 VCC VCCCB L7 55 AD2 21 PCLK L8 59 RI_OUT/PME H2 22 GND L9 63 VCCI H3 23 AD19 L10 67 MFUNC4 H4 24 AD18 L11 70 SUSPEND A9 120 CAD21 D6 132 CINT H10 85 CAD7 L12 75 CCD1 A10 116 CAD19 D7 128 CAD25 H11 86 VCC L13 76 CAD0 A11 112 CC/BE2 D8 121 CAD22 H12 87 CAD8 M1 35 SERR H13 88 CC/BE0 M2 36 PAR J1 25 AD17 M3 39 AD14 A12 110 CIRDY D9 117 CVS2 A13 109 CTRDY D10 113 CAD17 B1 2 GNT D11 103 CBLOCK J2 26 AD16 M4 43 AD11 B2 144 CAD31 D12 102 VCC J3 27 C/BE2 M5 47 AD8 B3 141 CAD29 D13 101 CPAR J4 28 FRAME M6 51 AD6 B4 138 VCC E1 12 C/BE3 J10 81 CAD3 M7 53 AD4 B5 134 CAUDIO E2 11 AD24 J11 82 CAD6 M8 58 GND B6 130 GND E3 10 AD25 J12 83 CAD5 M9 62 SPKROUT B7 125 CC/BE3 E4 9 AD26 J13 84 RSVD M10 66 VCC B8 123 CREQ E10 100 RSVD K1 29 IRDY M11 69 MFUNC6 B9 119 CRST E11 99 CC/BE1 K2 30 VCC M12 72 VPPD1 B10 115 CAD18 E12 98 CAD16 K3 31 TRDY M13 74 VCCD1 B11 111 CFRAME E13 97 CAD14 K4 41 AD12 N1 37 C/BE1 B12 108 CCLK F1 16 AD22 K5 45 AD10 N2 38 AD15 B13 107 CDEVSEL F2 15 AD23 K6 49 AD7 N3 40 AD13 C1 4 AD30 F3 14 VCC K7 56 AD1 N4 44 VCCP C2 3 F4 13 IDSEL K8 60 MFUNC0 N5 48 C/BE0 C3 142 CAD30 AD31 F10 96 CAD15 K9 64 MFUNC2 N6 52 AD5 C4 139 CAD27 F11 95 CAD12 K10 77 CAD2 N7 54 AD3 C5 135 CSTSCHG F12 94 GND K11 78 GND N8 57 AD0 C6 131 CVS1 F13 93 CAD13 K12 79 CAD1 N9 61 MFUNC1 C7 127 CAD24 G1 18 VCCP K13 80 CAD4 N10 65 MFUNC3 C8 122 VCC G2 17 AD21 L1 32 DEVSEL N11 68 MFUNC5 C9 118 CAD20 G3 19 AD20 L2 33 STOP N12 71 VPPD0 C10 114 GND G4 20 RST L3 34 PERR N13 73 VCCD0 † The PGE (LQFP) pin numbers are shown also. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 2. CardBus PC Card Signal Names – Sorted Alphabetically SIGNAL NAME 8 PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. SIGNAL NAME PIN NO. PGE GGU PGE GGU PGE GGU PGE GGU AD0 57 N8 CAD0 76 L13 CC/BE2 112 A11 MFUNC2 64 K9 AD1 56 K7 CAD1 79 K12 CC/BE3 125 B7 MFUNC3 65 N10 AD2 55 L7 CAD2 77 K10 CCLK 108 B12 MFUNC4 67 L10 AD3 54 N7 CAD3 81 J10 CCD1 75 L12 MFUNC5 68 N11 AD4 53 M7 CAD4 80 K13 CCD2 137 A4 MFUNC6 69 M11 AD5 52 N6 CAD5 83 J12 CCLKRUN 136 D5 PAR 36 M2 AD6 51 M6 CAD6 82 J11 CDEVSEL 107 B13 PCLK 21 H1 AD7 49 K6 CAD7 85 H10 CFRAME 111 B11 PERR 34 L3 AD8 47 M5 CAD8 87 H12 CGNT 106 C11 REQ 1 A1 AD9 46 L5 CAD9 89 G12 CINT 132 D6 RI_OUT/PME 59 L8 AD10 45 K5 CAD10 91 G11 CIRDY 110 A12 RST 20 G4 AD11 43 M4 CAD11 92 G10 CPAR 101 D13 SERR 35 M1 AD12 41 K4 CAD12 95 F11 CPERR 104 C13 RSVD 84 E10 AD13 40 N3 CAD13 93 F13 CREQ 123 B8 RSVD 100 J13 AD14 39 M3 CAD14 97 E13 CRST 119 B9 RSVD 143 A2 AD15 38 N2 CAD15 96 F10 CSERR 133 A5 SPKROUT 62 M9 AD16 26 J2 CAD16 98 E12 CSTOP 105 C12 STOP 33 L2 AD17 25 J1 CAD17 113 D10 CSTSCHG 135 C5 SUSPEND 70 L11 AD18 24 H4 CAD18 115 B10 CTRDY 109 A13 TRDY 31 K3 AD19 23 H3 CAD19 116 A10 CVS1 131 C6 VCC 14 F3 AD20 19 G3 CAD20 118 C9 CVS2 117 D9 VCC 30 K2 AD21 17 G2 CAD21 120 A9 DEVSEL 32 L1 VCC 50 L6 AD22 16 F1 CAD22 121 D8 FRAME 28 J4 VCC 66 M10 AD23 15 F2 CAD23 124 A8 GND 6 D3 VCC 86 H11 AD24 11 E2 CAD24 127 C7 GND 22 H2 VCC 102 D12 AD25 10 E3 CAD25 128 D7 GND 42 L4 VCC 122 C8 AD26 9 E4 CAD26 129 A6 GND 58 M8 VCC 138 B4 AD27 8 D1 CAD27 139 C4 GND 78 K11 VCCCB 90 G13 AD28 7 D2 CAD28 140 A3 GND 94 F12 VCCCB 126 A7 AD29 5 D4 CAD29 141 B3 GND 114 C10 VCCD0 73 N13 AD30 4 C1 CAD30 142 C3 GND 130 B6 VCCD1 74 M13 AD31 3 C2 CAD31 144 B2 GNT 2 B1 VCCI 63 L9 C/BE0 48 N5 CAUDIO 134 B5 IDSEL 13 F4 VCCP 18 G1 C/BE1 37 N1 CBLOCK 103 D11 IRDY 29 K1 VCCP 44 N4 C/BE2 27 J3 CC/BE0 88 H13 MFUNC0 60 K8 VPPD0 71 N12 C/BE3 12 E1 CC/BE1 99 E11 MFUNC1 61 N9 VPPD1 72 M12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 3. 16-Bit PC Card Signal Names – Sorted by BGA Terminal Number† PIN NO. GGU PGE PIN NO. SIGNAL NAME GGU PGE PIN NO. SIGNAL NAME GGU PGE PIN NO. SIGNAL NAME GGU PGE SIGNAL NAME A1 1 REQ C11 106 WE G10 92 OE L4 42 GND A2 143 D2 C12 105 A20 G11 91 CE2 L5 46 AD9 A3 140 D8 C13 104 A14 G12 89 A10 L6 50 VCC A4 137 CD2 D1 8 AD27 G13 90 VCCCB L7 55 AD2 A5 133 WAIT D2 7 AD28 H1 21 PCLK L8 59 RI_OUT/PME A6 129 A0 D3 6 GND H2 22 GND L9 63 VCCI A7 126 VCCCB D4 5 AD29 H3 23 AD19 L10 67 MFUNC4 A8 124 A3 D5 136 WP(IOIS16) H4 24 AD18 L11 70 SUSPEND A9 120 A5 D6 132 READY(IREQ) H10 85 D7 L12 75 CD1 A10 116 A25 D7 128 A1 H11 86 VCC L13 76 D3 A11 112 A12 D8 121 A4 H12 87 D15 M1 35 SERR A12 110 A15 D9 117 VS2 H13 88 CE1 M2 36 PAR A13 109 A22 D10 113 A24 J1 25 AD17 M3 39 AD14 B1 2 GNT D11 103 A19 J2 26 AD16 M4 43 AD11 B2 144 D10 D12 102 VCC J3 27 C/BE2 M5 47 AD8 B3 141 D1 D13 101 A13 B4 138 VCC E1 12 C/BE3 B5 134 BVD2(SPKR) E2 11 B6 130 GND E3 10 B7 125 REG E4 9 B8 123 INPACK E10 B9 119 RESET E11 B10 115 A7 E12 J4 28 FRAME M6 51 AD6 J10 81 D5 M7 53 AD4 AD24 J11 82 D13 M8 58 GND AD25 J12 83 D6 M9 62 SPKROUT AD26 J13 84 D14 M10 66 VCC 100 A18 K1 29 IRDY M11 69 MFUNC6 99 A8 K2 30 VCC M12 72 VPPD1 98 A17 K3 31 TRDY M13 74 VCCD1 B11 111 A23 E13 97 A9 K4 41 AD12 N1 37 C/BE1 B12 108 A16 F1 16 AD22 K5 45 AD10 N2 38 AD15 B13 107 A21 F2 15 AD23 K6 49 AD7 N3 40 AD13 C1 4 AD30 F3 14 VCC K7 56 AD1 N4 44 VCCP C2 3 AD31 F4 13 IDSEL K8 60 MFUNC0 N5 48 C/BE0 C3 142 D9 F10 96 IOWR K9 64 MFUNC2 N6 52 AD5 C4 139 D0 F11 95 A11 K10 77 D11 N7 54 AD3 C5 135 BVD1(STSCHG/RI) F12 94 GND K11 78 GND N8 57 AD0 C6 131 VS1 F13 93 IORD K12 79 D4 N9 61 MFUNC1 C7 127 A2 G1 18 VCCP K13 80 D12 N10 65 MFUNC3 C8 122 VCC G2 17 AD21 L1 32 DEVSEL N11 68 MFUNC5 C9 118 A6 G3 19 AD20 L2 33 STOP N12 71 VPPD0 RST L3 34 PERR N13 73 VCCD0 C10 114 GND G4 20 † The PGE (LQFP) pin numbers are shown also. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 4. 16-Bit PC Card Signal Names – Sorted Alphabetically PIN NO. SIGNAL NAME PGE GGU PIN NO. SIGNAL NAME PGE GGU PIN NO. SIGNAL NAME PGE GGU PIN NO. SIGNAL NAME PGE GGU A0 129 A6 AD10 45 K5 D4 79 K12 PAR 36 M2 A1 128 D7 AD11 43 M4 D5 81 J10 PCLK 21 H1 A2 127 C7 AD12 41 K4 D6 83 J12 PERR 34 L3 A3 124 A8 AD13 40 N3 D7 85 H10 REQ 1 A1 A4 121 D8 AD14 39 M3 D8 140 A3 READY(IREQ) 132 D6 A5 120 A9 AD15 38 N2 D9 142 C3 REG 125 B7 A6 118 C9 AD16 26 J2 D10 144 B2 RESET 119 B9 A7 115 B10 AD17 25 J1 D11 77 K10 RI_OUT/PME 59 L8 A8 99 E11 AD18 24 H4 D12 80 K13 RST 20 G4 A9 97 E13 AD19 23 H3 D13 82 J11 SERR 35 M1 A10 89 G12 AD20 19 G3 D14 84 J13 SPKROUT 62 M9 A11 95 F11 AD21 17 G2 D15 87 H12 A12 112 A11 AD22 16 F1 DEVSEL 32 L1 STOP 33 L2 SUSPEND 70 L11 A13 101 D13 AD23 15 F2 FRAME 28 A14 104 C13 AD24 11 E2 GND 6 J4 TRDY 31 K3 D3 VCC 14 F3 A15 110 A12 AD25 10 E3 GND 22 H2 VCC 30 K2 A16 108 B12 AD26 9 E4 GND A17 98 E12 AD27 8 D1 GND 42 L4 VCC 50 L6 58 M8 VCC 66 M10 A18 100 E10 AD28 7 D2 GND 78 K11 VCC 86 H11 A19 103 D11 AD29 5 D4 GND 94 A20 105 C12 AD30 4 C1 GND 114 F12 VCC 102 D12 C10 VCC 122 C8 A21 107 B13 AD31 3 C2 GND 130 B6 VCC 138 B4 A22 109 A13 BVD1(STSCHG/RI) 135 C5 GNT 2 B1 VCCCB 90 G13 A23 111 B11 BVD2(SPKR) 134 B5 IDSEL 13 F4 VCCCB 126 A7 A24 113 D10 C/BE0 48 N5 INPACK 123 B8 VCCD0 73 N13 A25 116 A10 C/BE1 37 N1 IORD 93 F13 VCCD1 74 M13 AD0 57 N8 C/BE2 27 J3 IOWR 96 F10 VCCI 63 L9 AD1 56 K7 C/BE3 12 E1 IRDY 29 K1 VCCP 18 G1 AD2 55 L7 CD1 75 L12 MFUNC0 60 K8 VCCP 44 N4 AD3 54 N7 CD2 137 A4 MFUNC1 61 N9 VPPD0 71 N12 AD4 53 M7 CE1 88 H13 MFUNC2 64 K9 VPPD1 72 M12 AD5 52 N6 CE2 91 G11 MFUNC3 65 N10 VS1 131 C6 AD6 51 M6 D0 139 C4 MFUNC4 67 L10 VS2 117 D9 AD7 49 K6 D1 141 B3 MFUNC5 68 N11 WAIT 133 A5 AD8 47 M5 D2 143 A2 MFUNC6 69 M11 WE 106 C11 AD9 46 L5 D3 76 L13 OE 92 G10 WP(IOIS16) 136 D5 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Terminal numbers are shown for both the PGE LQF package and the GGU ball grid array package. power supply TERMINAL FUNCTION NAME PGE NUMBER GGU NUMBER GND 6, 22, 42, 58, 78, 94, 114, 130 B6, C10, D3, F12, H2, K11, L4, M8 Device ground terminals VCC 14, 30, 50, 66, 86, 102, 122, 138 B4, C8, D12, F3, H11, K2, L6, M10 Power supply terminal for core logic (3.3 V) VCCCB 90, 126 A7, G13 Clamping voltage for PC Card interface. Indicates card signaling environment of 5 V or 3.3 V. Clamping voltage for multifunction terminals (5 V or 3.3 V) VCCI 63 L9 VCCP 18, 44 G1, N4 Clamping voltage for PCI signaling (5 V or 3.3 V) PC Card power switch TERMINAL NAME PIN NUMBER PGE GGU VCCD0 VCCD1 73 74 N13 M13 VPPD0 VPPD1 71 72 N12 M12 I/O TYPE FUNCTION Logic controls to the TPS2211 PC Card power interface switch to control AVCC. O Logic controls to the TPS2211 PC Card power interface switch to control AVPP. PCI system TERMINAL NAME PCLK PIN NUMBER PGE GGU 21 H1 I/O TYPE FUNCTION I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. PCI reset. When the PCI bus reset is asserted, RST causes the PCI1211 to place all output buffers in a high-impedance state and reset all internal registers. When RST is asserted, the device is completely nonfunctional. After RST is deasserted, the PCI1211 is in its default state. RST 20 G4 I When SUSPEND and RST are asserted, the device is protected from RST clearing the internal registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) PCI address and data TERMINAL NAME 12 PIN NUMBER I/O TYPE FUNCTION I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. PGE GGU AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 3 4 5 7 8 9 10 11 15 16 17 19 23 24 25 26 38 39 40 41 43 45 46 47 49 51 52 53 54 55 56 57 C2 C1 D4 D2 D1 E4 E3 E2 F2 F1 G2 G3 H3 H4 J1 J2 N2 M3 N3 K4 M4 K5 L5 M5 K6 M6 N6 M7 N7 L7 K7 N8 C/BE3 C/BE2 C/BE1 C/BE0 12 27 37 48 E1 J3 N1 N5 I/O PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). PAR 36 M2 I/O PCI bus parity. In all PCI bus read and write cycles, the PCI1211 calculates even parity across the AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI1211 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) PCI interface control TERMINAL NAME PIN NUMBER I/O TYPE FUNCTION PGE GGU DEVSEL 32 L1 I/O PCI device select. The PCI1211 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1211 monitors DEVSEL until a target responds. If no target responds before timeout occurs, the PCI1211 terminates the cycle with an initiator abort. FRAME 28 J4 I/O PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. GNT 2 B1 I PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1211 access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. IDSEL 13 F4 I Initialization device select. IDSEL selects the PCI1211 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. IRDY 29 K1 I/O PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PERR 34 L3 I/O PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register. REQ 1 A1 O PCI bus request. REQ is asserted by the PCI1211 to request access to the PCI bus as an initiator. SERR 35 M1 O PCI system error. SERR is an output that is pulsed from the PCI1211 when enabled through the command register indicating a system error has occurred. The PCI1211 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. STOP 33 L2 I/O PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. TRDY 31 K3 I/O PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) multifunction and miscellaneous pins TERMINAL NAME MFUNC0 PIN NUMBER PGE GGU 60 K8 I/O TYPE FUNCTION I/O Multifunction Terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, GPE, socket activity LED output, ZV output select, CardBus audio PWM, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. Multifunction Terminal 1. MFUNC1 can be configured as GPI1, GPO1, GPE, socket activity LED output, ZV output select, CardBus audio PWM, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. Serial Data (SDA). When the serial bus mode is implemented by pulling up the SCA and SCL terminals, the MFUNC1 terminal provides the SDA signaling. The two-pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. Refer to the serial bus interface protocol description on page 30 for details on other serial bus applications. MFUNC1 61 N9 I/O MFUNC2 64 K9 I/O Multifunction Terminal 2. MFUNC2 can be configured as PC/PCI DMA Request, GPI2, GPO2, socket activity LED output, ZV output select, CardBus audio PWM, GPE, RI_OUT, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. MFUNC3 65 N10 I/O Multifunction Terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. Refer to the multifunction routing register description on page 61 for configuration details. Multifunction Terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED, RI_OUT output, ZV output select, CardBus audio PWM, GPE, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. Serial Clock (SCL). When the serial bus mode is implemented by pulling the SDA and SCL terminals, the MFUNC4 terminal provides the SCL signaling. The two-pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. Refer to the serial bus interface protocol description on page 30 for details on other serial bus applications. MFUNC4 67 L10 I/O MFUNC5 68 N11 I/O Multifunction Terminal 5. MFUNC5 can be configured as PC/PCI DMA Grant, GPI4, GPO4, socket activity LED output, ZV output select, CardBus audio PWM, GPE, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. MFUNC6 69 M11 I/O Multifunction Terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. RI_OUT/PME 59 L8 O Ring Indicate Out and Power Management Event Output. Provides output for either RI_OUT or PME signals. SUSPEND 70 L11 I Suspend. SUSPEND is used to protect the internal registers from clearing when the RST signal is asserted. See suspend mode on page 39 for details. SPKROUT 62 M9 O Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1211 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR//CAUDIO inputs. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) The address and data and interface control terminals for the 16-bit PC Card are shown in the following two tables. 16-bit PC Card address and data TERMINAL NAME PIN NUMBER I/O TYPE FUNCTION PGE GGU A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 116 113 111 109 107 105 103 100 98 108 110 104 101 112 95 89 97 99 115 118 120 121 124 127 128 129 A10 D10 B11 A13 B13 C12 D11 E10 E12 B12 A12 C13 D13 A11 F11 G12 E13 E11 B10 C9 A9 D8 A8 C7 D7 A6 O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 87 84 82 80 77 144 142 140 85 83 81 79 76 143 141 139 H12 J13 J11 K13 K10 B2 C3 A3 H10 J12 J10 K12 L13 A2 B3 C4 I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) 16-bit PC Card interface control TERMINAL NAME BVD1 (STSCHG/RI) PGE 135 I/O TYPE FUNCTION I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 89 for enable bits. See ExCA card status-change register on page 88 and the ExCA interface status register on page 85 for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. GGU C5 BVD2 (SPKR) 134 B5 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 89 for enable bits. See ExCA card status-change register on page 88 and the interface status register on page 85 for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1211 and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. CD1 CD2 75 137 L12 A4 I PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see interface status register. CE1 CE2 88 91 H13 G11 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation. O I/O read. IORD is asserted by the PCI1211 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1211 asserts IORD during DMA transfers from the PC Card to host memory. INPACK IORD IOWR OE 16 PIN NUMBER 123 93 96 92 B8 F13 F10 G10 O O I/O write. IOWR is driven low by the PCI1211 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1211 asserts IOWR during transfers from host memory to the PC Card. Output enable. OE is driven low by the PCI1211 to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1211 asserts OE to indicate TC for a DMA write operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) 16-bit PC Card interface control (continued) TERMINAL NAME READY (IREQ) PIN NUMBER PGE 132 I/O TYPE FUNCTION GGU D6 I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I /O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG 125 B7 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1211 asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET 119 B9 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. WAIT 133 A5 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. WE 106 C11 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PC1211 asserts WE to indicate TC for a DMA read operation. Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. WP (IOIS16) 136 D5 I I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation. VS1 VS2 131 117 C6 D9 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the 16-bit PC Card. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) The interface system, address and data, and interface control terminals for the CardBus PC Card system are shown in the following three tables. CardBus PC Card interface system TERMINAL NAME PIN NUMBER PGE I/O TYPE FUNCTION GGU CCLK 108 B12 O CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CLKRUN, CINT, CSTSCHG, CAUDIO, CCD1, CCD2, and CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CCLKRUN 136 D5 O CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1211 to indicate that the CCLK frequency is going to be decreased. I/O CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be 3-stated, and the PCI1211 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. CRST 18 119 B9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) CardBus PC Card address and data TERMINAL NAME PIN NUMBER PGE GGU CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 144 142 141 140 139 129 128 127 124 121 120 118 116 115 113 98 96 97 93 95 92 91 89 87 85 82 83 80 81 77 79 76 B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13 CC/BE3 CC/BE2 CC/BE1 CC/BE0 12 27 37 48 E1 J3 N1 N5 CPAR 101 D13 I/O TYPE FUNCTION I/O PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit. I/O CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24). I/O CardBus parity. In all CardBus read and write cycles, the PCI1211 calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1211 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Terminal Functions (Continued) CardBus PC Card interface control TERMINAL NAME PIN NUMBER I/O TYPE FUNCTION CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1211 supports the binary audio mode and outputs a binary signal from the card to SPKROUT. PGE GGU CAUDIO 134 B5 I CBLOCK 103 D11 I/O CCD1 CCD2 75 137 L12 A4 I CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. CDEVSEL 107 B13 I/O CardBus device select. The PCI1211 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1211 monitors CDEVSEL until a target responds. If no target responds before timeout occurs, the PCI1211 terminates the cycle with an initiator abort. CFRAME 111 B11 I/O CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. CGNT 106 C11 I CardBus bus grant. CGNT is driven by the PCI1211 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CINT 132 D6 I CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. CIRDY 110 A12 I/O CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. CPERR 104 C13 I/O CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CREQ 123 B8 I CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CardBus lock. CBLOCK is used to gain exclusive access to a target. CSERR 133 A5 I CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1211 can report CSERR to the system by assertion of SERR on the PCI interface. CSTOP 105 C12 I/O CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CSTSCHG 135 C5 I CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status, and is used as a wake-up mechanism. CTRDY 109 A13 I/O CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. CVS1 CVS2 131 117 C6 D9 I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 power supply sequencing The PCI1211 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltage. The core power supply is always 3.3 V. The clamp voltage can be either 3.3 V or 5 V, depending on the interface. The following power-up and power-down sequences are recommended. The power-up sequence is: 1. Apply 3.3-V power to the core. 2. Assert PRST to the device to disable the outputs during power up. Output drivers must be powered up in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply. 3. Apply the clamp voltage. The power-down sequence is: 1. Use PRST to switch outputs to a high-impedance state. 2. Remove the clamp voltage. 3. Remove the 3.3-V power from the core. I/O characteristics Figure 1 shows a 3-state bidirectional buffer. The recommended operating conditions table, on page 119, provides the electrical characteristics of the inputs and outputs. NOTE: The PCI1211 meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus Specification Revision 2.2. VCCP Tied for Open Drain OE Pad Figure 1. 3-State Bidirectional Buffer NOTE: Unused pins (input or I/O) must be held high or low to prevent them from floating. clamping voltages The clamping voltages are set to match whatever external environment the PCI1211 will be working with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI1211 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, VCCP can be connected to a 5-V power supply. The PCI1211 requires three separate clamping voltages because it supports a wide range of features. The three voltages are listed and defined in the recommended operating conditions, on page 119. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 peripheral component interconnect (PCI) interface The PCI1211 is fully compliant with the PCI Local Bus Specification, Revision 2.2. The PCI1211 provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the VCCP terminals to the desired voltage level. In addition to the mandatory PCI signals the PCI1211 provides the optional interrupt signal INTA. PCI bus lock (LOCK) The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1211 as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal via the multifunction routing register, see the multifunction routing register description on page 61 for details. Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor). PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock. An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario, the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. The PCI1211 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the PCI Local Bus Specification, Revision 2.2, and the issue is resolved by the PCI master using LOCK. loading subsystem identification The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC ’97 requirement. The PCI1211 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by setting the SUBSYSRW bit in the system control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM). 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 loading subsystem identification (continued) In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The PCI1211 loads the data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the PCI reset from the entire PCI1211 core, including the serial bus state machine (see suspend mode, on page 39, for details on using SUSPEND). The PCI1211 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM. Refer to serial bus interface on page 30 for details on the two-wire serial bus controller and applications. PC Card applications This section describes the PC Card interfaces of the PCI1211. Discussions are provided for: D D D D D D D D Card insertion/removal and recognition P2C power-switch interface Zoom video support Speaker and audio applications LED socket activity indicator PC Card 16-distributed DMA support PC Card controller programming model CardBus socket registers PC Card insertion/removal and recognition The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, and CVS2 for CardBus). The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1995 PC Card Standard and is shown in Table 5. Table 5. PC Card Card-Detect and Voltage-Sense Connections CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE Ground Ground Open Open 5V 16-bit PC Card 5V Ground Ground Open Ground 5V 16-bit PC Card 5 V and 3.3 V Ground Ground Ground Ground 5V 16-bit PC Card 5 V, 3.3 V, and X.X V Ground Ground Open Ground LV 16-bit PC Card 3.3 V Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V Y.Y V Ground Ground Ground Open LV 16-bit PC Card Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V LV CardBus PC Card Y.Y V Connect to CVS1 Ground Open Connect to CCD2 Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 P2C power-switch interface (TPS2211) The PCI1211 provides a P2C (PCMCIA peripheral control) interface for control of the PC Card power switch. The VCCD and VPPD terminals are used with the TI TPS2211 single slot PC Card power interface switch to provide power switch support. Figure 2 shows the terminal assignments for the TPS2211. Figure 3 illustrates a typical application, where the PCI1211 represents the PC Card controller. VCCD0 VCCD1 3.3V 3.3V 5V 5V GND OC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SHDN VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V Figure 2. TPS2211 Terminal Assignments The PCI1211 also includes support for the Maxim 1602 single-channel CardBus and PCMCIA power-switching network. Application of this power switch would be similar to the TPS2211. Power Supply 12 V 5V 3.3 V Supervisor 12V 5V 3.3V SHDN SHDN TPS2211 AVPP AVCC PCI1211 (PCMCIA Controller) VCCD0 VCCD1 VPPD0 VPPD1 VPP1 VPP2 VCC VCC PC Card OC Figure 3. TPS2211 Typical Application zoom video support The PCI1211 allows for the implementation of zoom video for PC Cards. Zoom video is supported by setting the ZVENABLE bit in the card control register. Setting this bit puts PC Card-16 address lines A25–A4 of the PC Card interface in the high-impedance state. These lines can then be used to transfer video and audio data directly to the appropriate controller. Card address lines A3–A0 can still be used to access PC Card CIS registers for PC Card configuration. Figure 4 illustrates a PCI1211 ZV implementation. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 zoom video support (continued) Speakers CRT Motherboard PCI Bus VGA Controller Audio Codec Zoom Video Port PCM Audio Input 19 4 PC Card 19 PC Card Interface PCI1211 Video Audio 4 Figure 4. Zoom Video Implementation Using PCI1211 Not shown in Figure 4 is the multiplexing scheme used to route either a socket ZV source or an external ZV source to the graphics controller. A typical external source might be provided from a high-speed serial bus like IEEE1394. The PCI1211 provides ZVSTAT, ZVSEL0 signals on the multifunction terminals to switch external bus drivers. Figure 5 shows an implementation for switching between two ZV streams using external logic. PCI1211 ZVSTAT ZVSEL0 Figure 5. Zoom Video Switching Application The example shown in Figure 5 illustrates an implementation using standard 3-state bus drivers with active-low output enables. ZVSEL0 is an active-low output indicating that the Socket ZV mode is enabled. ZVSTAT is an active-high output indicating the PCI1211 socket is enabled for ZV mode. The implementation shown in Figure 5 can be used if PC Card ZV is prioritized over other sources. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 SPKROUT and CAUDPWM usage SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 pin becomes SPKR. This terminal is also used in CardBus binary audio applications, and is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI1211. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the PC Card socket is used in the PCI1211 to produce SPKROUT. This output is enabled by the SPKROUTEN bit in the card control register. Older controllers support CAUDIO in binary or PWM mode but use the same pin (SPKROUT). Some audio chips may not support both modes on one pin and may have a separate pin for binary and PWM. The PCI1211 implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal. The AUD2MUX bit located in the card control register is programmed to route a CardBus CAUDIO PWM terminal to CAUDPWM. Refer to the multifunction routing register description on page 61 for details on configuring the MFUNC terminals. Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM. System Core Logic BINARY_SPKR SPKROUT Speaker Subsystem PCI1211 CAUDPWM PWM_SPKR Figure 6. Sample Application of SPKROUT and CAUDPWM LED socket activity indicators A socket activity LED indicates when a PC Card is being accessed. The LED_SKT signal can be routed to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate socket activity. Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals. The LED signal is active high and is driven for 64-ms durations. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 7 can be implemented to provide LED signaling, and it is left for the board designer to implement the circuit that best fits the application. The LED activity signal is valid when a card is inserted, powered, and not in reset. For PC Card 16, the LED activity signal is pulsed when READY/IREQ is low. For CardBus cards, the LED activity signal is pulsed if CFRAME, CIRDY, or CREQ is active. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 LED socket activity indicators (continued) Current Limiting R ≈ 500 Ω PCI1211 LED ApplicationSpecific Delay Current Limiting R ≈ 500 Ω PCI1211 LED Figure 7. Two Sample LED Circuits As indicated, the LED signal is driven for 64 ms by a counter circuit. To avoid the possibility of the LED appearing to be stuck when the PCI clock is stopped, the LED signaling is cut-off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the CLKRUN protocol, or when in the D2 or D1 power state. If any additional socket activity occurs during this counter cycle, the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), the LED signal remains driven. PC Card16 Distributed DMA support The PCI1211 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. Table 6 shows the DDMA register configuration. Two critical PCI configuration header registers for DDMA are the socket DMA register 0 and the socket DMA register 1. Distributed DMA is enabled through socket DMA register 0 and the contents of this register configure the PC Card-16 terminal (SPKR, IOIS16, or INPACK) which is used for the DMA request signal, DREQ. The base address of the DDMA slave registers and the transfer size (bytes or words) are programmed through the socket DMA register 1. Refer to the PC Card controller programming model on page 43 and the accompanying register descriptions for details. Table 6. Distributed DMA Registers TYPE R W R W R DMA BASE ADDRESS OFFSET (HEX) REGISTER NAME Reserved Page Reserved Reserved N/A W Mode R Multichannel W Mask Reserved Reserved POST OFFICE BOX 655303 Current address 00 Base address Current count 04 Base count N/A Status Request Command N/A Master clear • DALLAS, TEXAS 75265 Reserved 08 0C 27 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PC Card16 Distributed DMA support (continued) The DDMA registers contain control and status information consistent with the 8237 DMA controller; however, the register locations are reordered and expanded in some cases. While the DDMA register definitions are identical to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI1211 implements these obsolete register bits as read-only, nonfunctional bits. The reserved registers shown in Table 6 are implemented as read-only and return zeros when read. Writes to reserved registers have no effect. The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ signal assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed above, this is done through socket DMA register 0 and socket DMA register 1. The DMA register set is then programmed similarly to an 8237 controller, and the PCI1211 awaits a DREQ assertion from the PC Card requesting a DMA transfer. DMA writes transfer data from the PC Card to PCI memory addresses. The PCI1211 accepts data 8 or 16 bits at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its REQ signal. Once granted, the PCI bus and the bus returns to an idle state. The PCI1211 initiates a PCI memory write command to the current memory address and transfers the data in a single data phase. After terminating the PCI cycle, the PCI1211 accepts the next byte(s) from the PC Card until the transfer count expires. DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ, the PCI1211 asserts REQ to acquire the PCI bus. Once granted the bus and the bus is idle, the PCI1211 initiates a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the programmed data width. After terminating the PCI cycle, the data is passed on to the PC Card. After terminating the PC Card cycle, the PCI1211 requests access to the PCI bus again until the transfer count has expired. The PCI1211 target interface acts normally during this procedure, and accepts I/O reads and writes to the DDMA registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1211 asserts TC and ends the PC Card cycle(s). TC is indicated in the DDMA status register. At the PC Card interface, the PCI1211 supports demand mode transfers. The PCI1211 asserts DACK during the transfer unless DREQ is deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations, and is mapped to WE PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all transfers, and the DREQ terminal is routed to one of three options which is programmed through socket DMA register 0. PC Card-16 PC/PCI DMA Some chipsets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol, the PCI1211 acts as a PCI target device to certain DMA related I/O addresses. The PCI1211 PCREQ and PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals. Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1211) requests a DMA transfer on a particular channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus, and grants the channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle and memory cycles are then presented on the PCI bus which perform the DMA transfers similarly to legacy DMA master devices. PC/PCI DMA is enabled for the PC Card-16 slot by setting bit 19 in the respective system control register. On power-up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 of the system control register is a global enable for PC/PCI DMA, and is set at power-up and never cleared if the PC/PCI DMA mechanism is implemented. The desired DMA channel for the PC Card-16 slot must be configured through bits 18–16 in the system control register. The channels are configured as indicated in Table 7. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 7. PC/PCI Channel Assignments SYSTEM CONTROL REGISTER DMA CHANNEL CHANNEL TRANSFER DATA WIDTH 0 Channel 0 8-bit DMA transfers 1 Channel 1 8-bit DMA transfers 1 0 Channel 2 8-bit DMA transfers 0 1 1 Channel 3 8-bit DMA transfers 1 0 0 Channel 4 Not used 1 0 1 Channel 5 16-bit DMA transfers 1 1 0 Channel 6 16-bit DMA transfers 1 1 1 Channel 7 16-bit DMA transfers BIT 18 BIT 17 BIT16 0 0 0 0 0 As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA register 0. The data transfer width is a function of channel number, and the DDMA slave registers are not used. When a DREQ is received from a PC Card, and the channel has been granted, the PCI1211 decodes the I/O addresses listed in Table 8 and performs actions dependent upon the address. Table 8. I/O Addresses Used for PC/PCI DMA DMA I/O ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE 00h Normal 0 I/O read/write 04h Normal TC 1 I/O read/write C0h Verify 0 I/O read C4h Verify TC 1 I/O read The PC/PCI DMA as a PC Card-16 DMA mechanism may not provide the performance levels of DDMA; however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master state machine is required to support PC/PCI DMA since the DMA control is centralized in the chipset. This DMA scheme is often referred to as centralized DMA for this reason. CardBus socket registers The PCI1211 contains all registers for compatibility with the latest PCI-to-PCMCIA CardBus bridge specification. These registers exist as the CardBus socket registers, and are listed in Table 9. Table 9. CardBus Socket Registers REGISTER NAME OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket power management 20h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 serial bus interface The PCI1211 provides a serial bus interface to accommodate loading subsystem identification and select register defaults through a serial EEPROM. The PCI1211 serial bus interface is compatible with various I2C and SMBus components. serial bus interface implementation The PCI1211 defaults to serial bus interface disabled. To enable the serial interface, appropriate pullup resistors must be implemented on the SDA and SCL signals, i.e., the MFUNC1 and MFUNC4 terminals. In addition, pullup resistors must be implemented on VCCD0 and VCCD1. When the interface is detected, the SBDETECT bit in the system control register is set. The SBDETECT bit is cleared by a write back of 1. The PCI1211 implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). The SCL signal is mapped to the MFUNC4 terminal and the SDA signal is mapped to the MFUNC1 terminal. The PCI1211 drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for standard mode I2C. Figure 8 illustrates an example application implementing the two-wire serial bus. VCC VCCD0 PCI1211 VCCD1 5V Pullup resistors are required on the SCL and SDA signals. MFUNC4 MFUNC1 A weak (43 kW) pullup resistor is implemented on VCCD0 and VCCD1 terminals to enable the serial EEPROM interface. Serial EEPROM Other Serial Device A2 A1 A0 SCL SCL SDA SDA Figure 8. Serial EEPROM Application Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow. serial bus interface protocol The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 8. The PCI1211 supports up to 100 kb/s data transfer rate and is compatible with standard mode I2C using seven-bit addressing. All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signalled when the SDA line transitions to a low state while SCL is in the high state as illustrated in Figure 9. The end of a requested data transfer is indicated by a stop condition, which is signalled by a low-to-high transition of SDA while SCL is in the high state as shown in Figure 9. Data on SDA must remain stable during the high state of the SCL signal as changes on the SDA signal during the high state of SCL is interpreted as control signals, that is, a start or a stop condition. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 serial bus interface protocol (continued) SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data Valid Figure 9. Serial Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited, however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. Figure 10 illustrates the acknowledge protocol. SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 10. Serial Bus Protocol Acknowledge The PCI1211 is a serial bus master; all other devices connected to the serial bus external to the PCI1211 are slave devices. As the bus master, the PCI1211 drives the SCL clock at nearly 100 kHz during bus cycles, and 3-states SCL (zero frequency) during idle states. Typically, the PCI1211 masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset, and may not be generated under software control. Refer to serial bus EEPROM application on page 32 for details on how the PCI1211 automatically loads the subsystem identification and other register defaults through a serial bus EEPROM. Figure 11 illustrates a byte write operation. The PCI1211 issues a start condition and sends the seven-bit slave device address and the command bit zero. A zero in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1211, then an appropriate status bit is set in the serial bus control and status register. The word address byte is then sent by the PCI1211 and another slave acknowledgment is expected. Then the PCI1211 delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 serial bus interface protocol (continued) Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 0 A Data Byte b7 b6 b5 b4 b3 b2 b1 b0 A b7 b6 b5 b4 b3 b2 b1 b0 A P R/W A = Slave acknowledgement S/P = Start/stop condition Figure 11. Serial Bus Protocol – Byte Write Figure 12 illustrates a byte read operation. The read protocol is very similar to the write protocol except the R/W command bit must be set to one to indicate a read-data transfer. In addition, the PCI1211 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCI1211 master. Slave Address S b6 b5 b4 b3 b2 b1 b0 1 A Word Address Data Byte b7 b6 b5 b4 b3 b2 b1 b0 A b7 b6 b5 b4 b3 b2 b1 b0 M P R/W M = Master acknowledgement A = Slave acknowledgement S/P = Start/stop condition Figure 12. Serial Bus Protocol – Byte Read serial bus EEPROM application When the PCI bus is reset, and the serial bus interface is detected, the PCI1211 attempts to read the subsystem identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be loaded with defaults through the EEPROM are provided in Table 10. Table 10. Registers and Bits Loadable Through Serial EEPROM PCI OFFSET OFFSET REFERENCE 40h 01h Subsystem identification 31–0 80h 02h System control register 31–30, 27, 26, 24, 15–14, 6–3, 1 8Ch 03h Multifunction routing register 27–0 90h 04h Retry status, Card control, device control, diagnostic 31, 28–24, 22, 19–16, 15, 7–6 REGISTER BITS LOADED FROM EEPROM Figure 13 details the EEPROM data format. This format must be followed for the PCI1211 to properly load initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets the ROM_ERR bit in the serial bus control and status register. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 serial bus EEPROM application (continued) Slave Address = 1010 000 Reference(0) Word Address 00h Byte 3 (0) Word Address 01h Reference(n) Byte 2 (0) Word Address 02h Byte 3 (n) Word Address 8 × (n–1) + 1 Byte 1 (0) Word Address 03h Byte 2 (n) Word Address 8 × (n–1) + 2 Byte 0 (0) Word Address 04h Word Address 8 × (n–1) Byte 1 (n) Word Address 8 × (n–1) + 3 RSVD Byte 0 (n) Word Address 8 × (n–1) + 4 RSVD RSVD RSVD RSVD Reference(1) Word Address 08h RSVD Word Address 8 × (n) EOL Figure 13. EEPROM Data Format The byte at the EEPROM word address 00h must either contain a valid PCI offset, as listed in Table 10, or an end-of-list (EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load from the EEPROM. Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered when programming the EEPROM. The serial EEPROM is addressed at slave address 1010000b by the PCI1211. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 8) assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 14. The address auto-increments after every byte transfer according to the doubleword read protocol. The word addresses align with the data format illustrated in Figure 13. The PCI1211 continues to load data from the serial EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain eight-byte data structures. The eight-byte data structure is important to provide correct addressing per the doubleword read format shown in Figure 14. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is 01h, 02h, 03h, 04h. If the offsets are not sequential, then the registers may be loaded incorrectly. Slave Address S 1 0 1 0 0 Word Address 0 0 Start 0 A Slave Address b7 b6 b5 b4 b3 b2 b1 b0 R/W Data Byte 3 M A = Slave acknowledgement A S 1 0 1 0 0 M Data Byte 1 M M = Master acknowledgement Data Byte 0 0 1 A R/W Restart Data Byte 2 0 M P S/P = Start/stop condition Figure 14. EEPROM Interface Doubleword Data Collection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 accessing serial bus devices through software The PCI1211 provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 11 illustrates the registers used to program a serial bus device through software. Table 11. PCI1211 Registers Used to Program Serial Bus Devices PCI OFFSET REGISTER NAME DESCRIPTION B0H Serial bus data Contains the data byte to send on write commands or the received data byte on read commands. B1H Serial bus index The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol. B2H Serial bus slave address Writes to this register initiate a serial bus transaction. The slave device address and the R/W command selector are programmed through this register. B3H Serial bus control and status Read data valid, general busy, and general error status are communicated through this register. In addition, the protocol select bit is programmed through this register. programmable interrupt subsystem Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI1211. The PCI1211 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1211 is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. The PCI1211 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1211, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts. The method by which any type of PCI1211 interrupt is communicated to the host interrupt controller varies from system to system. The PCI1211 offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All interrupt signalling is provided through the seven multifunction terminals, MFUNC0–MFUNC6. PC Card functional and card status change interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCI1211 and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals. Table 12 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are: D D D 34 16-bit memory card 16-bit I/O card CardBus cards POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PC Card functional and card status change interrupts (continued) Table 12. Interrupt Mask and Flag Registers CARD TYPE EVENT MASK FLAG Battery conditions (BVD1, BVD2) ExCA offset 05h/805h bits 1 and 0 ExCA offset 04h/804h bits 1 and 0 Wait states (READY) ExCA offset 05h/805h bit 2 ExCA offset 04h/804h bit 2 Change in card status (STSCHG) ExCA offset 05h/805h bit 0 ExCA offset 04h/804h bit 0 Interrupt request (IREQ) Always enabled PCI configuration offset 91h bit 0 Power cycle complete ExCA offset 05h/805h bit 3 ExCA offset 04h/804h bit 3 Change in card status (CSTSCHG) Socket mask bit 0 Socket event bit 0 Interrupt request (CINT) Always enabled PCI configuration offset 91h bit 0 Power cycle complete Socket mask bit 3 Socket event bit 3 Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1 16-bit memory 16 bit I/O 16-bit All 16-bit PC Cards CardBus Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type. Table 13 describes the PC Card interrupt events. Table 13. PC Card Interrupt Events and Description CARD TYPE 16-bit memory 16-bit I/O CardBus All PC Cards EVENT TYPE SIGNAL DESCRIPTION BVD1(STSCHG)//CSTSCHG A transition on BVD1 indicates a change in the PC Card battery conditions. BVD2(SPKR)//CAUDIO A transition on BVD2 indicates a change in the PC Card battery conditions. Batteryy conditions (BVD1, BVD2) CSC Wait states (READY) CSC READY(IREQ)//CINT A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data. Change in card status (STSCHG) CSC BVD1(STSCHG)//CSTSCHG The assertion of STSCHG indicates a status change on the PC Card. Interrupt request (IREQ) Functional READY(IREQ)//CINT The assertion of IREQ indicates an interrupt request from the PC Card. Change in card status (CSTSCHG) CSC BVD1(STSCHG)//CSTSCHG The assertion of CSTSCHG indicates a status change on the PC Card. Interrupt request (CINT) Functional READY(IREQ)//CINT The assertion of CINT indicates an interrupt request from the PC Card. Card insertion or removal CSC CD1//CCD1, CD2//CCD2 A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit//CardBus PC Card. Power cycle complete CSC N/A An interrupt is generated when a PC Card power-up cycle has completed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PC Card functional and card status change interrupts (continued) The naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well as CardBus. For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The CardBus signal name follows after a forward double slash (//). The PC Card standard describes the power-up sequence that must be followed by the PCI1211 when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI1211 interrupt scheme can be used to notify the host system (see Table 13), denoted by the power cycle complete event. This interrupt source is considered a PCI1211 internal event because it does not depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket. interrupt masks and flags Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 13 by setting the appropriate bits in the PCI1211. By individually masking the interrupt sources listed, software can control those events that cause a PCI1211 interrupt. Host software has some control over the system interrupt the PCI1211 asserts by programming the appropriate routing registers. The PCI1211 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. A discussion of interrupt routing is somewhat specific to the interrupt signaling method used, and is discussed in more detail in the following sections. When an interrupt is signaled by the PCI1211, the interrupt service routine must determine which of the events in Table 12 caused the interrupt. Internal registers in the PCI1211 provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken. Table 12 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts. Notice that there is not a mask bit to stop the PCI1211 from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization. There are various methods of clearing the interrupt flag bits listed in Table 12. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/81Eh), and defaults to the flag cleared on read method. The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning. using parallel IRQ interrupts The seven multifunction terminals, MFUNC6–MFUNC0, implemented in the PCI1211 may be routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA type IRQ interrupt signaling, software must program the device control register, located at PCI offset 92h, to select the parallel IRQ signaling scheme. Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals. A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 using parallel IRQ interrupts (continued) As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11, and IRQ15. The multifunction control register must be programmed to a value of 0x0FBA5432. This value routes the MFUNC0 terminal to INTA signaling, and routes the remaining terminals as illustrated in Figure 15. Not shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel PCI interrupts to the host. PCI1211 MFUNC1 IRQ3 PIC MFUNC2 IRQ4 MFUNC3 IRQ5 MFUNC4 IRQ10 MFUNC5 IRQ11 MFUNC6 IRQ15 Figure 15. Example of IRQ Implementation Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration of a system implementing the PCI1211. Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals. The parallel ISA type IRQ signaling from the MFUNC6–MFUNC0 terminals is compatible with those input directly into the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. There may be design constraints that demand more MFUNC6–MFUNC0 IRQ terminals than the PCI1211 makes available. A system designer may choose to implement an IRQSER deserializer companion chip, such as the Texas Instruments PCI950. To use a deserializer, the MFUNC3 terminal must be configured as IRQSER and connected to the deserializer, which outputs all 15 ISA IRQ’s and four PCI interrupts as decoded from the IRQSER stream. using parallel PCI interrupts Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode, parallel ISA IRQ signaling mode, and when only IRQs are serialized with the IRQSER protocol. The socket function interrupts are routed to INTA (MFUNC0). using serialized IRQSER interrupts The serialized interrupt protocol implemented in the PCI1211 uses a single terminal to communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on the IRQSER protocol refer to the document Serialized IRQ Support for PCI Systems. SMI support in the PCI1211 The PCI1211 provides a mechanism of interrupting the system when power changes have been made to the PC Card socket interface. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme. SMI interrupts are generated by the PCI1211, when enabled, after a write cycle to either the socket control register of the CardBus register set or the power control register of the ExCA register set causes a power cycle change sequence sent on the power switch interface. The SMI control is programmed through three bits in the system control register. These bits are SMIROUTE, SMISTATUS, and SMIENB. The SMI control bits function as described in Table 14. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 SMI support in the PCI1211 (continued) Table 14. SMI Control BIT NAME FUNCTION SMIROUTE SMI route. This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT SMI status. This bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1. SMIENB SMI interrupt mode enable. When set, SMI interrupt generation is enabled. If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC. The CSC interrupt can be either level or edge mode depending upon the CSCMODE bit in the ExCA global control register. If IRQ2 is selected by SMIROUTE, the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC1, MFUNC3, or MFUNC6 through the multifunction routing register. power management overview In addition to the low-power CMOS technology process used for the PCI1211, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section. CLKRUN protocol The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1211. CLKRUN signalling is provided through the MFUNC6 terminal. Since some chipsets do not implement CLKRUN, this is not always available to the system designer, alternate power savings features are provided. For details on the CLKRUN protocol refer to the PCI Mobile Design Guide. The PCI1211 does not permit the central resource to stop the PCI clock under any of the following conditions: D D D D D D The KEEPCLK bit in the system control register is set. The PC Card-16 resource manager is busy. The PCI1211 CardBus master state machine is busy. A cycle may be in progress on CardBus. The PCI1211 master is busy. There may be posted data from CardBus to PCI in the PCI1211. There are pending interrupts. The CardBus CCLK has not been stopped by the PCI1211 PCI CCLKRUN manager. The PCI1211 restarts the PCI clock using the clockk run protocol under any of the following conditions: D D D D D A PC Card-16 IREQ or a CardBus CINT has been asserted by either card. A CardBus wakeup (CSTSCHG) or PC Card-16 STSCHG/RI event occurs. A CardBus card attempts to start the CCLK using CCLKRUN. A CardBus card arbitrates for the CardBus bus using CREQ. A 16-bit DMA PC Card asserts DREQ. CardBus PC Card Power Management The PCI1211 implements its own card power management engine that can be used to turn off the CCLK to the socket when there is no activity to the CardBus PC Card. The PCI CCLKRUN protocol is followed on the CardBus interface to control this clock management. 16-Bit PC Card Power Management The COE and PWRDOWN bits in the ExCA registers are provided for 16-bit PC Card power management. The COE bit three states the card interface to save power. The power savings when using this feature are minimal. The COE bit will reset the PC Card when used, and the PWRDOWN bit will not. Furthermore, the PWRDOWN bit is an automatic COE, that is, the PWRDOWN performs the COE function when there is no card activity. NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDOWN modes. 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 suspend mode The SUSPEND signal is provided for backward compatibility, and gates the PCI reset (RST) signal from the PCI1211. However, additional functionality has been defined for SUSPEND to provide additional power-management options. SUSPEND provides a mechanism to gate the PCLK from the PCI1211, as well as gate RST. This can potentially save power while in an idle state; however, it requires substantial design effort to implement. Some issues to consider are: D D D What if a card is present in the socket? What if the card in the socket is powered? How to pass CSC (insertion/removal) events. Even without the PCI clock to the PCI1211 core, there are asynchronous-type functions (such as RI_OUT) that can pass CSC events, wake-up events, etc., back to the system. Figure 16 is a functional implementation diagram for SUSPEND. RST RSTIN SUSPEND PCI1211 Core SUSPENDIN GNT PCLKIN PCLK EXTERNAL SIGNALS INTERNAL SIGNALS Figure 16. SUSPEND Functional Implementation Figure 17 is a signal diagram of the suspend function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 suspend mode (continued) RST GNT SUSPEND PCLK External Terminals Internal Signals RSTIN SUSPENDIN PCLKIN Figure 17. Signal Diagram of Suspend Function ring indicate The RI_OUT output is an important feature in power management and is basically used so that a system can go into a suspended mode and wake up on modem rings and other card events. RI_OUT on the PCI1211 can be asserted under any of the following conditions: D D D A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call. A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up. A CSC event occurs, such as insertion/removal of cards, battery voltage levels. CSTSCHG from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two RI_OUT events are enabled separately. Figure 15 shows various enable bits for the PCI1211 RI_OUT function; however, it does not show the masking of CSC events. See interrupt masks and flags, on page 36, for a detailed description of CSC interrupt masks and flags. 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ring indicate (continued) RI_OUT Function CSTSMASK RIENB PC Card Socket Card I/F RINGEN RI_OUT CDRESUME Figure 18. RI_OUT Functional Diagram RI from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the interrupt and general control register. This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket. The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers. PCI power management (PCIPM) The PCI power-management (PCIPM) specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software-visible power-management states that result in varying levels of power savings. The four power-management states of PCI functions are: D D D D0 – Fully-on state D1 and D2 – Intermediate states D3 – Off state Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power state of the originating bridge device. For the operating system (OS) to power manage the device power states on the PCI bus, the PCI function should support four power-management operations. These operations are: D D D D Capabilities reporting Power status reporting Setting the power state System wake up. The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1 in the capabilities list (CAPLIST) bit in the status register (bit 4) and providing access to a capabilities list. The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1211, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, the next item pointer should be set to 0. The registers following the next item pointer are specific to the function’s capability. The PCIPM capability implements the register block outlined in Table 15. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PCI power management (PCIPM) (continued) Table 15. Power-Management Registers REGISTER NAME Power-management capabilities Data OFFSET Next item pointer PMCSR bridge support extensions Capability ID 0h Power-management control status (CSR) 4h The power management capabilities register is a static read-only register that provides information on the capabilities of the function related to power management. The PMCSR register enables control of power-management states and enables/monitors power-management events. The data register is an optional register that can provide dynamic data. For more information on PCI power management refer to the PCI Bus Power Management Interface Specification, Revision 1.0. ACPI Support The Advanced Configuration and Power Management (ACPI) Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCI1211 offers a generic interface that is compliant with ACPI design rules. Two doublewords of general purpose ACPI programming bits reside in the PCI1211 PCI configuration space at offset A8h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in GPE_STS and GPE_EN registers. The status and enable bits are implemented as defined by ACPI, and illustrated in Figure 19. Status Bit Event Input Event Output Enable Bit Figure 19. Block Diagram of a Status/Enable Cell The status and enable bits are used to generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events. For more information on ACPI refer to the Advanced Configuration and Power Interface Specification at: http://www.teleport.com/~acpi/. 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PC Card controller programming model This section describes the PCI1211 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI1211 function. PCI configuration registers The configuration header is compliant with the PCI specification as a CardBus bridge header, and is PC98/99 compliant as well. Table 16 shows the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers. Table 16. PCI Configuration Registers REGISTER NAME OFFSET Device ID Vendor ID 00h Status Command 04h Class code BIST Header type Latency timer Revision ID 08h Cache line size 0Ch CardBus socket/ExCA base address Secondary status CardBus latency timer Subordinate bus number 10h Reserved Capability pointer 14h CardBus bus number PCI bus number 18h CardBus Memory base register 0 1Ch CardBus Memory limit register 0 20h CardBus Memory base register 1 24h CardBus Memory limit register 1 28h CardBus I/O base register 0 2Ch CardBus I/O limit register 0 30h CardBus I/O base register 1 34h CardBus I/O limit register 1 Bridge control Subsystem ID Diagnostic 38h Interrupt pin Interrupt line Subsystem vendor ID 40h PC Card 16-bit I/F legacy-mode base address 44h Reserved 48h–7Ch System control 80h Reserved 84h–88h Multifunction routing 8Ch Device control Card control Retry status 90h Socket DMA register 0 94h Socket DMA register 1 98h Reserved Power-management capabilities PM data 3Ch 9Ch Next-item pointer PMCSR bridge support extensions Capability ID Power-management control/status A0h A4h General-purpose event enable General-purpose event status A8h General-purpose output General-purpose input ACh Serial bus control/status Serial bus slave address Serial bus index Reserved POST OFFICE BOX 655303 Serial bus data B0h B4h–FCh • DALLAS, TEXAS 75265 43 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 vendor ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 1 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 1 0 0 1 1 0 0 Vendor ID Register: Type: Offset: Default: Description: Vendor ID Read-only 00h 104Ch This register contains a value allocated by the PCI SIG (special interest group) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch. device ID register Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 Register: Type: Offset: Default: Description: 44 Device ID Read-only 02h AC1Eh This register contains a value assigned to the PCI1211 by TI. The device identification for the PCI1211 is AC1E. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 command register Bit 15 14 13 12 11 10 9 8 Type R R R R R R R R/W Default 0 0 0 0 0 0 0 0 Name 7 6 5 4 3 2 1 0 R R/W R R R R/W R/W R/W 0 0 0 0 0 0 0 0 Command Register: Type: Offset: Default: Description: Command Read-only, Read/Write (see individual bit descriptions) 04h 0000h This register provides control over the PCI1211 interface to the PCI bus. All bit functions adhere to the definitions in PCI Local Bus Specification, Revision 2.2. See Table 17 for the complete description of the register contents. Table 17. Command Register BIT SIGNAL TYPE 15–10 RSVD R Reserved. Bits 15–10 return 0s when read. Writes have no effect. FUNCTION 9 FBB_EN R Fast back-to-back enable. The PCI1211 does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. 8 SERR_EN R/W System Error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both bit 8 and bit 6 must be set for the PCI1211 to report address parity errors. 0 = Disable SERR output driver (default) 1 = Enable SERR output driver 7 STEP_EN R Address/data stepping control. The PCI1211 does not support address/data stepping, and bit 7 is hardwired to 0. Writes to this bit have no effect. 6 PERR_EN R/W Parity error response enable. Bit 6 controls the PCI1211’s response to parity errors through PERR. Data parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting SERR. 0 = PCI1211 ignores detected parity error (default) 1 = PCI1211 responds to detected parity errors 5 VGA_EN R VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette registers. The PCI1211 does not support VGA palette snooping; therefore, this bit is hardwired to 0. Bit 5 returns 0 when read. Writes to this bit have no effect. 4 MWI_EN R Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and Invalidate commands. The PCI1211 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. Bit 4 returns 0 when read. Writes to this bit have no effect. 3 SPECIAL R Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1211 does not respond to special cycle operations; therefore, this bit is hardwired to 0. Bit 3 returns 0 when read. Writes to this bit have no effect. 2 MAST_EN R/W Bus master control. Bit 2 controls whether or not the PCI1211 can act as a PCI bus initiator (master). The PCI1211 can take control of the PCI bus only when this bit is set. 0 = Disables the PCI1211’s ability to generate PCI bus accesses (default) 1 = Enables the PCI1211’s ability to generate PCI bus accesses 1 MEM_EN R/W Memory space enable. Bit 1 controls whether or not the PCI1211 can claim cycles in PCI memory space. 0 = Disables the PCI1211’s response to memory space accesses (default) 1 = Enables the PCI1211’s response to memory space accesses 0 IO_EN R/W I/O space control. Bit 0 controls whether or not the PCI1211 can claim cycles in PCI I/O space. 0 = Disables the PCI1211 from responding to I/O space accesses (default) 1 = Enables the PCI1211 to respond to I/O space accesses POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 status register Bit 15 14 13 12 11 10 9 8 R/WC R/WC R/WC R/WC R/WC R R 0 0 0 0 0 0 1 Name Type Default 7 6 5 4 3 2 1 0 R/WC R R R R R R R R 0 0 0 0 1 0 0 0 0 Status Register: Type: Offset: Default: Description: Status Read-only, Read/Write to Clear (see individual bit descriptions) 06h 0210h This register provides device information to the host system. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Local Bus Specification, Revision 2.2. PCI bus status is shown through each function. See Table 18 for the complete description of the register contents. Table 18. Status Register 46 BIT SIGNAL TYPE 15 PAR_ERR R/WC Detected parity error. Bit 15 is set when a parity error is detected (either address or data). FUNCTION 14 SYS_ERR R/WC Signaled system error. Bit 14 is set when SERR is enabled and the PCI1211 signals a system error to the host. 13 MABORT R/WC Received master abort. Bit 13 is set when a cycle initiated by the PCI1211 on the PCI bus has been terminated by a master abort. 12 TABT_REC R/WC Received target abort. Bit 12 is set when a cycle initiated by the PCI1211 on the PCI bus was terminated by a target abort. 11 TABT_SIG R/WC Signaled target abort. Bit 11 is set by the PCI1211 when it terminates a transaction on the PCI bus with a target abort. 10–9 PCI_SPEED R DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the PCI1211 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses. Data parity error detected. 0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred, and the following conditions were met: a. PERR was asserted by any PCI device including the PCI1211. b. The PCI1211 was the bus master during the data parity error. c. The parity error response bit is set in the command. 8 DATAPAR R/WC 7 FBB_CAP R Fast back-to-back capable. The PCI1211 cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0. 6 UDF R User-definable feature support. The PCI1211 does not support the user-definable features; thus, bit 6 is hardwired to 0. 5 66MHZ R 66-MHz capable. The PCI1211 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4 CAPLIST R Capabilities list. Bit 4 returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function. 3–0 RSVD R Reserved. Bits 3–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 revision ID register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 0 Name Revision ID Register: Type: Offset: Default: Description: Revision ID Read-only 08h 00h This register indicates the silicon revision of the PCI1211. PCI class code register Bit 23 22 21 20 19 18 17 16 15 14 13 Name 12 11 10 9 8 7 6 5 4 3 2 1 0 Class code Base class Sub class Programming interface Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: PCI Class code Read-only 09h 060700h This register recognizes the PCI1211 as a bridge device (06h), and CardBus bridge device (07h) with a 00h programming interface. cache line size register Bit 7 6 5 Name Type Default 4 3 2 1 0 Cache line size R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Cache line size Read/Write 0Ch 00h This register is programmed by host software to indicate the system cache line size. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 latency timer register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 Name Latency timer Type Default Register: Type: Offset: Default: Description: Latency timer Read/Write 0Dh 00h This register specifies the latency timer for the PCI1211 in units of PCI clock cycles. When the PCI1211 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI1211 transaction has terminated, the PCI1211 terminates the transaction when its GNT is deasserted. header type register Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 0 0 0 0 0 0 1 0 Name Header type Register: Type: Offset: Default: Description: Header type Read-only 0Eh 02h This register returns 02h when read, indicating that the PCI1211 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, leaving 80h–FFh is user-definable extension registers. BIST register Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name BIST Register: Type: Offset: Default: Description: 48 BIST Read-only 0Fh 00h Because the PCI1211 does not support a built-in self-test (BIST), this register returns the value of 00h when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 CardBus socket registers/ExCA registers base-address register Bit 31 30 29 28 27 26 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 Name Type Default 24 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 5 4 3 2 1 0 CardBus socket/ExCA registers base address Name Type 25 CardBus socket/ExCA registers base address R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: CardBus socket/ExCA registers base address Read-only, Read/Write 10h 0000 0000h This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4K-byte boundary. Bits 11–0 are read-only, returning 0s when read. When software writes all 1s to this register, the value readback is FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. capability pointer register Bit 7 6 5 Name 4 3 2 1 0 Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0 Register: Type: Offset: Default: Description: Capability pointer Read-only 14h A0h This register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. The socket has its own capability pointer register. This register returns A0h when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 secondary status register Bit 15 14 13 12 11 10 9 R/WC R/WC R/WC R/WC R/WC R R R/WC 0 0 0 0 0 0 1 0 Name Type Default 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Secondary status Register: Type: Offset: Default: Description: Secondary status Read-only, Read/Write to Clear (see individual bit descriptions) 16h 0200h This register is compatible with the PCI-to-PCI bridge secondary status register, and indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (offset 06h), and status bits are cleared by writing a 1. See Table 19 for the complete description of the register contents. Table 19. Secondary Status Register 50 BIT SIGNAL TYPE 15 CBPARITY R/WC Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). FUNCTION 14 CBSERR R/WC Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1211 does not assert CSERR. 13 CBMABORT R/WC Received master abort. Bit 13 is set when a cycle initiated by the PCI1211 on the CardBus bus has been terminated by a master abort. 12 REC_CBTA R/WC Received target abort. Bit 12 is set when a cycle initiated by the PCI1211 on the CardBus bus is terminated by a target abort. 11 SIG_CBTA R/WC Signaled target abort. Bit 11 is set by the PCI1211 when it terminates a transaction on the CardBus bus with a target abort. 10–9 CB_SPEED R CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the PCI1211 asserts CB_SPEED at a medium speed. CardBus data parity error detected. 0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred and the following conditions were met: a. CPERR was asserted on the CardBus interface. b. The PCI1211 was the bus master during the data parity error. c. The parity error response bit is set in the bridge control. 8 CB_DPAR R/WC 7 CBFBB_CAP R Fast back-to-back capable. The PCI1211 cannot accept fast back-to-back transactions; thus, bit 7 is hardwired to 0. 6 CB_UDF R User-definable feature support. The PCI1211 does not support the user-definable features; thus, bit 6 is hardwired to 0. 5 CB66MHZ R 66-MHz capable. The PCI1211 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4–0 RSVD R Reserved. Bits 4–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PCI bus number register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 PCI bus number Register: Type: Offset: Default: Description: PCI bus number Read/Write 18h 00h This register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI1211 is connected. The PCI1211 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. CardBus bus number register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CardBus bus number Register: Type: Offset: Default: Description: CardBus bus number Read/Write 19h 00h This register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI1211 is connected. The PCI1211 uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. subordinate bus number register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 Subordinate bus number Register: Type: Offset: Default: Description: Subordinate bus number Read/Write 1Ah 00h This register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The PCI1211 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 CardBus latency timer register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CardBus latency timer Type Default Register: Type: Offset: Default: Description: CardBus latency timer Read/Write 1Bh 00h This register is programmed by the host system to specify the latency timer for the PCI1211 CardBus interface in units of CCLK cycles. When the PCI1211 is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI1211 transaction has terminated, then the PCI1211 terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed. memory base registers 0, 1 Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Memory base registers 0, 1 R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: 52 23 Memory base registers 0, 1 Name Type 24 Memory base registers 0, 1 Read-only, Read/Write 1Ch, 24h 0000 0000h These registers indicate the lower address of a PCI memory address range and are used by the PCI1211 to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 11–0 always return 0s when read. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1211 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of memory to CardBus). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 memory limit registers 0, 1 Bit 31 30 29 28 27 26 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name Type Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Memory limit registers 0, 1 Name Type 24 Memory limit registers 0, 1 R/W R/W R/W R/W R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Memory limit registers 0, 1 Read-only, Read/Write 20h, 28h 0000 0000h These registers indicate the upper address of a PCI memory address range and are used by the PCI1211 to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 11–0 always return 0s when read. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1211 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of memory to CardBus). I/O base registers 0, 1 Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 I/O base registers 0, 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name Type Default I/O base registers 0, 1 Register: Type: Offset: Default: Description: I/O base registers 0, 1 Read-only, Read/Write 2Ch, 34h 0000 0000h These registers indicate the lower address of a PCI I/O address range and are used by the PCI1211 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64K-byte page, and the upper 16 bits (31–16) are a page register which locates this 64K-byte page in 32-bit PCI I/O address space. Bits 31–2 are read/write. Bits 1–0 always return 0s when read, forcing I/O windows to be aligned on a natural doubleword boundary. NOTE: Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 I/O limit registers 0, 1 Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Default 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 I/O limit registers 0, 1 Name Type 24 I/O limit registers 0, 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: I/O limit registers 0, 1 Read-only, Read/Write 30h, 38h 0000 0000h These registers indicate the upper address of a PCI I/O address range and are used by the PCI1211 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64K-byte page, and the upper 16 bits are a page register which locates this 64K-byte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64K-byte page (indicated by bits 31–16 of the appropriate I/O base) on doubleword boundaries. Bits 31–16 always return 0s when read. The page is set in the I/O base register. Bits 1–0 always return 0s when read, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to read-only bits have no effect. The PCI1211 assumes that the lower 2 bits of the limit address are 1s. NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction. 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 interrupt line register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 1 1 1 R/W R/W R/W R/W 1 1 1 1 1 Name Type Default Interrupt line Register: Type: Offset: Default: Description: Interrupt line Read/Write 3Ch FFh This register is used to communicate interrupt line routing information. interrupt pin register Bit 7 6 5 4 3 2 1 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Name Interrupt pin Register: Type: Offset: Default: Description: Interrupt pin Read-only 3Dh 01h The value read from the interrupt pin register is function dependent and reflects the interrupt signalling mode selected through the device control register (92h). The PCI1211 defaults to serialized PCI and ISA interrupt mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 bridge control register Bit 15 14 13 12 11 10 9 Type R R R R R R/W R/W R/W Default 0 0 0 0 0 0 1 1 Name 8 7 6 5 4 3 2 1 0 R/W R/W R/W R R/W R/W R/W R 0 1 0 0 0 0 0 0 Bridge control Register: Type: Offset: Default: Description: Bridge control Read-only, Read/Write (see individual bit descriptions) 3Eh 0340h This register provides control over various PCI1211 bridging functions. See Table 20 for a complete description of the register contents. Table 20. Bridge Control Register BIT SIGNAL TYPE 15–11 RSVD R 10 POSTEN R/W Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles. Note that bursted write data can be posted, but various write transactions may not. 9 PREFETCH1 R/W Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. Bit 9 is encoded as: 0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default). 8 PREFETCH0 R/W Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is encoded as: 0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default). 7 INTR R/W PCI interrupt – IREQ routing enable. Bit 7 is used to select whether PC Card functional interrupts are routed to PCI interrupts or the IRQ specified in the ExCA registers. 0 = Functional interrupts routed to PCI interrupts (default) 1 = Functional interrupts routed by ExCAs R/W CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted by passing a RST assertion to CardBus. 0 = CRST deasserted 1 = CRST asserted (default) Master abort mode. Bit 5 controls how the PCI1211 responds to a master abort when the PCI1211 is an initiator on the CardBus interface. This bit is common between each socket. 0 = Master aborts not reported (default) 1 = Signal target abort on PCI and SERR (if enabled) 6 56 FUNCTION Reserved. Bits 15–11 return 0s when read. CRST 5 MABTMODE R/W 4 RSVD R 3 VGAEN R/W VGA enable. Bit 3 affects how the PCI1211 responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded. 2 ISAEN R/W ISA mode enable. Bit 2 affects how the PCI1211 passes I/O cycles within the 64K-byte ISA range. This bit is not common between sockets. When this bit is set, the PCI1211 does not forward the last 768 bytes of each 1K I/O range to CardBus. Reserved. Bit 4 returns 0 when read. 1 CSERREN R/W CSERR enable. Bit 1 controls the response of the PCI1211 to CSERR signals on the CardBus bus. This bit is common between the two sockets. 0 = CSERR is not forwarded to PCI SERR. 1 = CSERR is forwarded to PCI SERR. 0 CPERREN R CardBus parity error response enable. Bit 0 controls the response of the PCI1211 to CardBus parity errors. This bit is common between the two sockets. 0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 subsystem vendor ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Subsystem vendor ID Register: Type: Offset: Default: Description: Subsystem vendor ID Read-only (read/write when bit 5 in the system control register is 0) 40h 0000h This register is used for system and option-card identification purposes, and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. subsystem ID register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 0 0 0 0 0 Subsystem ID Register: Type: Offset: Default: Description: Subsystem ID Read-only (read/write when bit 5 in the system control register is 0) 42h 0000h This register is used for system and option-card identification purposes, and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PC Card 16-bit I/F legacy-mode base address register Bit 31 30 29 28 27 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 Name Type Default 25 24 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 5 4 3 2 1 0 PC Card 16-bit I/F legacy-mode base address Name Type 26 PC Card 16-bit I/F legacy-mode base address R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: Type: Offset: Default: Description: PC Card 16-bit I/F legacy-mode base address Read-only, Read/Write (see individual bit descriptions) 44h 0000 0001h The PCI1211 supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. Refer to ExCA compatibility registers on page 80 for register offsets. system control register Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 System control R/W R/W R R R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 Name Type Default System control Register: Type: Offset: Default: Description: 58 System control Read-only, Read/Write (see individual bit descriptions) 80h 0044 9060h System-level initializations are performed through programming this doubleword register. See Table 21 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 21. System Control Register BIT SIGNAL TYPE FUNCTION Serialized PCI interrupt routing step. Bits 31–30 are used to configure the serialized PCI interrupt stream signaling, and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. Bits 31–30 are encoded as follows: 00 = INTA is signaled in the INTA IRQSER slot. 01 = INTA is signaled in the INTB IRQSER slot. 10 = INTA is signaled in the INTC IRQSER slot. 11 = INTA is signaled in the INTD IRQSER slot. 31–30 SER_STEP R/W 29–27 RSVD R 26 SMIROUTE R/W SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket. 0 = PC Card power change interrupts routed to IRQ2 (default) 1 = A CSC interrupt is generated on PC Card power changes. Reserved. These bits return 0s when read. 25 SMISTATUS R/W SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and the SMIENB bit is set. Writing a 1 to bit 25 clears the status. 0= SMI interrupt signaled (default) 1 = SMI interrupt not signaled 24 SMIENB R/W SMI interrupt mode enable. When bit 24 is set, the SMI interrupt signaling is enabled and generates an interrupt when a write to the socket power control occurs. This bit defaults to 0 (disabled). 23 RSVD R 22 CBRSVD R/W 21 VCCPROT R/W 20 REDUCEZV R/W 19 18–16 15 CDREQEN CDMACHAN MRBURSTDN Reserved. This bit returns 0 when read. CardBus reserved terminals signaling. When bit 22 is set, the RSVD CardBus terminals are driven low when a CardBus card is inserted. When this bit is low (as default), these signals are 3-stated. 0 = 3-state CardBus RSVD 1 = Drive Cardbus RSVD low (default) VCC protection enable. 0 = VCC protection enabled for 16-bit cards (default) 1 = VCC protection disabled for 16-bit cards Reduced Zoom Video Enable.When this bit is enabled, A25–A22 of the card interface for PC Card 16 cards is placed in the high impedance state. This bit should not be set for normal ZV operation. This bit is encoded as: 0 = Reduced zoom video disabled (default) 1 = Reduced zoom video enabled R/W PC/PCI DMA card enable. When bit 19 is set, the PCI1211 allows 16-bit PC Cards to request PC/PCI DMA using the DREQ signaling. DREQ is selected through the socket DMA register 0. 0 = Ignore DREQ signaling from PC Cards (default) 1 = Signal DMA request on DREQ R/W PC/PCI DMA channel assignment. Bits 18–16 are encoded as: 0–3 = 8-bit DMA channels 4 = PCI master; not used (default). 5–7 = 16-bit DMA channels R/W Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst downstream. 0 = Downstream memory read burst is disabled. 1 = Downstream memory read burst is enabled (default). 14 MRBURSTUP R/W Memory read burst enable upstream. When bit 14 is set, the PCI1211 allows memory read transactions to burst upstream. 0 = Upstream memory read burst is disabled (default). 1 = Upstream memory read burst is enabled. 13 SOCACTIVE R Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card, and is cleared upon read of this status bit. This bit is socket dependent. 0 = No socket activity (default) 1 = Socket activity 12 RSVD R Reserved. Bit 12 returns 1 when read. This is the power rail bit. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 21. System Control Register (Continued) BIT SIGNAL TYPE FUNCTION 11 PWRSTREAM R Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. This bit is cleared when the power stream is complete. 10 DELAYUP R Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay has expired. 9 DELAYDOWN R Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-down delay has expired. 8 INTERROGATE R Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when interrogation completes. 0 = Interrogation not in progress (default) 1 = Interrogation in progress 7 RSVD R Reserved. Bit 7 returns 0 when read. 6 PWRSAVINGS R/W Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock, the applicable CB state machine will not be clocked. 5 SUBSYSRW R/W Subsystem ID (SSID), subsystem vendor ID (SSVID), ExCA ID, and revision register read/write enable. 0 = SSID, SSVID, ExCA ID, and revision register are read/write. 1 = SSID, SSVID, ExCA ID, and revision register are read-only (default). 4 CB_DPAR R/W CardBus data parity SERR signaling enable 0 = CardBus data parity not signaled on PCI SERR 1 = CardBus data parity signaled on PCI SERR 3 CDMA_EN R/W PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set if MFUNC routing is configured for centralized DMA. 0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled 2 RSVD R 1 KEEPCLK R/W Keep clock. This bit works with PCI and CB CLKRUN protocols 0 = Allows normal functioning of both CLKRUN protocols. (default) 1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols. R/W RI_OUT/PME multiplex enable. 0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both are enabled at the same time, RI_OUT has precedence over PME. 1 = Only PME is routed to the RI_OUT/PME terminal. 0 60 RIMUX Reserved. Bit 2 returns 0 when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 multifunction routing register Bit 31 30 29 28 27 26 25 Type R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name Default 23 22 21 20 19 18 17 16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Multifunction routing Name Type 24 Multifunction routing R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Multifunction routing Read-only, Read/Write (see individual bit descriptions) 8Ch 0000 0000h This register is used to configure the MFUNC0–MFUNC6 terminals. These terminals may be configured for various functions. All multifunction terminals default to the general-purpose input configuration. Pullup resistors are required for terminals configured as outputs. This register is intended to be programmed once at power-on initialization. The default value for this register may also be loaded through a serial bus EEPROM. See Table 22 for a complete description of the register contents. Table 22. Multifunction Routing Register BIT SIGNAL TYPE 31–28 RSVD R 27–24 MFUNC6 R/W FUNCTION Reserved. These bits return 0s when read. Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal as follows: 0000 = RSVD, Reserved high impedance input (default) 0001 = CLKRUN, PCI clock control signal 0010 = IRQ2, Parallel ISA type 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = IRQ6, Parallel ISA type 0111 = IRQ7, Parallel ISA type 1000 = IRQ8, Parallel ISA type 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = IRQ12, Parallel ISA type 1101 = IRQ13, Parallel ISA type 1110 = IRQ14, Parallel ISA type 1111 = IRQ15, Parallel ISA type POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 22. Multifunction Routing Register (Continued) BIT 23–20 SIGNAL MFUNC5 TYPE FUNCTION R/W Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal as follows: 0000 = GPI4, General-purpose input (default) 0001 = GPO4, General-purpose output 0010 = PCGNT, PC/PCI (centralized) DMA grant 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0, Zoom video select output 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = LED_SKT, Socket activity LED 1101 = LED_SKT, Socket activity LED 1110 = GPE, General-Purpose event signal 1111 = IRQ15, Parallel ISA type Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal as follows: NOTE: When the serial bus mode is implemented by pulling up the VPPD0 and VPPD1 terminals, the MFUNC4 terminal provides the SCL signaling. 19–16 15–12 62 MFUNC4 MFUNC3 R/W R/W 0000 = GPI3, General-purpose input (default) 0001 = GPO3, General-purpose output 0010 = LOCK, PCI atomic transfer support mechanism 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0, Zoom video select output 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = RI_OUT, Ring-indicate output 1101 = LED_SKT, Socket activity LED 1110 = GPE, General-purpose event signal 1111 = IRQ15, Parallel ISA type Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal as follows: 0000 = RSVD, Reserved high impedance input (default) 0001 = IRQSER, Serial interrupt stream, IRQ and optional PCI 0010 = IRQ2, Parallel ISA type 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = IRQ6, Parallel ISA type 0111 = IRQ7, Parallel ISA type 1000 = IRQ8, Parallel ISA type 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = IRQ12, Parallel ISA type 1101 = IRQ13, Parallel ISA type 1110 = IRQ14, Parallel ISA type 1111 = IRQ15, Parallel ISA type POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 22. Multifunction Routing Register (Continued) BIT 11–8 SIGNAL MFUNC2 TYPE FUNCTION R/W Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal as follows: 0000 = GPI2, General-purpose input (default) 0001 = GPO2, General-purpose output 0010 = PCREQ, PC/PCI (centralized) DMA request 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0, Zoom video select output 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = RI_OUT, Ring-indicate output 1101 = IRQ13, Parallel ISA type 1110 = GPE, General-purpose event signal 1111 = IRQ7, Parallel ISA type Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows: NOTE: When the serial bus mode is implemented by pulling up the VPPD0 and VPPD1 terminals, the MFUNC1 terminal provides the SDA signaling. 7–4 3–0 MFUNC1 MFUNC0 R/W R/W 0000 = GPI1, General-purpose input (default) 0001 = GPO1, General-purpose output 0010 = IRQ2, Parallel ISA type 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0, Zoom video select output 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = LED_SKT, Socket activity LED 1101 = IRQ13, Parallel ISA type 1110 = GPE, General-purpose event signal 1111 = IRQ15, Parallel ISA type Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal as follows: 0000 = GPI0, General-purpose input (default) 0001 = GPO0, General-purpose output 0010 = INTA, PCI interrupt signal, INTA 0011 = IRQ3, Parallel ISA type 0100 = IRQ4, Parallel ISA type 0101 = IRQ5, Parallel ISA type 0110 = ZVSTAT, Zoom video status output 0111 = ZVSEL0, Zoom video select output 1000 = CAUDPWM, PWM output of CAUDIO CardBus terminal 1001 = IRQ9, Parallel ISA type 1010 = IRQ10, Parallel ISA type 1011 = IRQ11, Parallel ISA type 1100 = LED_SKT, Socket activity LED 1101 = IRQ13, Parallel ISA type 1110 = GPE, General-purpose event signal 1111 = IRQ15, Parallel ISA type POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 retry status register Bit 7 6 5 4 3 2 1 0 R/W R/W R R 1 1 0 R/WC R R/WC R 0 0 0 0 0 Name Type Default Retry status Register: Type: Offset: Default: Description: Retry status Read-only, Read/Write, Read/Write to Clear (see individual bit descriptions) 90h C0h This register enables the retry timeout counters and displays the retry expiration status. The flags are set when the PCI1211 retries a PCI or CardBus master request, and the master does not return within 215 PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI command, PCI status, and bridge control registers by the PCI SIG. See Table 23 for a complete description of the register contents. Table 23. Retry Status Register BIT 64 SIGNAL TYPE FUNCTION 7 PCIRETRY R/W PCI retry timeout counter enable. Bit 7 is encoded: 0 = PCI retry counter disabled 1 = PCI retry counter enabled (default) 6 CBRETRY R/W CardBus retry timeout counter enable. Bit 6 is encoded: 0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default) 5–4 RSVD R 3 TEXP_CB R/WC 2 RSVD R 1 TEXP_PCI R/WC 0 RSVD R Reserved. These bits return 0s when read. CardBus target retry expired. Write a 1 to clear bit 3. 0 = Inactive (default) 1 = Retry has expired. Reserved. Bit 2 returns 0 when read. PCI target retry expired. Write a 1 to clear bit 1. 0 = Inactive (default) 1 = Retry has expired. Reserved. Bit 0 returns 0 when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 card control register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R 0 0 0 R R/W R/W R/WC 0 0 0 0 0 Name Type Default Card control Register: Type: Offset: Default: Description: Card control Read-only, Read/Write, Read/Write to Clear (see individual bit descriptions) 91h 00h This register is provided for PCI1130 compatibility. RI_OUT is enabled through this register. See Table 24 for a complete description of the register contents. Table 24. Card Control Register BIT SIGNAL TYPE FUNCTION 7 RIENB R/W Ring-indicate output enable. 0 = Disables any routing of RI_OUT signal (default). 1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal when RIMUX is set to 0, or for routing to MFUNC2/4. 6 ZVENABLE R/W Compatibility ZV mode enable. When set, the PC Card socket interface ZV terminals enter a high-impedance state. These bits have no assigned function. 5 No function R/W 4–3 RSVD R 2 AUD2MUX R/W CardBus Audio-to-CAUDPWM. When set, the CAUDIO signal (PWM) is routed to the CAUDPWM signal which can be routed to a multifunction terminal. Reserved. Bits 4–3 default to 0. 1 SPKROUTEN R/W Speaker out enable. This bit is the enable for routing PC Card SPKR through to the SPKROUT terminal. The SPKROUT terminal drives valid data only when the socket SPKROUTEN bit is set. 0 = SPKR to SPKROUT not enabled (default) 1 = SPKR to SPKROUT enabled 0 IFG R/WC Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a functional interrupt is signaled from a PC Card interface. Write back a 1 to clear this bit. 0 = No PC Card functional interrupt detected (default). 1 = PC Card functional interrupt detected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 device control register Bit 7 6 5 4 3 2 1 0 Type R R/W R/W R Default 0 1 1 R/W R/W R/W R/W 0 0 1 1 0 Name Device control Register: Type: Offset: Default: Description: Device control Read-only, Read/Write (see individual bit descriptions) 92h 66h This register is provided for PCI1130 compatibility The mode select and socket-capable force bits are programmed through this register. See Table 25 for a complete description of the register contents. Table 25. Device Control Register 66 BIT SIGNAL TYPE 7 RSVD R FUNCTION 6 3VCAPABLE R/W 3-V socket capable force 0 = Not 3-V capable 1 = 3-V capable (default) 5 IO16R2 R/W Diagnostic bit. 4 RSVD R 3 TEST R/W TI test. Only a 0 should be written to bit 3. This bit can be set to shorten the interrogation counter. Reserved. Bit 7 returns 0 when read. Reserved. Bit 4 returns 0 when read. Writes have no effect. 2–1 INTMODE R/W Interrupt mode. Bits 2–1 select the interrupt signaling mode. The interrupt mode bits are encoded: 00 = Parallel PCI interrupts only 01 = Parallel IRQ and parallel PCI interrupts 10 = IRQ serialized interrupts and parallel PCI interrupt 11 = IRQ and PCI serialized interrupts (default) 0 RSVD R/W Reserved. This bit is reserved for test purposes. Only 0 should be written to this bit. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 diagnostic register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 1 1 R/W R/W R/W R/W 0 0 0 0 1 Name Diagnostic Type Default Register: Type: Offset: Default: Description: Diagnostic Read/Write 93h 61h This register is provided for internal TI test purposes. It is a read/write register, but should not be accessed during normal operation. See Table 26 for a complete description of the register contents. Table 26. Diagnostic Register BIT SIGNAL TYPE FUNCTION 7 TRUE_VAL R/W True value. This bit defaults to 0 when read. This bit is encoded as: 0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Reads all 1s in reads to the PCI vendor ID and PCI device ID registers 6 RSVD R/W Reserved. This bit has no function. 5 CSC R/W CSC Interrupt Routing Control. 0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1 1 = CSC interrupts routed to PCI if ExCA 805 bits 7:4 = 0000b. (default) In this case, the setting of ExCA 803 bit 4 is a “don’t care” 4 DIAG4 R/W Diagnostic RETRY_DIS. Delayed transaction disable. 3 DIAG3 R/W 2 DIAG2 R/W Diagnostic RETRY_EXT. Extends the latency from 16 to 64. Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. 1 DIAG1 R/W Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215. 0 ASYNCINT R/W Global asynchronous interrupt enable. When set to a 1, bit 0 enables the asynchronous generation of CSC interrupts. socket DMA register 0 Bit 31 30 29 28 27 26 25 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name 24 23 22 21 20 19 18 17 16 R R R R R R R 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Socket DMA register 0 Name Socket DMA register 0 Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket DMA register 0 Read-only, Read/Write (see individual bit descriptions) 94h 0000 0000h This register provides control over the PC Card DMA request (DREQ) signaling. See Table 27 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 67 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 27. Socket DMA Register 0 BIT SIGNAL TYPE 31–2 RSVD R 1–0 DREQPIN FUNCTION Reserved. Bits 31–2 return 0s when read. DMA request (DREQ). Bits 1–0 indicate which pin on the 16-bit PC Card interface will be used as DREQ during DMA transfers. This field is encoded as: 00 = Socket not configured for DMA (default). 01 = DREQ uses SPKR. 10 = DREQ uses IOIS16. 11 = DREQ uses INPACK. R/W socket DMA register 1 Bit 31 30 29 28 27 26 25 Name Type 24 23 22 21 20 19 18 17 16 Socket DMA register 1 R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Type Default Socket DMA register 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket DMA register 1 Read-only, Read/Write (see individual bit descriptions) 98h 0000 0000h This register provides control over the distributed DMA (DDMA) registers and the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI I/O address space. See Table 28 for a complete description of the register contents. NOTE: 32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits. Table 28. Socket DMA Register 1 BIT SIGNAL TYPE 31–16 RSVD R 15–4 DMABASE R/W 3 EXTMODE R 2–1 0 68 XFERSIZE DDMAEN FUNCTION Reserved. Bits 31–16 return 0s when read. DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K bytes of I/O address space. The lower 4 bits are hardwired to 0 and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary. Extended addressing. This feature is not supported by the PCI1211 and always returns a 0. R/W Transfer size. Bits 2–1 specify the width of the DMA transfer on the PC Card interface and are encoded as: 00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved R/W DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value of DMABASE. 0 = Disabled (default) 1 = Enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 capability ID register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 1 Name Capability ID Register: Type: Offset: Default: Description: Capability ID Read-only A0h 01h This register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. next-item pointer register Bit 7 6 5 4 Type R R R R Default 0 0 0 0 Name 3 2 1 0 R R R R 0 0 0 0 Next-item pointer Register: Type: Offset: Default: Description: Next-item pointer Read-only A1h 00h This register is used to indicate the next item in the linked list of the PCI power management capabilities. Because the PCI1211 functions include only one capabilities item, this register returns 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 69 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 power-management capabilities register Bit 15 14 13 12 11 10 Type R R R R R R R R R Default 0 1 1 1 1 1 1 0 0 Name 9 8 7 6 5 4 3 2 1 0 R R R R R R R 0 1 0 0 0 0 1 Power-management capabilities Register: Type: Offset: Default: Description: Power-management capabilities Read-only (see individual bit descriptions) A2h 7E21h This register contains information on the capabilities of the PC Card function related to power management. Both PCI1211 CardBus bridge functions support D0, D2, and D3 power states. See Table 29 for a complete description of the register contents. Table 29. Power-Management Capabilities Register BIT SIGNAL TYPE FUNCTION 15–11 PME_CAP R PME support. This 5-bit field indicates the power states from which the PCI1211 supports asserting PME. A 0 for any bit indicates that the CardBus function cannot assert PME from that power state. These five bits return 01111b when read. Each of these bits is described below: Bit 15 contains the value 0, indicating that PME cannot be asserted from D3cold state. Bit 14 contains the value 1, indicating that PME can be asserted from D3hot state. Bit 13 contains the value 1, indicating that PME can be asserted from D2 state. Bit 12 contains the value 1, indicating that PME can be asserted from D1 state. Bit 11 contains the value 1, indicating that PME can be asserted from the D0 state. 10 D2_CAP R D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device power state. 9 D1_CAP R D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device power state. 8–6 RSVD R Reserved. These bits return 000b when read. 5 DSI R Device-specific initialization. Bit 5 returns 1 when read, indicating that the CardBus controller function require special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it. 4 AUX_PWR R Auxiliary power source. This bit returns 0 when read, indicating that the function supplies its own auxiliary power source. 3 PMECLK R PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the PCI1211 to generate PME. 2–0 VERSION R Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power management (PM) registers as described in the PCI Bus Power Management Interface Specification, Revision 1.0. 70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 power-management control/status register Bit 15 14 13 12 11 10 R/WC R R R R R R R/W R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R R R R/W R/W 0 0 0 0 0 0 0 Power-management control/status Register: Type: Offset: Default: Description: Power-management control/status Read-only, Read/Write, Read/Write to Clear (see individual bit descriptions) A4h 0000h This register determines and changes the current power state of the PCI1211 CardBus function. The contents of this register are not affected by the internally-generated reset caused by the transition from D3hot to D0 state. See Table 30 for a complete description of the register contents. Table 30. Power-Management Control/Status Register BIT SIGNAL TYPE FUNCTION 15 PMESTAT R/WC PME status. Bit 15 is set when the CardBus function would normally assert PME, independent of the state of the PME_EN bit. Bit 15 is cleared by a write back of 1, and this also clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect. 14–13 DATASCALE R Data scale. This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit. 12–9 DATASEL R Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data as indicated by the DYN_DATA bit. 8 PME_EN R/W PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, assertion of PME is disabled. 7–5 RSVD R Reserved. Bits 7–5 return 0s when read. 4 DYN_DATA_PME_EN R Dynamic data PME enable. Bit 4 returns 0 when read since the CardBus function does not report dynamic data. 3–2 RSVD R Reserved. Bits 3–2 return 0s when read. 1–0 PWR_STATE R/W Power state. This 2-bit field is used both to determine the current power state of a function, and to set the function into a new power state. This field is encoded as: 00 = D0 01 = D1 10 = D2 11 = D3hot POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 71 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 power-management control/status register bridge support extensions Bit 7 6 Type R R R R R Default 1 1 0 0 0 Name 5 4 3 2 1 0 R R R 0 0 0 Power-management control/status register bridge support extensions Register: Type: Offset: Default: Description: Power-management control/status register bridge support extensions Read-only A6h C0h The power-management control/status register bridge support extensions supports PCI bridge specific functionality. See Table 31 for a complete description of the register contents. Table 31. Power-Management Control/Status Register Bridge Support Extensions BIT SIGNAL TYPE 7 BPCC_EN R Bus power/clock control. When read, bit 7 returns a 1. FUNCTION 6 B2_B3 R B2/B3 support for D3hot. ThIs bit returns a 1 when read. 5–0 RSVD R Reserved. These bits return 0s when read. power management data register Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 3 2 1 0 R R R R 0 0 0 0 Power management data Register: Type: Offset: Default: Description: 72 4 Power management data Read-only A7h 00h This register returns zeros when read since the CardBus functions do not report dynamic data. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 general-purpose event status register Bit 15 14 13 12 11 10 R/WC R R R R/WC R R R/WC R R 0 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R/WC R/WC R/WC R/WC R/WC 0 0 0 0 0 0 Power-management control/status Register: Type: Offset: Default: Description: General-purpose event status Read-only, Read/Write to Clear (see individual bit descriptions) A8h 0000h This register contains status bits that are set when events occur that are controlled by the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1 to the corresponding bit location. The status bits in this register do not depend upon the state of a corresponding bit in the general-purpose enable register. See Table 32 for a complete description of the register contents. Table 32. General-Purpose Event Status Register BIT SIGNAL TYPE FUNCTION PC card ZV Status. Bit 15 is set on a change in status of the ZVENABLE bit in the PC card controller function of the PCI1211. 15 ZV_STS R/WC 14–12 RSVD R 11 PWR_STS R/WC 10–9 RSVD R 8 VPP12_STS R/WC Reserved. These bits return 0s when read. Power change status. Bit 11 is set when software has changed the power state the socket. A change in either VCC or VPP for the socket causes this bit to be set. Reserved. These bits return 0s when read. 12 Volt VPP request status. Bit 8 is set when software has changed the requested Vpp level to or from 12 Volts for the PC Card socket. 7–5 RSVD R 4 GP4_STS R/WC Reserved. These bits return 0s when read. GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level. 3 GP3_STS R/WC GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level . 2 GP2_STS R/WC GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level. 1 GP1_STS R/WC GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level. 0 GP0_STS R/WC GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 73 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 general-purpose event enable register Bit 15 14 13 12 11 10 R/W R R R R/W R R R/W R 0 0 0 0 0 0 0 0 0 Name Type Default 9 8 7 6 5 4 3 2 1 0 R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 General-purpose event enable Register: Type: Offset: Default: Description: General-purpose event enable Read-only, Read/Write (see individual bit descriptions) AAh 0000h This register contains bits that are set to enable a GPE signal. The GPE signal is driven until the corresponding status bit is cleared and the event is serviced. The GPE can be signaled only if one of the multifunction terminals, MFUNC6–MFUNC0, are configured for GPE signaling. See Table 33 for a complete description of the register contents. Table 33. General-Purpose Event Enable Register BIT SIGNAL TYPE FUNCTION PC card socket ZV enable. When bit 15 is set, a GPE is signaled on a change in status of ZVENABLE in the PC Card controller function of the PCI1211. 15 ZV_EN R/W 14–12 RSVD R 11 PWR_EN R/W 10–9 RSVD R 8 VPP12_EN R/W 7–5 RSVD R 4 GP4_EN R/W GPI4 event enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5 terminal input level if configured as GPI4. 3 GP3_EN R/W GPI3 event enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4 terminal input level if configured as GPI3. 2 GP2_EN R/W GPI2 event enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2 terminal input if configured as GPI2. 1 GP1_EN R/W GPI1 event enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1 terminal input if configured as GPI1. 0 GP0_EN R/W GPI0 event enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0 terminal input if configured as GPI0. 74 Reserved. These bits return 0s when read. Power change event enable. When bit 11 is set, a GPE is signaled on when software has changed the power state of the socket. Reserved. These bits return 0s when read. 12 Volt VPP request event enable. When bit 8 is set, a GPE is signaled when software has changed the requested VPP level to or from 12 Volts for the card socket. Reserved. These bits return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 general-purpose input register Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 0 X X X X X General-purpose input Register: Type: Offset: Default: Description: General-purpose input Read-only (see individual bit descriptions) ACh 00XXh This register provides the logical value of the data input from the GPI terminals, MFUNC5–MFUNC4 and MFUNC2–MFUNC0. See Table 34 for a complete description of the register contents. Table 34. General-Purpose Input Register BIT SIGNAL TYPE 15–5 RSVD R Reserved. Bits 15–5 return 0s when read. Writes have no effect. FUNCTION 4 GPI4_DATA R GPI4 Data Bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal. Writes have no effect. 3 GPI3_DATA R GPI3 Data Bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal. Writes have no effect. 2 GPI2_DATA R GPI2 Data Bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal. Writes have no effect. 1 GPI1_DATA R GPI1 Data Bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal. Writes have no effect. 0 GPI0_DATA R GPI0 Data Bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 75 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 general-purpose output register Bit 15 14 13 12 11 10 9 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 General-purpose output Register: Type: Offset: Default: Description: General-purpose output Read-only, Read/Write (see individual bit descriptions) AEh 0000h This register is used for control of the general-purpose outputs. See Table 35 for a complete description of the register contents. Table 35. General-Purpose Output Register 76 BIT SIGNAL TYPE 15–5 RSVD R FUNCTION 4 GPO4_DATA R/W GPO4 Data Bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5 terminal if configured as GPO4. Reads return the last data value written. 3 GPO3_DATA R/W GPIO3 Data Bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4 terminal if configured as GPO3. Reads return the last data value written. 2 GPO2_DATA R/W GPO2 Data Bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2 terminal if configured as GPO2. Reads return the last data value written. 1 GPO1_DATA R/W GPO1 Data Bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1 terminal if configured as GPO1. Reads return the last data value written. 0 GPO0_DATA R/W GPO0 Data Bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0 terminal if configured as GPO0. Reads return the last data value written. Reserved. Bits 15–5 return 0s when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 serial bus data register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 Serial bus data Register: Type: Offset: Default: Description: Serial bus data Read/Write B0h 00h This register is for programmable serial bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. To write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit must be reset. On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of this register are valid read data from the serial bus interface. See Table 36 for a complete description of the register contents. Table 36. Serial Bus Data Register BIT SIGNAL TYPE FUNCTION 7–0 SBDATA R/W Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid. serial bus index register Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 Serial bus index Register: Type: Offset: Default: Description: Serial bus index Read/Write B1h 00h This register is for programmable serial bus byte reads and writes. This register represents the byte address when generating cycles on the serial bus interface. To write a byte, the serial bus data register must be programmed with the data, this register must be programmed with the byte address, and the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator. On byte reads, the word address is programmed into this register, the serial bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 37 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 77 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 37. Serial Bus Index Register BIT SIGNAL TYPE FUNCTION 7–0 SBINDEX R/W Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface. serial bus slave address register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 Serial bus slave address Register: Type: Offset: Default: Description: Serial bus slave address Read/Write B2h 00h This register is for programmable serial bus byte read and write transactions. To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit. On byte reads, the byte address is programmed into the serial bus index register, this register must be programmed with both the 7-bit slave address and the read/write indicator bit must be set, and the REQBUSY bit in the serial bus control and status register must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface. See Table 38 for a complete description of the register contents. Table 38. Serial Bus Slave Address Register 78 BIT SIGNAL TYPE FUNCTION 7–1 SLAVADDR R/W Serial bus slave address. This bit field represents the slave address of a read or write transaction on the serial interface. 0 RWCMD R/W Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses 0 = A byte write access is requested to the serial bus interface 1 = A byte read access is requested to the serial bus interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 serial bus control and status register Bit 7 6 5 R/W R R R 0 0 0 0 Name Type Default 4 3 2 1 0 R/WC R/W R/WC R/WC 0 0 0 0 Serial bus control and status Register: Type: Offset: Default: Description: Serial bus control and status Read-only, Read/Write, Read/Write to Clear (see individual bit descriptions) B3h 00h This register is used to communicate serial bus status information and select the quick command protocol. The REQBUSY bit in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 39 for a complete description of the register contents. Table 39. Serial Bus Control and Status Register BIT SIGNAL TYPE FUNCTION Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte protocol is used on read commands. The word address byte in the serial bus index register is not output by the PCI1211 when bit 7 is set. 7 PROT_SEL R/W 6 RSVD R Reserved. Bit 6 returns 0 when read. R Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write) is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register. Bit 5 must be polled on reads from the serial interface. After the byte read access has been requested, the read data is valid in the serial bus data register. R Serial EEPROM Busy status. Bit 4 indicates the status of the PCI1211 serial EEPROM circuitry. Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus EEPROM. 0 = Serial EEPROM circuitry is not busy 1 = Serial EEPROM circuitry is busy Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected. Pullup resistors must be implemented on the MFUNC1 and MFUNC4 (SDA and SCL) terminals for bit 3 to be set. If bit 3 is reset, then the MFUNC4 and MFUNC1 terminals can be used for alternate functions such as general-purpose inputs and outputs. 0 = Serial bus interface not detected 1 = Serial bus interface detected 5 4 REQBUSY ROMBUSY 3 SBDETECT R/WC 2 SBTEST R/W 1 0 REQ_ERR ROM_ERR Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes. 0 = Serial bus clock at normal operating frequency, 100 kHz (default) 1 = Serial bus clock frequency increased for test purposes [ R/WC Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during a requested cycle, and may be set due to a missing acknowledge. Bit 1 is cleared by a write back of 1. 0 = No error detected during user requested byte read or write cycle 1 = Data error detected during user requested byte read or write cycle R/WC EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the auto-load from the serial bus EEPROM, and may be set due to a missing acknowledge. Bit 0 is also set on invalid EEPROM data formats. Refer to serial bus interface on page 30 for details on EEPROM data format. Bit 0 is cleared by a write back of 1. 0 = No error detected during auto-load from serial bus EEPROM 1 = Data error detected during auto-load from serial bus EEPROM POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 79 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA compatibility registers The exchangeable card architecture (ExCA) registers implemented in the PCI1211 are register-compatible with the Intel 82365SL–DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-Bit I/F legacy mode base address register. The offsets from this base address run contiguous from 00h to 3Fh for the socket. Refer to Figure 20 for an ExCA I/O mapping illustration. PCI1211 Configuration Registers Host I/O Space Offset Offset CardBus Socket/ExCA Base Address 10h PC Card ExCA Registers Index Data 16-Bit Legacy-Mode Base Address 00h 3Fh 44h Figure 20. ExCA Register Access Through I/O The TI PCI1211 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus socket registers/ExCA registers base address register (PCI register 10h) at memory offset 800h. Refer to Figure 21 for an ExCA memory mapping illustration. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K window at memory offset 0h. PCI1211 Configuration Registers Offset Host Memory Space Offset 00h CardBus Socket/ExCA Base Address 10h CardBus Socket Registers 20h 800h 16-Bit Legacy-Mode Base Address 44h ExCA Registers 844h Figure 21. ExCA Register Access Through Memory 80 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA compatibility registers (continued) The interrupt registers, as defined by the 82365SL–DL Specification, in the ExCA register set control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1211 to ensure that all possible PCI1211 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h. Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity. Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. (Table 40 identifies each ExCA register and its respective ExCA offset.) Memory windows have 4K-byte granularity. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 81 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 40. ExCA Registers and Offsets PCI MEMORY ADDRESS OFFSET (HEX) ExCA OFFSET (HEX) Identification and revision 800 00 Interface status 801 01 Power control 802 02 Interrupt and general control 803 03 Card status change 804 04 Card status-change-interrupt configuration 805 05 Address window enable 806 06 I / O window control 807 07 I / O window 0 start-address low byte 808 08 I / O window 0 start-address high byte 809 09 I / O window 0 end-address low byte 80A 0A EXCA REGISTER NAME 82 I / O window 0 end-address high byte 80B 0B I / O window 1 start-address low byte 80C 0C I / O window 1 start-address high byte 80D 0D I / O window 1 end-address low byte 80E 0E I / O window 1 end-address high byte 80F 0F Memory window 0 start-address low byte 810 10 Memory window 0 start-address high byte 811 11 Memory window 0 end-address low byte 812 12 Memory window 0 end-address high byte 813 13 Memory window 0 offset-address low byte 814 14 Memory window 0 offset-address high byte 815 15 Card detect and general control 816 16 Reserved 817 17 Memory window 1 start-address low byte 818 18 Memory window 1 start-address high byte 819 19 Memory window 1 end-address low byte 81A 1A Memory window 1 end-address high byte 81B 1B Memory window 1 offset-address low byte 81C 1C Memory window 1 offset-address high byte 81D 1D Global control 81E 1E Reserved 81F 1F POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 40. ExCA Registers and Offsets (Continued) PCI MEMORY ADDRESS OFFSET (HEX) ExCA OFFSET (HEX) Memory window 2 start-address low byte 820 20 Memory window 2 start-address high byte 821 21 Memory window 2 end-address low byte 822 22 Memory window 2 end-address high byte 823 23 Memory window 2 offset-address low byte 824 24 Memory window 2 offset-address high byte 825 25 Reserved 826 26 Reserved 827 27 Memory window 3 start-address low byte 828 28 Memory window 3 start-address high byte 829 29 Memory window 3 end-address low byte 82A 2A EXCA REGISTER NAME Memory window 3 end-address high byte 82B 2B Memory window 3 offset-address low byte 82C 2C Memory window 3 offset-address high byte 82D 2D Reserved 82E 2E Reserved 82F 2F Memory window 4 start-address low byte 830 30 Memory window 4 start-address high byte 831 31 Memory window 4 end-address low byte 832 32 Memory window 4 end-address high byte 833 33 Memory window 4 offset-address low byte 834 34 Memory window 4 offset-address high byte 835 35 I/O window 0 offset-address low byte 836 36 I/O window 0 offset-address high byte 837 37 I/O window 1 offset-address low byte 838 38 I/O window 1 offset-address high byte 839 39 Reserved 83A 3A Reserved 83B 3B Reserved 83C 3C Reserved 83D 3D Reserved 83E 3E Reserved 83F 3F Memory window page 0 840 – Memory window page 1 841 – Memory window page 2 842 – Memory window page 3 843 – Memory window page 4 844 – POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 83 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA identification and revision register (index 00h) Bit 7 6 5 Type R R R/W R/W Default 1 0 0 0 Name 4 3 2 1 0 R/W R/W R/W R/W 0 1 0 0 ExCA identification and revision Register: Type: Offset: Default: Description: ExCA identification and revision Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 800h; ExCA offset 00h 84h This register provides host software with information on 16-bit PC Card support and Intel 82365SL-DF compatibility. See Table 41 for a complete description of the register contents. Table 41. ExCA Identification and Revision Register (Index 00h) BIT 84 SIGNAL TYPE FUNCTION Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the PCI1211. The PCI1211 supports both I/O and memory 16-bit PC cards. 7–6 IFTYPE R 5–4 RSVD R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation. 3–0 365REV R/W Intel 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCI1211. Host software can read this field to determine compatibility to the Intel 82365SL-DF register set. This field defaults to 0100b upon PCI1211 reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA interface status register (index 01h) Bit 7 6 5 Type R R R R Default 0 0 X X Name 4 3 2 1 0 R R R R X X X X ExCA interface status Register: Type: Offset: Default: Description: ExCA interface status Read-only (see individual bit descriptions) CardBus socket address + 801h; ExCA offset 01h 00XX XXXXb This register provides information on the current status of the PC Card interface. An X in the default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 42 for a complete description of the register contents. Table 42. ExCA Interface Status Register (Index 01h) BIT SIGNAL TYPE 7 RSVD R 6 CARDPWR R 5 READY R FUNCTION Reserved. Bit 7 returns 0 when read. Writes have no effect. Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the power control register is programmed. Bit 6 is encoded as: 0 = VCC and VPP to the socket turned off (default) 1 = VCC and VPP to the socket turned on Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface. 0 = PC Card not ready for data transfer 1 = PC Card ready for data transfer 4 CARDWP R Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to the PCI1211 whether or not the memory card is write protected. Furthermore, write protection for an entire PCI1211 16-bit memory window is available by setting the appropriate bit in the memory window offset high-byte register. 0 = WP is 0. PC Card is R/W. 1 = WP is 1. PC Card is read-only. 3 CDETECT2 R Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket. 0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted. 2 CDETECT1 R Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket. 0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted. 1–0 BVDSTAT R Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0 reflects BVD1. 00 = Battery dead 01 = Battery dead 10 = Battery low; warning 11 = Battery good When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 85 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA power-control register (index 02h) Bit 7 6 5 4 R/W R R R/W 0 0 0 0 Name Type Default 3 2 1 0 R/W R R/W R/W 0 0 0 0 ExCA power control Register: Type: Offset: Default: Description: ExCA power control Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 802h; ExCA offset 02h 00h This register provides PC Card power control. Bit 7 of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 43 for a complete description of the register contents. Table 43. ExCA Power-Control Register (Index 02h) BIT TYPE FUNCTION Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1211. This bit is encoded as: 0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled 7 COE R/W 6–5 RSVD R 4–3 EXCAVCC R/W 2 RSVD R 1–0 86 SIGNAL EXCAVPP R/W Reserved. Bits 6–5 return 0s when read. Writes have no effect. VCC. Bits 4–3 are used to request changes to card VCC. This field is encoded as: 00 = 0 V (default) 01 = 0 V reserved 10 = 5 V 11 = 3 V Reserved. Bit 2 returns 0 when read. Writes have no effect. VPP. Bits 1–0 are used to request changes to card VPP. The PCI1211 ignores this field unless VCC to the socket is enabled (i.e., 5 V or 3.3 V). This field is encoded as: 00 = 0 V (default) 01 = VCC 10 = 12 V 11 = 0 V reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA interrupt and general-control register (index 03h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA interrupt and general control Register: Type: Offset: Default: Description: ExCA interrupt and general control Read/Write (see individual bit descriptions) CardBus socket address + 803h; ExCA offset 03h 00h This register controls interrupt routing for I/O interrupts, as well as other critical 16-bit PC Card functions. See Table 44 for a complete description of the register contents. Table 44. ExCA Interrupt and General-Control Register (Index 03h) BIT SIGNAL TYPE FUNCTION 7 RINGEN R/W Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as: 0 = Ring indicate disabled (default) 1 = Ring indicate enabled 6 RESET R/W Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6 affects 16-bit cards only. This bit is encoded as 0 = RESET signal asserted (default) 1 = RESET signal deasserted 5 CARDTYPE R/W Card type. Bit 5 indicates the PC card type. This bit is encoded as: 0 = Memory PC Card installed (default) 1 = I/O PC Card installed R/W PCI Interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7–4 in the ExCA card status change interrupt configuration register. This bit is encoded as: 0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts. R/W Card interrupt select for I/O PC Card functional interrupts. Bits 3–0 select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as: 0000 = No interrupt routing (default). CSC interrupts routed to PCI interrupts. This bit setting is OR’ed with ExCA bit 4 for backwards compatibility. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0100 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 4 3–0 CSCROUTE INTSELECT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 87 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA card status-change register (index 04h) Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 4 3 2 1 0 R R R R 0 0 0 0 ExCA card status change Register: Type: Offset: Default: Description: ExCA card status change Read-only (see individual bit descriptions) CardBus socket address + 804h; ExCA offset 04h 00h This register controls interrupt routing for I/O interrupts as well as other critical 16–bit PC Card functions. This register reflects the status of PC Card CSC interrupt sources. The card status change interrupt register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled and that particular event occurs, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit write back of 1 to the status bit. The choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the global control register. See Table 45 for a complete description of the register contents. Table 45. ExCA Card Status-Change Register (Index 04h) BIT SIGNAL TYPE 7–4 RSVD R Reserved. Bits 7–4 return 0s when read. Writes have no effect. 3 CDCHANGE R Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface. This bit is encoded as: 0 = No change detected on either CD1 or CD2 1 = Change detected on either CD1 or CD2 2 READYCHANGE R FUNCTION Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCI1211 interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now ready to accept new data. This bit is encoded as: 0 = No low-to-high transition detected on READY (default) 1 = Detected low-to-high transition on READY When a 16-bit I/O card is installed, bit 2 is always 0. 1 BATWARN R Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the source of a PCI1211 interrupt was due to a battery-low warning condition. This bit is encoded as: 0 = No battery warning condition (default) 1 = Detected battery warning condition When a 16-bit I/O card is installed, bit 1 is always 0. 0 BATDEAD R Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates whether the source of a PCI1211 interrupt was due to a battery dead condition. This bit is encoded as: 0 = STSCHG deasserted (default) 1 = STSCHG asserted Ring indicate. When the PCI1211 is configured for ring indicate operation, bit 0 indicates the status of RI. 88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA card status-change-interrupt configuration register (index 05h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA status-change-interrupt configuration Register: Type: Offset: Default: Description: ExCA card status-change-interrupt configuration Read/Write (see individual bit descriptions) CardBus socket address + 805h; ExCA offset 05h 00h This register controls interrupt routing for card status-change interrupts, as well as masking CSC interrupt sources. See Table 46 for a complete description of the register contents. Table 46. ExCA Card Status-Change-Interrupt Configuration Register (Index 05h) BIT SIGNAL TYPE FUNCTION 7–4 CSCSELECT R/W Interrupt select for card status change. Bits 7–4 select the interrupt routing for card status change interrupts. 0000 = CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register (PCI Offset 93h) is set to 1b. In this case bit 4 of ExCA 803 is a “don’t care”. This is the default setting. 0000 = No ISA interrupt routing if bit 5 of the diagnostic register (PCI Offset 93h) is set to 0b. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803 to 1b. This field is encoded as: 0000 = No interrupt routing (default) 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled 3 CDEN R/W Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as: 0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes R/W Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation 2 READYEN 1 BATWARNEN R/W Battery Warning Enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation 0 BATDEADEN R/W Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt. 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 89 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA address window enable register (index 06h) Bit 7 6 5 R/W R/W R R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA address window enable Register: Type: Offset: Default: Description: ExCA address window enable Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 806h; ExCA offset 06h 00h This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI1211 does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 47 for a complete description of the register contents. Table 47. ExCA Address Window Enable Register (Index 06h) BIT 90 SIGNAL TYPE FUNCTION 7 IOWIN1EN R/W I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the card. This bit is encoded as: 0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled 6 IOWIN0EN R/W I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the card. This bit is encoded as: 0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled 5 RSVD R 4 MEMWIN4EN R/W Memory window 4 enable. Bit 4 enables/disables memory window 4 for the card. This bit is encoded as: 0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled 3 MEMWIN3EN R/W Memory window 3 enable. Bit 3 enables/disables memory window 3 for the card. This bit is encoded as: 0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled 2 MEMWIN2EN R/W Memory window 2 enable. Bit 2 enables/disables memory window 2 for the card. This bit is encoded as: 0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled 1 MEMWIN1EN R/W Memory window 1 enable. Bit 1 enables/disables memory window 1 for the card. This bit is encoded as: 0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled 0 MEMWIN0EN R/W Memory window 0 enable. Bit 0 enables/disables memory window 0 for the card. This bit is encoded as: 0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled Reserved. Bit 5 returns 0 when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA I/O window control register (index 07h) Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA I/O window control Register: Type: Offset: Default: Description: ExCA I/O window control Read/Write (see individual bit descriptions) CardBus socket address + 807h; ExCA offset 07h 00h This register contains parameters related to I/O window sizing and cycle timing. See Table 48 for a complete description of the register contents. Table 48. ExCA I/O Window Control Register (Index 07h) BIT 7 6 SIGNAL WAITSTATE1 ZEROWS1 TYPE FUNCTION R/W I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. R/W I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 5 IOSIS16W1 R/W I/O window 1 IOIS16 source. Bit 5 controls the I/O window automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16. 4 DATASIZE1 R/W I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if the I/O window 1 IOIS16 source bit (bit 5) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. R/W I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. 3 WAITSTATE0 2 ZEROWS0 R/W I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 1 IOSIS16W0 R/W I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16. 0 DATASIZE0 R/W I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if the I/O window 0 IOIS16 source bit (bit 1) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 91 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA I/O window 0 and 1 start-address low-byte register (index 08h, 0Ch) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 start-address low byte Register: Offset: Register: Offset: Type: Default: Size: Description: ExCA I/O window 0 start-address low byte CardBus socket address + 808h; ExCA offset 08h ExCA I/O window 1 start-address low byte CardBus socket address + 80Ch; ExCA offset 0Ch Read/Write 00h One byte These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the start address. ExCA I/O window 0 and 1 start-address high-byte register (index 09h, 0Dh) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 start-address high byte Register: Offset: Register: Offset: Type: Default: Size: Description: 92 4 ExCA I/O window 0 start-address high byte CardBus socket address + 809h; ExCA offset 09h ExCA I/O window 1 start-address high byte CardBus socket address + 80Dh; ExCA offset 0Dh Read/Write 00h One byte These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA I/O window 0 and 1 end-address low-byte register (index 0Ah, 0Eh) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 end-address low byte Register: Offset: Register: Offset: Type: Default: Size: Description: ExCA I/O window 0 end-address low byte CardBus socket address + 80Ah; ExCA offset 0Ah ExCA I/O window 1 end-address low byte CardBus socket address + 80Eh; ExCA offset 0Eh Read/Write 00h One byte These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the end address. ExCA I/O window 0 and 1 end-address high-byte register (index 0Bh, 0Fh) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 end-address high byte Register: Offset: Register: Offset: Type: Default: Size: Description: ExCA I/O window 0 end-address high byte CardBus socket address + 80Bh; ExCA offset 0Bh ExCA I/O window 1 end-address high byte CardBus socket address + 80Fh; ExCA offset 0Fh Read/Write 00h One byte These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 93 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA memory window 0–4 start-address low-byte register (index 10h, 18h, 20h, 28h, 30h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 94 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 start-address low byte Register: Offset: Register: Offset: Register: Offset: ExCA memory window 0 start-address low byte CardBus socket address + 810h; ExCA offset 10h ExCA memory window 1 start-address low byte CardBus socket address + 818h; ExCA offset 18h ExCA memory window 2 start-address low byte CardBus socket address + 820h; ExCA offset 20h Register: Offset: Register: Offset: Type: Default: Size: Description: ExCA memory window 3 start-address low byte CardBus socket address + 828h; ExCA offset 28h ExCA memory window 4 start-address low byte CardBus socket address + 830h; ExCA offset 30h Read/Write 00h One byte These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA memory window 0–4 start-address high-byte register (index 11h, 19h, 21h, 29h, 31h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 start-address high byte Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: Size: Description: ExCA memory window 0 start-address high byte CardBus socket address + 811h; ExCA offset 11h ExCA memory window 1 start-address high byte CardBus socket address + 819h; ExCA offset 19h ExCA memory window 2 start-address high byte CardBus socket address + 821h; ExCA offset 21h ExCA memory window 3 start-address high byte CardBus socket address + 829h; ExCA offset 29h ExCA memory window 4 start-address high byte CardBus socket address + 831h; ExCA offset 31h Read/Write 00h One byte These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory window data width and wait states are set in this register. See Table 49 for a complete description of the register contents. Table 49. ExCA Memory Window 0–4 Start-Address High-Byte Register (Index 11h, 19h, 21h, 29h, 31h) BIT 7 SIGNAL DATASIZE TYPE FUNCTION R/W Data size. Bit 7 controls the memory window data width. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. 6 ZEROWAIT R/W Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 16-bit cycles are reduced to equivalent of two ISA cycles. 5–4 SCRATCH R/W Scratch pad bits. Bits 5–4 have no effect on memory window operation. 3–0 STAHN R/W Start-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window start address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 95 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA memory window 0–4 end-address low-byte register (index 12h, 1Ah, 22h, 2Ah, 32h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 end-address low byte Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: Size: Description: 96 4 ExCA memory window 0 end-address low byte CardBus socket address + 812h; ExCA offset 12h ExCA memory window 1 end-address low byte CardBus socket address + 81Ah; ExCA offset 1Ah ExCA memory window 2 end-address low byte CardBus socket address + 822h; ExCA offset 22h ExCA memory window 3 end-address low byte CardBus socket address + 82Ah; ExCA offset 2Ah ExCA memory window 4 end-address low byte CardBus socket address + 832h; ExCA offset 32h Read/Write 00h One byte These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA memory window 0–4 end-address high-byte register (index 13h, 1Bh, 23h, 2Bh, 33h) Bit 7 6 5 R/W R/W R R R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 end-address high byte Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: Size: Description: ExCA memory window 0 end-address high byte CardBus socket address + 813h; ExCA offset 13h ExCA memory window 1 end-address high byte CardBus socket address + 81Bh; ExCA offset 1Bh ExCA memory window 2 end-address high byte CardBus socket address + 823h; ExCA offset 23h ExCA memory window 3 end-address high byte CardBus socket address + 82Bh; ExCA offset 2Bh ExCA memory window 4 end-address high byte CardBus socket address + 833h; ExCA offset 33h Read-only, Read/Write (see individual bit descriptions) 00h One byte These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory window wait states are set in this register. See Table 50 for a complete description of the register contents. Table 50. ExCA Memory Window 0–4 End-Address High-Byte Register (Index 13h, 1Bh, 23h, 2Bh, 33h) BIT SIGNAL TYPE FUNCTION Wait state. Bits 7–6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits. 7–6 MEMWS R/W 5–4 RSVD R 3–0 ENDHN R/W Reserved. Bits 5–4 return 0s when read. Writes have no effect. End-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window end address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 97 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA memory window 0–4 offset-address low-byte register (index 14h, 1Ch, 24h, 2Ch, 34h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 offset-address low byte Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: Size: Description: 98 4 ExCA memory window 0 offset-address low byte CardBus socket address + 814h; ExCA offset 14h ExCA memory window 1 offset-address low byte CardBus socket address + 81Ch; ExCA offset 1Ch ExCA memory window 2 offset-address low byte CardBus socket address + 824h; ExCA offset 24h ExCA memory window 3 offset-address low byte CardBus socket address + 82Ch; ExCA offset 2Ch ExCA memory window 4 offset-address low byte CardBus socket address + 834h; ExCA offset 34h Read/Write 00h One byte These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3 and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA memory window 0–4 offset-address high-byte register (index 15h, 1Dh, 25h, 2Dh, 35h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type 4 3 2 1 0 R/W R/W R/W 0 0 0 ExCA memory window 0–4 offset-address high byte Default Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default: Size: Description: ExCA memory window 0 offset-address high byte CardBus socket address + 815h; ExCA offset 15h ExCA memory window 1 offset-address high byte CardBus socket address + 81Dh; ExCA offset 1Dh ExCA memory window 2 offset-address high byte CardBus socket address + 825h; ExCA offset 25h ExCA memory window 3 offset-address high byte CardBus socket address + 82Dh; ExCA offset 2Dh ExCA memory window 4 offset-address high byte CardBus socket address + 835h; ExCA offset 35h Read/Write (see individual bit descriptions) 00h One byte These registers contain the high six bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3 and 4. The lower six bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. See Table 51 for a complete description of the register contents. Table 51. ExCA Memory Window 0–4 Offset-Address High-Byte Register (Index 15h, 1Dh, 25h, 2Dh, 35h) BIT 7 SIGNAL WINWP TYPE FUNCTION R/W Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is encoded as: 0 = Write operations are allowed (default). 1 = Write operations are not allowed. 6 REG R/W Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as: 0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory. 5–0 OFFHB R/W Offset-address high byte. Bits 5–0 represent the upper address bits A25–A20 of the memory window offset address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 99 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA I/O window 0 and 1 offset-address low-byte register (index 36h, 38h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R 0 0 0 ExCA I/O window 0 and 1 offset-address low byte Register: Offset: Register: Offset: Type: Default: Size: Description: ExCA I/O window 0 offset-address low byte CardBus socket address + 836h; ExCA offset 36h ExCA I/O window 1 offset-address low byte CardBus socket address + 838h; ExCA offset 38h Read-only, Read/Write (see description) 00h One byte These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the offset address, and bit 0 is always 0. ExCA I/O window 0 and 1 offset-address high-byte register (index 37h, 39h) Bit 7 6 5 R/W R/W R/W R/W R/W 0 0 0 0 0 Name Type Default 3 2 1 0 R/W R/W R/W 0 0 0 ExCA I/O window 0 and 1 offset-address high byte Register: Offset: Register: Offset: Type: Default: Size: Description: 100 4 ExCA I/O window 0 offset-address high byte CardBus socket address + 837h; ExCA offset 37h ExCA I/O window 1 offset-address high byte CardBus socket address + 839h; ExCA offset 39h Read/Write 00h One byte These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the offset address. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA card detect and general-control register (index 16h) Bit 7 6 5 Type R R W R/W Default X X 0 0 Name 4 3 2 1 0 R R R/W R 0 0 0 0 ExCA I/O card detect and general control Register: Type: Offset: Default: Description: ExCA card detect and general control Read-only, Write-only, Read/Write (see individual bit descriptions) CardBus socket address + 816h; ExCA offset 16h XX00 0000b This register controls how the ExCA registers for the socket respond to card removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 52 for a complete description of the register contents. Table 52. ExCA Card Detect and General-Control Register (Index 16h) BIT 7 6 5 SIGNAL VS2STAT VS1STAT SWCSC TYPE FUNCTION R VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have a default value. 0 = VS2 low 1 = VS2 high R VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have a default value. 0 = VS1 low 1 = VS1 high W Software card detect interrupt. If the card detect enable bit in the card status change interrupt configuration register is set, writing a 1 to bit 5 causes a card-detect card-status change interrupt for the associated card socket. If the card detect enable bit is cleared to 0 in the card status change interrupt configuration register, writing a 1 to the software card detect interrupt bit has no effect. Bit 5 is write-only. A read always returns 0. Card detect resume enable. If bit 4 is set to 1, then once a card detect change has been detected on CD1 and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until the card status change bit in the card status change register is cleared. If this bit is a 0, then the card detect resume functionality is disabled. 0 = Card detect resume disabled (default) 1 = Card detect resume enabled 4 CDRESUME R/W 3–2 RSVD R 1 REGCONFIG R/W 0 RSVD R Reserved. Bits 3–2 return 0s when read. Writes have no effect. Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card removal event. This bit is encoded as: 0 = No change to ExCA registers on card removal (default) 1 = Reset ExCA registers on card removal Reserved. Bit 0 returns 0 when read. Writes have no effect. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 101 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA global-control register (index 1Eh) Bit 7 6 5 4 Type R R R R/W Default 0 0 0 0 Name 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA global control Register: Type: Offset: Default: Description: ExCA global control Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 81Eh; ExCA offset 1Eh 00h This register controls the PC Card socket. The host interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See Table 53 for a complete description of the register contents. Table 53. ExCA Global-Control Register (Index 1Eh) BIT SIGNAL TYPE 7–5 RSVD R 4 No function R/W This bit has no assigned function. R/W Level/edge interrupt mode select. Bit 3 selects the signaling mode for the PCI1211 host interrupt PC. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. 3 2 IFCMODE R/W Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA card status change register. This bit is encoded as: 0 = Interrupt flags are cleared by read of CSC register (default). 1 = Interrupt flags are cleared by explicit write back of 1. 1 CSCMODE R/W Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1211 host interrupt for card status changes. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. R/W Power-down mode select. When bit 0 is set to 1, the PCI1211 is in power-down mode. In power-down mode, the PCI1211 card outputs are 3-stated until an active cycle is executed on the card interface. Following an active cycle, the outputs are again 3-stated. The PCI1211 still receives DMA requests, functional interrupts, and/or card status change interrupts; however, an actual card access is required to wake up the interface. This bit is encoded as: 0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled. 0 102 INTMODE FUNCTION Reserved. Bits 7–5 return 0s when read. Writes have no effect. PWRDWN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 ExCA memory window 0–4 page register Bit 7 6 5 R/W R/W R/W R/W 0 0 0 0 Name Type Default 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 ExCA memory window 0–4 page Register: Type: Offset: Default: Description: ExCA memory window 0–4 page Read/Write CardBus socket address + 840h 841h, 842h, 843h, 844h 00h The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any one of 256 16M-byte regions in the 4G-byte PCI address space. These registers are accessible only when the ExCA registers are memory mapped, i.e., these registers can not be accessed using the index/data I/O scheme. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 103 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 CardBus socket registers The PCMCIA CardBus specification requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI1211 provides the CardBus socket/ExCA base address register (PCI offset 10h) to locate these CardBus socket registers in PCI memory address space. Each socket has a separate base address register for accessing the CardBus socket registers (see Figure 22). Table 54 gives the location of the socket registers in relation to the CardBus socket/ExCA base address. The PCI1211 implements an additional register at offset 20h that provides power management control for the socket. PCI1211 Configuration Registers Host Memory Space Offset Offset 00h CardBus Socket Registers 10h CardBus Socket/ExCA Base Address 20h 800h ExCA Registers 44h 16-Bit Legacy-Mode Base Address 844h Figure 22. Accessing CardBus Socket Registers Through PCI Memory Table 54. CardBus Socket Registers REGISTER NAME 104 OFFSET Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h Reserved 18h Reserved 1Ch Socket power management 20h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 socket event register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket event Name Socket event Type R R R R R R R R R R R R R/WC R/WC R/WC R/WC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket event Read-only, Read/Write to Clear (see individual bit descriptions) CardBus socket address + 00h 0000 0000h This register indicates that a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register. All bits in this register are cleared by PCI reset. They can be immediately set again, if, when coming out of PC Card reset, the bridge finds the status unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software must clear this register before enabling interrupts. If it is not cleared when interrupts are enabled, an interrupt is generated (but not masked) based on any bit set. See Table 55 for a complete description of the register contents. Table 55. Socket Event Register BIT SIGNAL TYPE FUNCTION 31–4 RSVD R 3 PWREVENT R/WC Power cycle. Bit 3 is set when the PCI1211 detects that the PWRCYCLE bit in the socket present-state register has changed. This bit is cleared by writing a 1. 2 CD2EVENT R/WC CCD2. Bit 2 is set when the PCI1211 detects that the CDETECT2 field in the socket present-state register has changed. This bit is cleared by writing a 1. 1 CD1EVENT R/WC CCD1. Bit 3 is set when the PCI1211 detects that the CDETECT1 field in the socket present-state register has changed. This bit is cleared by writing a 1. 0 CSTSEVENT R/WC CSTSCHG. Bit 0 is set when the CARDSTS field in the socket present-state register has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For 16-bit PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1. Reserved. Bits 31–4 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 105 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 socket mask register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket mask Name Socket mask Type R R R R R R R R R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket mask Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 04h 0000 0000h This register allows software to control the CardBus card events that generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register. See Table 56 for a complete description of the register contents. Table 56. Socket Mask Register BIT SIGNAL TYPE 31–4 RSVD R 3 2–1 0 106 PWRMASK CDMASK CSTSMASK FUNCTION Reserved. Bits 31–4 return 0s when read. R/W Power cycle. Bit 3 masks the PWRCYCLE bit in the socket present state register from causing a status change interrupt. 0 = PWRCYCLE event does not cause CSC interrupt (default). 1 = PWRCYCLE event causes CSC interrupt. R/W Card detect mask. Bits 2–1 mask the CDETECT1 and CDETECT2 bits in the socket present-state register from causing a CSC interrupt. 00 = Insertion/removal does not cause CSC interrupt (default). 01 = Reserved (undefined) 10 = Reserved (undefined) 11 = Insertion/removal causes CSC interrupt. R/W CSTSCHG mask. Bit 0 masks the CARDSTS field in the socket present-state register from causing a CSC interrupt. 0 = CARDSTS event does not cause CSC interrupt (default). 1 = CARDSTS event causes CSC interrupt. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 socket present-state register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 1 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket present state Name Socket present state Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X Register: Type: Offset: Default: Description: Socket present state Read-only CardBus socket address + 08h 3000 00XXh This register reports information about the socket interface. Writes to the socket force event register are reflected here, as well as general socket interface status. Information about PC Card VCC support and card type is updated only at each insertion. Also note that the PCI1211 uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected in this register. See Table 57 for a complete description of the register contents. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 107 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 57. Socket Present-State Register BIT SIGNAL TYPE FUNCTION 31 YVSOCKET R YV socket. Bit 31 indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The PCI1211 does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event register. 30 XVSOCKET R XV socket. Bit 30 indicates whether or not the socket can supply VCC = X.X V to PC Cards. The PCI1211 does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force event register. 29 3VSOCKET R 3-V socket. Bit 29 indicates whether or not the socket can supply VCC = 3.3 V to PC Cards. The PCI1211 does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force event register. 28 5VSOCKET R 5-V socket. Bit 28 indicates whether or not the socket can supply VCC = 5 V to PC Cards. The PCI1211 does support 5-V VCC; therefore, this bit is always set unless overridden by the socket force event register. 27–14 RSVD R Reserved. Bits 27–14 return 0s when read. 13 YVCARD R YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V. 12 XVCARD R XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V. 11 3VCARD R 3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V. 10 5VCARD R 5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V. R Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software R Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI1211. 0 = Normal operation (default) 1 = Potential data loss due to card removal R Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not updated until a valid PC Card is inserted into the socket. 0 = Normal operation (default) 1 = Unrecognizable PC Card detected 9 8 7 DATALOST NOTACARD 6 IREQCINT R READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface. 0 = READY(IREQ)//CINT low 1 = READY(IREQ)//CINT high 5 CBCARD R CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 4 16BITCARD R 16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 3 PWRCYCLE R Power cycle. Bit 3 indicates that the status of each card powering request. This bit is encoded as: 0 = Socket powered down (default) 1 = Socket powered up R CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD2 low (PC Card may be present) 1 = CCD2 high (PC Card not present) 2 108 BADVCCREQ CDETECT2 1 CDETECT1 R CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD1 low (PC Card may be present) 1 = CCD1 high (PC Card not present) 0 CARDSTS R CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface. 0 = CSTSCHG low 1 = CSTSCHG high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 socket force event register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket force event Name Socket force event Type R W W W W W W W W R W W W W W W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket force event Read-only, Write-only (see individual bit descriptions) CardBus socket address + 0Ch 0000 0000h This register is used to force changes to the socket event register and the socket present state register. The CVSTEST bit in this register must be written when forcing changes that require card interrogation. See Table 58 for a complete description of the register contents. Table 58. Socket Force Event Register BIT SIGNAL TYPE 31–15 RSVD R Reserved. Bits 31–15 return 0s when read. FUNCTION 14 CVSTEST W Card VS test. When bit 14 is set, the PCI1211 reinterrogates the PC Card, updates the socket present state register, and reenables the socket power control. 13 FYVCARD W Force YV card. Writes to bit 13 cause the YVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 12 FXVCARD W Force XV card. Writes to bit 12 cause the XVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 11 F3VCARD W Force 3-V card. Writes to bit 11 cause the 3VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 10 F5VCARD W Force 5-V card. Writes to bit 10 cause the 5VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 9 FBADVCCREQ W Force bad VCC request. Changes to the BADVCCREQ bit in the socket present state register can be made by writing to bit 9. 8 FDATALOST W Force data lost. Writes to bit 8 cause the DATALOST bit in the socket present state register to be written. 7 FNOTACARD W Force not a card. Writes to bit 7 cause the NOTACARD bit in the socket present state register to be written. 6 RSVD R Reserved. Bit 6 returns 0 when read. 5 FCBCARD W Force CardBus card. Writes to bit 5 cause the CBCARD bit in the socket present state register to be written. 4 F16BITCARD W Force 16-bit card. Writes to bit 4 cause the 16BITCARD bit in the socket present state register to be written. 3 FPWRCYCLE W Force power cycle. Writes to bit 3 cause the PWREVENT bit in the socket event register to be written, and the PWRCYCLE bit in the socket present state register is unaffected. 2 FCDETECT2 W Force CCD2. Writes to bit 2 cause the CD2EVENT bit in the socket event register to be written, and the CDETECT2 bit in the socket present state register is unaffected. 1 FCDETECT1 W Force CCD1. Writes to bit 1 cause the CD1EVENT bit in the socket event register to be written, and the CDETECT1 bit in the socket present state register is unaffected. 0 FCARDSTS W Force CSTSCHG. Writes to bit 0 cause the CSTSEVENT bit in the socket event register to be written, and the CARDSTS bit in the socket present state register is unaffected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 109 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 socket control register Bit 31 30 29 28 27 26 25 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 24 23 22 21 20 19 18 17 16 R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Socket control Name Socket control Type R R R R R R R R R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket control Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 10h 0000 0000h This register provides control of the voltages applied to the socket and instructions for CB CLKRUN protocol. The PCI1211 ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 59 for a complete description of the register contents. Table 59. Socket Control Register BIT SIGNAL TYPE 31–8 RSVD R 7 STOPCLK R/W VCC control. Bits 6–4 are used to request card VCC changes. 000 = Request power off (default) 001 = Reserved 010 = Request VCC = 5 V 011 = Request VCC = 3.3 V 100 = Request VCC = X.X V 101 = Request VCC = Y.Y V 110 = Reserved 111 = Reserved VCCCTRL R/W 3 RSVD R 110 VPPCTRL Reserved. Bits 31–8 return 0s when read. CB CLKRUN protocol instructions. 0 = CB CLKRUN protocol can only attempt to stop/slow the CB clock if the socket is idle and the PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock. (default) 1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle. 6–4 2–0 FUNCTION R/W Reserved. Bit 3 returns 0 when read. VPP control. Bits 2–0 are used to request card VPP changes. 000 = Request power off (default) 001 = Request VPP = 12 V 010 = Request VPP = 5 V 011 = Request VPP = 3.3 V 100 = Request VPP = X.X V 101 = Request VPP = Y.Y V 110 = Reserved 111 = Reserved POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 socket power management register Bit 31 30 29 28 27 26 Type R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 Name 25 24 23 22 21 20 19 18 17 16 R R R R R R R/W 0 0 0 0 0 0 0 6 5 4 3 2 1 0 Socket power management Name Socket power management Type R R R R R R R R R R R R R R R R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Socket power management Read-only, Read/Write (see individual bit descriptions) CardBus socket address + 20h 0000 0000h This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See Table 60 for a complete description of the register contents. Table 60. Socket Power Management Register BIT SIGNAL TYPE FUNCTION 31–26 RSVD R Reserved. Bits 31–26 return 0s when read. 25 SKTACCES R Socket access status. This bit provides information on when a socket access has occurred. This bit is cleared by a read access. 0 = A PC card access has not occurred (default). 1 = A PC card access has occurred. 24 SKTMODE R Socket mode status. This bit provides clock mode information. 0 = Clock is operating normally. 1 = Clock frequency has changed. 23–17 RSVD R Reserved. Bits 23–17 return 0s when read. 16 CLKCTRLEN R/W 15–1 RSVD R 0 CLKCTRL R/W CardBus clock control enable. When bit 16 is set, clock control (CLKCTRL bit 0) is enabled. 0 = Clock control is disabled (default). 1 = Clock control is enabled. Reserved. Bits 15–1 return 0s when read. CardBus clock control. The bit determines whether the CB CLKRUN protocol will attempt to stop or slow the CB clock during idle states. Bit 16 enables this bit. 0 = Allows CB CLKRUN protocol to stop the CB clock (default). 1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 111 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 distributed DMA (DDMA) registers The DMA base address, programmable in PCI configuration space at offset 98h, points to a 16-byte region in PCI I/O space where the DDMA registers reside. The names and locations of these registers are summarized in Table 61. These PCI1211 register definitions are identical in function, but differ in location, to the 8237 DMA controller. The similarity between the register models retains some level of compatibility with legacy DMA and simplifies the translation required by the master DMA device when it forwards legacy DMA writes to DMA channels. While the DMA register definitions are identical to those in the 8237 of the same name, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment. In such cases, the PCI1211 implements these obsolete register bits as read-only nonfunctional bits. The reserved registers shown in Table 61 are implemented as read-only and return 0s when read. Writes to reserved registers have no effect. Table 61. Distributed DMA Registers TYPE R W R W 112 DMA BASE ADDRESS OFFSET (HEX) REGISTER NAME Reserved Page Reserved Reserved R N/A W Mode R Multichannel W Mask Reserved Reserved POST OFFICE BOX 655303 Current address 00 Base address Current count 04 Base count N/A Status Request Command N/A Master clear • DALLAS, TEXAS 75265 Reserved 08 0C PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 DDMA current address/base address register Bit 15 14 13 R/W R/W R/W R/W Default 0 0 0 0 Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 DDMA current address/base address Name Type 12 DDMA current address/base address Register: Type: Offset: Default: Size: Description: DDMA current address/base address Read/Write DDMA base address + 00h 0000h Two bytes This register is used to set the starting (base) memory address of a DDMA transfer. Reads from this register indicate the current memory address of a direct memory transfer. For the 8-bit DDMA transfer mode, the current address register contents are presented on AD15–AD0 of the PCI bus during the address phase. Bits 7–0 of the page register are presented on AD23–AD16 of the PCI bus during the address phase. For the 16-bit DDMA transfer mode, the current address register contents are presented on AD16–AD1 of the PCI bus during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the page register are presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored. DDMA page register Bit 7 6 5 4 Name Type Default 3 2 1 0 DDMA page R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Size: Description: DDMA page Read/Write DDMA base address + 02h 00h One byte This register is used to set the upper byte of the address of a DDMA transfer. Details of the address represented by this register are explained in DDMA current address/base address register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 113 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 DDMA current count/base count register Bit 15 14 13 R/W R/W R/W R/W Default 0 0 0 0 Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 Name Type Default 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 DDMA current count/base count Name Type 12 DMA current count/base count Register: Type: Offset: Default: Size: Description: DDMA current count/base count Read/Write DDMA base address + 04h 0000h Two bytes This register is used to set the total transfer count, in bytes, of a direct memory transfer. Reads to this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after each transfer. Likewise, the count is decremented by 2 in the 16-bit transfer mode. DDMA command register Bit 7 6 5 4 Type R R R R Default 0 0 0 0 Name 3 2 1 0 R R/W R R 0 0 0 0 DDMA command Register: Type: Offset: Default: Size: Description: DDMA command Read-only, Read/Write (see individual bit descriptions) DDMA base address + 08h 00h One byte This register is used to enable and disable the DMA controller. Bit 2, the only read/write bit, defaults to 0 enabling the DMA controller. All other bits are reserved. See Table 62 for a complete description of the register contents. Table 62. DDMA Command Register BIT TYPE TYPE 7–3 RSVD R 2 DMAEN R/W 1–0 RSVD R 114 FUNCTION Reserved. Bits 7–3 return 0s when read. DMA controller enable. Bit 2 enables and disables the distributed DMA slave controller in the PCI1211 and defaults to the enabled state. 0 = DMA controller enabled (default) 1 = DMA controller disabled Reserved. Bits 1–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 DDMA status register Bit 7 6 5 4 3 2 1 0 Type R R R R Default 0 0 0 R R R R 0 0 0 0 0 Name DDMA status Register: Type: Offset: Default: Size: Description: DDMA status Read-only (see individual bit descriptions) DDMA base address + 08h 00h One byte This register indicates the terminal count and DMA request (DREQ) status. See Table 63 for a complete description of the register contents. Table 63. DDMA Status Register BIT 7–4 3–0 SIGNAL DREQSTAT TC TYPE FUNCTION R Channel request. In the 8237, bits 7–4 indicate the status of DREQ of each DMA channel. In the PCI1211, these bits indicate the DREQ status of the single socket being serviced by this register. All four bits are set when the PC Card asserts DREQ and are reset when DREQ is deasserted. The status of the mask bit in the multichannel mask register has no effect on these bits. R Channel terminal count. The 8327 uses bits 3–0 to indicate the TC status of each of its four DMA channels. In the PCI1211, these bits report information about a single DMA channel; therefore, all four of these register bits indicate the TC status of the single socket being serviced by this register. All four bits are set when the TC is reached by the DMA channel. These bits are reset when read or the DMA channel is reset. DDMA request register Bit 7 6 5 4 3 2 1 0 Type W W W W W W W W Default 0 0 0 0 0 0 0 0 Name DDMA request Register: Type: Offset: Default: Size: Description: DDMA request Write-only DDMA base address + 09h 00h One byte This register is used to request a DDMA transfer through software. Any write to this register enables software requests, and this register is to be used in block mode only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 115 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 DDMA mode register Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R R 0 0 0 0 0 Name Type Default DDMA mode Register: Type: Offset: Default: Size: Description: DDMA mode Read-only, Read/Write (see individual bit descriptions) DDMA base address + 0Bh 00h One byte This register is used to set the DDMA transfer mode. See Table 64 for a complete description of the register contents. Table 64. DDMA Mode Register BIT 7–6 SIGNAL DMAMODE TYPE R/W 5 INCDEC R/W Address increment/decrement. The PCI1211 uses bit 5 to select the memory address in the current address/base address register to increment or decrement after each data transfer. This is in accordance with the 8237 use of this register bit, and is encoded as follows: 0 = Addresses increment (default). 1 = Addresses decrement. 4 AUTOINIT R/W Auto initialization 0 = Auto initialization disabled (default) 1 = Auto initialization enabled Transfer type. Bits 3–2 select the type of direct memory transfer to be performed. A memory write transfer moves data from the PCI1211 PC Card interface to memory, and a memory read transfer moves data from memory to the PCI1211 PC Card interface. The field is encoded as: 00 = No transfer selected (default) 01 = Write transfer 10 = Read transfer 11 = Reserved 3–2 XFERTYPE R/W 1–0 RSVD R 116 FUNCTION Mode select. The PCI1211 uses bits 7–6 to determine the transfer mode. 00 = Demand mode select (default) 01 = Single mode select 10 = Block mode select 11 = Reserved Reserved. Bits 1–0 return 0s when read. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 DDMA master clear register Bit 7 6 5 Type W W W W Default 0 0 0 0 Name 4 3 2 1 0 W W W W 0 0 0 0 DDMA master clear Register: Type: Offset: Default: Size: Description: DDMA master clear Write-only DDMA base address + 0Dh 00h One byte This register is used to reset the DMA controller and resets all DDMA registers. DDMA multichannel/mask register Bit 7 6 5 Type R R R R Default 0 0 0 0 Name 4 3 2 1 0 R R R R 0 0 0 0 DDMA multichannel/mask Register: Type: Offset: Default: Size: Description: DDMA multichannel/mask Read-only (see individual bit descriptions) DDMA base address + 0Fh 00h One byte The PCI1211 uses only the least-significant bit of this register to mask the PC Card DMA channel. The PCI1211 sets the mask bit when the PC Card is removed. Host software is responsible for either resetting the socket’s DMA controller or reenabling the mask bit. See Table 65 for a complete description of the register contents. Table 65. DDMA Multichannel/Mask Register BIT SIGNAL TYPE 7–1 RSVD R Reserved. Bits 7–1 return 0s when read. FUNCTION 0 MASKBIT R Mask select. Bit 0 masks incoming DREQ signals from the PC Card. When set, the socket ignores DMA requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced normally. 0 = DDMA service provided on card DREQ 1 = Socket DREQ signal ignored (default) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 117 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 absolute maximum ratings over operating temperature ranges (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Clamping voltage range, VCCCB, VCCI, VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VDD0 + 0.5 V MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCI + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VDD0 + 0.5 V MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCI + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. 2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. 118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 recommended operating conditions (see Note 3) OPERATION VCC Commercial Supply voltage (core) VCCP PCI I/O clamping voltage Commercial VCCCB PC Card I/O clamping voltage Commercial VCCI Miscellaneous I/O clamping voltage Commercial MIN NOM MAX 3.3 V 3 3.3 3.6 3.3 V 3 3.3 3.6 4.75 5 5.25 5V 3.3 V 5V 3.3 V 5V 3.3 V PCI VO¶ Output Out ut voltage tt Input transition time (tr and tf) TA TJ# Operating ambient temperature range 3.6 5 5.25 VCCCB MISC‡ 2 VCCI Fail safe§ 2 VCC 2.2 VCC 3.3 V 0 0.3VCCP 5V 0 0.8 3.3 V 0 0.325VCCCB 5V 0 0.8 MISC‡ 0 0.8 Fail safe§ 0 0.8 CD Pins* 0 0.75 PCI 0 VCCP PC Card 0 VCCCB MISC‡ 0 VCCI Fail safe§ 0 VCC PCI 0 VCC PC Card 0 VCC MISC‡ 0 VCC Fail safe§ 0 VCC PCI and PC Card 1 4 Miscellaneous, and fail safe 0 6 0 V V V V VCCP 2.4 PC Card Input In ut voltage 3.3 VCCP PCI VI 3 4.75 VCCCB 5V Low level input voltage Low-level 5.25 2 CD Pins* VIL† 3.6 5 0.475VCCCB 3.3 V PC Card High level input voltage High-level 3.3 0.5VCCP 5V VIH† 3 4.75 UNIT 25 70 V V V V ns °C °C † Applies to external inputs and bidirectional buffers without hysteresis ‡ Miscellaneous pins are 70, 62, 59, 60, 61, 64, 65, 67, 68, and 69 for the PGE packaged device and L11, M9, L8, K8, N9, K9, N10, L10, N11, and M11 for the GGU packaged device (SUSPEND, SPKROUT, RI_OUT, multifunction terminals (MFUNC0–MFUNC6), and power switch control pins). § Fail-safe pins are 75, 117, 131, and 137 for the PGE packaged device and L12, D9, C6, and A4 for the GGU packaged device (card detect and voltage sense pins). * CD Pins are 75 and 137. ¶ Applies to external output buffers # These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. Virtual junction temperature 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 115 119 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER PINS OPERATION PCI and Misc1§ VOH High-level output voltage (see Note 4) PC Card 3.3 V 5V Low level output voltage Low-level 2.4 0.9VCC IOH = –0.15 mA 2.4 IOH = –12 mA 2.1 IOH = –4 mA 2.1 5V IOL = 1.5 mA IOL = 6 mA V 0.1VCC 0.55 IOL = 0.7 mA 0.1VCC 5V IOL = 0.7 mA 0.55 Misc2¶ IOL = 12 mA 0.5 Misc3# 0.5 3.6 V IOL = 4 mA VI = VCC 5.25 V VI = VCC –1 3.6 V VI = VCC† VI = VCC† 10 PC Card 3-state output,, high-impedance g state output current (see Note 4) Output pins IOZH 3-state output,, high-impedance state g output current Output pins IIL Lo le el input Low-level inp t current c rrent (see Note 5) 5.25 V Input pins VI = GND VI = GND I/O pins Input pins High-level input current I/O pins Fail-safe pins –1 25 –1 –10 VI = VCC‡ VI = VCC‡ 10 10 5.25 V VI = VCC‡ VI = VCC‡ 3.6 V VI = VCC 10 3.6 V 5.25 V 3.6 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V µA µA µA A 20 25 VCCD pins$ 3.6 V VI = VCC 300 § Misc1 includes MFUNC6(69), MFUNC5(68), MFUNC4(67), MFUNC3(65), and MFUNC2(64). ¶ Misc2 includes MFUNC1(61), MFUNC0(60), and SERR(35). # Misc3 includes SPKROUT(62) and RI_OUT(59). † For PCI pins, VI = VCCP. For PC Card pins, VI = VCCCB. For miscellaneous pins, VI = VCCI ‡ For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. $ VCCD pins include VCCD0(73) and VCCD1(74). NOTES: 4. VOH and IOL are not tested on SERR(35, M1) and RI_OUT(59, L8) because they are open drain outputs. 5. IIL is not tested on VCCD0 (73, N13) and VCCD1(74, M13) because they are pulled down with an internal resistor. 120 UNIT 0.9VCC IOH = –0.15 mA 3.3 V MAX 3.3 V IOZL IIH IOH = –2 mA 5V Misc3# VOL IOH = –0.5 mA MIN 3.3 V Misc2¶ PCI and Misc1§ TEST CONDITIONS µA PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 24 and Figure 25) ALTERNATE SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT tc Cycle time, PCLK tcyc 30 ns twH Pulse duration, PCLK high thigh 11 ns twL Pulse duration, PCLK low tlow 11 ns ∆v/∆t Slew rate, PCLK tr, tf 1 tw Pulse duration, RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN 100 ms trst-clk 4 V/ns PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 6 and Figures 19 and 22) ALTERNATE SYMBOL PARAMETER tpd d g Propagation delayy time,, See Note 7 MIN PCLK-to-shared signal valid delay time tval PCLK-to-shared signal invalid delay time tinv 2 2 Enable time, high impedance-to-active delay time from PCLK ton tdis Disable time, active-to-high impedance delay time from PCLK toff Setup time before PCLK valid UNIT 11 tsu th Hold time after PCLK high MAX CL = 50 pF, pF See Note 7 ten tsu th TEST CONDITIONS ns ns 28 ns 7 ns 0 ns NOTES: 6. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 7. PCI shared signals are AD31–AD0, C/BE3–0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 121 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD† (pF) IOL (mA) IOH (mA) VLOAD (V) 50 8 –8 0 3 50 8 –8 1.5 50 8 –8 ‡ IOL From Output Under Test Test Point VLOAD CLOAD † CLOAD includes the typical load-circuit distributed capacitance IOH ‡ VLOAD – VOL = 50 Ω, where V OL = 0.6 V, IOL = 8 mA IOL LOAD CIRCUIT VCC Timing Input (see Note A) 50% VCC 0V 50% VCC 50% VCC 0V tf Low-Level Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES 50% VCC tpd 50% VCC VOH 50% VCC VOL tpd Waveform 1 (see Notes B and C) VOH 50% VCC VOL Waveform 2 (see Notes B and C) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 50% VCC 0V tPLZ tpd 50% VCC VCC 50% VCC 0V VCC tPZL 50% VCC tpd Out-of-Phase Output Output Control (low-level enabling) 0V In-Phase Output 50% VCC VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC VCC 50% VCC 0V tw VCC tr Input (see Note A) 50% VCC th tsu 90% VCC Data Input 10% VCC High-Level Input 50% VCC tPHZ tPZH 50% VCC VCC ≅ 50% VCC VOL + 0.3 V VOL VOH VOH – 0.3 V ≅ 50% VCC 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the following characteristics: PRR = 1 MHz, ZO = 50 Ω, tr = 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ, VOL and VOH are measured values. Figure 23. Load Circuit and Voltage Waveforms 122 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PCI BUS PARAMETER MEASUREMENT INFORMATION thigh tlow 2V 2 V MIN Peak-to-Peak 0.8 V tf tr tcyc Figure 24. PCLK Timing Waveform PCLK trst RSTIN tsrst-clk Figure 25. RSTIN Timing Waveforms PCLK 1.5 V tval PCI Output tinv 1.5 V Valid ton toff PCI Input Valid tsu th Figure 26. Shared Signals Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 123 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PC Card cycle timing The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. The PC Card address setup and hold times are a function of the wait-state bits. Table 66 shows address setup time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 67 and Table 68 show command active time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 69 shows address hold time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 66. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles TS1 – 0 = 01 (PCLK/ns) WAIT-STATE BITS I/O 3/90 Memory WS1 0 2/60 Memory WS1 1 4/120 Table 67. PC Card Command Active Cycle Time, tc(A), 8-Bit PCI Cycles WAIT-STATE BITS ZWS TS1 – 0 = 01 (PCLK/ns) 0 0 19/570 1 X 23/690 0 1 7/210 00 0 19/570 01 X 23/690 10 X 23/690 11 X 23/690 00 1 7/210 WS I/O Memory Table 68. PC Card Command Active Cycle Time, tc(A), 16-Bit PCI Cycles WAIT-STATE BITS WS I/O Memory 124 ZWS TS1 – 0 = 01 (PCLK/ns) 0 0 7/210 1 X 11/330 0 1 N/A 00 0 9/270 01 X 13/390 10 X 17/510 11 X 23/630 00 1 5/150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 Table 69. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles TS1 – 0 = 01 (PCLK/ns) WAIT-STATE BITS I/O 2/60 Memory WS1 0 2/60 Memory WS1 1 3/90 timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see Note 8 and Figure 27) ALTERNATE SYMBOL MIN MAX UNIT tsu tsu Setup time, CE1 and CE2 before WE/OE low T1 60 ns Setup time, CA25–CA0 before WE/OE low T2 ns tsu tpd Setup time, REG before WE/OE low T3 tsu(A)+2PCLK 90 Propagation delay time, WE/OE low to WAIT low T4 tw th Pulse duration, WE/OE low T5 Hold time, WE/OE low after WAIT high T6 th tsu Hold time, CE1 and CE2 after WE/OE high T7 Setup time (read), CDATA15–CDATA0 valid before OE high T8 th th Hold time (read), CDATA15–CDATA0 valid after OE high T9 0 ns Hold time, CA25–CA0 and REG after WE/OE high T10 ns tsu th Setup time (write), CDATA15–CDATA0 valid before WE low T11 th(A)+1PCLK 60 Hold time (write), CDATA15–CDATA0 valid after WE low T12 240 ns ns ns 200 ns ns 120 ns ns ns NOTE 8: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock. timing requirements over recommended ranges of supply voltage and operating free-air temperature, I/O cycles (see Figure 28) ALTERNATE SYMBOL MIN MAX UNIT tsu tsu Setup time, REG before IORD/IOWR low T13 Setup time, CE1 and CE2 before IORD/IOWR low tsu tpd Setup time, CA25–CA0 valid before IORD/IOWR low Propagation delay time, IOIS16 low after CA25–CA0 valid T16 tpd tw Propagation delay time, IORD low to WAIT low T17 35 ns Pulse duration, IORD/IOWR low T18 TcA ns th th Hold time, IORD low after WAIT high T19 Hold time, REG low after IORD high T20 th th Hold time, CE1 and CE2 after IORD/IOWR high Hold time, CA25–CA0 after IORD/IOWR high tsu th Setup time (read), CDATA15–CDATA0 valid before IORD high T23 Hold time (read), CDATA15–CDATA0 valid after IORD high tsu th Setup time (write), CDATA15–CDATA0 valid before IOWR low Hold time (write), CDATA15–CDATA0 valid after IOWR high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 60 ns T14 60 ns T15 tsu(A)+2PCLK ns 35 ns ns 0 ns T21 120 ns T22 th(A)+1PCLK 10 ns T24 0 ns T25 90 ns T26 90 ns ns 125 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see Figure 29) ALTERNATE SYMBOL PARAMETER BVD2 low to SPKROUT low tpd d BVD2 high to SPKROUT high Propagation delay time IREQ to IRQ15–IRQ3 30 30 30 PC Card PARAMETER MEASUREMENT INFORMATION CA25–CA0 T10 REG CE1, CE2 T1 WE, OE T5 T7 T3 T2 T6 T4 WAIT T12 T11 CDATA15–CDATA0 (write) T8 T9 CDATA15–CDATA0 (read) With no wait state With wait state Figure 27. PC Card Memory Cycle 126 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 30 T27 T28 STSCHG to IRQ15–IRQ3 MIN ns PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 PC Card PARAMETER MEASUREMENT INFORMATION CA25–CA0 T16 T22 IOIS16 REG T20 CE1, CE2 T14 IORD, IOWR T13 T15 T18 T21 T19 T17 WAIT T26 T25 CDATA15–CDATA0 (write) T23 T24 CDATA15–CDATA0 (read) With no wait state With wait state Figure 28. PC Card I/O Cycle BVD2 T27 SPKROUT IREQ T28 IRQ15–IRQ3 Figure 29. Miscellaneous PC Card Delay Times POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 127 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 MECHANICAL DATA PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 128 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI1211 GGU/PGE PC CARD CONTROLLERS SCPS033A – OCTOBER 1998 MECHANICAL DATA GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY 9,60 TYP 12,10 SQ 11,90 0,80 N M L K J H G F E D C B A 0,80 1 2 3 4 5 6 7 8 9 10 11 12 13 0,95 0,85 1,40 MAX Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,45 0,35 0,10 4073221/B 11/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Micro Star BGA configuration Micro Star is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 129 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated