SN54LV244A, SN74LV244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS383L − SEPTEMBER 1997 − REVISED APRIL 2005 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 20 2Y4 1A1 1OE VCC 1 2 19 2OE 3 18 1Y1 4 17 2A4 16 1Y2 5 SN54LV244A . . . FK PACKAGE (TOP VIEW) 1A2 2Y3 1A3 2Y2 1A4 15 2A3 14 1Y3 6 7 8 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 13 2A2 12 1Y4 9 10 11 1Y1 2A4 1Y2 2A3 1Y3 2Y1 GND 2A1 1Y4 2A2 2 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 VCC 20 2A1 1 Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN74LV244A . . . RGY PACKAGE (TOP VIEW) SN54LV244A . . . J OR W PACKAGE SN74LV244A . . . DB, DGV, DW, NS OR PW PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND D 1OE D D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports GND D D Ioff Supports Partial-Power-Down Mode 2OE D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP (Output Ground Bounce) description/ordering information These octal buffers/line drivers are designed for 2-V to 5.5-V VCC operation. ORDERING INFORMATION QFN − RGY SN74LV244ARGYR Tube of 25 SN74LV244ADW Reel of 2000 SN74LV244ADWR SOP − NS Reel of 2000 SN74LV244ANSR 74LV244A SSOP − DB Reel of 2000 SN74LV244ADBR LV244A Tube of 70 SN74LV244APW Reel of 2000 SN74LV244APWR Reel of 250 SN74LV244APWT TVSOP − DGV Reel of 2000 SN74LV244ADGVR LV244A CDIP − J Tube of 20 SNJ54LV244AJ SNJ54LV244AJ CFP − W Tube of 85 SNJ54LV244AW SNJ54LV244AW LCCC − FK Tube of 55 SNJ54LV244AFK SNJ54LV244AFK TSSOP − PW −55°C to 125°C † TOP-SIDE MARKING Reel of 1000 SOIC − DW −40°C 40 C to 85°C 85 C ORDERABLE PART NUMBER PACKAGE† TA LV244A LV244A LV244A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2005, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV244A, SN74LV244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS383L − SEPTEMBER 1997 − REVISED APRIL 2005 description/ordering information (continued) The ’LV244A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 POST OFFICE BOX 655303 19 11 9 13 7 15 5 17 3 • DALLAS, TEXAS 75265 2Y1 2Y2 2Y3 2Y4 SN54LV244A, SN74LV244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS383L − SEPTEMBER 1997 − REVISED APRIL 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W (see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV244A, SN74LV244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS383L − SEPTEMBER 1997 − REVISED APRIL 2005 recommended operating conditions (see Note 5) SN54LV244A VCC Supply voltage VCC = 2 V VIH High level input voltage High-level MIN MAX 2 5.5 1.5 Low level input voltage Low-level VI Input voltage VO Output voltage VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 Δt/Δv Input transition rise or fall rate 0.5 TA 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 5.5 High or low state 0 VCC 0 VCC 3-state 0 5.5 0 5.5 −50 −50 VCC = 2.3 V to 2.7 V −2 −2 VCC = 3 V to 3.6 V −8 −8 −16 −16 50 50 VCC = 2.3 V to 2.7 V 2 2 VCC = 3 V to 3.6 V 8 8 VCC = 4.5 V to 5.5 V 16 16 VCC = 2.3 V to 2.7 V 200 200 VCC = 3 V to 3.6 V 100 100 20 20 Operating free-air temperature −55 125 V VCC × 0.3 0 VCC = 4.5 V to 5.5 V V V VCC = 2.3 V to 2.7 V VCC = 2 V Low level output current Low-level 5.5 VCC × 0.7 VCC = 4.5 V to 5.5 V IOL 2 UNIT 1.5 VCC × 0.7 VCC = 2 V High level output current High-level MAX VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V IOH MIN VCC = 2.3 V to 2.7 V VCC = 2 V VIL SN74LV244A −40 85 V V μA mA μA mA ns/V °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV244A, SN74LV244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS383L − SEPTEMBER 1997 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV244A PARAMETER VOH TEST CONDITIONS MIN SN74LV244A TYP MAX MIN IOH = −50 μA 2 V to 5.5 V IOH = −2 mA 2.3 V 2 2 IOH = −8 mA 3V 2.48 2.48 4.5 V 3.8 IOH = −16 mA VOL VCC VCC−0.1 TYP MAX VCC−0.1 V 3.8 IOL = 50 μA 2 V to 5.5 V 0.1 0.1 IOL = 2 mA 2.3 V 0.4 0.4 IOL = 8 mA 3V 0.44 0.44 4.5 V 0.55 0.55 IOL = 16 mA UNIT V II VI = 5.5 V or GND 0 to 5.5 V ±1 ±1 μA IOZ VO = VCC or GND 5.5 V ±5 ±5 μA ICC VI = VCC or GND, 5.5 V 20 20 μA Ioff VI or VO = 0 to 5.5 V 5 μA Ci VI = VCC or GND IO = 0 0 5 3.3 V 2.3 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y tpd PARAMETER LOAD CAPACITANCE 2.3 free-air TA = 25°C MIN CL = 15 pF p pF temperature SN54LV244A range, SN74LV244A TYP MAX MIN MAX MIN MAX 7.5* 12.5* 1* 15* 1 15 8.9* 14.6* 1* 17* 1 17 9.1* 14.1* 1* 16* 1 16 A Y 9.5 15.3 1 18 1 18 ten OE Y 10.8 17.8 1 21 1 21 tdis OE 13.4 19.2 1 21 1 21 CL = 50 pF Y tsk(o) 2 UNIT ns ns 2 * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y tpd A Y ten OE Y tdis OE PARAMETER Y LOAD CAPACITANCE free-air TA = 25°C MIN CL = 15 pF p CL = 50 pF temperature SN54LV244A SN74LV244A TYP MAX MIN MAX MIN MAX 5.4* 8.4* 1* 10* 1 10 6.3* 10.6* 1* 12.5* 1 12.5 7.6* 11.7* 1* 13* 1 13 6.8 11.9 1 13.5 1 13.5 7.8 14.1 1 16 1 16 11 16 1 18 1 18 tsk(o) 1.5 range, UNIT ns ns 1.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV244A, SN74LV244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS383L − SEPTEMBER 1997 − REVISED APRIL 2005 switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A Y ten OE Y tdis OE Y tpd A Y ten OE Y tdis OE Y PARAMETER LOAD CAPACITANCE free-air TA = 25°C MIN CL = 15 pF p CL = 50 pF temperature SN54LV244A range, SN74LV244A TYP MAX MIN MAX MIN MAX 3.9* 5.5* 1* 6.5* 1 6.5 4.5* 7.3* 1* 8.5* 1 8.5 6.5* 12.2* 1* 13.5* 1 13.5 4.9 7.5 1 8.5 1 8.5 5.6 9.3 1 10.5 1 10.5 8.8 14.2 1 15.5 1 15.5 tsk(o) 1 UNIT ns ns 1 * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6) SN74LV244A PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.55 V VOL(V) Quiet output, minimum dynamic VOL −0.5 V VOH(V) Quiet output, minimum dynamic VOH 2.9 V VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage 2.31 V 0.99 V TYP UNIT NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz VCC 3.3 V 14 5V 16 pF SN54LV244A, SN74LV244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS383L − SEPTEMBER 1997 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC 50% VCC Input 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH tPHL VOH In-Phase Output 50% VCC tPHL Out-of-Phase Output 0V 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 14-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV244ADBLE OBSOLETE SSOP DB 20 SN74LV244ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APWLE OBSOLETE TSSOP PW 20 TBD Call TI SN74LV244APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APWRG3 PREVIEW TSSOP PW 20 2000 SN74LV244APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV244APWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD Addendum-Page 1 TBD Lead/Ball Finish Call TI Call TI MSL Peak Temp (3) Call TI Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 14-May-2010 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV244ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LV244ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LV244A : • Enhanced Product: SN74LV244A-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.0 Q1 SN74LV244ADBR SSOP DB 20 2000 330.0 16.4 SN74LV244ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV244ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LV244ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74LV244APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LV244APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LV244ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 Pack Materials-Page 1 8.2 B0 (mm) PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV244ADBR SSOP DB 20 2000 346.0 346.0 33.0 SN74LV244ADGVR TVSOP DGV 20 2000 346.0 346.0 29.0 SN74LV244ADWR SOIC DW 20 2000 346.0 346.0 41.0 SN74LV244ANSR SO NS 20 2000 346.0 346.0 41.0 SN74LV244APWR TSSOP PW 20 2000 346.0 346.0 33.0 SN74LV244APWT TSSOP PW 20 250 346.0 346.0 33.0 SN74LV244ARGYR VQFN RGY 20 3000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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