EMA6DXV5T1, EMA6DXV5T5 Preferred Devices Dual Common Emitter Bias Resistor Transistor PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network http://onsemi.com This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. The device is housed in the SOT−553 package which is designed for low power surface mount applications. • • • • • • • Simplifies Circuit Design Reduces Board Space Reduces Component Count Moisture Sensitivity Level: 1 ESD Rating − Human Body Model: Class 1 − Machine Model: Class B Available in 7 Inch Tape and Reel Lead−Free Solder Plating PNP SILICON BIAS RESISTOR TRANSISTOR EMA6 / UMA6N (3) R1 (4) (5) / (6) 5 Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc IC 100 mAdc Collector Current 1 SOT−553 CASE 463B MARKING DIAGRAM 5 THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Total Device Dissipation TA = 25°C Derate above 25°C PD 230 (Note 1) 338 (Note 2) 1.8 (Note 1) 2.7 (Note 2) mW Thermal Resistance − Junction-to-Ambient RJA 540 (Note 1) 370 (Note 2) °C/W Thermal Resistance − Junction-to-Lead RJL 264 (Note 1) 287 (Note 2) °C/W TJ, Tstg −55 to +150 °C Junction and Storage Temperature Range UD M 1 °C/W UD= Specific Device Code M = Date Code ORDERING INFORMATION Device Package Shipping EMA6DXV5T1 SOT−553 4 mm pitch 4000/Tape & Reel EMA6DXV5T5 SOT−553 2 mm pitch 8000/Tape & Reel DEVICE MARKING AND RESISTOR VALUES Device Marking R1 (K) R2 (K) EMA6DXV5T1 UD 47 ∞ Preferred devices are recommended choices for future use and best overall value. 1. FR−4 @ Minimum Pad 2. FR−4 @ 1.0 x 1.0 inch Pad Semiconductor Components Industries, LLC, 2003 September, 2003 − Rev. 0 (1) R2 MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating (2) 1 Publication Order Number: EMA6DXV5T1/D EMA6DXV5T1, EMA6DXV5T5 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Min Typ Max Unit Collector−Base Cutoff Current (VCB = 50 V, IE = 0) ICBO − − 100 nAdc Collector−Emitter Cutoff Current (VCE = 50 V, IB = 0) ICEO − − 500 nAdc Emitter−Base Cutoff Current (VEB = 6.0 V, IC = 0) IEBO − − 0.2 mAdc Collector−Base Breakdown Voltage (IC = 10 A, IE = 0) V(BR)CBO 50 − − Vdc Collector−Emitter Breakdown Voltage (Note 3) (IC = 2.0 mA, IB = 0) V(BR)CEO 50 − − Vdc hFE 160 350 − VCE(sat) − − 0.25 Vdc Output Voltage (on) (VCC = 5.0 V, VB = 3.5 V, RL = 1.0 k) VOL − − 0.2 Vdc Output Voltage (off) (VCC = 5.0 V, VB = 0.25 V, RL = 1.0 k) VOH 4.9 − − Vdc R1 32.9 47 61.1 k Characteristic OFF CHARACTERISTICS ON CHARACTERISTICS (Note 3) DC Current Gain (VCE = 10 V, IC = 5.0 mA) Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 1.0 mA) Input Resistor 3. Pulse Test: Pulse Width < 300 s, Duty Cycle < 2.0% PD, POWER DISSIPATION (mW) 350 300 250 200 150 RJA= 370°C/W 100 50 0 −50 0 50 100 TA, AMBIENT TEMPERATURE (5°C) Figure 1. Derating Curve http://onsemi.com 2 150 EMA6DXV5T1, EMA6DXV5T5 INFORMATION FOR USING THE SOT−553 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.3 0.0118 0.45 0.0177 1.0 0.0394 1.35 0.0531 0.5 0.5 0.0197 0.0197 mm inches SOT−553 SOT−553 POWER DISSIPATION SOLDERING PRECAUTIONS The power dissipation of the SOT−553 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT−553 package, PD can be calculated as follows: PD = The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. TJ(max) − TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 150 milliwatts. PD = 150°C − 25°C 833°C/W = 150 milliwatts The 833°C/W for the SOT−553 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT−553 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 3 EMA6DXV5T1, EMA6DXV5T5 PACKAGE DIMENSIONS SOT−553 XV5 SUFFIX 5−LEAD PACKAGE CASE 463B−01 ISSUE O A −X− 5 C K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4 1 2 B −Y− 3 D G S J 5 PL 0.08 (0.003) M X Y DIM A B C D G J K S MILLIMETERS MIN MAX 1.50 1.70 1.10 1.30 0.50 0.60 0.17 0.27 0.50 BSC 0.08 0.18 0.10 0.30 1.50 1.70 INCHES MIN MAX 0.059 0.067 0.043 0.051 0.020 0.024 0.007 0.011 0.020 BSC 0.003 0.007 0.004 0.012 0.059 0.067 Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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