ONSEMI MAC8SDG

MAC8SD, MAC8SM, MAC8SN
Preferred Device
Sensitive Gate Triacs
Silicon Bidirectional Thyristors
Designed for industrial and consumer applications for full wave
control of ac loads such as appliance controls, heater controls, motor
controls, and other power switching applications.
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Features
TRIACS
8 AMPERES RMS
400 thru 800 VOLTS
• Sensitive Gate Allows Triggering by Microcontrollers and other
•
•
•
•
•
•
•
•
•
Logic Circuits
Uniform Gate Trigger Currents in Three Quadrants; Q1, Q2, and Q3
High Immunity to dv/dt − 25 V/ms Minimum at 110°C
High Commutating di/dt − 8.0 A/ms Minimum at 110°C
Maximum Values of IGT, VGT and IH Specified for Ease of Design
On-State Current Rating of 8 Amperes RMS at 70°C
High Surge Current Capability − 70 Amperes
Blocking Voltage to 800 Volts
Rugged, Economical TO−220AB Package
Pb−Free Packages are Available*
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
VDRM,
VRRM
Value
Unit
On-State RMS Current
(Full Cycle Sine Wave, 60 Hz, TC = 70°C)
IT(RMS)
8.0
A
ITSM
70
A
PGM
16
W
PG(AV)
0.35
W
Operating Junction Temperature Range
TJ
−40 to +110
°C
Storage Temperature Range
Tstg
−40 to +150
°C
Average Gate Power
(t = 8.3 ms, TC = 70°C)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 5
2
TO−220AB
CASE 221A−09
STYLE 4
3
x
A
Y
WW
G
A2sec
Peak Gate Power
(Pulse Width ≤ 1.0 ms, TC = 70°C)
MAC8SxG
AYWW
400
600
800
20
(t = 8.3 ms)
MARKING
DIAGRAM
V
I2t
Circuit Fusing Consideration
MT1
G
1
Peak Repetitive Off−State Voltage (Note 1)
(TJ = −40 to 110°C,
Sine Wave, 50 to 60 Hz, Gate Open)
MAC8SD
MAC8SM
MAC8SN
Peak Non-Repetitive Surge Current
(One Full Cycle Sine Wave, 60 Hz,
TJ = 110°C)
MT2
1
= D, M, or N
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN ASSIGNMENT
1
Main Terminal 1
2
Main Terminal 2
3
Gate
4
Main Terminal 2
ORDERING INFORMATION
Device
Package
Shipping
MAC8SD
TO−220AB
50 Units / Rail
MAC8SDG
TO−220AB
(Pb−Free)
50 Units / Rail
MAC8SM
TO−220AB
50 Units / Rail
MAC8SMG
TO−220AB
(Pb−Free)
50 Units / Rail
MAC8SN
TO−220AB
50 Units / Rail
MAC8SNG
TO−220AB
(Pb−Free)
50 Units / Rail
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MAC8S/D
MAC8SD, MAC8SM, MAC8SN
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance,
Junction−to−Case
Junction−to−Ambient
Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds
Symbol
Value
Unit
RqJC
RqJA
2.2
62.5
°C/W
TL
260
°C
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic
Symbol
Min
Typ
Max
Unit
−
−
−
−
0.01
2.0
−
−
1.85
−
−
−
2.0
3.0
3.0
5.0
5.0
5.0
−
3.0
10
−
−
−
5.0
10
5.0
15
20
15
0.45
0.45
0.45
0.62
0.60
0.65
1.5
1.5
1.5
di/dt(c)
8.0
10
−
A/ms
dv/dt
25
75
−
V/ms
OFF CHARACTERISTICS
Peak Repetitive Blocking Current
(VD = Rated VDRM, VRRM; Gate Open)
TJ = 25°C
TJ = 110°C
IDRM,
IRRM
mA
ON CHARACTERISTICS
Peak On-State Voltage (Note ) (ITM = 11A)
VTM
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 W)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
IGT
Holding Current (VD = 12V, Gate Open, Initiating Current = 150mA)
IH
Latching Current (VD = 24V, IG = 5mA)
MT2(+), G(+)
MT2(−), G(−)
MT2(+), G(−)
IL
mA
mA
mA
VGT
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100W)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)
V
V
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current
VD = 400 V, ITM = 3.5 A, Commutating dv/dt = 10 V m/sec,
Gate Open, TJ = 110°C, f = 500 Hz, Snubber: CS = 0.01 mF,
RS =15 W, See Figure 16.)
Critical Rate of Rise of Off-State Voltage
(VD = Rate VDRM, Exponential Waveform, RGK = 510 W, TJ = 110°C)
2. Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%.
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2
MAC8SD, MAC8SM, MAC8SN
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Symbol
Parameter
VTM
VDRM
Peak Repetitive Forward Off State Voltage
IDRM
Peak Forward Blocking Current
VRRM
Peak Repetitive Reverse Off State Voltage
IRRM
Peak Reverse Blocking Current
VTM
Maximum On State Voltage
IH
Holding Current
on state
IH
IRRM at VRRM
off state
IH
Quadrant 3
MainTerminal 2 −
VTM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
Quadrant II
(+) MT2
(−) IGT
GATE
Quadrant I
(+) IGT
GATE
MT1
MT1
REF
REF
IGT −
+ IGT
(−) MT2
Quadrant III
Quadrant 1
MainTerminal 2 +
(−) MT2
Quadrant IV
(+) IGT
GATE
(−) IGT
GATE
MT1
MT1
REF
REF
−
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in−phase signals (using standard AC lines) quadrants I and III are used.
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3
+ Voltage
IDRM at VDRM
I T, INSTANTANOUS ON-STATE CURRENT (AMPS)
100
a = 30 and 60°
90
a
a
80
a = CONDUCTION ANGLE
90°
180°
70
60
DC
0
2
4
6
8
10
IT(RMS), RMS ON−STATE CURRENT (AMPS)
12
25
a
120°
a = CONDUCTION ANGLE
15
10
a = 30°
5
0
0
Typical @ TJ = 25°C
Maximum @
TJ = 110°C
10
1
Maximum @
TJ = 25°C
1
2
12
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VT, INSTANTANEOUS ON−STATE VOLTAGE (VOLTS)
6
1
ZqJC(t) = RqJC(t) r(t)
0.1
0.01
0.1
1
Figure 3. On−State Characteristics
10
100
t, TIME (ms)
1@10 4
1000
Figure 4. Transient Thermal Response
10
25
I L , LATCHING CURRENT (mA)
I H , HOLDING CURRENT (mA)
4
6
8
10
IT(RMS), RMS ON−STATE CURRENT (AMPS)
Figure 2. Maximum On−State Power Dissipation
100
0.5
90°
60°
Figure 1. RMS Current Derating
0.1
DC
180°
a
20
R(t) , TRANSIENT THERMAL RESISTANCE (NORMALIZED)
T C , MAXIMUM ALLOWABLE CASE TEMPERATURE (°C)
110
P(AV), AVERAGE POWER DISSIPATION (WATTS)
MAC8SD, MAC8SM, MAC8SN
8
6
MT2 NEGATIVE
4
MT2 POSITIVE
2
20
15
Q3
10
5
Q1
0
−40 −25
−10
5
20
35
50
65
80
TJ, JUNCTION TEMPERATURE (°C)
95
0
110
−40 −25
−10
5
20
35
50
65
TJ, JUNCTION TEMPERATURE (°C)
80
95
Figure 6. Typical Latching Current Versus
Junction Temperature
Figure 5. Typical Holding Current Versus
Junction Temperature
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4
110
MAC8SD, MAC8SM, MAC8SN
1
V GT, GATE TRIGGER VOLTAGE (VOLTS)
IGT, GATE TRIGGER CURRENT (mA)
14
12
10
8
Q3
6
Q2
4
2
Q1
0
−40 −25
−10
5
20
35
50
65
TJ, JUNCTION TEMPERATURE (°C)
80
95
Q1
0.9
Q3
0.8
0.7
Q3
0.6
0.5
Q2
0.4
Q1
0.3
−40 −25
110
−10
5
20
35
50
65
TJ, JUNCTION TEMPERATURE (°C)
110
130
200
RG − MT1 = 510 W
TJ = 110°C
180
120
VPK = 400 V
160
140
STATIC dv/dt (V/mS)
STATIC dv/dt (V/mS)
95
Figure 8. Typical Gate Trigger Voltage Versus
Junction Temperature
Figure 7. Typical Gate Trigger Current Versus
Junction Temperature
600 V
800 V
120
TJ = 100°C
110
110°C
100
100
90
120°C
80
60
100
80
200
300
400
500
600
700
800
RGK, GATE−MT1 RESISTANCE (OHMS)
900
400
1000
450
500
550
600
650
VPK, Peak Voltage (Volts)
700
750
800
Figure 10. Typical Exponential Static dv/dt Versus
Peak Voltage, MT2(+)
Figure 9. Typical Exponential Static dv/dt Versus
Gate−MT1 Resistance, MT2(+)
350
130
120
300
110
STATIC dv/dt (V/mS)
VPK = 400 V
STATIC dv/dt (V/mS)
80
600 V
800 V
100
90
TJ = 100°C
250
110°C
200
RG − MT1 = 510 W
RG − MT1 = 510 W
150
80
70
100
105
TJ, Junction Temperature (°C)
100
110
400
450
500
550
600
650
VPK, Peak Voltage (Volts)
700
750
800
Figure 12. Typical Exponential Static dv/dt Versus
Peak Voltage, MT2(−)
Figure 11. Typical Exponential Static dv/dt Versus
Junction Temperature, MT2(+)
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MAC8SD, MAC8SM, MAC8SN
350
300
VPK = 400 V
300
VPK = 400 V
STATIC dv/dt (V/mS)
600 V
250
200
800 V
150
RG − MT1 = 510 W
600 V
200
800 V
150
100
TJ = 110°C
50
100
100
105
TJ, Junction Temperature (°C)
110
Figure 13. Typical Exponential Static dv/dt Versus
Junction Temperature, MT2(−)
(dv/dt)c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/m s)
100
200
300
400
500
600
700
800
RGK, GATE−MT1 RESISTANCE (OHMS)
900
100
VPK = 400 V
90°C
10
100°C
f=
1
2 tw
tw
(di/dt)c =
VDRM
6f ITM
1000
110°C
1
1
5
10
15
20
25
30
(di/dt)c, CRITICAL RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 15. Critical Rate of Rise of
Commutating Voltage
LL
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
CHARGE
1N4007
MEASURE
I
TRIGGER
CHARGE
CONTROL
NON-POLAR
CL
1000
Figure 14. Typical Exponential Static dv/dt Versus
Gate−MT1 Resistance, MT2(−)
TRIGGER CONTROL
STATIC dv/dt (V/mS)
250
RS
−
CS
MT2
1N914 51 W
ADJUST FOR +
di/dt(c)
200 V
MT1
G
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 16. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
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6
MAC8SD, MAC8SM, MAC8SN
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−09
ISSUE AA
−T−
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−− 0.080
STYLE 4:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MAC8S/D