MC44605 High Safety, Latched Mode, GreenLinet PWM Controller for (Multi) Synchronized Applications The MC44605 is a high performance current mode controller that is specifically designed for off−line converters. This circuit has several distinguishing features that make it particularly suitable for multisynchronized monitor applications. The MC44605 synchronization arrangement enables operation from 16 kHz up to 130 kHz. This product was optimized to operate with universal mains voltage, i.e., from 80 V to 280 V, and its high current totem pole output makes it ideally suited for driving a power MOSFET. The MC44605 protections enable a well−controlled and safe power management. Four major faults while detected, activate the analogic counter of a disabling block designed to perform a latched circuit output inhibition. http://onsemi.com MARKING DIAGRAM 16 PDIP−16 P SUFFIX CASE 648 MC44605P AWLYYWWG 1 1 A WL YY WW G Features • Pb−Free Package is Available* = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Current Mode Controller • • • • • • • • • • • Current Mode Operation up to 250 kHz Output Switching Frequency Inherent Feed Forward Compensation Latching PWM for Cycle−by−Cycle Current Limiting Oscillator with Precise Frequency Control Externally Programmable Reference Current Secondary or Primary Sensing (Availability of Error Amplifier Output) Synchronization Facility High Current Totem Pole Output Vcc Undervoltage Lockout with Hysteresis Low Output dV/dT for Low EMI Radiations Low Startup and Operating Current Safety/Protection Features • • • • • • • Soft−Start Feature Demagnetization (Zero Current Detection) Protection Overvoltage Protection Facility against Open Loop EHT Overvoltage Protection (E.H.T.OVP): Detection of too High Synchronization Pulses Winding Short Circuit Detection (W.S.C.D.) Limitation of the Maximum Input Power (M.P.L.): Calculation of Input Power for Overload Protection Overheating Detection (O.H.D.): to Prevent the Power Switch from an Excessive Heating PIN CONNECTIONS VCC 1 16 Rref VC 2 15 WSCD* Program Output 3 14 Voltage Feedback Input GND 4 13 Error Amp Output Max Power Limitation 5 12 Disabling Block (Cext) Overheating Detection Current Sense Input 6 11 Soft−Start Input 7 10 Osc Capacitor (CT) Demagnetization Detection Input 8 9 Sync and EHTOVP Input (Top View) *Winding Short Circuit Detection ORDERING INFORMATION Device Package Shipping MC44605P PDIP−16 25 Units/Rail MC44605PG PDIP−16 (Pb−Free) 25 Units/Rail Latched Disabling Mode • When one of the following faults is detected: EHT overvoltage, • Winding Short Circuit (WSCD), a too high input power (M.P.L.), power switch overheating (O.H.D.), an analogic counter is activated If the counter is activated for a time that is long enough, the circuit gets definitively disabled. The latch can only be reset by making decrease the Vcc down to about 3.0 V, i.e., practically by unplugging or turning off the SMPS. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 5 1 Publication Order Number: MC44605/D MC44605 Block Diagram R ref V CC 16 1 i ref V ref Demagnetization Detection Input 8 Demagnetization Management C T 10 Synchronization and EHTOVP 9 Input 2 VC W.S.C.D* Comparator − V ref V shift Level Programmation Vcs dis MPL UVLO2 V CC enable 15 dis OHD Disout Error AMP V CC Over Voltage Management V WSCD Sf dis MPL I sense Voltage Feedback 14 Input + 4 Gnd Thermal Shutdown V shift Disabling Block V ref Current Sense 3 Output Buffer Set Q PWM Latch Reset Vcs I sense C ext 12 Disout VS Sf E.H.T.OVP Block 18 V UVLO1 UVLO2 I ref Oscillator V CC Supply Initialization Block Reference Block V DT Output V cc enable V demag out I ref dis OHD V cs 2 MPL block O.H.D. block 5 6 Soft−Start UVLO1 V CC enable E/A Output 13 7 11 Current Maximum Over Soft−Start Heating Sense Input Power Limitation Detection Input *W.S.C.D. = Winding Short Circuit Detection http://onsemi.com 2 MC44605 WSCD Programmation MC44605 MAXIMUM RATINGS Rating Pin # Symbol Value Unit (ICC + IZ) 40 mA VC VCC 18 V IO(Source) IO(Sink) −750 750 W 5.0 J Soft−Start VSS −0.3 to 2.2 V V Current Sense, Voltage Feedback, E/A Output, CT, Rref, MPL, OHD, Cext, WSCD Vin −0.3 to 5.5 V Total Power Supply and Zener Current Output Supply Voltage with Respect to Ground 2 1 Output Current Source Sink 3 mA Output Energy (Capacitive Load per Cycle) E.H.T.OVP, Sync Input Current V mA Source 9 6 Isync (Source) IEHT (Source) −4.0 Sink 9 6 Isync (Sink) IEHT (Sink) 10 Idemag−ib (Source) Idemag−ib (Sink) −4.0 10 IE/A (Sink) 20 mA PD RJA 0.6 100 W °C/W Operating Junction Temperature TJ 150 °C Operating Ambient Temperature TA −25 to +85 °C Demagnetization Detection Input Current Source Sink 8 Error Amplifier Output Sink Current 13 mA Power Dissipation and Thermal Characteristics Maximum Power Dissipation at TA = 85°C Thermal Resistance, Junction−to−Air Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V, Rref = 10 k, CT = 2.2 nF, for typical values TA = 25°C, for min/max values TA = −25° to +85°C unless otherwise noted.) (Note 1) Characteristic Pin # Symbol Min Typ Max VOL − − − − 1.0 1.4 1.5 2.0 1.2 2.0 2.0 2.7 − − − − 0.1 0.1 1.0 1.0 1.0 Unit OUTPUT SECTION (Note 2) Output Voltage (Note 3) Low Level Drop Voltage High Level Drop Voltage 3 (ISink = 100 mA) (ISink = 500 mA) (ISource = 200 mA) (ISource = 500 mA) V VOH Output Voltage During Initialization Phase VCC − 0 to 1.0 V, ISink = 10 A VCC − 1.0 to 5.0 V, ISink = 100 A VCC − 5.0 to 13 V, ISink = 1.0 A 3 VOL V Output Voltage Rising Edge Slew−Rate (CL = 1.0 nF, TJ = 25°C) dVo/dT − 300 − V/s Output Voltage Falling Edge Slew−Rate (CL = 1.0 nF, TJ = 25°C) dVo/dT − −300 − V/s 1. Adjust VCC above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 2. No output signal when the Error Amplifier output is in Low State, i.e., when for instance, VFB = 2.7 V. 3. VC must be greater than 5.0 V. http://onsemi.com 3 MC44605 ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V, Rref = 10 k, CT = 2.2 nF, for typical values TA = 25°C, for min/max values TA = −25° to +85°C unless otherwise noted.) (Note 4) Characteristic Pin # Symbol Min Typ Max Unit Voltage Feedback Input (VE/A out = 2.5 V) 14 VFB 2.4 2.5 2.6 V Input Bias Current (VFB = 2.5 V) 14 IFB−ib −2.0 −0.6 − A AVOL 65 70 − ERROR AMPLIFIER SECTION Open Loop Voltage Gain (VE/A out = 2.0 V to 4.0 V) Unity Gain Bandwidth TJ = 25°C TA = −25° to +85°C BW Voltage Feedback Input Line Regulation (VCC = 10 V to 15 V) VFBline−reg Output Current Sink (VE/A out = 1.5 V, VFB = 2.7 V) TA = −25° to +85°C Source (VE/A out = 5.0 V, VFB = 2.3 V) TA = −25° to +85°C 13 Output Voltage Swing High State (IE/A out (source) = 0.5 mA, VFB = 2.3 V) Low State (IE/A out (sink) = 0.33 mA, VFB = 2.7 V) 13 dB MHz − − − − − 5.5 −10 − 10 mV mA ISink 2.0 12 − −2.0 − −0.2 VOH VOL 5.5 − 6.5 1.0 7.5 1.1 ISource V CURRENT SENSE SECTION Maximum Current Sense Input Threshold (VFeedback (pin14) = 2.3 V and VSoft−Start (pin11) = 1.2 V) 7 Vcs−th 0.96 1.0 1.04 V Input Bias Current 7 Ics−ib −10 −2.0 − A tPLH(In/Out) − 120 200 ns FOSC 16 − 20 kHz Frequency Change with Voltage (VCC = 10 V to 15 V) FOSC/V − 0.05 − %/V Frequency Change with Temperature (TA = −25° to +85°C) FOSC/T − 0.05 − %/°C Ratio Charge Current/Reference Current (TA = −25° to +85°C) Icharge/Iref 0.39 − 0.48 − D 72 75 78 % Vsyncth −250 −200 −150 mV NEG−SYNC −0.65 −0.5 −0.34 V Propagation Delay (Current Sense Input to Output at VTH of MOS transistor = 3.0 V) OSCILLATOR AND SYNCHRONIZATION SECTION Frequency (TA = −25° to +85°C) Free Mode Oscillator Ratio = Idischarge/(Idischarge + Icharge) Synchronization Input Threshold Voltage 9 Negative Clamp Level (Isyncth−in = 2.0 mA) UNDERVOLTAGE LOCKOUT SECTION Startup Threshold 1 Vstup−th 13.6 14.5 15.4 V Disable Voltage After Threshold Turn−On (UVLO 1) (TA = −25° to +85°C) 1 Vdisable1 8.3 − 9.6 V Disable Voltage After Threshold Turn−On (UVLO 2) (TA = −25° to +85°C) 1 Vdisable2 7.0 7.5 8.0 V 4. Adjust VCC above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. http://onsemi.com 4 MC44605 ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V, Rref = 10 k, CT = 2.2 nF, for typical values TA = 25°C, for min/max values TA = −25° to +85°C unless otherwise noted.) (Note 5) Characteristic Pin # Symbol Min Typ Max Unit Reference Output Voltage (VCC = 10 V to 15 V) 16 Vref 2.4 2.5 2.6 V Reference Current Range (Iref = Vref/Rref, R = 5.0 k to 25 k) 16 Iref −500 − −100 A Vref −40 − 40 mV Vdemag−th tPLH(In/Out) Idemag−lb 50 − −0.5 65 0.5 − 80 − − mV s A Minimum Off−Time when the pin 8 is grounded TDEM−GND 1.5 3.0 4.5 s Negative Clamp Level (Idemag = −2.0 mA) CLVL−neg −0.50 −0.38 −0.25 V Positive Clamp Level (Idemag = +2.0 mA) CLVL−pos 0.50 0.72 0.85 V Ratio Charge Current/Iref (TA = −25° to +85°C) Iss−ch/Iref 0.37 − 0.43 − Discharge Current (Vsoft−start = 1.0 V) Idischarge 1.5 5.0 − mA Clamp Level VSS−CLVL 2.2 2.4 2.6 V VSSinhi 30 − 150 mV VCSsoft−start 0.45 0.5 0.55 V REFERENCE SECTION Reference Voltage Over Iref Range DEMAGNETIZATION DETECTION SECTION (Note 6) Demagnetization Detect Input Demagnetization Comparator Threshold (Vpin9 Decreasing) Propagation Delay (Input to Output, Low to High) Input Bias Current (Vdemag = 65 mV) 8 SOFT−START SECTION (Note 7) Circuit Inhibition Threshold (Note 8) VCS Soft−Start Clamp Level (Rsoft−start = 5 k) OVERVOLTAGE SECTION Propagation Delay (VCC > 18.1 V to Vout Low) TPHL(In/Out) 1.0 − 4.0 s Protection Level on VCC (TA = −25° to +85°C) VCC prot 15.9 − 18.1 V NEG−SYN C −0.65 −0.5 −0.35 V Vref 7.0 7.4 7.8 V IEHTOVP −5.0 − 0 A Vshift 70 100 120 mV ΓMPL 0.185 0.240 0.295 V−1 VMPL−th 2.4 2.5 2.6 V ΓOHD 1.15 1.50 1.85 V−1 VOHD−th 2.4 2.5 2.6 V EHT OVP SECTION (Note 9) Negative Clamp Level (Isynch−in = −2.0 mA) EHT OVP Input Threshold EHT OVP Input Bias Current (VEHT OVP(pin 9) = 0 V) 9 WINDING SHORT CIRCUIT DETECTION SECTION WSCD Threshold with Ipin15 = 200 A MPL & OHD SECTION MPL Parameter (Note 10) MPL Comparator Threshold (Note 11) OHD Parameter (Note 12) OHD Comparator Threshold (Note 13) 5. Adjust VCC above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 6. This function can be inhibited by connecting pin 8 to GND. In this case, there is a minimum off−time equal to TDEM−GND. 7. The MC44605 can be shut down by connecting soft−start pin (pin 11) to GND. 8. The circuit is shutdown if the soft−start pin voltage is lower than this level. 9. This function can be inhibited by connecting pin 9 to GND. In this case, the synchronization block is inhibited too and the MC44605 works in free mode. 10. This parameter is defined in the MPL §. This parameter is obtained by measuring the MPL pin average current and dividing this result by the corresponding squared VCS, the measured frequency value and the CT value deducted from the measured frequency value. Measurement conditions: VFeedback(pin 14) = 2.3 V, Vsoft−start(pin 11) = 0.5 V and pins 7, 8, and 9 connected to GND (the working frequency is typically equal to 18 kHz − Rref = 10 k "1%, CT = 2.2 nF). 11. The MPL comparator output is DisMPL. 12. This parameter is defined in the OHD §. This parameter is obtained by measuring the OHD pin average current and dividing this result by the corresponding squared VCS value and multiplying it by the Rref value. Measurement conditions: VFeedback(pin 14) = 2.3 V, Vsoft−start(pin 11) = 0.5 V and pins 7, 8, and 9 connected to GND (the working frequency is typically equal to 18 kHz − Rref = 10 k "1%, CT = 2.2 nF). 13. The OHD comparator output is DisOHD. http://onsemi.com 5 MC44605 ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V, Rref = 10 k, CT = 2.2 nF, for typical values TA = 25°C, for min/max values TA = −25° to +85°C unless otherwise noted.) (Note 14) Characteristic Pin # Symbol Min Typ Max Unit DISABLING BLOCK SECTION TWSCD − 4.0 − s Ratio (EHTOVP and WSCD Disabling Capacitor Charge Current)Iref IDis−H/Iref 90 100 110 % Ratio (MPL and OHD Disabling Capacitor Charge Current)Iref IDis−L/Iref 2.7 3.1 3.5 % VCCDis 1.0 − 5.0 V Delay Pulse Width Minimum VCC Value Enabling the Disabling Block Latch (Note 15) TOTAL DEVICE Power Supply Current ICC mA Startup−Up (VCC = 5.0 V with VCC increasing) − 0.35 0.55 Startup−Up (VCC = 9.0 V with VCC increasing) − 0.35 0.55 Startup−Up (VCC = 12 V with VCC increasing) − 0.35 0.55 Operating TA = −25°C to +85°C (Note 16) − 20 25 Disabling Mode (VCC = 6.0 V) (Note 17) Power Supply Zener Voltage (ICC = 35 mA) Thermal Shutdown − − 0.55 VZ 18.5 − − V − − 155 − °C 14. Adjust VCC above the startup threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 15. Once a fault detection activated it, the Disabling Block Latch gets reset when the VCC becomes lower than this threshold. 16. Refer to Note 14. 17. This consumption is measured while the circuit is inhibited by the Definitive Latch. http://onsemi.com 6 MC44605 Pin Name Pin Description 1 VCC This pin is the positive supply of the IC. 2 VC The output high state, VOH, is set by the voltage applied to this pin. With a separate connection to the power source, it gives the possibility to set by means of an external resistor the output source current at a different value than the sink current. 3 Output 4 GND The ground pin is a single return typically connected back to the power source. It is used as control and power ground. 5 Maximum Power Limitation This block enables to estimate the input power. When this calculated power is detected as too high, a fault information is sent to the disabling block in order to definitively disable the circuit. 6 Over−Heating Detection 7 Current Sense Input A voltage proportional to the current flowing into the power switch is connected to this input. The PWM latch uses this information to terminate the conduction of the output buffer. A maximum level of 1 V allows to limit the inductor current. 8 Demagnetization Detection A voltage delivered by an auxiliary transformer winding provides to the demagnetization pin an indication of the magnetization state of the flyback energy reservoir. A zero voltage detection corresponds to a complete core demagnetization. The demagnetization detection prevents the oscillator from a re−start and so the circuit from a new conduction phase, if the fly−back is not in a dead−time state. This function can be inhibited by connecting Pin 8 to GND but in this case, there is a minimum off−time typically equal to 3 s. 9 Synchronization and E.H.T.OVP Input Activating the synchronization input pin with a pulse higher or equal to the negative threshold (typically −200 mV) allows the next switching period to be reinitialized. The oscillator is free when connecting Pin 9 to GND. When the E.H.T.OVP pin receives a voltage that is greater than 7.5 V, the disabling block Cext capacitor is charged so that the circuit gets definitively disabled if the Cext voltage becomes higher than Vref. This block is incorporated to detect and disable the device when the synchronization pulses are too high. 10 Oscillator Capacitor CT The free mode oscillator frequency is programmed by the capacitor CT choice together with the Rref resistance value. CT, connected between pin 10 and GND, generates the oscillator sawtooth. 11 Soft−Start A capacitor connected to this pin can temporary reduce the maximum inductor peak current. By this way, a soft−start can be performed. By connecting pin 11 to Ground, the MC44605 is shutdown. 12 Cext (Disabling Block) When a too high synchronization pulse voltage (E.H.T.OVP) or a winding short circuit (WSCD) is detected, the capacitor Cext is charged using a current source IDis− H. In the case of a MPL or OHD fault detection, Cext is charged using IDis−L. If the Cext capacitor voltage gets higher than Vref, the circuit is definitively disabled. Then, to re−start, the converter must be switched off in order to make VCC decrease down to about 0 V. 13 E/A Output 14 Voltage Feedback This is the inverting input of the Error Amplifier. It can be connected to the Switching Mode Power Supply output through an optical (or else) feedback loop or to the subdivided VCC voltage in case of primary sensing technic. 15 Winding Short Circuit Detection Programmation The W.S.C.D. block is incorporated to detect the transformer Winding Short Circuits. This function is performed by detecting the inductor overcurrents thanks to a comparator which threshold is programmable to be well adapted to any application. 16 Rref The output current capability is suited for driving a power MOSFET. This block estimates the MOSFET heating. When this calculated heating is too high, the device gets definitively disabled (disabling block action). The error amplifier output is made available for loop compensation. The Rref value fixes the internal reference current that is particularly used to perform the precise oscillator waveform. The current range goes from 100 A up to 500 A. http://onsemi.com 7 MC44605 Summary of the Main Design Equations The following table consists of equations enabling to dimension a multisynchronized SMPS operating in discontinuous mode. Poutmax is the maximum power the load may draw in normal working. Pin max + ƪ Lp max + Ǹ2·Vac 2 min Ǹ 2 L ƫ NVo 2 min Pin max )NVo fsync max Lp Vac fsync max min Ipk max2 Rds on The inductor value Lp must be chosen lower than Lpmax or ideally equal to this value (to optimize the application design−in). In effect, if Lp was higher than Lpmax, a synchronized and discontinuous working could not be guaranteed (in some cases, the demagnetization phase would not be finished while a new conduction phase should start to follow the synchronization). Ipkmax is the maximum inductor peak current. This current is obtained when the power to transfer is maximum at the minimum synchronization frequency (60 W output, 30 kHz in the proposed application). Pin max fsync min ǸPinmax Pon max + 1 3 The maximum input power Pinmax is easily deducted by dividing Poutmax by the efficiency (η). In this kind of application, the efficiency is generally taken equal to 80%. η Ǹ2·Vac Ipk max + d max + Poutmax d max dmax is the maximum duty cycle. The duty cycle is maximum at the lowest input voltage when the power demand is maximum while the synchronization frequency also is maximum. Ponmax is the maximum MOSFET on−time losses that are proportional to Ipkmax, dmax and Rdson (on−time MOSFET resistor). This conduction losses estimation enables to dimension the power MOSFET. (V ) max + ǒǸ2 DS (V ) max + D ǒ Vac maxǓ ) (N Ǹ2 Vout) Ǔ Vac max ) Vout N (VDS)max is the maximum voltage the power switch must be able to face. In fact, this calculation does not take into account the turnings off spikes. So, it is necessary to take a margin of at least about 50 V. (VD)max is the maximum voltage the high voltage secondary diode must be able to face. Because of the turning off spikes, a margin must also be taken. (AL) and (ni) are the magnetic parameters. (ni) max + N A + L (N n L Vout P n )2 Vout Ipk max (ni)max must not exceed the ferrite (ni). Otherwise, the transformer may get saturated when the peak current is high. (AL) is the ferrite constant that links the primary inductor value to the squared number of primary turns: Lp = AL x np2. + Error Amplifier 1.0 mA Compensation A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage gain of 70 dB. The non inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current with the inverting input at 2.5 V is −2.0 A. This can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. RFB Rf Error Amplifier 13 14 2.5 V Cf 2R R Voltage Feedback Input 1.0 V Current Sense Comparator GND 4 MC44605 From Power Supply Output R1 R2 Figure 1. Error Amplifier Compensation http://onsemi.com 8 MC44605 The Error Amp Output (Pin 13) is provided for external loop compensation. The output voltage is offset by two diodes drops ([1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Source Output (Pin 3) when Pin 13 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft−start interval. The Error Amp minimum feedback resistance is limited by the amplifier’s minimum source current (0.2 mA) and the required output voltage (VOH) to reach the current sense comparator’s 1.0 V clamp level: R1(min) + (3 V I pk I +1V R S As depicted in Figure 3, an undervoltage lockout has been incorporated to guarantee that the IC is fully functional before allowing the system working. In effect, the VCC is connected to the non inverting input of a comparator that has an upper threshold equal to 14.5 V (typical Vstup−th) and a lower one equal to 7.5 V (typical Vdisable 2). This hysteresis comparator enables or disables the reference block that generates the voltage and current sources required by the system. This block particularly, produces Vref (pin 16 voltage) and Iref that is determined by the resistor Rref connected between pin 16 and the ground: The MC44605 operates as a current mode controller. The circuit uses a current sense comparator to compare the inductor current to the threshold level established by the Error Amplifier output (Pin 13). When the current reaches the threshold, the current sense comparator terminates the output switch conduction that has been initiated by the oscillator, by resetting the PWM Latch. Thus the error signal controls the peak inductor current on a cycle−by−cycle basis. This configuration ensures that only one single pulse appears at the Source Output during the appropriate oscillator cycle. I ref + V R ref where V + 2.5 V (typically) ref ref VCC (Pin 1) Vin Rref Pin 16 Vref enable VC CSTARTUP 14 1 0 R2 Q1 Vdemag out 3 1 S R3 Q Thermal Protection pk(max) Undervoltage Lockout Section Current Sense Comparator and PWM Latch VS * 1.4 V (pin13) 3 R S The Current Sense Comparator threshold is internally clamped to 1.0 V. Therefore the maximum peak switch current is: 1 V) ) 1.4 V + 22 kΩ 0.2 mA UVLO Disout [ R STARTUP 14.5 V CUVLO1 PWM Latch Substrate Current Sense Comparator 0 Vdisable 7.5 V Current Sense 7 C Vdisable1 9.0 V R Reference Block: Voltage and Current Sources Generator (Vref, Iref, ...) UVLO1 (to SOFT−START) MC44605 RS Figure 3. VCC Management Figure 2. Output Totem Pole In addition to this, VCC is compared to a second threshold level that is nearly equal to 9.0 V (Vdisable1) so that a signal UVLO1 is generated to reset the soft−start block and so, to disable the output stage (refer to the Soft−Start §) as soon as VCC becomes lower than Vdisable 1. In this way, the circuit is reset and made ready for a next startup, before the reference block is disabled (refer to Figure 3). Thus, finally the upper limit for the minimum normal operating voltage The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the power switch Q1. This voltage is monitored by the Current Sense Input (Pin 7) and compared to a level derived from the Error Amp output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 13 where: http://onsemi.com 9 MC44605 is 9.4 V (maximum value of Vdisable 1) and so the minimum hysteresis is 4.2 V. [(Vstup−th)min = 13.6 V]. The large hysteresis and the low startup current of the MC44605 make it ideally suited for off−line converter applications where efficient bootstrap startup techniques are required. The MC44605 oscillator achieves four functions: — it fixes the free mode frequency — it takes into account the synchronization signal — it does not allow a new power switch conduction if the flyback is not in a dead−time state when the circuit works in demagnetization mode (pin 8 connected) — it builds the Sf pulse required by the MPL block During the operating mode, the oscillator sawtooth can vary between a valley value (1.6 V typically) and a peak one (3.6 V typically) and presents three distinct phases: — the CT charge — the CT discharge — the phase during which the oscillator voltage is maintained equal to its valley value. This happens at the end of a discharge cycle when the synchronization or demagnetization condition does not allow a new CT charge phase. During this sequence, IREGUL compensates the charge current Icharge. The oscillator has two working modes: — a free one when there is no synchronization — a synchronized one. In the free working, the oscillator grows up from its valley value to its peak one for the charge phase and when once the peak value is reached, a discharge sequence makes the CT voltage decrease down to its valley value. When the decrease phase is finished, a new charge cycle occurs if the demagnetization condition is achieved (VDT high). Otherwise there is a REGUL phase until VDT gets high. In the synchronized mode, the charge cycle is only allowed when the synchronization signal gets high while a dead time has been detected (VDT high). This charge phase is stopped when the synchronization signal has got low and when the oscillator voltage is higher than Vint, the intermediary voltage level used to generate the calibrated pulse Sf by comparing the CT voltage to this threshold. So, when these two conditions are performed, a discharge sequence is set until the oscillator voltage is equal to its valley value. Then, the CT voltage is maintained constant thanks to the “REGUL” arrangement until the next synchronization pulse. In both cases, during the charge phase, a signal VS is generated. When Sf becomes high. VS gets high and remains in this state until the PWN latch is set of Sf is low. Then, VS keeps low until the next Sf high level. This oscillator behavior is obtained using the process described in Figure 5b. Soft−Start Control Section The Vcs value is clamped down to the pin 11 voltage. So, if a capacitor is connected to this pin, its voltage increases slowly at the startup (the capacitor is charged by an internal current source 0.4 Iref). So, Vcs is limited during the startup and then a soft−start is performed. This pin can be used to inhibit the circuit by applying a voltage that is lower than VSSinhi (refer to page 4). Particularly, the MC44605 can be shutdown by connecting the soft−start pin to ground. As soon as Vdis1 is detected (that is Vcc lower than Vdisable1), a signal UVLO1 is generated until the Vcc falls down to Vdis2 (refer to the undervoltage lockout section §). During the delay between the disable1 and the disable2, using a transistor controlled by UVLO1, the pin 11 voltage is made equal to zero in order to make the soft−start arrangement ready to work for the next re−start. Vref Vcs 0.4 Iref Pin 11 Soft Start Capacitor DZ Output Inhibition 2.4 V UVLO1 VSSlnhi MC44605 Figure 4. Soft−Start Oscillator Section (Figures 5 & 5b) The oscillator and synchronization represented in Figure 5b. behavior is http://onsemi.com 10 MC44605 a − Free mode Inductor current V DT Oscillator Vint Sf Output b − Synchronized mode Synchro input Inductor current V DT Oscillator Vint Sf Output Figure 5b. Oscillator Behavior http://onsemi.com 11 MC44605 In effect, the output of the latch L1 is: — high during the oscillator capacitor charge and during the REGUL phase — low for the oscillator capacitor discharge Now, the latch L2 is set when the L1 output is high and the synchronization condition is performed (that is: sync = 1 − free mode or synchro signal high state) and during the dead−time (VDT high). So, this latch is set for the CT charge. On the other hand, this latch is reset by the signal used to reset L1. Consequently, it is reset at the end of the charge phase. So, in any case, QL2 is: — high during the CT charge cycle — low in the other cases Thus, this latch enables to obtain a signal that is high for the charge phase and low in the other cases, whatever the mode (synchronized or free) and whatever the synchronization pulses width (higher than the delay necessary for the oscillator to reach its intermediary value or lower than this delay) in the synchronized mode. That is why: — the discharge current source must be connected to the oscillator capacitor when QL1 is low. The condition (CT voltage higher than the valley value) is added to stop the discharge phase as soon as the oscillator voltage is detected as lower than the valley value (without any delay due to the L1 latch propagation time). — the REGUL current source must be connected when: • QL1 is high (charge or REGUL phase) • QL2 is low (the oscillator is not in a charge phase) On the other hand, the oscillator charge is stopped when: — the oscillator voltage reaches the peak value in the free mode — the oscillator voltage is higher than the intermediary value (Vint) and the synchronization signal is negative, in the synchronized mode. Consequently, in any case, QL2 that is high during the oscillator charge phase, is high for the delay during which the oscillator voltage grows from the valley value up to the intermediary one. That is why the signal Sf (refer to the MPL block) that must be high when the oscillator voltage is between the valley value and the intermediary one during the charge phase (QL2 high), is obtained using an AND gate with the following inputs: — QL2 (QL2 high <=> charge phase) — COSCINT (COSCINT high <=> the CT voltage is lower than the intermediary value). So, using the output of this AND gate, Sf is obtained. This signal Sf is connected to a logic block consisting of two AND gates and an OR one. This block aims at supplying a signal VS that: — gets high as soon as Sf becomes high if the PWM latch output is low — gets low as soon as the PWM latch is set and then remains low until the next cycle. Vref Icharge COSCINT Vint & sync DISCH PWM Latch Output COSC HIGH 3.6 V & Sf COSCINT PWM VS Latch Set & & COSC LOW QL2 1.6 V VDT (from demag CT<1.6 V block) sync SQ & SQ 10 CT L1 DISCH R DISCH L2 Q R COSC REGUL 1 0 0 & 1 QL2 Iregul MC44605 Idischarge Figure 5. Oscillator Synchronization Section (Note 1) The synchronization block consists of a protection arrangement similar to the demagnetization block one (a diode + a negative active clamping system (Note 2)). In addition to this, a high value resistor (R − about 50 k) is incorporated as the pin 9 input is also used by the EHTOVP section. The signal obtained at the output of this protection arrangement, is compared to a negative threshold (−200 mV, typically) so that when the synchronization pulse applied to the pin 9 (through a resistor or a resistors divider to adapt this input to the EHTOVP function), is higher than this threshold, the system considers that the synchronization condition is performed (free mode or synchronization signal high level). Note 1. The synchronization can be inhibited by connecting the pin 9 to the ground. By this means, a free mode is obtained. Note 2. This negative active clamping system works even if the circuit is off. This feature is really useful as synchronization pulses may be applied while the product is off. http://onsemi.com 12 MC44605 VCC Synchro. Signal A diode D is incorporated to clamp the positive applied voltages while an active clamping system limit the negative voltages to typically −0.33 V. This negative clamp level is high enough to avoid the substrate diode switching on. A latch system is incorporated to keep the demagnetization block output level low as soon as a voltage lower than 65 mV is detected and as long as a new restart is produced (high level on the output (refer to Figure 8). This process avoids that any ringing on the signal used on the pin 8, disrupts the demagnetization detection (refer to Figure 7). Finally, this method results in a very accurate demagnetization phase detection, and the signal VDT drawn from this block is high only for the dead time. Therefore, an oscillator re−start and so, a new power switch conduction is only allowed during the dead−time. For a higher safety, the Vdemagout output of the demagnetization block is also directly connected to the output, to disable it during the demagnetization phase (refer to the block diagram). The demagnetization detection can be inhibited by connecting pin 8 to the ground but in this case, a timer (about 3 s) that is incorporated to set the latch when it can not be set by Vdemagout, results in a minimum off−time (refer to Figure 8). E.H.T. OVP Block Negative Active Clamping System Pin 9 sync R −200 mV MC44605 Figure 6. Synchronization Demagnetization Section This block is incorporated to detect the complete core demagnetization in order to prevent the power MOSFET from switching on if the converter is not in a dead time phase. That is why this block inhibits any oscillator re−start as long as the inductor current is not finished (from the beginning of the on−time to the end of the demagnetization phase). In a fly−back, a good means to detect the demagnetization phase consists in using the VCC winding voltage. In effect, this voltage is: — negative during the on−time, — positive during the off−time, — equal to zero for the dead−time with generally a ringing (refer to Figure 7). Output Buffer 3 s Zero Current Detection R Q Demag Q S Negative Active Clamping System Vdemag out 0.75 V VCC Vpin 8 Pin 8 65 mV C DEM 65 mV Oscillator D VDT −0.33 V Figure 8. Demagnetization Block On−Time Off−Time Dead−Time Overvoltage Protection Section Figure 7. Demagnetization Detection The overvoltage arrangement compares a portion Vcc to Vref (2.5 V) (refer to Figure 9). In fact, this threshold corresponds to a VCC equal to to 17 V. When the Vcc is higher than this level, the output is latched off until a new circuit re−start. That is why, the MC44605 demagnetization detection consists of a comparator that compares the VCC winding voltage to a reference that is typically equal to 65 mV. http://onsemi.com 13 MC44605 Vref For instance, if this threshold value is required to be equal to 30 V, Vpin9 must be equal to 7.5 V when the synchronization pulse value is 30 V. So, in this case: VCC In Delay τ 5.0 s T 0 30 Out 2.5 V r2 + 7.5 r1 ) r2 Then, the ratio (r1/r2) can be deducted: Enable In COVLO VOVP out τ Out Delay r1 + 3 r2 So, as r1 and r2 must be negligible in relation to R (about 50 k), the couple of resistors can be chosen as follows: 2.0 s 2.5 V (Vref) (If VOVP out = 1.0, the Output is Disabled) r1 + 3 kΩ and: Figure 9. Overvoltage Protection r2 + 1 kΩ A delay (2 s) is incorporated in order to avoid any activation due to interferences by only taking into account the overvoltages that last at least 2 s. The VCC is connected when once the circuit has started−up in order to limit the circuit startup consumption (T is switched on when once Vref has been generated). The overvoltage section is enabled 5 s after the regulator has started to allow the reference Vref to stabilize. Winding Short Circuit Detection Section (WSCD) The MC44605 being designed to control a Fly−Back SMPS, this block is incorporated to detect a short circuit on a transformer winding or on an output diode (refer to Figure 11). + E.H.T. Overvoltage Protection Section AC Line + Lp This block uses the synchronization input as this section is incorporated to detect too high synchronization pulses and then to activate the device definitive latch in this case. r1 Lleak MC44605 VCC Synchro. Pulses Negative Active Clamping System RS Synchronization Block Figure 11. Winding Short Circuit Fault Disabling Block Pin 9 2R r2 4V + CEHTOVP In the case of a Winding Short Circuit, the primary inductor Lp is short circuited and then the current increase is only controlled by the leakage inductor Lleak. In current mode, the power switch conduction is stopped when the inductor current is detected as high enough, by the controller. In fact, when the current sense resistor (Rs) voltage gets equal to Vcs, the current sense comparator switches to reset the output. Now, the circuit has a propagation delay and the power switch needs some time to turn off. Consequently, there is a delay t between the moment at which the Rs voltage gets equal to Vcs and the actual current increase stop. So, this results in an overcurrent (refer to Figure 12). E.H.T. OVP R Vref MC44605 Figure 10. E.H.T. OVP This block consists of a high impedance resistors bridge (R is nearly equal to 50 k − refer to Figure 10) so that the EHTovp threshold is 7.5 V. So, using an external resistors bridge (r1, r2 <<R), the synchronization pulse level above which the working must be considered as wrong, can be adjusted. http://onsemi.com 14 MC44605 (Vin x t/Lleak (VCS + Vshift)/RS Power Switch Current Finally, when there is a winding short circuit, an overcurrent is detected by the WSCD comparator. The output of this comparator, VWSCD, is connected to the disabling block (refer to the disabling block §). Vin x t/Lp VCS/RS Maximum Power Limitation Section (MPL) The MPL block is designed to calculate this input power using the following equation: Pin + 1 2 t Figure 12. Overcurrent in a WSCD Case δt P where: Vin is the input voltage (rectified a.c. line) While in a WSCD case: (Ipk) WSCD + Vin δt L Leak V Consequently, as the leakage inductor value is generally much lower than the primary one (less than 5% generally), the overcurrent is much higher in the WSCD case. That is why this fault can be detected by detecting the high overcurrents. So, the WSCD block consists of comparing the sensed current to a reference equal to: (Vcs + Vshift), where Vshift is a voltage proportional to the current injected in the pin 15 (refer to Figure 13). Isense CWSCD VWSCD k MPL (Sf) + k1 (Sf) T Vcs 2 MPL R C ref T where: k1 is a constant On the other hand, kMPL that is depending on the reference current source Iref, is proportional to 1/Rref: k R Disabling Block +R Now, as Sf is built comparing the oscillator to a constant level, (Sf) is proportional to Rref and CT: MPL + k2 1 R ref where: k2 is a constant Pin 15 3.75 Vshift MPL where: kMPL is the multiplier gain (Sf) is the width of the calibrated pulse T is the switching (oscillator) period Vin Pin 7 f As Vcs is proportional to the inductor peak current (Vcs = Rs x Ipk), the squared Ipk value is estimated by building a current source proportional to Vcs2. This current is chopped by a calibrated pulse Sf, generated at each new oscillator cycle (refer to Figure 14). Finally, using an external resistor and capacitor network (RMPL, CMPL) on the MPL pin, a voltage VMPL, proportional to the input power can be obtained. In effect, Now, in normal working, this overcurrent Ipk is equal to: Ipk + Vin L Ipk 2 P where: Lp is the inductor value Ipk is the inductor peak current f is the switching frequency time t L So: Vshift shift = 500 V Ishift MPL +R MPL k1 Vcs 2 k2 f C T where: CT is the oscillator capacitor Vcs Finally: MC44605 V Figure 13. WSCD MPL +R MPL Γ MPL Vcs 2 f C T where: ΓMPL is the MPL parameter as defined in the specification. This is a constant equal to the product (k1 x k2). Now, as the overcurrent level depends on the input voltage Vin, it is preferable to use a Vshift proportional to this input voltage instead of a constant Vshift. So, the WSCD pin must be connected to Vin through a resistor that fixes Vshift by adjusting the current injected in this pin 15. Now, as: Pin + 1 2 http://onsemi.com 15 L P Ipk 2 f MC44605 and: Vcs + R As in the MPL section, the squared Ipk term is estimated by building a current source proportional to Vcs2. The duty cycle is taken into account thanks to the action on this current source of a “chopper” controlled by the circuit output. By this means, the pin 6 average current is proportional to the squared peak current multiplied to the duty cycle (refer to Figure 14). So, using an external resistor and capacitor network (ROHD, COHD) on this pin, a voltage VOHD, proportional to the conduction losses can be obtained. Like in the MPL block, this voltage VOHD, is compared to 2.5 V. If VOHD gets higher than this threshold, the disabling block is activated by DisOHD (output of the comparator). The external resistor ROHD choice enables to obtain a calculated VOHD equal to 2.5 V when the conduction losses are equal to their maximum value. In effect, Ipk S So: V MPL + 2 R Γ MPL C MPL L P R 2 S T Pin A comparator is used to compare VMPL to Vref, the output of which, DisMPL, is connected to the “definitive inhibition latch” of the disabling block. So, when the calculated power is higher than the threshold, the circuit is definitively disabled (the system considers that there is an overload condition). Finally, replacing VMPL by 2.5 V (the threshold value), the RMPL value to be used, can be deducted: R MPL + 1.25 Γ C MPL T L P R 2 (Pin) max S V Vcs OHD +R k OHD Vcs 2 OHD d where: kOHD is the multiplier gain Now, as kOHD that is depending on the reference current source Iref, is proportional to 1/Rref: x k kOHDVcs2 kMPLVcs2 TOHD TMPL OHD 1 R ref + k2 where: k2 is a constant Output So: Sf DisOHD R MPL C MPL VMPL C OHD R OHD V Disabling Block DisMPL R OHD R ref Vcs 2 d V Ipk OHD + 3 R OHD R ref Γ R OHD dson R 2 S p on So, by choosing the value of ROHD, the heating corresponding to Vref is determined. If the MOSFET dissipation is such that the heating is higher than this threshold, the “definitive inhibition latch” of the Disabling Block is activated and so, the output gets definitively disabled. Overheating Detection Section (O.H.D.) In the MPL block, the converter input power is calculated. In the O.H.D. block, that is the power MOSFET heating which is calculated, using the following equation: Ipk 2 S So, replacing Vcs and using the pon equation: Figure 14. OHD and MPL dson Γ OHD Vcs + R R d Now, as: MC44605 p on + 1 3 OHD + Vcs 2 R ref k2 OHD where: ΓOHD is the OHD parameter as defined in the specification. This is a constant equal to k2. VMPL 2.5 V +R Finally: V 2.5 V OHD d where: pon are the power switch on−time losses Rdson is the conduction MOSFET resistor d is the duty cycle http://onsemi.com 16 MC44605 Consequently, by replacing VOHD by 2.5 V (threshold value) in the last equation, the value ROHD to use, can be deducted: R OHD + 2.5 3 Γ R ref R 2 OHD S R Vref Vref 104% Iref 3.4% Iref dson (p on) max 1 where: (pon)max are the maximum on time losses that are 0 DisOHD 1 0 E.H.T.OVP Q S DisMPL Pin 12 VWSCD R Disabling Block Section This section consists of a “definitive inhibition latch” (directly supplied by the Vcc) that disables the output (the output is forced to zero). In effect, this block aims at definitively disabling the circuit when one of the following faults is detected: — a Winding Short Circuit — too high synchronization pulses — a too high input power — a too high power switch (MOSFET) heating The signals corresponding to these faults are high when a fault is detected (for instance, when the input power is detected as too high, DisMPL is high). When one (or several) of these four faults is detected, a current source charges Cext (with a certain duty cycle) and when its voltage becomes higher than Vref, the definitive inhibition latch is activated. Thus, the circuit gets definitively disabled after a delay depending on Cext. According to the detected fault, the current that charges Cext is not the same: The typical values are: — 260 A for EHTOVP and WSCD — 8.5 A for OHD and MPL when Rref is equal to 10 k. VCC R ext C ext acceptable. Delay 4S Definitive Inhibition Latch 2.5 V Output Buffer MC44605 Figure 15. Disabling Block This latch is reset when the Vcc falls down to about 3.0 V. In this case, if a new startup is performed, the circuit will work normally (until this fault or another one is detected). Practically, to re−start after a fault has shutdown the circuit, the converter must be turned off for a time long enough to enable the Vcc capacitor discharge (repair time...). Note: As VWSCD is generally a really narrow pulse, it is necessary to add a latch and a delay to build a 4 s width pulse when VWSCD becomes high. http://onsemi.com 17 MC44605 Application Schematic 90 Vac to 264 Vac 1nF / 1KV RFI Filter R1 1 / 5W 4.7 M C4....C7 1nF/500V Vin D1 ... D4 1N4007 160 V/0.1 A 100 F 400 V MR856 47 K 1.8 M 100 F 2x150 K// 47 nF 1N4934 47 k/2W SYNC 100 F 25 V 3.3 k 1.2 k 9 8 10 7 11 6 70 V/0.2 A 1N4937 1N4937 100 F 1F 120 pF 27 K Laux 2.2 nF 470 k 12 1N4148 13 1 nF 14 22 k MC44605P 10 nF 40 V/0.5 A 1nF 1 F 1N4937 105 k 4.7 F 5 4 22 k 16 1 10 k Lp 470 F 470 pF MTA4N60E 39 2 4.7 F 340 K 3 15 100 k 1N4937 1 k 100 220 nF 1305 V/0.65 A 1N4934 1000 F 10 k 470 330 1 k 100 k 8 V/0.5 A 0.22 1N4934 1000 F 2.2 k 270 226 k MOC8103 10 k Vin 1N4733 100 nF 2.2 k 6.8 nF 33 nF TL431 3.6 k 65 W output SMPS controlled by the MC44605 Mains input range: 90 Vac <−> 264 Vac Synchronization range: 30 kHz <−> 100 kHz Orega Transformer ref. G5984−00 (Lp = 195 H) http://onsemi.com 18 MC44605 Performances Input Voltage 90−260 Vac Synchronization Range 30 to 100 kHz 160 V 100 mA 70 V 200 mA 40 V 500 mA 13.5 V 650 mA 8.0 V 500 mA Outputs 30 kHz Measured Efficiency (Pout = 64 W) 60 kHz 100 kHz Standby Losses (No Load − Pout = 0) 83% 110 Vac 81% 220 Vac 82% 110 Vac 80% 220 Vac 80% 110 Vac 2.0 W 3.2 W 28 V 30 kHz 60 kHz 100 kHz Overheating Detection (Pout = 64 W): The input rms levels at which the circuit detects an OHD case. Winding Short Circuit Detection 80% 220 Vac 220 Vac EHTovp Threshold Maximum Power Limitation 110 Vac (Input) 110 Vac (Input) 86 W (Input) 220 Vac 87 W 110 Vac 90 W 220 Vac 95 W 110 Vac 94 W 220 Vac 110 W 30 kHz 85 V 60 kHz 76 V 100 kHz 76 V Fully Functional (Tested by short circuiting one output diode or one transformer winding) http://onsemi.com 19 MC44605 PACKAGE DIMENSIONS PDIP−16 CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L S −T− SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 GreenLine is a trademark of Motorola, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 20 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC44605/D