MC34023, MC33023 High Speed Single−Ended PWM Controller The MC34023 series are high speed, fixed frequency, single−ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off−Line and DC−to−DC converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, a wide bandwidth error amplifier, a high speed current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, and a latch for single pulse metering. The flexibility of this series allows it to be easily configured for either current mode or voltage mode control. http://onsemi.com PDIP−16 P SUFFIX CASE 648 16 1 SOIC−16W DW SUFFIX CASE 751G 16 Features • • • • • • • • • • • • • • 1 50 ns Propagation Delay to Output High Current Totem Pole Output Wide Bandwidth Error Amplifier Fully−Latched Logic with Double Pulse Suppression Latching PWM for Cycle−By−Cycle Current Limiting Soft−Start Control with Latched Overcurrent Reset Input Undervoltage Lockout with Hysteresis Low Startup Current (500 mA Typ) Internally Trimmed Reference with Undervoltage Lockout 90% Maximum Duty Cycle (Externally Adjustable) Precision Trimmed Oscillator Voltage or Current Mode Operation to 1.0 MHz Functionally Similar to the UC3823 Pb−Free Packages are Available* Vref Clock RT CT 16 5 6 16 16 MC34023P AWLYYWWG 1 A WL YY WW G = = = = = Assembly Location Wafer Lot Year Work Week Pb−Free Package PIN CONNECTIONS VCC UVLO Error Amp Inverting Input 1 Error Amp 2 Noninverting Input Error Amp Output 3 16 Vref 15 VCC 14 Output Clock 4 Oscillator 13 VC 12 Power Ground RT 5 13 7 Ramp Error Amp 3 Output Noninverting Input 2 8 VC 14 Error Amp Latching PWM 12 11 Current Limit Reference 10 Ground CT 6 Output Ramp 7 Power Ground Soft−Start 8 9 Current Limit/ Shutdown (Top View) Inverting Input 1 Soft−Start MC33023DW AWLYYWWG 1 15 5.1V Reference 4 MARKING DIAGRAMS 11 Current 9 Limit Ref Current Limit/ Shutdown Soft−Start 10 Ground This device contains 176 active transistors. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Figure 1. Simplified Application © Semiconductor Components Industries, LLC, 2005 October, 2005 − Rev. 6 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 1 Publication Order Number: MC34023/D MC34023, MC33023 ORDERING INFORMATION Package Shipping † MC33023DW SOIC−16W 47 Units / Rail MC33023DWG SOIC−16W (Pb−Free) 47 Units / Rail MC33023DWR2 SOIC−16W 1000 Units / Reel MC33023DWR2G SOIC−16W (Pb−Free) 1000 Units / Reel MC34023P PDIP−16 25 Units / Rail MC34023PG PDIP−16 (Pb−Free) 25 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS Symbol Value Unit Power Supply Voltage Rating VCC 30 V Output Driver Supply Voltage VC 20 V Output Current, Source or Sink (Note 1) DC Pulsed (0.5 ms) IO Current Sense, Soft−Start, Ramp, and Error Amp Inputs Vin −0.3 to +7.0 V Error Amp Output and Soft−Start Sink Current IO 10 mA Clock and RT Output Current ICO 5.0 mA Power Dissipation and Thermal Characteristics SO−16L Package (Case 751G) Maximum Power Dissipation @ TA = + 25°C Thermal Resistance, Junction−to−Air DIP Package (Case 648) Maximum Power Dissipation @ TA = + 25°C Thermal Resistance, Junction−to−Air PD RqJA 862 145 mW °C/W PD RqJA 1.25 100 W °C/W Operating Junction Temperature TJ +150 °C Operating Ambient Temperature (Note 2) MC34023 MC33023 TA 0 to +70 −40 to +105 Storage Temperature Range Tstg −55 to +150 A 0.5 2.0 °C °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 2 MC34023, MC33023 ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 2], unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Vref 5.05 5.1 5.15 V Line Regulation (VCC = 10 V to 30 V) Regline − 2.0 15 mV Load Regulation (IO = 1.0 mA to 10 mA) Regload − 2.0 15 mV REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = + 25°C) Temperature Stability TS − 0.2 − mV/°C Total Output Variation over Line, Load, and Temperature Vref 4.95 − 5.25 V Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = + 25°C) Vn − 50 − mV Long Term Stability (TA = +125°C for 1000 Hours) S − 5.0 − mV ISC − 30 − 65 −100 mA fosc 380 370 400 400 420 430 Frequency Change with Voltage (VCC = 10 V to 30 V) Dfosc/DV − 0.2 1.0 % Frequency Change with Temperature (TA = Tlow to Thigh) Dfosc/DT − 2.0 − % Sawtooth Peak Voltage VOSC(P) 2.6 2.8 3.0 V Sawtooth Valley Voltage VOSC(V) 0.7 1.0 1.25 V VOH VOL 3.9 − 4.5 2.3 − 2.9 Input Offset Voltage VIO − − 15 mV Input Bias Current IIB − 0.6 3.0 mA Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = + 25°C Line (VCC = 10 V to 30 V) and Temperature (TA = Tlow to Thigh) kHz Clock Output Voltage High State Low State V ERROR AMPLIFIER SECTION Input Offset Current Open−Loop Voltage Gain (VO = 1.0 V to 4.0 V) Gain Bandwidth Product (TJ = + 25°C) Common Mode Rejection Ratio (VCM = 1.5 V to 5.5 V) IIO − 0.1 1.0 mA AVOL 60 95 − dB GBW 4.0 8.3 − MHz CMRR 75 95 − dB Power Supply Rejection Ratio (VCC = 10 V to 30 V) PSRR 85 110 − dB Output Current, Source (VO = 4.0 V) Output Current, Sink (VO = 1.0 V) ISource ISink 0.5 1.0 3.0 3.6 − − mA Output Voltage Swing, High State (IO = − 0.5 mA) Output Voltage Swing, Low State (IO = 1 mA) VOH VOL 4.5 0 4.75 0.4 5.0 1.0 V Slew Rate SR 6.0 12 − V/ms IIB − −0.5 −5.0 mA DC(max) DC(min) 80 − 90 − − 0 % Vth 1.1 1.25 1.4 V tPLH(in/out) − 60 100 ns Ichg 3.0 9.0 20 mA Idischg 1.0 4.0 − mA PWM COMPARATOR SECTION Ramp Input Bias Current Duty Cycle, Maximum Duty Cycle, Minimum Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V) Propagation Delay (Ramp Input to Output, TJ = + 25°C) SOFT−START SECTION Charge Current (VSoft−Start = 0.5 V) Discharge Current (VSoft−Start = 1.5 V) 1. Maximum package power dissipation limits must be observed. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for MC34023 Thigh = +70°C for MC34023 = −40°C for MC33023 = +105°C for MC33023 http://onsemi.com 3 MC34023, MC33023 ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Input Bias Current (Pin 9(12) = 0 V to 4.0 V) IIB − − 15 mA Current Limit Comparator Input Offset Voltage (Pin 11(14) = 1.1 V) VIO − − 45 mV CURRENT SENSE SECTION Current Limit Reference Input Common Mode Range (Pin 11(14)) TJ = + 25°C VCMR 1.0 − 3.0 V Vth 1.25 1.40 1.55 V tPLH(in/out) − 50 80 ns VOL − − 13 12 0.25 1.2 13.5 13 0.4 2.2 − − VOL(UVLO) − 0.25 1.0 V Output Leakage Current (VC = 20 V) IL − 100 500 mA Output Voltage Rise Time (CL = 1.0 nF, TJ = + 25°C) tr − 30 60 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = + 25°C) tf − 30 60 ns Vth(on) 8.8 9.2 9.6 V VH 0.4 0.8 1.2 V − − 0.5 20 1.2 30 Shutdown Comparator Threshold Propagation Delay (Current Limit/Shutdown to Output, TJ = + 25°C) OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA) High State (ISource = 20 mA) (ISource = 200 mA) V VOH Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 0.5 mA) UNDERVOLTAGE LOCKOUT SECTION Startup Threshold (VCC Increasing) UVLO Hysteresis Voltage (VCC Decreasing After Turn−On) TOTAL DEVICE ICC Power Supply Current Startup (VCC = 8.0 V) Operating mA 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for MC34023 Thigh = +70°C for MC34023 = −40°C for MC33023 = +105°C for MC33023 http://onsemi.com 4 MC34023, MC33023 R T , TIMING RESISTOR (Ω ) 1 3 5 2 4 7 6 9 1200 VCC = 15 V TA = + 25°C f osc, OSCILLATOR FREQUENCY (kHz) 100 k 1000 8 CT = 10 k 1. 100 nF 2. 47 nF 3. 22 nF 4. 10 nF 5. 4.7 nF 6. 2.2 nF 1.0 k 7. 1.0 nF 8. 470 pF 9. 220 pF 470 104 105 106 100 1000 fosc, OSCILLATOR FREQUENCY (Hz) −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 100 125 Gain 60 Phase 90 40 20 , EXCESS PHASE (°C) VTH, ZERO DUTY CYCLE (V) 1.30 θ A VOL, OPEN LOOP VOLTAGE GAIN (dB) RT = 36 k CT = 1.0 nF Figure 3. Oscillator Frequency versus Temperature 45 135 0 1.0 k 10 k 100 k f, FREQUENCY (Hz) 50 kHz 200 0 −55 100 100 RT = 3.6 k CT = 1.0 nF 400 0 10 400 kHz VCC = 15 V 600 107 120 −20 RT = 1.2 k CT = 1.0 nF 800 Figure 2. Timing Resistor versus Oscillator Frequency 80 1.0 MHz 1.0 M 1.28 VCC = 15 V Pin 7(9) = 0 V 1.26 1.24 1.22 1.20 −55 10 M Figure 4. Error Amp Open Loop Gain and Phase versus Frequency −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) Figure 5. PWM Comparator Zero Duty Cycle Threshold Voltage versus Temperature 2.55 V 3.0 V 2.5 V 2.5 V 2.45 V 2.0 V 0.1 ms/DIV 0.1 ms/DIV Figure 6. Error Amp Small Signal Transient Response Figure 7. Error Amp Large Signal Transient Response http://onsemi.com 5 I SC, REFERENCE SHORT CIRCUIT CURRENT (mA Vref , REFERENCE VOLTAGE CHANGE (mV) MC34023, MC33023 0 −5.0 VCC = 15 V TA = −55°C −10 TA = +125°C TA = + 25°C −15 −20 −25 −30 10 0 20 30 40 ISource, SOURCE CURRENT (mA) 50 66 65.6 65.2 64.8 64.4 64 −55 100 125 2.0 mV/DIV Vref LOAD REGULATION 1.0 mA to 10 mA (2.0 ms/DIV) Figure 10. Reference Line Regulation Figure 11. Reference Load Regulation 1.50 Vth, THRESHOLD VOLTAGE (V) VIO, CURRENT LIMIT INPUT OFFSET VOLTAGE (mV) 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) Vref LINE REGULATION 10 V to 24 V (2.0 ms/DIV) 100 VCC = 15 V Pin 11(14) = 1.1 V 20 −20 −60 −100 −55 −25 Figure 9. Reference Short Circuit Current versus Temperature 2.0 mV/DIV Figure 8. Reference Voltage Change versus Source Current 60 VCC = 15 V −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 1.46 1.42 1.38 1.34 1.30 −55 125 VCC = 15 V Figure 12. Current Limit Comparator Input Offset Voltage versus Temperature −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 Figure 13. Shutdown Comparator Threshold Voltage versus Temperature http://onsemi.com 6 125 Vsat , OUTPUT SATURATION VOLTAGE (V) 10 VCC = 15 V 9.0 VCC 8.0 7.5 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Source Saturation (Load to Ground) VCC = 15 V 80 ms Pulsed Load 120 Hz Rate TA = 25°C −2.0 8.5 7.0 −55 0 −1.0 9.5 2.0 1.0 Ground 0 0 0.2 Sink Saturation (Load to VCC) 0.4 0.6 0.8 IO, OUTPUT LOAD CURRENT (A) Figure 14. Soft−Start Charge Current versus Temperature Figure 15. Output Saturation Voltage versus Load Current OUTPUT RISE & FALL TIME 1.0 nF LOAD 50 ns/DIV OUTPUT RISE & FALL TIME 10 nF LOAD 50 ns/DIV Figure 16. Drive Output Rise and Fall Time Figure 17. Drive Output Rise and Fall Time 30 I CC , SUPPLY CURRENT (mA) I chg, SOFT-START CHARGE CURRENT (μ A) MC34023, MC33023 RT = 3.65 kW CT = 1.0 nF 25 20 VCC Increasing 15 VCC Decreasing 10 5.0 0 0 4.0 8.0 12 VCC, SUPPLY VOLTAGE (V) 16 Figure 18. Supply Voltage versus Supply Current http://onsemi.com 7 20 1.0 MC34023, MC33023 VCC 16 Clock 4 4.2 V 5 Oscillator RT 15 Reference Regulator Vref VCC UVLO VCC 9.2 V 13 Vref UVLO VC 14 6 CT Ramp 7 1.25 V S 3 2 Error Amp Current Limit + 11 Current Limit Reference 9.0 mA 1 8 9 Current Limit/Shutdown Soft−Start CSS Q PWM Latch Error Amp Output Noninverting Input Inverting Input Output 12 Power Ground R PWM Comparator 0.5 V R Soft−Start Latch Q S 10 1.4 V Shutdown Ground Figure 19. Representative Block Diagram CT Clock Soft−Start Error Amp Output Ramp PWM Comparator Output Figure 20. Current Limit Operating Waveforms http://onsemi.com 8 Vin MC34023, MC33023 OPERATING DESCRIPTION output of the error amplifier to less than its normal output voltage, thus limiting the duty cycle. The time it takes for a capacitor to reach full charge is given by: The MC33023 and MC34023 series are high speed, fixed frequency, single−ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off−Line and DC−to−DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 19. t [ (4.5 • 10 5) C Soft-Start A Soft−Start latch is incorporated to prevent erratic operation of this circuitry. Two conditions can cause the Soft−Start circuit to latch so that the Soft−Start capacitor stays discharged. The first condition is activation of an undervoltage lockout of either VCC or Vref. The second condition is when current sense input exceeds 1.4 V. Since this latch is “set dominant”, it cannot be reset until either of these signals is removed and, the voltage at CSoft−Start is less than 0.5 V. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. The RT pin is set to a temperature compensated 3.0 V. By selecting the value of RT, the charge current is set through a current mirror for the timing capacitor CT. This charge current runs continuously through CT. The discharge current is ratioed to be 10 times the charge current, which yields the maximum duty cycle of 90%. CT is charged to 2.8 V and discharged to 1.0 V. During the discharge of CT, the oscillator generates an internal blanking pulse that resets the PWM Latch and, inhibits the outputs. The threshold voltage on the oscillator comparator is trimmed to guarantee an oscillator accuracy of 5.0% at 25°C. Additional dead time can be added by externally increasing the charge current to CT as shown in Figure 24. This changes the charge to discharge ratio of CT which is set internally to Icharge/10 Icharge. The new charge to discharge ratio will be: % Deadtime + PWM Comparator and Latch A PWM circuit typically compares an error voltage with a ramp signal. The outcome of this comparison determines the state of the output. In voltage mode operation the ramp signal is the voltage ramp of the timing capacitor. In current mode operation the ramp signal is the voltage ramp induced in a current sensing element. The ramp input of the PWM comparator is pinned out so that the user can decide which mode of operation best suits the application requirements. The ramp input has a 1.25 V offset such that whenever the voltage at this pin exceeds the error amplifier output voltage minus 1.25 V, the PWM comparator will cause the PWM latch to set, disabling the outputs. Once the PWM latch is set, only a blanking pulse by the oscillator can reset it, thus initiating the next cycle. I additional ) I charge 10 (I charge) A bidirectional clock pin is provided for synchronization or for master/slave operation. As a master, the clock pin provides a positive output pulse during the discharge of CT. As a slave, the clock pin is an input that resets the PWM latch and blanks the drive output, but does not discharge CT. Therefore, the oscillator is not synchronized by driving the clock pin alone. Figures 28, 29 and 30 provide suggested synchronization. Current Limiting and Shutdown A pin is provided to perform current limiting and shutdown operations. Two comparators are connected to the input of this pin. The reference voltage for the current limit comparator is not set internally. A pin is provided so the user can set the voltage. When the voltage at the current limit input pin exceeds the externally set voltage, the PWM latch is set, disabling the output. In this way cycle−by−cycle current limiting is accomplished. If a current limit resistor is used in series with the power devices, the value of the resistor is found by: Error Amplifier A fully compensated Error Amplifier is provided. It features a typical DC voltage gain of 95 dB and a gain bandwidth product of 8.3 MHz with 75 degrees of phase margin (Figure 4). Typical application circuits will have the noninverting input tied to the reference. The inverting input will typically be connected to a feedback voltage generated from the output of the switching power supply. Both inputs have a common mode voltage (VCM) input range of 1.5 V to 5.5 V. The Error Amplifier Output is provided for external loop compensation. R Sense + I Limit Reference Voltage I pk (switch) If the voltage at this pin exceeds 1.4 V, the second comparator is activated. This comparator sets a latch which, in turn, causes the soft start capacitor to be discharged. In this way a “hiccup” mode of recovery is possible in the case of output short circuits. If a current limit resistor is used in series with the output devices, the peak current at which the controller will enter a “hiccup” mode is given by: Soft−Start Latch Soft−Start is accomplished in conjunction with an external capacitor. The Soft−Start capacitor is charged by an internal 9.0 mA current source. This capacitor clamps the I shutdown + http://onsemi.com 9 1.4 V R Sense MC34023, MC33023 In certain applications, it may be desirable to disable the current limit comparator. This can be accomplished by biasing pin 11 to a level greater than 1.4 V but less than 3.0 V. Under these conditions, the shutdown comparator and soft−start latch are activated during an overcurrent event causing the converter to enter an hiccup mode. specific part in question. The PC board lead lengths must be less than 0.5 inches for effective bypassing for snubbing. Instabilities In current mode control, an instability can be encountered at any given duty cycle. The instability is caused by the current feedback loop. It has been shown that the instability is caused by a double pole at half the switching frequency. If an external ramp (Se) is added to the on−time ramp (Sn) of the current−sense waveform, stability can be achieved. One must be careful not to add too much ramp compensation. If too much is added the system will start to perform like a voltage mode regulator. All benefits of current mode control will be lost. Figure 26 is an example of one way in which external ramp compensation can be implemented. Undervoltage Lockout There are two undervoltage lockout circuits within the IC. The first senses VCC and the second Vref. During power−up, VCC must exceed 9.2 V and Vref must exceed 4.2 V before the outputs can be enabled and the Soft−Start latch released. If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs are disabled and the Soft−Start latch is activated. When the UVLO is active, the part is in a low current standby mode allowing the IC to have an off−line bootstrap startup circuit. Typical startup current is 500 mA. Ramp Compensation Output Ramp Input The MC34023 has a high current totem pole output specifically designed for direct drive of power MOSFETs. It is capable of up to ± 2.0 A peak drive current with a typical rise and fall time of 30 ns driving a 1.0 nF load. Separate pins for VC and Power Ground are provided. With proper implementation, a significant reduction of switching transient noise imposed on the control circuitry is possible. The separate VC supply input also allows the designer added flexibility in tailoring the drive voltage independent of VCC. 1.25 V Ramp Compensation Se Current Signal Sn Figure 21. Ramp Compensation A simple equation can be used to calculate the amount of external ramp slope necessary to add that will achieve stability in the current loop. For the following equations, the calculated values for the application circuit in Figure 35 are also shown. Reference A 5.1 V bandgap reference is pinned out and is trimmed to an initial accuracy of ±1.0% at 25°C. This reference has short circuit protection and can source in excess of 10 mA for powering additional control system circuitry. Se + Design Considerations Do not attempt to construct the converter on wire−wrap or plug−in prototype boards. With high frequency, high power, switching power supplies it is imperative to have separate current loops for the signal paths and for the power paths. The printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input filter capacitor. Shown in Figure 36 is a printed circuit layout of the application circuit. Note how the power and ground traces are run. All bypass capacitors and snubbers should be connected as close as possible to the where: VO = NP, NS = = Ai = = L= RS = VO L ǒ Ǔ NS NP (R S)A i DC output voltage number of power transformer primary or secondary turns gain of the current sense network (see Figures 24 and 25) output inductor current sense resistance ǒǓ 5 2 (0.3)(0.55) For the application circuit: S e + 1.8 μ 8 = 0.115 V/ms http://onsemi.com 10 MC34023, MC33023 PIN FUNCTION DESCRIPTION Pin DIP/SOIC Function 1 Error Amp Inverting Input Description 2 Error Amp Noninverting Input 3 Error Amp Output 4 Clock 5 RT The value of RT sets the charge current through timing Capacitor, CT. 6 CT In conjunction with RT, the timing Capacitor sets the switching frequency. 7 Ramp Input 8 Soft−Start 9 Current Limit/ Shutdown This pin is usually used for feedback from the output of the power supply. This pin is used to provide a reference in which an error signal can be produced on the output of the error amp. Usually this is connected to Vref, however an external reference can also be used. This pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output LC filter. This is a bidirectional pin used for synchronization. For voltage mode operation this pin is connected to CT. For current mode operation this pin is connected through a filter to the current sensing element. A capacitor at this pin sets the Soft−Start time. This pin has two functions. First, it provides cycle−by−cycle current limiting. Second, if the current is excessive, this pin will reinitiate a Soft−Start cycle. 10 Ground 11 Current Limit Reference Input This pin is the ground for the control circuitry. 12 Power Ground 13 VC 14 Output 15 VCC This pin is the positive supply of the control IC. 16 Vref This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier. This pin voltage sets the threshold for cycle−by−cycle current limiting. This is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. This is a separate power source connection for the outputs that is connected back to the power source input. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This is a high current totem pole output. 4 4 5 5 Oscillator Oscillator 6 CT 7 CT From Current Sense Element 1.25 V 7 Vref 1.25 V 3 1 3 1 Output Voltage Feedback Input 6 Output Voltage Feedback Input 2 In voltage mode operation, the control range on the output of the Error Amplifier from 0% to 90% duty cycle is from 2.25 V to 4.05 V. Vref 2 In current mode control, an RC filter should be placed at the ramp input to filter the leading edge spike caused by turn−on of a power MOSFET. Figure 22. Voltage Mode Operation Figure 23. Current Mode Operation http://onsemi.com 11 MC34023, MC33023 9 9 The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. If a transformer is used, the gain can be calculated by: Ai + Rw ISense ISense The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. The gain can be calculated by: R Sense turns ratio Ai Figure 24. Resistive Current Sensing Rw turns ratio + Figure 25. Primary Side Current Sensing 4 5 Oscillator 6 CT Current Sense Information C1 R1 R2 1.25 V 7 3 This method of slope compensation is easy to implement, however, it is noise sensitive. Capacitor C1 provides AC coupling. The oscillator signal is added to the current signal by a voltage divider consisting of resistors R1 and R2. Figure 26A. Slope Compensation (Noise Sensitive) Current Sense Transformer Rw Rf Output RM CM Output Figure 26. Ramp Input RM Ramp Input 7 1.25 V CM Current Sense Resistor Cf 3 Rf 7 1.25 V 3 Cf When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and capacitor CM provide the added slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you can assume that its charge is linear. First choose CM, then RM can be adjusted to achieve the required slope. The diode provides a reset pulse at the ramp input at the end of every cycle. The charge current IM can be calculated by IM = CMSe. Then RM can be calculated by RM = VCC/IM. Figure 26B. Slope Compensation (Noise Immune) http://onsemi.com 12 MC34023, MC33023 5.0 V 0V 4 5 6 RT Oscillator CT Vref 4 RDT 5 6 RT Oscillator CT Additional dead time can be added by the addition of a dead time resistor from Vref to CT. See text on Oscillator section for more information. The sync pulse fed into the clock pin must be at least 3.9 V. RT and CT need to be set 10% slower than the sync frequency. This circuit is also used in Voltage Mode operation for master/slave operation. The clock signal would be coming from the master which is set at the desired operating frequency, while the slave is set 10% slower. Figure 27. Dead Time Addition Figure 28. External Clock Synchronization 4 4 Vref 5 Master Oscillator 5 Slave Oscillator 6 6 CT RT Figure 29. Current Mode Master/Slave Operation Over Short Distances Reference 20 16 MMBT3906 1.0 k 4 NC 4.7 k 4 2200 1.15 RT 5 6 5 Master Oscillator MMBD0914 430 6 MMBT3904 CT RT CT Figure 30. Synchronization Over Long Distances http://onsemi.com 13 Slave Oscillator MC34023, MC33023 1 2 + Vref R1 R2 IB 8 + CSS Base Charge Removal − 15 14 In voltage mode operation, the maximum duty cycle can be clamped. By the addition of a PNP transistor to buffer the clamp voltage, the Soft−Start current is not affected by R1. The new equation for Soft−Start is t[ V clamp ) 0.6 9.0 μA Vin VC 0 12 To Current Sense Input RS (CSS) The totem pole output can furnish negative base current for enhanced transistor turn−off, with the addition of the capacitor in series with the base. In current mode operation, this circuit will limit the maximum voltage allowed at the ramp input to end a cycle. Figure 31. Buffered Maximum Clamp Level Figure 32. Bipolar Transistor Drive Vin VC VC 15 14 15 14 12 To Current Sense Input RS 12 A series gate resistor may be needed to dampen high frequency parasitic oscillation caused by the MOSFET’s input capacitance and any series wiring inductance in the gate−source circuit. The series resistor will also decrease the MOSFET switching speed. A Schottky diode can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. The Schottky diode also prevents substrate injection when the output pin is driven below ground. The totem pole output can easily drive pulse transformers. A Schottky diode is recommended when driving inductive loads at high frequencies. The diode can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. Figure 33. MOSFET Parasitic Oscillations Figure 34. Isolated MOSFET Drive http://onsemi.com 14 2.0 k 22 k 0.01 8 Figure 35. Application Circuit http://onsemi.com 15 Error Amp Q S R 9.0 μA PWM Comparator 4.2 V L1 − 2 turns #48 AWG (1300 strands litz wire) Core: Philips 3F3, part #EP10−3F3 Bobbin: Philips part #EP10PCB1−8 L = 1.8 μ H Coilcraft P3270−A S R Q 10 Soft−Start Latch 0.5 V PWM Latch Vref UVLO Reference Regulator T1 − Primary: 8 turns #48 AWG (1300 strands litz wire) Secondary: 2 turns 0.003’’ (2 layers) copper foil Bootstrap: 1 turn added to secondary #36 AWG Core: Philips 3F3, part #4312 020 4124 Bobbin: Philips part #4322 021 3525 Coilcraft P3269−A 0.1 Soft−Start 2 1 1.25 V Oscillator + 2 − 5(1.5 Ω ) resistors in parallel 1 − 10(1.0 μF) ceramic capacitors in parallel Insulators − All power devices are insulated with Berquist Sil−Pad 150 Heatsinks − Power FET: AAVID Heatsink #533902B02552 with clip Output Rectifiers: AAVID Heatsink #533402B02552 with clip 47 k Vref 0.015 μ F 6 1000 pF 3 5 1.2 k 7 4 16 1.0 Vref 1.4 V Shutdown Current Limit 9.2 V VCC UVLO Condition V in = 48 V, IO = 7.5 A V in = 48 V, IO = 7.5 A Output Ripple Efficiency V in = 48 V, IO = 4.0 A to 7.5 A 220 pF 1.0 k 3.9 k MUR410 Result 10 μ F L1 22 1500 pF 1 1.8 69.8% 10 mVp−p 54 mV = ± 1.0% 14 mV = ± 0.275% MBR2535 CTL Load Regulation 100 1600 pF 50 0.3 Ω 2 100 1500 pF 22 V in = 40 V to 56 V, IO = 7.5A Test 47 100 47 IRF640 1N5819 4.7 10 10 47 k T1 1N5819 Line Regulation 9 11 12 14 13 15 4.7 V in = 40 V to 56 V VO = 5.0 V MC34023, MC33023 MC34023, MC33023 MBR 2535CTI 1N5819 1N5819 +10 1000 pF 4.0″ 1N5819 MC34023 100 pF 100 pF 1500 pF 0.01 0.01 0.01 2200 pF MBR 2535CTI 100 6.5″ (Top View) Figure 36. PC Board With Components http://onsemi.com 16 1500 pF MC34023, MC33023 (Top View) 4.0″ 6.5″ (Bottom View) Figure 37. PC Board Without Components http://onsemi.com 17 MC34023, MC33023 PACKAGE DIMENSIONS PDIP−16 P SUFFIX CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L DIM A B C D F G H J K L M S S −T− SEATING PLANE K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOIC−16W DW SUFFIX CASE 751G−03 ISSUE C A D 9 1 8 h X 45 _ E 0.25 H 8X M B M 16 q 16X M 14X e B B T A MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ S B S L A 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. A1 SEATING PLANE T C ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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