SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 D Low Power Drain . . . 900 µW Typical With D D D D D D D D D LP211 . . . D PACKAGE LP311 . . . D, P, OR PS PACKAGE (TOP VIEW) 5-V Supply Operates From ±15 V or From a Single Supply as Low as 3 V Output Drive Capability of 25 mA Emitter Output Can Swing Below Negative Supply Response Time . . . 1.2 µs Typ Low Input Currents: Offset Current . . . 2 nA Typ Bias Current . . . 15 nA Typ Wide Common-Mode Input Range: −14.5 V to 13.5 V Using ±15-V Supply Offset Balancing and Strobe Capability Same Pinout as LM211, LM311 Designed To Be Interchangeable With Industry-Standard LP311 EMIT OUT IN+ IN− VCC− 1 8 2 7 3 6 4 5 VCC+ COL OUT BAL/STRB BALANCE description/ordering information The LP211 and LP311 devices are low-power versions of the industry-standard LM211 and LM311 devices. They take advantage of stable, high-value, ion-implanted resistors to perform the same function as the LM311 series, with a 30:1 reduction in power consumption, but only a 6:1 slowdown in response time. They are well suited for battery-powered applications and all other applications where fast response times are not needed. They operate over a wide range of supply voltages, from ±18 V down to a single 3-V supply with less than 300-µA current drain, but are still capable of driving a 25-mA load. The LP211 and LP311 are quite easy to apply free of oscillation if ordinary precautions are taken to minimize stray coupling from the output to either input or to the trim pins. In addition, offset balancing is available to minimize input offset voltage. Strobe capability also is provided to turn off the output (regardless of the inputs) by pulling the strobe pin low. The LP211 is characterized for operation from −25°C to 85°C. The LP311 is characterized for operation from 0°C to 70°C. ORDERING INFORMATION TA VIO max AT 25°C PACKAGE† PDIP (P) −0°C to 70°C 7.5 mV SOIC (D) SOP (PS) −25°C to 85°C 7.5 mV SOIC (D) ORDERABLE PART NUMBER Tube of 50 LP311P Tube of 75 LP311D Reel of 2500 LP311DR Reel of 2000 LP311PSR Tube of 75 LP211D Reel of 2500 LP211DR TOP-SIDE MARKING LP311P LP311 L311 LP211 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 functional block diagram BALANCE BAL/STRB IN+ COL OUT IN− EMIT OUT absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (see Note 1): VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V Input voltage, VI (either input, see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V Voltage from emitter output to VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V Voltage from collector output to VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Voltage from collector output to emitter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Duration of output short circuit (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Package thermal impedance, θJA (see Notes 5 and 6): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC−. 2. Differential input voltages are at IN+ with respect to IN−. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage of ±15 V, whichever is less. 4. The output may be shorted to ground or to either power supply. 5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 6. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN 2 (|VCC±| ≤ 15 V) Input voltage VCC+ − VCC− Supply voltage VCC− + 0.5 3.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT VCC+ − 1.5 V 30 V SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) PARAMETER VID VOL Input offset voltage Low-level output voltage TEST CONDITIONS TA 25°C MIN Input offset current IIB Input bias current MAX 2 7.5 RS < 100 kΩ, kΩ See Note 7 VID < −10 mV, See Note 8 IOL = 25 mA, 25°C 0.4 1.5 VCC = 4.5 V, VID < −10 mV, See Note 8 VCC− = 0, IOL = 1.6 mA, Full range 0.1 0.4 2 25 Full range 10 See Note 7 UNIT mV V 25°C IIO TYP† Full range 35 25°C 15 Full range nA 100 150 nA Low-level strobe current V(strobe) = 0.3 V, See Note 9 VID < −10 mV, 25°C 100 300 µA A IO(off) Output off-state current VID > 10 mV, VCE = 35 V 25°C 0.2 100 nA AVD Large-signal differential-voltage amplification RL = 5 kΩ ICC+ Supply current from VCC+ VID = −50 mV, 25°C RL = ∞ 40 Full range 100 150 V/mV 300 µA ICC− Supply current from VCC− VID = 50 mV, RL = ∞ Full range − 80 − 180 µA † All typical values are at VCC± = ±15 V, TA = 25°C. NOTES: 7. The offset voltages and offset currents given are the maximum values required to drive the output within 1 V of either supply with a 1-mA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and input impedance. 8. Voltages are with respect to EMIT OUT and VCC− tied together. 9. The strobe should not be shorted to ground; it should be current driven at 100 µA to 300 µA. switching characteristics, VCC± = ±5 V, TA = 25°C (unless otherwise noted) PARAMETER Response time TEST CONDITIONS TYP UNIT See Note 10 1.2 µs NOTE 10: The response time is specified for a 100-mV input step with 5-mV overdrive. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLCS003D − JUNE 1987 − REVISED SEPTEMBER 2003 TYPICAL APPLICATION CIRCUIT VCC+ 3 kΩ BAL/STRB 3 kΩ BALANCE TTL Strobe BAL/ STRB 2N2222 15 kΩ NOTE: If offset balancing is not used, the BALANCE and BAL/STRB pins should be shorted together. NOTE: Do not connect strobe pin directly to ground, because the output is turned off whenever current is pulled from the strobe pin. Figure 2. Strobing Figure 1. Offset Balancing 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty LP211D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP211DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP211DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP211DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP211P OBSOLETE PDIP P 8 LP311D ACTIVE SOIC D 8 LP311DE4 ACTIVE SOIC D LP311DG4 ACTIVE SOIC LP311DR ACTIVE LP311DRE4 Lead/Ball Finish MSL Peak Temp (3) TBD Call TI 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP311DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP311P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type LP311PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type LP311PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP311PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP311PWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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