NCP1526 400 mA, 1.2 V, High−Efficiency, Step−Down Converter with Low Noise Voltage Regulator Optimized for RF Module The NCP1526 product is a monolithic integrated circuit combining step−down PWM DC−DC converter dedicated to the portable applications powered from one cell Li−ion or three cell Alkaline/ NiCd/NiMH batteries and a low noise output voltage regulator dedicated to supply RF sensitive module in the portable applications. The DC−DC converter operates with a fixed output voltage of 1.2 V and delivers up to 400 mA. It uses synchronous rectification to increase efficiency and reduces external part count. The device also has a built−in 3.0 MHz (nominal) oscillator which reduces component size by allowing small inductor and capacitors. It includes an integrated soft−start, cycle−by−cycle current limiting, and thermal shutdown protection. The additional 2.80 V very low noise, low drop output regulator, is available with 150 mA current capability, current limitation and overtemperature protection. Finally, the NCP1526 is available in a space saving, ultra low profile 3x3 mm 10 pin UDFN package (thickness 0.55 mm max). http://onsemi.com MARKING DIAGRAM 1526 A L Y W G • • • • • • PIN CONNECTIONS FB EN1 EN2 GND2 BYPASS − Up to 85% Efficiency − Output Current Capability 400 mA − 3.0 MHz Switching Frequency − 1.2 V Fixed Output Voltage − Synchronous Rectification for Higher Efficiency LDO Regulator − 2.80 V Output Voltage − Up to 150 mA Output Current Capability − Very Low Noise: 45 mVRMS All Pins are Fully ESD Protected 2.7 V to 5.5 V Input Voltage Range Thermal Limit Protection 3.0 mm x 3.0 mm x 0.55 mm UDFN Package This is a Pb−Free Device VIN1 LX GND1 VIN2 V1 (Top View) ORDERING INFORMATION Device NCP1526MUTXG Package Shipping† UDFN−10 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Typical Applications • • • • • = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Features • Step−Down Converter 1526 ALYWG G 10 PIN DFN MU SUFFIX CASE 506AT Cellular Phones, Smart Phones and PDAs Digital Still Cameras MP3 Players and Portable Audio Systems Wireless and DSL Modems Portable Equipment © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 0 1 Publication Order Number: NCP1526/D NCP1526 Vbattery OFF ON BUCK OFF ON LDO 1 FB 2 EN1 LX 9 3 EN2 GND1 8 4 GND2 VIN2 7 5 BYPASS V1 6 C1 VIN1 10 L1 Vout BUCK C3 Vout LDO C2 C5 C4 Figure 1. Typical Applications Circuit Vbattery FB OFF ON EN1 ILIMIT 1 VIN1 REFERENCE VOLTAGE PWM CONTROL 2 VIN1 OFF ON EN2 GND2 10 3 4 LOGIC CONTROL Buck Converter 9 LX 4.7 mF Vout BUCK 1.20 V, 400 mA 2.2 mH 4.7 mF Q2 VIN2 LOGIC CONTROL LDO Q1 VIN1 Thermal Shutdown 8 7 GND1 VIN2 Vbattery 4.7 mF BYPASS V1 BLOCK 5 6 100 nF V1 Vout LDO 2.80 V, 150 mA 1 mF Figure 2. Simplified Block Diagram http://onsemi.com 2 NCP1526 PIN FUNCTION DESCRIPTION (Pin out provided for concept purpose only and might change in the final product.) Pin No. Symbol Function Description 1 FB Analog Input Feedback voltage from the output of the power supply. This is the input to the error amplifier. 2 EN1 Digital Input Enable for DC−DC converter. This pin is active high. It is turned off by logic LOW on this pin. Do not float this pin. 3 EN2 Digital Input EN2 enables the LDO.A HIGH level on this pin activates the voltage regulator. It is turned off by logic LOW on this pin. Do not float this pin. 4 GND2 Power Ground Ground connection for the LDO section and must be connected to the system ground. 5 BYPASS 6 V1 Output Power This pin provides the output voltage supplied by the LDO. This pin requires 1.0 mF decoupling capacitor. 7 VIN2 Power Input Input battery voltage to supply voltage regulator blocks. The pin requires a 4.7 mF decoupling capacitor. 8 GND1 Power Ground This pin is the GROUND reference for the DC−DC converter and the output control. The pin must be connected to the system ground. 9 LX Analog Output Connection from Power MOSFETs to the inductor. An output discharge circuit sinks current from this pin. 10 VIN1 Power Input Bypass is the bandgap reference for the LDO. This pin requires a 100 nF bypass capacitor for low noise. This pin cannot be used for an external source. Input battery voltage to supply the analog and digital blocks of the DC−DC converter. The pin must be decoupled to ground by a 4.7 mF ceramic capacitor. MAXIMUM RATINGS Rating Symbol Value Unit Minimum Voltage All Pins Vmin −0.3 V Maximum Voltage All Pins (Note 2) Vmax 7.0 V Maximum Voltage EN1, EN2, FB, LX Vmax VIN + 0.3 V UDFN10 Package (Note 5) Thermal Resistance, Junction−to−Air RqJA 240 °C/W Operating Ambient Temperature Range TA −40 to 85 _C Storage Temperature Range Tstg −55 to 150 _C Junction Operating Temperature TJ −40 to 125 _C Latch−up Current Maximum Rating (TA = 85°C) (Note 4) FB pin Latch−up Current Maximum Rating (TA = 85°C) (Note 4) Other pins Lu "70 "100 mA 2.0 200 kV V ESD Withstand Voltage (Note 3) Human Body Model Machine Model Vesd Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C. 2. According to JEDEC standard JESD22−A108B. 3. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) per JEDEC standard: JESD22−A114. Machine Model (MM) per JEDEC standard: JESD22−A115. 4. Latchup current maximum rating per JEDEC standard: JESD78. 5. The exposed flag shall be connected to ground. 6. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. http://onsemi.com 3 NCP1526 ELECTRICAL CHARACTERISTICS, DC/DC Converter (Typical values are referenced to TA = +25°C, Min and Max values are referenced −40°C to +85°C ambient temperature, unless otherwise noted, operating conditions VIN = 3.6 V, unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit Input Voltage Range 10 Vin 2.7 − 5.2 V Quiescent Current, Iout = 0 mA, No Switching Quiescent Current, Iout = 0 mA, Oscillator Running 8 Iq ON − − 250 550 350 − mA Quiescent Current, EN Low 8 Iq OFF − 0.2 1.5 mA Undervoltage Lockout (VIN Increase) 10 VUVLO − 2.5 − V Undervoltage Lockout Hysteresis 10 VHUVLO − 100 − mV Positive Going Input High Voltage Threshold, EN0 Signal 2, 3 VIH 1.2 − − V Negative Going Input High Voltage Threshold, EN0 Signal 2, 3 VIL − − 0.4 V − 1000 − mA 1.164 1.2 1.236 − − 30 35 − − − "5.0 − − − 0.2 0.5 − − VIN1 PIN EN1, EN2 PIN DC−DC CONVERTER SECTION Peak Inductor Current 9 ILIM Feedback Voltage Threshold Overtemperature 1 VFB Load Transient Response, Rise/Fall Time 1.0 ms 1.0 mA to 300 mA Load Step 1.0 mA to 400 mA Load Step − Line Transient Response, Iout = 100 mA, 3.0 V to 3.6 V Line Step − VOUT Output Voltage Load Regulation Iout = 1.0 mA to 300 mA Iout = 1.0 mA to 400 mA − VOUT Output Voltage Line Regulation, Iout = 100 mA, VIN = 2.7 V to 5.2 V − VOUT − 0.1 − % Output Voltage Ripple, Iout = 300 mA − VOUT − 5.0 − mV Oscillator Frequency 9 FOSC 2.4 3.0 3.6 MHz P−Ch On−Resistance 1 RLxH − 400 − mW N−Ch On−Resistance 1 RLxL − 400 − mW P−Ch Leakage Current 1 ILeakH − 0.05 − mA N−Ch Leakage Current 1 ILeakL − 0.01 − mA Soft−Start Time − Tstart − 100 300 ms http://onsemi.com 4 VOUT V mV mVpp % NCP1526 ELECTRICAL CHARACTERISTICS for LDO (Typical values are referenced to TA = +25°C, Min and Max values are referenced −40°C to +85°C ambient temperature, unless otherwise noted, operating conditions 3 V < VIN < 5.2 V, unless otherwise noted.) Characteristic Pin Symbol Min Typ Max Unit Input Voltage Range 7 Vin 3 − 5.2 V Quiescent Current On State VIN2 = 4.2 V, Iout = 0 mA 4 Iq ON − 70 95 mA Quiescent Current Off State 4 Iq OFF − 0.2 − mA Output Voltage, Iout = 0 mA to 150 mA 6 V1 2.716 2.80 2.884 V Maximum Output Current 6 Iout 150 − − mA Output Voltage Line Regulation, Iout = 10 mA 6 V1 − 10 − mV Load Regulation, Iout = 1.0 mA to 150 mA, VIN = 3.6 V 6 V1 − 20 − mV Power Supply Ripple Rejection on V1, (0.2 Vp−p), Cout = 1.0 mF, Vin = 3.6 V 1.0 kHz Iout1 = 100 mA 100 kHz, Iout1 = 100 mA 6 PSRR VIN2 PIN LDO SECTION Dropout Voltage, Iout = 150 mA dB − − 67 45 − − VINA−V1 − − 150 mV Output Short Circuit Current 6 ISC 250 300 − mA Output Noise Voltage, 100 Hz to 100 kHz, Iout = 10 mA, Cout= 1.0 mF 6 VN − 45 − mVrms Turn ON Output Voltage, Vin = 3.6 V 6 Ton − 80 150 ms 5 VBY − 1.5 − V BYPASS PIN Output Voltage, Cby = 100 nF http://onsemi.com 5 NCP1526 TYPICAL CHARACTERISTICS NCP1526 circuit on Figure 2, Vin = 3.6 V, TA = 25°C, unless otherwise noted 100 90 80 STEP DOWN CONVERTER EFFICIENCY (%) Vin = 2.7 V Vin = 3.6 V 70 Vin = 5.2 V 60 50 40 30 0 100 200 300 STEP DOWN CONVERTER LOAD REGULATION (%) TA = −40°C 80 70 TA = 25°C 60 50 40 0 200 300 400 Figure 3. Step Down Converter Efficiency vs. Output Current Figure 4. Step Down Converter Efficiency vs. Temperature Vin = 3.6 V 1.0 TA = −40°C TA = 25°C 0 TA = 85°C −1.0 −2.0 0 100 200 300 400 Iout (mA) 1.225 1.215 Vin = 2.7 V Vin = 3.6 V 1.205 Vin = 5.2 V 1.195 −50 −25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 6. Step Down Converter Output Voltage vs. Temperature at Iout = 100 mA Figure 5. Step Down Converter Load Regulation vs. Temperature Vin = 3.6 V 5.0 100 Iout = 100 mA 4.0 90 3.0 2.0 EFFICIENCY (%) FREQUENCY VARIATION (%) 100 Iout (mA) 2.0 1.0 0 −1.0 −2.0 −3.0 TA = −40°C 80 70 TA = 25°C TA = 85°C 60 50 40 −4.0 −5.0 TA = 85°C Iout, OUTPUT CURRENT (mA) 3.0 −3.0 90 30 400 STEP DOWN CONVERTER OUTPUT VOLTAGE (V) STEP DOWN CONVERTER EFFICIENCY (%) 100 2.7 3.2 3.7 4.2 4.7 5.2 30 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vin, INPUT VOLTAGE (V) Vin, INPUT VOLTAGE (V) Figure 7. Step Down Converter Switching Frequency vs. Input Voltage Figure 8. Step Down Converter Efficiency vs. Input Voltage at Iout = 100 mA http://onsemi.com 6 NCP1526 TYPICAL CHARACTERISTICS NCP1526 circuit on Figure 2, Vin = 3.6 V, TA = 25°C, unless otherwise noted 1.0 1.0 LINE REGULATION (%) LINE REGULATION (%) 2.0 Iout = 400 mA Iout = 100 mA 0 Iout = 0.1 mA −1.0 −2.0 2.7 3.2 3.7 4.2 4.7 0.5 TA = −40°C 0 TA = 25°C −0.5 −1.0 5.2 TA = 85°C 2.7 3.2 3.7 4.2 4.7 Vin, (V) Vin (V) Figure 9. Step Down Converter Line Regulation vs. Output Current Figure 10. Step Down Converter Line Regulation vs. Temperature at Iout = 100 mA 5.2 Iout 200 mA / Div VEN 1 V / Div Vout 20 mV / Div Vout 500 mV / Div 20 ms / Div 40 ms / Div Figure 11. Step Down Converter Soft Start Time Figure 12. Step Down Converter Load Transient Response VLX 2 V / Div Vin 200 mV / Div Vin 2 V / Div Vout 10 mV / Div Vout 10 mV / Div 10 ms / Div Iout 200 mA / Div 100 ms / Div Figure 13. Step Down Converter PWM Mode of Operation Figure 14. Step Down Converter Line Transient Response http://onsemi.com 7 NCP1526 TYPICAL CHARACTERISTICS 1.0 1.0 0.6 0.5 Vin = 3.6 V Vin = 2.7 V 0.2 LOAD REGULATION (%) LOAD REGULATION (%) NCP1526 circuit on Figure 2, Vin = 3.6 V, TA = 25°C, unless otherwise noted Vin = 5.2 V −0.2 −0.6 −1.0 0 50 100 TA = 25°C 0 TA = −40°C −0.5 −1.0 150 TA = 85°C 0 30 60 120 Iout, OUTPUT CURRENT (mA) Iout, (mA) Figure 15. LDO Load Regulation Figure 16. LDO Load Regulation vs. Temperature 150 Iout 200 mA / Div Vout 1 V / Div Vout 20 mV / Div EN 2 V / Div 100 ms / Div 10 ms / Div Figure 17. LDO Turn On Time from Enable Figure 18. LDO Load Transient Response 100 10,000 Band Power 100 Hz to 100 KHz: 17 mVrms 90 NOISE (mV/√Hz) QUIESCENT CURRENT (mA) 90 80 70 1,000 100 60 50 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 10 5.0 5.2 100 1,000 10,000 100,000 Vin (V) FREQUENCY (Hz) Figure 19. LDO Quiescent Current vs. Input Voltage Figure 20. LDO Noise (DC/DC Converter Off) http://onsemi.com 8 NCP1526 TYPICAL CHARACTERISTICS NCP1526 circuit on Figure 2, Vin = 3.6 V, TA = 25°C, unless otherwise noted 1,000 100 90 TA = −40°C DROPOUT (mV) 100 10 1.0 100 TA = 25°C 70 60 TA = 85°C 50 40 30 20 Band Power 100 Hz to 100 KHz: 27 mVrms 1,000 10,000 100,000 10 0 0 30 60 90 120 FREQUENCY (Hz) Iout, (mA) Figure 21. LDO Noise (DC/DC Converter On) Figure 22. LDO Dropout Voltage vs. Output Current 20 10 0 −10 GAIN (dB) NOISE (mV/√Hz) 80 −20 −30 −40 −50 −60 −70 −80 −90 10 100 1,000 10,000 100,000 1,000,000 (Hz) Figure 23. LDO PSRR at Iout = 100 mA, Vin = 3.6 V http://onsemi.com 9 150 NCP1526 DC−DC OPERATION DESCRIPTION Detailed Description The NCP1526 uses a constant frequency, voltage mode step−down architecture. Both the main (P−Channel MOSFET) and synchronous (N−Channel MOSFET) switches are internal. It delivers a constant voltage from either a single Li−Ion or three cell NiMH/NiCd battery to portable devices such as cell phones and PDA. The output voltage accuracy is well within 3% of the 1.20 V. The NCP1526 can source at least 400 mA. at a fixed 3.0 MHz frequency. The switching of the PMOS Q1 is controlled by a flip−flop driven by the internal oscillator and a comparator that compares the error signal from an error amplifier with the PWM ramp. At the beginning of each cycle, the main switch Q1 is turned ON by the rising edge of the internal oscillator clock. When the PWM ramp becomes higher than the error voltage amplifier the PWM comparator resets the flip−flop, Q1 is turned OFF and the synchronous switch Q2 is turned ON. Q2 replaces the external Schottky diode to reduce the conduction loss and improve the efficiency. To avoid overall power loss, a certain amount of dead time is introduced to ensure Q1 is completely turned OFF before Q2 is being turned ON. PWM Operating Mode The output voltage of NCP1526 is regulated by modulating the on−time pulse width of the main switch Q1 3.6040 3.6000 3.5960 400 m 200 m 0.00 400 m 300 m 200 m 400 m 100 m −200 m 1.205 1.200 1.195 3.70 1.35 −1.00 Vin IPFET IL INFET VO VLX Figure 24. Waveforms During PWM Operation Soft−Start Cycle−by−Cycle Current Limitation The NCP1526 uses soft−start to limit the inrush current when the device is initially powered up or enabled. Soft−start is implemented by gradually increasing the reference voltage until it reaches the full reference voltage. During startup, a pulsed current source charges the internal soft−start capacitor to provide gradually increasing reference voltage. When the voltage across the capacitor ramps up to the nominal reference voltage, the pulsed current source will be switched off and the reference voltage will switch to the regular reference voltage. From the block diagram (Figure 2), an ILIM comparator is used to realize cycle−by−cycle current limit protection. The comparator compares the LX pin voltage with the reference voltage, which is biased by a constant current. If the inductor current reaches the limit, the ILIM comparator detects the LX voltage falling below the reference voltage and releases the signal to turn off the switch Q1. The cycle−by−cycle current limit is set at 1000 mA (nom). http://onsemi.com 10 NCP1526 Shutdown Mode Due to the nature of the buck converter, the output L−C filter must be selected to work with internal compensation. For NCP1526, the internal compensation is internally fixed and it is optimized for an output filter of L = 2.2ĂmH and COUT = 4.7ĂmF The corner frequency is given by: When the EN1 pin has a voltage applied of less than 0.4 V, the DC−DC converter block will be disabled. In shutdown mode, the internal reference, oscillator and most of the control circuitries are turned off. Therefore, the typical current consumption will be 0.2 mA (typical value). Applying a voltage above 1.2 V to EN1 pin will enable the DC−DC converter for normal operation. The device will go through soft−start to normal operation. fc + Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. If the junction temperature exceeds 160_C, the device shuts down. In this mode switch Q1 and Q2 and the control circuits are all turned off. The device restarts in soft−start after the temperature drops below 135°C. This feature is provided to prevent catastrophic failures from accidental device overheating and it is not intended as a substitute for proper heatsinking. The input voltage VIN1 must reach 2.5 V (typ) before the NCP1526 enables the DC−DC converter output to begin the startup sequence (see soft−start section). The UVLO threshold hysteresis is typically 100 mV. APPLICATION INFORMATIONS + 1 2p Ǹ2.2 mH 4.7 mF + 49.5 KHz Inductance (L) Output Capacitor (Cout) 1 mH 10 mF 2.2 mH 4.7 mF 4.7 mH 2.2 mF Inductor selection The inductor parameters directly related to device performances are saturation current and DC resistance and inductance value. The inductor ripple current (DIL) decreases with higher inductance: Input Capacitor Selection In PWM operating mode, the input current is pulsating with large switching noise. Using an input bypass capacitor can reduce the peak current transients drawn from the input supply source, thereby reducing switching noise significantly. The capacitance needed for the input bypass capacitor depends on the source impedance of the input supply. The maximum RMS current occurs at 50% duty cycle with maximum output current, which is IO, max/2. For NCP1526, a low profile ceramic capacitor of 4.7 mF should be used for most of the cases. For effective bypass results, the input capacitor should be placed as close as possible to the VIN Pin. ǒ Ǔ Vout V DIL + 1 * out L fsw Vin DIL peak to peak inductor ripple current L inductor value fsw Switching frequency The Saturation current of the inductor should be rated higher than the maximum load current plus half the ripple current: DI IL(MAX) + IO(MAX) ) L 2 Table 1. List of Input Capacitors TDK Cout Table 2. L−C Filter Example Undervoltage Lockout Taiyo Yuden 1 The device operates with inductance value between 1 mH and maximum of 4.7 mH. If the corner frequency is moved, it is recommended to check the loop stability depending of the output ripple voltage accepted and output current required. For lower frequency, the stability will be increase; a larger output capacitor value could be chosen without critical effect on the system. On the other hand, a smaller capacitor value increases the corner frequency and it should be critical for the system stability. Take care to check the loop stability. The phase margin is usually higher than 45°. Thermal Shutdown Murata 2p ǸL IL(MAX) Maximum inductor current IO(MAX) Maximum Output current The inductor’s resistance will factor into the overall efficiency of the converter. For best performances, the DC resistance should be less than 0.3 W for good efficiency. GRM188R60J475KE GRM21BR71C475KA JMK212BY475MG C2012X5ROJ475KB C1632X5ROJ475KT Output L−C filter Design Considerations: The NCP1526 is built in 3ĂMHz frequency and uses voltage mode architecture. The correct selection of the output filter ensures good stability and fast transient response. http://onsemi.com 11 NCP1526 LDO Operation Table 3. List of Inductors FDK MIPW3226 series TDK VLF3010AT series Taiyo Yuden LQ CBL2012 Voltage Regulator V1 V1 is a 2.80 V, 3% low drop voltage regulator dedicated to RF sensitive module. It can deliver up to 150 mA and is totally protected against short to ground (current limitation) and overtemperature (thermal shutdown circuit with hysteresis). The PSRR of the reference is in excess of 67 dB at 1.0 kHz. The output of the V1 requires a 1.0 mF capacitor for stability. An additional 100 nF capacitor is necessary on the BYPASS pin for a low output noise. If the BYPASS pin is supporting an additional load, the stability and performance of the V1 will be diminished. Since the input voltage can go as low as 3.0 V, the reference output will be affected and can drop as low as 150 mV below the input voltage at 150 mA output current. During this low dropout, the PSRR of the reference is reduced. V1 is active when logic high is applied to the EN2 pin. It is turned off by a logic low on the EN2 pin. DO1605−T series Coil craft LPO3008 Output capacitor selection Selecting the proper output capacitor is based on the desired output ripple voltage. Ceramic capacitors with low ESR values will have the lowest output ripple voltage and are strongly recommended. The output capacitor requires either an X7R or X5R dielectric. The output ripple voltage in PWM mode is given by: DVout + DIL ǒ4 1 fsw Cout Ǔ ) ESR Table 4. List of Output Capacitors Murata GRM188R60J475KE 4.7 mF Reference Bypass Capacitor Node (Bypass) An optional 100 nF BYPASS capacitor creates a low pass filter for LDO noise reduction. The output voltage noise is 45 mVRMS with CBYPASS = 0.1 mF and COUT = 1.0 mF. If the BYPASS pin is supporting an additional load, the stability and performance of the NCP1526 will be diminished. GRM21BR71C475KA Taiyo Yuden TDK GRM188R60OJ106ME 10 mF JMK212BY475MG 4.7 mF JMK212BJ106MG 10 mF C2012X5ROJ475KB 4.7 mF Current Limiting The output voltage regulator limits the output current to ISC = 300 mA (typ). If the LDO output current exceeds ISC, the output voltage drops. C1632X5ROJ475KT C2012X5ROJ106K 10 mF OUTPUT VOLTAGE OPTIONS AVAILABLE UPON REQUEST Shutdown Mode When the EN2 pin has a voltage applied of less than 0.4 V, the output voltage regulator will be disabled. In shutdown mode, the internal reference and most of the control circuitries are turned off. Therefore, the typical current consumption will be 0.2 mA (typical value). Applying a voltage above 1.2 V to EN2 pin will enable the LDO for normal operation. DC/DC Converter 0.9 1.0 1.1 1.2 1.3 OUTPUT VOLTAGE OPTIONS AVAILABLE UPON REQUEST 1.4 Fixed Output Voltage (V) 1.5 LDO 1.6 2.5 1.7 2.6 1.8 2.7 1.9 Fixed Output Voltage (V) 2.5 2.8 2.85 2.7 3.0 3.0 3.1 3.3 3.3 http://onsemi.com 12 NCP1526 APPLICATION BOARD PCB Layout Recommendations Good PCB layout plays an important role in switching mode power conversion. Careful PCB layout can help to minimize ground bounce, EMI noise and unwanted feedback that can affect the performance of the converter. Hints suggested below can be used as a guideline in most situations. 1. Use star−ground connection to connect the IC ground nodes and capacitor GND nodes together at one point. Keep them as close as possible, and then connect this to the ground plane through several vias. This will reduce noise in the ground plane by preventing the switching currents from flowing through the ground plane. 2. Place the power components (i.e., input capacitor, inductor and output capacitor) as close together as possible for best performance. All connecting traces must be short, direct, and wide to reduce voltage errors caused by resistive losses through the traces. 3. Separate the feedback path of the output voltage from the power path. Keep this path close to the NCP1526 circuit. And also route it away from noisy components. This will prevent noise from coupling into the voltage feedback trace. The following shows the NCP1526 demo board schematic and layout and bill of materials: Vbattery 1 OFF OFF BUCK ON LDO ON FB 2 EN1 3 EN2 4 GND2 5 BYPASS C1 VIN1 10 LX 9 GND1 8 VIN2 7 V1 6 L1 Vout BUCK Vout LDO C4 C2 C5 Figure 25. NCP1526 Board Schematic Figure 26. NCP1526 Board Layout http://onsemi.com 13 C3 NCP1526 J5 HEADER 2 2 1 EN1 T POINT A J9 Vin 1 2 3 en2 0 0 EN2 T POINT A J12 Vin 1 2 3 en2 0 J13 CON3 BNC H 0 0 4.7 m C1 CON3 BNC H Vin J10 U1 NCP1526 10 FB VIN1 L1 2.2 mH lx 9 EN1 LX 8 EN2 GND1 7 GND2 VIN2 Vout 2 BYPASS V1 6 11 EP C4 C3 C2 1m 4.7 m 100 n 1 en1 2 en2 3 4 bp 5 HEADER 2 Vout 1 1 2 HEADER 2 1 2 C5 4.7 m J7 0 J8 2 0 0 J6 0 1 JUMPER1 J11 2 1 JUMPER1 Figure 27. Schematics Figure 28. Board Layout (Top View) http://onsemi.com 14 0 0 NCP1526 Figure 29. Board Layout (Bottom View) Bill of Materials Item Part Description Ref PCB Footprint Manufacturer Manufacturer Reference 1 NCP1526 U1 UDFN ON Semiconductor NCP1526 2 4.7 mF ceramic capacitor 6.3 V X5R C1, C4, C5 0805 Murata GRM21 series 3 1 mF ceramic capacitor 6.3 V X5R C3 0805 Murata GRM21 series 4 100 nF ceramic capacitor 10 V X7R C2 0805 Murata GRM19 series 6 SMD Inductor L1 1605 Coilcraft DO1605 series 7 I/O connector, it can be plugged by BLZ5.08/2 (Weidmüller reference) J5, J6, J7 − Weidmüller SL5.08/2/90B 8 Jumper Header vertical mount 3*1, 2.54 mm J10, J13 − Tyco electronics/AMP 5−826629−0 9 Jumper connector, 400 mils J8, J11 − Harwin D3082−B01 http://onsemi.com 15 NCP1526 PACKAGE DIMENSIONS 10 PIN UDFN CASE 506AT−01 ISSUE O D PIN ONE REFERENCE 0.15 C 2X A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B ÍÍÍ ÍÍÍ ÍÍÍ E DIM A A1 A3 b D D2 E E2 e K L 0.15 C 2X A3 0.10 C A 10X 0.08 C MIN 0.45 0.00 0.18 2.40 1.70 0.30 MILLIMETERS NOM MAX 0.50 0.55 0.03 0.05 0.127 REF 0.25 0.30 3.00 BSC 2.50 2.60 3.00 BSC 1.80 1.90 0.50 BSC 0.19 TYP 0.40 0.50 SOLDERING FOOTPRINT* A1 C 2.6016 SEATING PLANE D2 10X L 1 e 5 8X 2.1746 1.8508 3.3048 E2 10X K 10 10X 6 b 0.5651 10X 0.10 C A 0.05 C 10X 0.3008 B 0.5000 PITCH DIMENSIONS: MILLIMETERS NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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