SAMSUNG K7P161866A-HC33

K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
Document Title
512Kx36 & 1Mx18 Synchronous Pipelined SRAM
Revision History
Draft Date
Remark
- Initial Document
Dec. 2001
Advance
- Absolute maximum ratings are changed
VDD : 2.815 - > 3.13
VDDQ : 2.815 - > 2.4
VTERM : 2.815 - > VDDQ+0.5 (2.4V MAX)
Oct. 2002
Advance
Rev. No.
History
Rev. 0.0
Rev. 0.1
- Recommended DC operating conditions are changed
VREF / VCM-CLK : 0.68 - > 0.6, 0.95 - > 0.9
- DC characteristics is changed
ISBZZ : 150 - > 128
- AC Characteristics are changed
TAVKH / TDVKH / TWVKH / TSVKH : 0.4 / 0.5 / 0.5 - > 0.3 / 0.3 / 0.3
TKHAX / TKHDX / TKHWX / TKHSX : 0.5 / 0.5 / 0.5 - > 0.5 / 0.6 / 0.6
Rev. 0.2
- Recommended DC operating condition is changed
Max VDIF-CLK : VDDQ+0.3 -> VDDQ+0.6
Jan. 2003
Advance
Rev. 0.3
- Correct typo
VDD -> VDDQ: in MODE CONTROL at page4
Sep. 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
512Kx36 & 1Mx18 Synchronous Pipelined SRAM
FEATURES
• 512Kx36 or 1Mx18 Organizations.
• 2.5V Core/1.5V Output Power Supply (1.9V max VDDQ).
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).
Organization
512Kx36
1Mx18
Part Number
Maximum
Frequency
Access
Time
K7P163666A-HC33
333MHz
1.5
K7P163666A-HC30
300MHz
1.6
K7P163666A-HC25
250MHz
2.0
K7P161866A-HC33
333MHz
1.5
K7P161866A-HC30
300MHz
1.6
K7P161866A-HC25
250MHz
2.0
Read
Address
Register
SA[0:18] or SA[0:19]
1
Write
Address
Register
CK
Latch
SS
SW
SW
Register
SW
Register
SWx
Register
SWx
Register
SS
Register
SS
Register
0
Row Decoder
FUNCTIONAL BLOCK DIAGRAM
Column Decoder
Write/Read Circuit
Latch
SWx
(x=a, b, c, d)
or (x=a, b)
512Kx36
or
1Mx18
Array
0
1
Data In
Register
Data Out
Register
G
ZZ
K
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
CK
K
PIN DESCRIPTION
Pin Name
Pin Description
Pin Name
Pin Description
K, K
Differential Clocks
SAn
Synchronous Address Input
DQn
Bi-directional Data Bus
G
Asynchronous Output Enable
SW
Synchronous Global Write Enable
SS
Synchronous Select
SWa
Synchronous Byte a Write Enable
TCK
JTAG Test Clock
SWb
Synchronous Byte b Write Enable
TMS
JTAG Test Mode Select
VREF
M 1 , M2
HSTL Input Reference Voltage
Read Protocol Mode Pins ( M1=VSS, M2=VDDQ )
SWc
Synchronous Byte c Write Enable
TDI
JTAG Test Data Input
SWd
Synchronous Byte d Write Enable
TDO
JTAG Test Data Output
ZZ
Asynchronous Power Down
ZQ
Output Driver Impedance Control
VDD
Core Power Supply
VSS
GND
VDDQ
Output Power Supply
NC
No Connection
-2-
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7P163666A(512Kx36)
1
2
3
4
5
6
7
A
VDDQ
SA13
SA10
NC
SA7
SA4
VDDQ
B
NC
SA18
SA9
NC
SA8
SA17
NC
C
NC
SA12
SA11
VDD
SA6
SA5
NC
D
DQc8
DQc9
VSS
ZQ
VSS
DQb9
DQb8
E
DQc6
DQc7
VSS
SS
VSS
DQb7
DQb6
F
VDDQ
DQc5
VSS
G
VSS
DQb5
VDDQ
G
DQc3
DQc4
SWc
NC
SWb
DQb4
DQb3
H
DQc1
DQc2
VSS
NC
VSS
DQb2
DQb1
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
DQd1
DQd2
VSS
K
VSS
DQa2
DQa1
L
DQd3
DQd4
SWd
K
SWa
DQa4
DQa3
M
VDDQ
DQd5
VSS
SW
VSS
DQa5
VDDQ
N
DQd6
DQd7
VSS
SA0
VSS
DQa7
DQa6
P
DQd8
DQd9
VSS
SA1
VSS
DQa9
DQa8
R
NC
SA15
M1
VDD
M2
SA2
NC
T
NC
NC
SA14
SA16
SA3
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
1
2
3
4
5
6
7
A
VDDQ
SA13
SA10
NC
SA7
SA4
VDDQ
B
NC
SA19
SA9
NC
SA8
SA17
NC
C
NC
SA12
SA11
VDD
SA6
SA5
NC
D
DQb1
NC
VSS
ZQ
VSS
DQa9
NC
E
NC
DQb2
VSS
SS
VSS
NC
DQa8
F
VDDQ
NC
VSS
G
VSS
DQa7
VDDQ
G
NC
DQb3
SWb
NC
NC
NC
DQa6
H
DQb4
NC
VSS
NC
VSS
DQa5
NC
K7P161866A(1Mx18)
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
NC
DQb5
VSS
K
VSS
NC
DQa4
L
DQb6
NC
NC
K
SWa
DQa3
NC
M
VDDQ
DQb7
VSS
SW
VSS
NC
VDDQ
N
DQb8
NC
VSS
SA0
VSS
DQa2
NC
P
NC
DQb9
VSS
SA1
VSS
NC
DQa1
R
NC
SA15
M1
VDD
M2
SA2
NC
T
NC
SA18
SA14
NC
SA3
SA16
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
-3-
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
FUNCTION DESCRIPTION
The K7P163666A and K7P161866A are 18,874,368 bit Synchronous Pipeline Mode SRAM. It is organized as 524,288 words of 36
bits(or 1,048,576 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology.
Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the
updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one
cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second
edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this
cycle, signaling that the SRAM should drive out the data.
During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multiple SRAM cycles to perform a single read operation.
Write (Stire) Operation
All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,
one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the
Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.
Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write
cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of
read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the
same as the SW signal.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be
done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is
the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.
Programmable Impedance Output Buffer Operation
This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance
can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM
and VSS. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250Ω
resistor will give an output buffer impedance of 50Ω. The allowable range of RQ is from 175Ω to 350Ω. Internal circuits evaluate and
periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evaluation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the
optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.
Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance
match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum
number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configuration by connecting ZQ to VSS or VDD.
Mode Control
There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDDQ. These
mode pins must be set at power-up and must not change during device operation.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.
Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
-4-
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
FUNCTION DESCRIPTION
The K7P163666A and K7P161866A are 18,874,368 bit Dual Mode (supports both Register Register and Late Select Mode) SRAM
devices. They are organized as 524,288 words by 36 bits for K7P163666A and 1,048,576 words by 18 bits for K7P161866A, fabricated using Samsung's advanced CMOS technology. Late Write/Pipelined Read(RR) for x36/x18 organizations and Late Write/Late
Select Read(LS) for x36 organization are supported.
The chip is operated with a single +2.5V power supply and is compatible wtih HSTL input and output. The package is 119(7x17)
Plastic Ball Grid Array with balls on a 1.27mm pitch.
Read Operation for Register Register Mode(x36 and x18)
During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is
read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock.
Read Operation for Late Select Mode(x36)
During read operations, addresses(SA) and controls except the Way Select Address(SAS) are registered during the first rising edge
of K clock. The internal array(x72 bit data) is read between the first edge and the second edge, and as the Way Select Address(SAS)
is registered at the second clock edge, x36 bit data is mux selected before the output register.
Write Operation(Late Write)
During write operations, addresses including the Way Select Address(SAS) and controls are registered at the first rising edge of K
clock and data inputs are registered at the following rising edge of K clock. Write addresses and data inputs are stored in the data in
registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM array. Byte write
operation is supported using SW[a:d] and the timing of SW[a:d] is the same as the SW signal.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be
done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is
the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.
Programmable Impedance Output Buffer Operation
This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance
can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM
and VSS. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250Ω
resistor will give an output buffer impedance of 50Ω. The allowable range of RQ is from 175Ω to 350Ω. Internal circuits evaluate and
periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evaluation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the
optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.
Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance
match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum
number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configuration by connecting ZQ to VSS or VDD.
Mode Control
There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDD. These
mode pins must be set at power-up and must not change during device operation.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.
Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
-5-
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
TRUTH TABLE
K
ZZ
G
SS
SW
SWa
SWb
SWc
SWd
DQa
DQb
DQc
DQd
Operation
X
H
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Power Down Mode. No Operation
X
L
H
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Output Disabled.
↑
L
L
H
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Output Disabled. No Operation
↑
L
L
L
H
X
X
X
X
DOUT DOUT DOUT DOUT Read Cycle
↑
L
X
L
L
H
H
H
H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
No Bytes Written
↑
L
X
L
L
L
H
H
H
DIN
Hi-Z
Hi-Z
Hi-Z
Write first byte
↑
L
X
L
L
H
L
H
H
Hi-Z
DIN
Hi-Z
Hi-Z
Write second byte
↑
L
X
L
L
H
H
L
H
Hi-Z
Hi-Z
DIN
Hi-Z
Write third byte
↑
L
X
L
L
H
H
H
L
Hi-Z
Hi-Z
Hi-Z
DIN
Write fourth byte
↑
L
X
L
L
L
L
L
L
DIN
DIN
DIN
DIN
Write all bytes
NOTE : K & K are complementary
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Core Supply Voltage Relative to VSS
VDD
-0.5 to 3.13
V
Output Supply Voltage Relative to VSS
VDDQ
-0.5 to 2.4
V
Voltage on any I/O pin Relative to VSS
VTERM
-0.5 to VDDQ+0.5 (2.4V MAX)
V
Output Short-Circuit Current
IOUT
25
mA
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature
TSTG
-55 to 125
°C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Core Power Supply Voltage
Parameter
VDD
2.37
2.5
2.63
V
Output Power Supply Voltage
VDDQ
1.4
1.5
1.9
V
VIH
VREF+0.1
-
VDDQ+0.3
V
Input High Level
VIL
-0.3
-
VREF-0.1
V
VREF
0.6
0.75
0.9
V
Clock Input Signal Voltage
VIN-CLK
-0.3
-
VDDQ+0.3
V
Clock Input Differential Voltage
VDIF-CLK
0.1
-
VDDQ+0.6
V
Clock Input Common Mode Voltage
VCM-CLK
0.6
0.75
0.9
V
Input Low Level
Input Reference Voltage
-6-
Note
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
PIN CAPACITANCE
Parameter
Input Capacitance
Data Output Capacitance
Symbol
Test Condition
Min
Max
Unit
CIN
VIN=0V
-
4
pF
COUT
VOUT=0V
-
5
pF
NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=1MHz)
DC CHARACTERISTICS
Symbol
Min
Max
Unit
Note
Average Power Supply Operating Current-x36
(VIN=VIH or VIL, ZZ & SS=VIL)
IDD33
IDD30
IDD25
-
700
620
550
mA
1, 2
Average Power Supply Operating Current-x18
(VIN=VIH or VIL, ZZ & SS=VIL)
IDD33
IDD30
IDD25
-
650
570
500
mA
1, 2
Power Supply Standby Current
(VIN=VIH or VIL, ZZ=VIH)
ISBZZ
-
128
mA
1
Active Standby Power Supply Current
(VIN=VIH or VIL, SS=VIH, ZZ=VIL)
ISBSS
-
200
mA
1
Input Leakage Current
(VIN=VSS or VDDQ)
ILI
-1
1
µA
Output Leakage Current
(VOUT=VSS or VDDQ, DQ in High-Z)
ILO
-1
1
µA
Output High Voltage(Programmable Impedance Mode)
VOH1
VDDQ/2
VDDQ
V
3,5
Output Low Voltage(Programmable Impedance Mode)
VOL1
VSS
VDDQ/2
V
4,5
Output High Voltage(IOH=-0.1mA)
VOH2
VDDQ-0.2
VDDQ
V
6
Output Low Voltage(IOL=0.1mA)
VOL2
VSS
0.2
V
6
Output High Voltage(IOH=-6mA)
VOH3
VDDQ-0.4
VDDQ
V
6
Output Low Voltage(IOL=6mA)
VOL3
VSS
0.4
V
6
Parameter
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω.
5. Programmable Impedance Output Buffer Mode. The ZQ pin is connected to VSS through RQ.
6. Minimum Impedance Output Buffer Mode. The ZQ pin is connected to VSS or VDD.
-7-
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
AC TEST CONDITIONS (TA=0 to 70°C, VDD=2.37 -2.63V, VDDQ=1.5V)
Parameter
Symbol
Value
Unit
VDD
2.37~2.63
V
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
VDDQ
1.5
V
VIH/VIL
1.25/0.25
V
Input Reference Level
VREF
0.75
V
Input Rise/Fall Time
TR/TF
0.5/0.5
ns
0.75
V
Cross Point
V
Input and Out Timing Reference Level
Clock Input Timing Reference Level
NOTE : Parameters are tested with RQ=250Ω and VDDQ=1.5V.
AC TEST OUTPUT LOAD
50Ω
50Ω
VDDQ/2
5pF
25Ω
DQ
VDDQ/2
50Ω
50Ω
VDDQ/2
5pF
AC CHARACTERISTICS
Parameter
Symbol
-33
-30
-25
Min
Max
Min
Max
Min
Max
Unit
Clock Cycle Time
tKHKH
3.0
-
3.3
-
4.0
-
ns
Clock High Pulse Width
tKHKL
1.2
-
1.3
-
1.6
-
ns
Clock Low Pulse Width
tKLKH
1.2
-
1.3
-
1.6
-
ns
Clock High to Output Valid
tKHQV
-
1.5
-
1.6
-
2.0
ns
Clock High to Output Hold
tKHQX
0.5
-
0.5
-
0.5
-
ns
Address Setup Time
tAVKH
0.3
-
0.3
-
0.3
-
ns
Address Hold Time
tKHAX
0.5
-
0.6
-
0.6
-
ns
Write Data Setup Time
tDVKH
0.3
-
0.3
-
0.3
-
ns
Write Data Hold Time
tKHDX
0.5
-
0.6
-
0.6
-
ns
SW, SW[a:d] Setup Time
tWVKH
0.3
-
0.3
-
0.3
-
ns
SW, SW[a:d] Hold Time
tKHWX
0.5
-
0.6
-
0.6
-
ns
SS Setup Time
tSVKH
0.3
-
0.3
-
0.3
-
ns
SS Hold Time
tKHSX
0.5
-
0.6
-
0.6
-
ns
Clock High to Output Hi-Z
tKHQZ
-
1.5
-
1.6
-
2.0
ns
Clock High to Output Low-Z
tKHQX1
0.5
-
0.5
-
0.5
-
ns
G High to Output High-Z
tGHQZ
-
1.5
-
1.6
-
2.0
ns
G Low to Output Low-Z
tGLQX
0.5
-
0.5
-
0.5
-
ns
G Low to Output Valid
tGLQV
-
1.5
-
1.6
-
2.0
ns
ZZ High to Power Down(Sleep Time)
tZZE
-
15
-
15
-
15
ns
ZZ Low to Recovery(Wake-up Time)
tZZR
-
20
-
20
-
20
ns
-8-
Note
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low)
1
2
3
4
5
6
7
8
K
tKHKH
tAVKH
SAn
A1
tKHAX
tKHKL
tKLKH
A2
A3
A4
A5
A4
A6
A7
tKHSX
tSVKH
SS
tWVKH
tKHWX
tWVKH
tKHWX
tKHWX
tWVKH
SW
SWx
tKHQZ
tKHQV
Q2
Q1
DQn
tKHDX
tDVKH tKHDX
tKHQX
tKHQX1
D4
D3
Q5
Q4
NOTE
1. D3 is the input data written in memory location A3.
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the
last write cycle address.
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (G Controlled, SS=Low)
1
2
3
4
5
6
7
8
K
tKHKH
SAn
A1
A3
A2
A4
A5
A4
A6
A7
G
SW
SWx
tGHQZ
tGLQV
tGLQX
DQn
Q1
Q2
D3
D4
Q5
Q4
NOTE
1. D3 is the input data written in memory location A3.
2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last
write cycle address.
-9-
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
TIMING WAVEFORMS OF STANDBY CYCLES
1
2
3
4
5
6
7
8
K
tKHKH
SAn
A1
A2
A1
A2
A3
SS
SW
SWx
tZZR
tZZE
ZZ
tKHQV
tKHQV
DQn
Q1
Q2
Q1
- 10
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must
be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left
unconnected.
JTAG Instruction Coding
JTAG Block Diagram
IR2 IR1 IR0 Instruction
SRAM
CORE
M1
M2
TDI
BYPASS Reg.
TDO
Identification Reg.
Instruction Reg.
Notes
0
0
SAMPLE-Z Boundary Scan Register
0
0
1
IDCODE
0
1
0
SAMPLE-Z Boundary Scan Register
Identification Register
1
2
1
0
1
1
BYPASS
Bypass Register
3
1
0
0
SAMPLE
Boundary Scan Register
4
1
0
1
BYPASS
Bypass Register
3
1
1
0
BYPASS
Bypass Register
3
1
1
1
BYPASS
Bypass Register
3
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
3. Bypass register is initiated to VSS when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI when
exiting the Shift DR states.
4. SAMPLE instruction does not places DQs in Hi-Z.
Control Signals
TMS
TCK
TDO Output
0
TAP Controller
TAP Controller State Diagram
1
Test Logic Reset
0
0
Run Test Idle
1
Select DR
0
1
1
Exit2 DR
1
Update DR
0
- 11
1
Capture IR
0
0
1
Exit1 DR
0
Pause DR
1
Select IR
0
1
Capture DR
0
Shift DR
1
1
1
0
0
Shift IR
1
0
Exit1 IR
0
Pause IR
1
Exit2 IR
1
Update IR
1
0
0
0
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
ID Register
Boundary Scan
512Kx36
3 bits
1 bits
32 bits
70 bits
1Mx18
3 bits
1 bits
32 bits
51 bits
ID REGISTER DEFINITION
Part
Revision Number
(31:28)
Part Configuration
(27:18)
Vendor Definition
(17:12)
Samsung JEDEC Code
(11: 1)
Start Bit(0)
512Kx36
0000
00111 00100
XXXXXX
00001001110
1
1Mx18
0000
01000 00011
XXXXXX
00001001110
1
BOUNDARY SCAN EXIT ORDER(x36)
BOUNDARY SCAN EXIT ORDER(x18)
36
3B
SA9
SA8
5B
35
26
3B
SA9
SA8
5B
25
37
2B
SA18
SA17
6B
34
27
2B
SA19
SA17
6B
24
38
3A
SA10
SA7
5A
33
28
3A
SA10
SA7
5A
23
39
3C
SA11
SA6
5C
32
29
3C
SA11
SA6
5C
22
40
2C
SA12
SA5
6C
31
30
2C
SA12
SA5
6C
21
41
2A
SA13
SA4
6A
30
31
2A
SA13
SA4
6A
20
42
2D
DQc9
DQb9
6D
29
DQa9
6D
19
43
1D
DQc8
DQb8
7D
28
32
1D
DQb1
44
2E
DQc7
DQb7
6E
27
33
2E
DQb2
45
1E
DQc6
DQb6
7E
26
DQa8
7E
18
46
2F
DQc5
DQb5
6F
25
DQa7
6F
17
47
2G
DQc4
DQb4
6G
24
48
1G
DQc3
DQb3
7G
23
DQa6
7G
16
49
2H
DQc2
DQb2
6H
22
DQa5
6H
15
50
1H
DQc1
DQb1
7H
21
35
1H
DQb4
51
3G
SWc
SWb
5G
20
36
3G
SWb
52
4D
ZQ
G
4F
19
37
4D
ZQ
G
4F
14
53
4E
SS
K
4K
18
38
4E
SS
K
4K
13
54
4G
NC*
12
55
4H
NC*
56
4M
1
34
2G
DQb3
K
4L
17
39
4G
NC
K
4L
SWa
5L
16
40
4H
NC
SWa
5L
11
SW
DQa1
7K
15
41
4M
SW
DQa4
7K
10
DQa3
6L
9
1
57
3L
SWd
DQa2
6K
14
58
1K
DQd1
DQa3
7L
13
59
2K
DQd2
DQa4
6L
12
42
2K
DQb5
60
1L
DQd3
DQa5
6M
11
43
1L
DQb6
61
2L
DQd4
DQa6
7N
10
62
2M
DQd5
DQa7
6N
9
44
2M
DQb7
DQa2
6N
8
63
1N
DQd6
DQa8
7P
8
45
1N
DQb8
DQa1
7P
7
64
2N
DQd7
DQa9
6P
7
ZZ
7T
6
46
2P
DQb9
SA3
5T
5
SA2
6R
4
3
65
1P
DQd8
ZZ
7T
6
66
2P
DQd9
SA3
5T
5
67
3T
SA14
SA2
6R
4
47
3T
SA14
68
2R
SA15
SA16
4T
3
48
2R
SA15
69
4N
SA0
SA1
4P
2
70
3R
M1
M2
5R
1
49
4N
SA0
SA1
4P
50
2T
SA18
SA16
6T
2
51
3R
M1
M2
5R
1
NOTE :1. Pins 4G and 4H are no connection pin to internal chip. The scanned data are fixed to "0" and "1" respectively.
- 12
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VDD
2.37
Input High Level
VIH
1.7
2.5
2.63
V
-
VDD+0.3
V
Input Low Level
VIL
-0.3
-
0.8
V
Output High Voltage(IOH=-2mA)
VOH
2.1
-
VDD
V
Output Low Voltage(IOL=2mA)
VOL
VSS
-
0.2
V
Note
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Symbol
Min
Unit
Input High/Low Level
Parameter
VIH/VIL
2.5/0.0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
ns
1.25
V
Input and Output Timing Reference Level
Note
1
NOTE : 1. See SRAM AC test output load on page 7.
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
tCHCH
50
-
ns
TCK High Pulse Width
tCHCL
20
-
ns
TCK Low Pulse Width
tCLCH
20
-
ns
TMS Input Setup Time
tMVCH
5
-
ns
TMS Input Hold Time
tCHMX
5
-
ns
TDI Input Setup Time
tDVCH
5
-
ns
TDI Input Hold Time
tCHDX
5
-
ns
SRAM Input Setup Time
tSVCH
5
-
ns
SRAM Input Hold Time
tCHSX
5
-
ns
Clock Low to Output Valid
tCLQV
0
10
ns
TCK Cycle Time
Note
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLCH
TMS
TDI
PI
(SRAM)
tCLQV
TDO
- 13
Sep. 2003
Rev 0.3
K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
119 BGA PACKAGE DIMENSIONS
14.00±0.10
1.27
1.27
22.00±0.10
Indicator of
Ball(1A) Location
20.50±0.10
C0.70
C1.00
0.750±0.15
1.50REF
0.60±0.10
NOTE :
1. All Dimensions are in Millimeters.
2. Solder Ball to PCB Offset : 0.10 MAX.
3. PCB to Cavity Offset : 0.10 MAX.
0.60±0.10
12.50±0.10
119 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter
Symbol
Thermal Resistance
Unit
Note
1W Heating
Junction to Ambient(at still air)
Theta_JA
TBD
°C/W
Junction to Case
Theta_JC
TBD
°C/W
Junction to Board
Theta_JB
TBD
°C/W
2W Heating
NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA.
- 14
Sep. 2003
Rev 0.3