Ordering number : EN8765 Monolithic Linear IC LA6541ND For CD Players and Recorders Four-Channel Driver IC Overview The LA6541ND is a four-channel driver IC for CD players and recorders (four BTL amplifier channels). Features • Four BTL connection power amplifier channels • IO max 0.7A • Built-in level shifters • Muting circuit (on/off control of all outputs) (This circuit applies to the BTL amplifier circuits. It does not control operation of the regulator.) • Built-in regulator (provides a 5V output using an external pnp transistor) • Thermal protection circuit (thermal shutdown circuit) Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage Symbol Conditions VCC max For each of the channel 1 to 4 outputs Ratings Unit 14 V 0.7 A Maximum output current IO max Maximum input voltage VIN 13 V Muting pin application voltage VMUTE 13 V Allowable power dissipation Pd max 1.5 W Operating temperature Topr -20 to +75 °C Storage temperature Tstg -55 to +150 °C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 32807 TI IM B8-7420 No.8765-1/9 LA6541ND Recommended Operating Conditions at Ta = 25°C Parameter Symbol Supply voltage 1 VCC1 Supply voltage 2 VCC2 Conditions Ratings Only used by the BTL amplifiers (Not used by the 5V regulator circuit) Unit 5.6 to 13.0 V 3.9 to 13.0 V Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 8V, VREF = 2.5V, unless especially specified. Parameter Symbol Ratings Conditions min typ Unit max Overall Characteristics No-load current drain, on state ICCON All outputs on, MUTE: high 20 40 mA No-load current drain, off state ICCOFF All outputs off, MUTE: low 15 35 mA 175 200 °C -50 50 mV 1.5 VCC-1.5 Thermal shutdown circuit TSD (Design guarantee value *1) operating temperature 150 Output Amplifier Block Output offset voltage VOFF The voltage difference between each of the + or - outputs. VREF input voltage range VINVREF Output voltage Voltage gain, input to output VO The voltage across the outputs when VG RL = 8Ω The voltage gain from an input to the 4 corresponding +/- outputs. *2 Slew rate Muting on voltage SR VMUTE (Design guarantee value *1) The voltage at which the output on/off state changes V 4.7 V 9 dB 0.15 V/µs 1.2 V Power Supply Block (Using a 2SB632K) 5V power supply voltage IO = 200mA 4.75 5.00 5.25 V Line regulation ∆VOLIN 5.6V ≤ VCC ≤ 12V 20 100 mV Load regulation ∆VOLOAD 5mA ≤ IO ≤ 200mA 50 150 mV Reset Block RESET pin high-level voltage VORH RESET pin low-level voltage VORL RESET pin threshold voltage RESET pin hysteresis RESET pin output delay time 4.98 5.23 V ISRL = 2mA, Cd-GND 100 200 mV VRT *4 4.2 VHYS *5 td 4.73 Cd = 0.1µF 40 80 10 V 200 mV ms *1: These parameters are not tested. *2: The gain from input to output when only the VIN* pins are used. *3: The MUTE pin voltage when the output changes between the on and off states. When the MUTE pin is high, all the BTL amplifiers will be on, and the when MUTE is low, all the BTL amplifiers will be off. *4: The 5V regulator voltage when the RESET pin goes from high to low. *5: The 5V regulator voltage difference between the RESET pin going from high to low the RESET pin going from low to high. That is, the hysteresis. No.8765-2/9 LA6541ND Package Dimensions unit : mm (typ) 3307 27.0 10.16 16 8.6 30 15 0.25 1 0.51 min (3.25) 3.0 3.95 max 0.95 0.48 (1.04) 1.78 SANYO : DIP30SDLF(400mil) Pd max - Ta Allowable power dissipation, Pd max - W 2.0 1.5 Independent IC 1.5 1.0 0.9 0.5 0 --20 0 20 40 60 Ambient temperature, Ta - °C 80 100 ILA07099 No.8765-3/9 LA6541ND Block Diagram VCC1 1 MUTE 2 30 VCC2 29 VREF 28 VIN4 MUTE (output on/off control) + 15.4kΩ 15.4kΩ 11kΩ VIN1 3 11kΩ - - + + 27 VG4 VO1+ 5 26 VO4+ VO1- 6 25 VO4- GND 7 24 GND GND 8 23 GND 22 GND 21 VO3- 20 VO3+ 19 VIN3G 18 VIN3 17 CD 16 RESET Level shifter 4 Level shifter VG1 - VO2- 10 VO2+ 11 VG2 12 Level shifter 9 Level shifter + GND 15.4kΩ 15.4kΩ 11kΩ 11kΩ VIN2 13 REG_C 14 REG_B 15 - - + + Connect to the external PNP taransistor collector Connect to the external PNP taransistor base 5VREG RESET No.8765-4/9 LA6541ND Pin Functions Pin No. Pin Name 1 VCC1 Power supply (This pin is shorted to VCC2 (pin 30) Description 2 MUTE Output on/off control 3 VIN1 Channel 1 input 4 VG1 Channel 1 input (Gain setting) 5 VO1+ Channel 1 output (+) 6 VO1- Channel 1 output (-) 7 GND GND pin 8 GND GND pin 9 GND GND pin 10 VO2- Channel 2 output (-) 11 VO2+ Channel 2 output (+) 12 VG2 Channel 2 input (Gain setting) 13 VIN2 Channel 2 input 14 REG_C Connect this pin to the external pnp transistor collector. (This is the 5V regulator output) 15 REG_B Connect this pin to the external pnp transistor base. 16 RESET Reset output 17 CD 18 VIN3 Channel 3 input (Gain setting) 19 VG3 Channel 3 input (Gain setting) 20 VO3+ Channel 3 output (+) 21 VO3- Channel 3 output (-) 22 GND GND pin 23 GND GND pin 24 GND GND pin 25 VO4- Channel 4 output (-) 26 VO4+ Channel 4 output (+) 27 VG4 Channel 4 input (Gain setting) 28 VIN4 Channel 4 input (Gain setting) 29 VREF Reference voltage input 30 VCC2 Power supply (This pin is shorted to VCC1 (pin 1) Connection for the reset delay time setting capacitor No.8765-5/9 LA6541ND Equivalent Circuits 3 4 13 12 18 19 28 27 Pin Description Name VIN1 VG1 Equivalent Circuit Input pins. VIN* VING* VIN2 VG2 VCC VIN3 VG3 GND GND VCC 11kΩ Pin No. VCC VIN4 VG4 GND 6 11 10 20 21 26 25 VO1+ VO1- Output pins. VCC VO2+ VO2- 33kΩ 5 VO3+ VO3- VCC VO4+ VO4- VO* -/+ GND GND 2 MUTE Muting control input. VCC The outputs will be on when the MUTE VCC pin is at the high level. pin is at the low level; in particular, the MUTE outputs go to the high-impedance state at GND this time. 29 VREF Reference voltage input. 30kΩ 40kΩ The outputs will be off when the MUTE VREF VCC VCC GND GND Continued on next page. No.8765-6/9 LA6541ND Continued from preceding page. Pin No. 16 Pin Description Name RESET Equivalent Circuit Reset output. VCC When REG C (5VREG) is high, RESET will be high. REG_C(5VREG) When REG C (5VREG) is low, RESET GND VCC will be low. See section 11, Reset Operation, for details on the reset operation. RESET GND GND 17 CD Reset output delay time setting. The delay time until the point the reset output switches from low to high is set by the capacitor connected between this pin and ground. See section 11, Reset Operation, for details on the reset operation. VCC GND GND CD No.8765-7/9 LA6541ND Application Circuit Example VCC 1 MUTE VCC1 VCC2 30 2 MUTE MUTE 29 3 VIN1 VIN4 28 4 VG1 VG4 27 5 VO1+ VO4+ 26 SPINDLE input SPINDLE VREF input (Reference voltage) FOCUS input FOCUS M 6 VO1- VO4- 25 7 GND GND 24 LA6541ND 8 GND GND 23 9 GND GND 22 10 VO2- VO3- 21 TRACKING M SLED 11 VO2+ VO3+ 20 12 VG2 VIN3G 19 13 VIN2 VIN3 18 TRACKING input SPINDLE input 5V output + 14 REG_C CD 17 Reset delay time input 100µF 15 REG_B RESET 16 VCC No.8765-8/9 LA6541ND Reset Operation REG_C (5VREG) 5V 100mV 4.2V T RESET T td td *1: td is the delay time. It is set by an external capacitor connected between the CD pin and ground. *2: The voltage at which RESET changes state is a typical value (voltage). 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2007. Specifications and information herein are subject to change without notice. PS No.8765-9/9