Ordering number : EN5904 LA6543M Monolithic Linear IC LA6543M 4-Channel Bridge (BTL) Driver for CD-ROM Overview Package Dimensions The LA6543M is a 4-channel bridge (BTL) driver developed for CD-ROM applications. unit: mm 3129-MFP36SLF [LA6543M] Functions 19 36 1 18 0.25 0.4 0.8 0.85 0.1 • Divided output stage power supply (VS1: CH1, CH2, CH3; VS2: CH4) 2.25 2.5max 15.3 0.65 7.9 • Integrated muting circuit (MUTE: Output OFF at Low, output ON at High. MUTE1 is for channel 1, and MUTE2 for channels 2, 3 and 4.) • Integrated thermal shutdown circuit 9.2 10.5 • 4-channel power amplifier with bridge circuit (BTL) • IO max: 1A SANYO : MFP36SLF Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage 1 Symbol Conditions Ratings VCCmax Unit 14 V Maximum supply voltage 2 VSmax VS1, 2 14 V Input voltage VINmax Input pins VIN1 to 4 13 V Mute pin voltage Allowable power dissipation 13 V IC only 0.9 W Specified substrate Note 1 2.1 W VMUTEmax Pd max Operating temperature Topr – 20 to +75 °C Storage temperature Tstg – 55 to +150 °C Note 1: Specified substrate 76.1 x 114.3 x 1.6 (t)mm, glass exposy Operating Conditions at Ta = 25°C Parameter Symbol Recommended operation voltage 1 VCC Recommended operation voltage 2-1 VS1 Recommended operation voltage 2-2 VS2 Conditions Ratings Unit 4 to 13 V VS1: CH1 to CH3 4 to 13 V VS2: CH4 output reference power supply 4 to 13 V *VCC > VS1, 2 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N1798RM(KI) No. 5904-1/7 LA6543M Electrical Characteristics at VCC = 12V, VS = 5V, Ta = 25°C Parameter Symbol Ratings Conditions min VCC no-load current drain VS1 no-load current drain VS2 no-load current drain Output offset voltage All outputs ON (MUTE1, MUTE2: High) ICC2 All outputs OFF (MUTE1, MUTE2: Low) 5 10 mA IS1-1 CH1 - CH2 ON (MUTE1, MUTE2: High) 20 30 mA IS1-2 CH1 - CH2 OFF (MUTE1, MUTE2: Low) 4 mA IS2-1 CH3 - CH4 ON (MUTE1, MUTE2: High) 10 mA IS2-2 CH3 - CH4 OFF (MUTE1, MUTE2: Low) 4 mA +50 mV VIN Output voltage (source) 5 Unit max ICC 1 VOF1 to 4 Input voltage range typ 10 5 Potential difference between plus and minus outputs for CH1 to CH4 –50 0.5 Input voltage range for VIN1 to VIN4 Vsource Plus and minus outputs at high level 4.4 20 5 4.7 mA V V I O = 700 mA (sink) Vsink Plus and minus outputs at low level 0.3 0.6 V I O = 700 mA Closed circuit voltage gain Slew rate VG1 Voltage gain between CH1 to CH3 BTL amplifiers VG2 Voltage gain between CH4 BTL amplifiers SR 7 dB 14 dB (Note 1) 0.5 V/µs Mute ON voltage VMUTE MUTE1, MUTE2 voltage when output is ON (Note 2) 1.5 2 V Mute ON current IMUTE MUTE1, MUTE2 current when output is ON (Note 2) 6 10 µA Allowable power dissipation, Pd max – mW Note 1: Guaranteed design value Note 2: MUTE turns amplifier output ON at High and OFF at Low. (Output impedance becomes high.) This applies to MUTE1 and MUTE2. Pd max – Ta 2.4 With substrate 2.1 IC only 0.9 2.0 1.6 1.2 0.8 0.4 0 –20 0 20 40 60 75 80 100 Ambient temperature, Ta – ˚C No. 5904-2/7 LA6543M Pin Assignment RF 1 36 RF RF 2 35 RF NC 3 34 VSS1 VSS2 4 33 VSS1-OUT VSS2-OUT 5 32 VO1 MUTE1 6 31 VO2 VIN1 7 30 VS1 VG1 8 29 VO3 VIN2 9 28 VO4 VG2 10 27 VO5 VIN3 11 26 VO6 VG3 12 25 VS2 VIN4 13 24 VO7 VG4 14 23 VO8 MUTE2 15 22 VREF OUT VCC 16 21 VREF IN RF 17 20 RF RF 18 19 RF LA6543M Top view A11323 No. 5904-3/7 LA6543M Pin Function Pin number Pin name Equivalent circuit Pin function 1, 2 17, 18 19, 20 RF Substrate (minimum potential) VCC 35, 36 16 7 V IN1 Input pin for CH1 9 V IN2 Input pin for CH2 11 V IN3 13 V IN4 8 VG1 10 VG2 VG3 14 VG4 16 V CC 22 V REFOUT Input pin for CH3 Drive 12 11 9 VIN 13 7 Input pin for CH4 11kΩ Input pin for CH1 (gain adjustment) 12 8 VG 14 10 Input pin for CH2 (gain adjustment) A GND VREF OUT 22 Input pin for CH3 (gain adjustment) 1 2 17 18 19 20 35 36 Input pin for CH4 (gain adjustment) Power supply A10991 Level shift circuit reference voltage (V REF1 buffer amplifier output) 3 NC 4 V SS 2 5 V SS 2-OUT May not be used. Connect to V S 2 Output stage reference voltage output (V S 2-V BE)/2: typ) 6 MUTE1 15 MUTE2 16 6 15 CH1 output ON/OFF VCC CH2 to CH4 output ON/OFF MUTE1,2 To bias circuit 1 2 17 18 19 20 35 36 A10993 21 Level shift circuit reference voltage input V REFIN (V REF1 buffer amplifier input) 23 V O8 24 V O7 CH4 non-inverted output (AMP7 output) 26 V O6 CH3 inverted output (AMP6 output) 27 V O5 28 V O4 29 V O3 31 V O2 32 V O1 25 VS2 30 VS1 33 V SS 1-OUT VCC 23 VO 24 26 27 Drive 28 29 31 32 CH4 inverted output (AMP8 output) 16 CH3 non-inverted output (AMP5 output) CH2 inverted output (AMP4 output) CH2 non-inverted output (AMP3 output) 1 2 17 18 19 20 35 36 A10992 CH1 inverted output (AMP2 output) CH1 non-inverted output (AMP1 output) CH3 (AMP5, AMP6), CH4 (AMP7, AMP8) output stage power supply CH1 (AMP1, AMP2), CH2 (AMP3, AMP4) output stage power supply Output stage reference voltage (V SS1/2:typ) (V REF2 buffer amplifier input) 34 V SS 1 Connect to VS1 (resistance split to generate V SS1-OUT) No. 5904-4/7 LA6543M Block Diagram RF RF Thermal shutdown 1 MUTE1 2 MUTE2 36 RF CH2(VO3-VO4) CH3(VO5-VO6) CH4(VO7-VO8) 35 RF CH1(VO1-VO2) NC 3 VSS2-OUT 5 MUTE1 6 VIN1 7 VG1 8 VIN2 9 VO1 to VO2 VG2 10 VIN4 13 VG4 14 32 VO1 – + 31 VO2 30 VS1 – + 29 VO3 – + 28 VO4 – + 27 VO5 26 VO6 – + Level shift VG3 12 – + Level shift VIN3 11 MUTE2 15 33 VSS1-OUT Level shift 4 – + Level shift VSS2 34 VSS1 – + – + 24 VO7 – + 23 VO8 25 VS2 VO3 to VO8 22 VREF OUT – + VCC 16 21 VREF IN RF 17 20 RF RF 18 19 RF A10994 System Diagram (relationship between power supply and MUTE) MUTE1 CH1 CH2 MUTE2 VS1 CH3 CH4 VS2 A10995 No. 5904-5/7 LA6543M Sample Application Circuit VS(5V) 1 RF RF 36 2 RF RF 35 3 (NC) VSS1 34 4 VSS2 VSS1-OUT 33 5 VSS2-OUT VO1 32 6 MUTE1 VO2 31 7 VIN1 VS1 30 8 VG1 VO3 29 9 VIN2 VO4 28 10 Gain setting VG2 VO5 27 11 VIN3 VO6 26 12 VG3 VS2 25 13 VIN4 VO7 24 14 Gain setting VG4 VO8 23 M Loading input Gain setting Focus input Tracking input Loading Focus LA6543M Tracking Gain setting Sled input M VCC (12V) 15 MUTE2 16 VCC 17 RF RF 20 18 RF RF 19 Sled VREF OUT 22 VREF IN 21 Reference voltage A10996 No. 5904-6/7 LA6543M Gain Setting (input pins and adjustment pins) A simplified diagram of VIN and VG is shown below. 1) Consider an 11 kΩ (typ.) inserted between VIN and VG. 2) When only VIN and not VG is used, the BTL gain (between VO+ and VO–) is set to 6 dB (0 dB for AMP only). This also applies for the case when VIN is not used and an 11 kΩ external resistor is connected to VG for input. 3) Gain is set by the input impedance as seen from point A. When VG only is used and the external resistor is R, the BTL gain (between VO+ and VO–) is 20 log (11 kΩ/R) + 6 dB. When an 11 kΩ resistor is inserted between VIN and VG, and input is via VIN, the combined resistance Rz as seen from point A is Rz = 5.5 kΩ. Gain is 20 log (11 kΩ/5.5 kΩ) + 6 dB = 12 dB. VG 11 kΩ VIN Level shift – VREF1 + VREF VSS CH4 only 11 kΩ – AMP1 + VO+ – AMP2 + VO– A – VREF2 + 11 kΩ GND A10997 Offset Voltage This IC incorporates a level shifter circuit. The input references the voltage VREF to be applied and references the voltage (VSS – VBE (0.7))/2V to be output. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 5904-7/7