SANYO LC7941KDR

Ordering number : ENA0573
LC7940KD
LC7941KDR
CMOS IC
Dot-Matrix LCD Drivers
Overview
The LC7940KD and LC7941KDR are segment driver LSIs for driving large, dot-matrix LCD displays. They read 4-bit
parallel or serial input, display data from a controller into an 80-bit latch, and then generate LCD drive signals
corresponding to that data. The LC7940KD and LC7941KDR feature mirror-image pin assignments, allowing them to be
used together to increase component density. They are designed to be used with the LC7942KD (QIP80D) common
driver to drive large LCD panels.
Features
• 80 built-in LCD display drive circuits
• 1/8 to 1/128 display duty cycle
• Serial or 4-bit parallel data input
• Chip disable for low power dissipation for large-sized panels
• Bias supply voltage can be supplied externally
• Operating supply voltage and ambient temperature
VDD (logic block): 2.7 to 5.5V/-20 to +85°C
VDD-VEE (LCD block): 8 to 20V/-20 to +85°C
• CMOS process
• Package: QIP100D(LC7940KD)/QIP100DR(LC7941KDR)
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
N2206HKIM B8-8529 No.A0573-1/13
LC7940KD / LC7941KDR
Package Dimensions
unit: mm (typ)
3180 [LC7940KD]
23.2
1.6
0.65
0.575
0.3
0.15
80
81
51
50
15.6
14.0
1
30
21.6
0.8
31
100
2.45max
1.6
17.2
0.65
0.825
20.0
2.15
0.8
SANYO : QIP100D(14X20)
Package Dimensions
unit: mm (typ)
3329 [LC7941KDR]
23.2
0.8
20.0
80
51
50
100
31
14.0
17.2
81
1
30
0.65
0.15
0.3
(2.15)
0.1
2.45MAX
(0.58)
SANYO : QIP100DR(14X20)
No.A0573-2/13
LC7940KD / LC7941KDR
O51
O55
O54
O53
O52
O59
O58
O57
O56
O67
O66
O65
O64
O63
O62
O61
O60
O72
O71
O70
O69
O68
O76
O75
O74
O73
O80
O79
O78
O77
Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
LC7940KD
O50
O49
O48
O47
O46
O45
O44
O43
O42
O41
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O30
O26
O27
O28
O29
O22
O23
O24
O25
O14
O15
O16
O17
O18
O19
O20
O21
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
O5
O6
O7
O8
O1
O2
O3
O4
1 2 3 4 5 6
O9
O10
O11
O12
O13
NC
CDO
NC
DISPOFF
P/S
VSS
VEE
V4
V3
NC
VDD
V1
M
DI1
DI2
DI3
SDI
LOAD
CDI
CP
O30
O26
O27
O28
O29
O14
O15
O16
O17
O18
O19
O20
O21
O22
O23
O24
O25
O7
O8
O9
O10
O11
O12
O13
O5
O6
O1
O2
O3
O4
Top view
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
LC7941KDR
O31
O32
O33
O34
O35
O36
O37
O38
O39
O40
O41
O42
O43
O44
O45
O46
O47
O48
O49
O50
O51
O55
O54
O53
O52
O59
O58
O57
O56
O67
O66
O65
O64
O63
O62
O61
O60
O72
O71
O70
O69
O68
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
O76
O75
O74
O73
1 2 3 4 5 6
O80
O79
O78
O77
CP
CDI
LOAD
SDI
DI3
DI2
DI1
M
V1
VDD
NC
V3
V4
VEE
VSS
P/S
DISPOFF
NC
CDO
NC
Top view
No.A0573-3/13
LC7940KD / LC7941KDR
O80
O79
O3
O2
O1
Block Diagram
V1
V3
VDD
4 Level LCD Drive Circuit
(80 bits)
V4
VSS
VEE
80
Level Shifter (80 bits)
M
80
DISPOFF
2nd Latch (80 bits)
80
1st Latch (80 bits)
4
SDI
DI3
DI2
4 bits
Data Bus
Interface
Address Decoder
Address Counter
(7bits)
DI1
P/S
20
SER/PAR
Control
Chip Disable &
Latch Control
CDO
CDI
CP
LOAD
No.A0573-4/13
LC7940KD / LC7941KDR
Pin Function
Pin No
Symbol
I/O
90
VDD
Supply
95
VSS
87
94
VEE
92
89
V1
89
92
V3
88
93
V4
LC7940KD
LC7941KDR
91
86
Function
LCD panel drive voltage supplies
VDD-VSS is the logic supply.
VDD-VEE is the LCD supply.
Supply
LCD panel drive voltage supplies
V1 and VEE are selected levels.
V3 and V4 are not-selected levels.
100
81
CP
I
Display data input clock (falling edge trigger).
99
82
CDI
I
Chip disable.
98
83
LOAD
I
Data is read in When LOW, and not read in When HIGH.
Display data latch clock (falling edge trigger).
On the falling edge, the LCD drive signals set by the display data are output.
97
84
SDI
I
Serial data input.
96
85
DI3
I
4-bit parallel data input pins.
Data input
95
86
DI2
DI1
I
I
LCD driver output
SDI
O4
O8
O80
DI3
O3
O7
O79
DI2
O2
O6
DI1
O1
O5
→
O78
O77
94
87
93
88
M
I
LCD panel drive voltage output alternation control signal.
85
96
P/S
I
Data input mode select. 4-bit parallel input when HIGH, and serial input when LOW.
82
99
CDO
O
In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.
Cascade connection pin for extension segment drivers.
Data is read out when HIGH. Goes LOW after data is read out.
Connected to the CDI input of the next chip.
1 to 80
80 to 1
O1 to O80
O
LCD drive outputs.
The output drive level is determined by the display data, M signal and DISPOFF input
as shown below.
M
Q
DISPOFF
Output
L
L
H
V3
L
H
H
V1
H
L
H
V4
H
H
H
*
*
L
VEE
V1
Note* don’t care (tied HIGH or LOW)
84
97
DISPOFF
I
O1 to O80 output control input pin.
When LOW, V1 is output on the O1 to O80 outputs.
See the truth table.
81
91
NC
83
98
NC
90
100
NC
-
No connection.
No.A0573-5/13
LC7940KD / LC7941KDR
Specifications
Absolute Maximum Ratings at Ta=25±2°C, VSS = 0V
Symbol
Conditions
Maximum supply voltage (logic)
Parameter
VDD max
-
-0.3 to +7.0
Maximum supply voltage (LCD)
VDD-VEE max
0 to 22
V
-
-0.3 to VDD +0.3
V
Maximum input voltage
Ratings
Unit
*1
VI max
V
Operating temperature range
Topr
-
-20 to +85
°C
Storage temperature range
Tstg
-
-40 to +125
°C
Note *1 The following relations between elements should be maintained:
VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V
Allowable Operating Ranges at Ta = -20 to 85°C, VSS = 0V
Parameter
Symbol
Ratings
Conditions
min
Supply voltage (logic)
VDD
Supply voltage (LCD)
VDD-VEE
*2, 3
typ
Unit
max
2.7
-
5.5
V
8
-
20
V
Input high level voltage
VIH
CP, CDI, DI1 to DI3, M, SDI, P/S,
DISPOFF, and LOAD
0.8VDD
-
-
V
Input low level voltage
VIL
CP, CDI, DI1 to DI3, M, SDI, P/S,
DISPOFF, and LOAD
-
-
0.2VDD
V
CP Shift clock frequency
fCP
CP
-
-
3.3
CP pulse width
tWC
CP
100
-
-
LOAD pulse width
tWL
LOAD
100
-
-
ns
-
-
ns
DIn and SDI to CP setup time
tSETUP
DIn and SDI to CP
80
DIn and SDI to CP hold time
tHOLD
DIn and SDI to CP
CP to LOAD time
tCL1
MHz
ns
80
-
-
ns
CP to LOAD
0
-
-
ns
100
-
-
ns
-
-
tCL2
CP to LOAD
LOAD to CP time
tLC
LOAD to CP
CP rise time
tR
CP
-
-
50
ns
tF
CP fall time
100
ns
CP
-
-
50
ns
LOAD rise time
tRL
LOAD
-
-
50
ns
LOAD fall time
tFL
LOAD
-
-
50
ns
Note *2 The following relations between elements should be maintained:
VDD≥V1>V3>V4>VEE, VDD-V3≤7V, V4-VEE≤7V
*3 When the power is turned on, either the logic system power must be turned on before the LCD drive system
power or else they must both be turned on at the same time. When the power is turned off, either the LCD drive
system power must be turned off before the logic system power, or else both must be turned off at the same
time.
No.A0573-6/13
LC7940KD / LC7941KDR
Electrical Characteristics at Ta = 25±2°C, VDD = 2.7 to 5.5V
Parameter
Symbol
Ratings
Conditions
Input high level current
IIH
VIN = VDD: LOAD, CP, CDI, P/S, DI1 to DI3, SDI, M,
and DISPOFF
Input low level current
IIL
VIN = VSS: LOAD, CP, CDI, P/S, DI1 to DI3, SDI, M,
and DISPOFF
min
typ
-
-
-
VOH
IOH = -400µA: CDO
VDD-0.4
-
Output low level voltage
VOL
IOL = 400µA: CDO
-
-
Driver on resistance
RON
VDD-VEE = 18V, |VDE-Vo| = 0.25V *4
-
IST
CDI = VDD, VDD-VEE = 18V,
CP = 3.3MHz, Output unloaded: VSS
Operating current drain
µA
1
-1
Output high level voltage
Standby current drain
Unit
max
µA
V
0.4
0.7
V
2
kΩ
-
-
200
µA
ISS *5
VDD-VEE = 18V, CP = 3.3MHz, LOAD = 5.156kHz
M = 52Hz: VSS
-
-
1.0
mA
IEE *6
VDD-VEE = 18V, CP = 3.3MHz, LOAD = 5.156kHz
M = 52Hz: VEE
-
-
0.1
mA
Note *4 VDE = one of V1, V3, V4 or VEE. V1 = VDD, V3 = 9/11(VDD-VEE), V4 = 2/11(VDD-VEE)
*5 ISS is the current flowing from VDD-VSS.
*6 IEE is the current flowing from VDD-VEE
Switching Characteristics at Ta = 25±2°C, VSS = 0V, VDD = 2.7 to 5.5V
Parameter
Symbol
Output delay time
Ratings
Conditions
tD
min
typ
-
-
CL=30pF: CDO
Unit
max
200
ns
Switching Characteristics Diagram
tR
tWC
tWC
tF
0.8VDD
0.8VDD
CP
0.2VDD
0.2VDD
tSETUP
SDI
0.8VDD
DI1 to 3
0.2VDD
tCL(1)
tHOLD
tFL
tCL(2)
tRL
tLC
LOAD
tWL
tD
tD
0.8VDD
CDO
0.2VDD
No.A0573-7/13
R
R
VEE
+
V5
4
4
V1 V3
V4 VEE
240
+
239
V1 V3
V4 VEE
M
V1 V3
V4 VEE
LC7940KD-#2
160
M
CDO
159
V4
4
161
LC7940KD-#3
CDI
CDI
CDO
LCD Panel (240×100 Pixels)
81
7R
6
V1 V2
V5 VEE
O36
100
M
LOAD
CP
Serial Data
V1 V3
V4 VEE
LC7940KD-#1
80
V3
V2
CP #2
DIO1 O1
M
LC7942KD
4
V1 V2
V5 VEE
79
+
+
V1
O1
LC7942KD
CP #1 O64
DIO64
DIO1
2
R
R
VDD
Serial
Data
CP
LOAD
M
••••
••••
M
••••
••••
FLM
••••
••••
Controller
LOAD
CP
SDI
CDI
LC7940KD / LC7941KDR
Application Notes LCD Panel1
1
No.A0573-8/13
7R
R
R
R
R
VDD
V5
V4
V3
V2
VEE
Power supply
circuit
+
+
+
+
V1
CP
4bit
Data
LOAD
M
6
4
DIO1 O1
DIO1 O1
4
4
V1 V2
V5 VEE
CP
O36
LC7942KD-#2
M
DIO64
O64
CP
LC7942KD-#1
M
LC7940KD-#8
4
V1 V3
V4 VEE
100
••••
FLM
LC7941KDR-#8
2
4
4
LC7941KDR-#2
2
4
LC7940KD-#2
LCD Panel (640×200 Pixels)
••••
••••
4bit
Data
2
2
2
CDO
CDO
4
V1 V3
V4 VEE
O80
4
M
O1
4
4bit
Data
CDI
2
4
CDI
4bit Data
CP
LOAD
2
V1 V3
V4 VEE
CP
LOAD
LC7940KD-#1
O80
O1
LC7941KDR-#1
M
••••
••••
4
••••
••••
2
••••
Controller
LC7940KD / LC7941KDR
Application Notes LCD Panel2
No.A0573-9/13
LC7940KD / LC7941KDR
100×240-Pixel LCD Panel Application
A100×240-Pixel LCD Panel requires the following drivers.
• 3×LC7940KD (or LC7941KDR) drivers
• 2×LC7942KD drivers
An example using 1/100 duty cycle is shown below.
1,79
(m, n): Pixel address
Frame signal
Segment line (n)
Common line (m)
O1
1,1
1,2
RS/LS O2
2,1
2,2
DIO1
∼
1,79
1,80
1,81
∼
1,82
1,160
1,161
∼
1,240
2,240
LC7942KD
RS/LS O2
66,1
66,2
LC7942KD
#2
CP
M
O36
∼
∼
100,1
100,2
∼
65,80
65,81
∼
∼
∼
64,160 64,161
65,160 65,161
100,79 100,80 100,81 100,82
∼
∼
∼
64,240
65,240
100,160 100,161
∼
65,2
64,81
∼
65,1
64,80
∼
O1
DIO1
∼
∼
64,2
∼
64,1
∼
63,2
∼
63,1
∼
∼
O63
DIO64 O64
LCD Panel (100×240 Pixels)
∼
∼
#1
CP
M
∼
100,240
DIO64
O1
CP
LOAD
M
SDI
LC7940KD O80
(LC7941KDR)
CDO
CDI
#3
P/S
DI1
DI2
DI3
CP
LOAD
M
SDI
DI3
DI2
O2
O80
LC7940KD
CDI (LC7941KDR) #2 CDO
P/S
O1
DI1
M
CDO
LOAD
CP
SDI
DI3
O80
Data shift
clock
Serial data
Alternating signal
Data latch clock
P/S
CDI
O2
O79
LC7940KD
(LC7941KDR) #1
DI2
O1
DI1
O37 to 64
are open.
(1) The LC7942KD chips are cascaded by connecting DIO64 on chip 1 to DIO1 on chip 2.
For a 100-bit shift register, O37 to O64 on chip 2 are left open.
(2) The LC7940KD (or LC7941KDR) chips are cascaded by connecting CDO on chip 1 to CDI on chip 2,
and CDO on chip 2 to CDI on chip 3. CDI on chip 1 is tied to GND, and CDO on chop 3 is not used.
This configulation allows the input of 240-bit serial data.
No.A0573-10/13
LC7940KD / LC7941KDR
100×240-pixel LCD Panel Timing Diagram
M
LOAD
CP
SDI
1,1
∼
1,2
1,79
1,80
1,81
∼
1,160
1,161
∼
1,240
#1
CDO #2
#3
Chip 1 data read
Chip 2 data read
Chip 3 data read
1 line (240 bits)
M
LOAD
CP
SDI
1,1
∼
1,2
1,239
1,240
2,1
∼
2,240
3,1
∼
100,240
2nd line data read
1st line data read
1 frame (100×240 bits)
M
#1 DIO1
LOAD
#1
2,1
∼
98,1
99,1
100,1
1,1
∼
99,1
100,1
O2
1,2
2,2
∼
98,2
99,2
100,2
1,2
∼
99,2
100,2
O80
1,80
2,80
∼
98,80
99,80
100,80
1,80
∼
99,80
100,80
O1
1,81
2,81
∼
98,81
99,81
100,81
1,81
∼
99,81
100,81
O80
1,160
2,160
∼
98,160
99,160
100,160 1,160
∼
99,160
100,160
O1
1,161
2,161
∼
98,161
99,161
100,161 1,161
∼
99,161
100,161
1,240
2,240
∼
98,240
99,240
100,240 1,240
∼
99,240
100,240
∼
#3
∼
#2
O80
LCD driver output data
1,1
∼
O1
No.A0573-11/13
LC7940KD / LC7941KDR
Segment Data Not Multiples of 4
Example.
LCD Panel (100×230 pixels)
∼
∼
∼
O1 • • • • • O80
O1 • • • • • O80
O1 • • • • • O70
LC7940KD
#1
LC7940KD
#2
LC7940KD
#3
LOAD
SDI
m,1
m,2
∼
,228
m,229
m,230
m+1,1
,228
m+1,2
m+1,229 m+1,230
If this timing data is sent, data elements (m, 229), (m, 230), (m+1, 229),(m+1, 230)… will not appear in the output
(O69 and O70 on chip 3). This is because the LC7940KD (or LC7941KDR) converts serial/parallel data in 4-bit units,
which also decrease power dissipation.
For data that is not a multiple of 4, like 230, the following scheme is used.
LOAD
SDI
m,1
m,2
∼
,228
m,229
Valid display data
m,230
m,231
m,232
Dummy data
Multiple of 4
In this case, (m, 231) is output on O71 on chip 3, and (m, 232) on O72 on chip 3. However, these outputs are not
connected to the panel and are, therefore, invalid.
No.A0573-12/13
LC7940KD / LC7941KDR
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
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and all semiconductor products fail with some probability. It is possible that these probabilistic failures
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
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reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
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This catalog provides information as of November, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0573-13/13