Ordering number : ENA0575 LC7942KD CMOS IC Dot-Matrix LCD Drivers Overview The LC7942KD is a common driver LSI for driving large dot-matrix LCD displays. It features a built-in 64-bit bidirectional shift register and a 4-level LCD driver. It can also be connected in cascade to increase the number of bits. The LC7942KD is designed to be used with LC7940KD (QIP100D) or LC7941KDR (QIP100DR) segment drivers to drive large LCD panels. Features • 64 built-in LCD display drive circuits • 1/64 to 1/128 display duty cycle • Input/outputs for cascade conection • Bias supply voltages can be supplied externally • Operating supply voltage and ambient temperature: 2.7 to 5.5V logic supply (VDD) at Ta = -20 to +85°C 8 to 20V LCD supply (VDD-VEE) at Ta = -20 to +85°C • CMOS process • package: QIP80D Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206HKIM B8-8531 No.A0575-1/8 LC7942KD Package Dimensions unit: mm (typ) 3177 23.2 1.6 1.0 20.0 0.8 0.8 0.35 0.15 64 65 41 15.6 24 0.8 1 2.45max 25 80 1.6 17.2 14.0 0.8 40 2.15 21.6 0.8 SANYO : QIP80D(14X20) O3 O2 O1 O5 O4 O8 O7 O6 O12 O11 O10 O9 O17 O16 O15 O14 O13 O24 O23 O22 O21 O20 O19 O18 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 LC7942KD DIO1 NC CP NC M NC VSS RS/LS VDD DISPOFF V1 V2 V5 VEE NC DIO64 O63 O64 O59 O60 O61 O62 O54 O55 O56 O57 O58 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 O48 O49 O50 O51 O52 O53 1 O41 O42 O43 O44 O45 O46 O47 O25 O26 O27 O28 O29 O30 O31 O32 O33 O34 O35 O36 O37 O38 O39 O40 Top view No.A0575-2/8 LC7942KD Block Diagram O1 O2 O3 ------------------ O63 O64 V1 VDD V2 4 Level LCD Drive Circuit (64 bits) V5 VSS VEE Level Shifter (64bits) M DISPOFF DIO1 I/O Bidirectional Shift Register (64 bits) I/O DIO64 RS/LS CP No.A0575-3/8 LC7942KD Pin Function Pin No. Pin name Input/Output 32 VDD Supply 34 VSS 27 VEE 30 V1 29 V2 28 V5 Functions VDD-VSS is the logic supply. VDD-VEE is the LCD supply. Supply LCD panel drive voltage supplies. V1 and VEE are selected levels. V2 and V5 are non-selected levels. 38 CP I 40 DIO1 I/O 25 DIO64 I/O RS/LS Data Transfer Direction DIO1 DIO64 I L (right shift) O1→O64 IN OUT H (left shift) O64→O1 OUT IN 33 RS/LS Display data input clock (falling-edge trigger). 36 M I LCD panel drive voltage alternating control signal. 31 DISPOFF I O1 to O64 output control input pins. 41 to 80 O1 to O40 Output 1 to 24 O41 to O64 LCD drive outputs The output drive level is determined by the display data, M signal and DISPOFF input as shown below. M Data DISPOFF L L H V2 L H H VEE H L H V5 H H H V1 * * L V1 Output * Don’t care (To be set to either “H” or “L”) 26 NC - No connection 35 37 39 No.A0575-4/8 LC7942KD Specifications Absolute Maximum Ratings at Ta=25±2°C, VSS = 0V Symbol Conditions Maximum supply voltage (logic) Parameter VDD max - -0.3 to +7.0 Maximum supply voltage (LCD) VDD-VEE max 0 to 22 V - -0.3 to VDD +0.3 V Maximum input voltage Ratings Unit *1 VIN max V Operating temperature range Topr - -20 to +85 °C Storage temperature range Tstg - -40 to +125 °C Note *1 The voltages V1, V2, and V5 must obey the relationships: VDD≥V1>V2>V5>VEE, VDD-V2≤7V, V5-VEE≤7V Allowable Operating Ranges at Ta = -20 to 85°C, VSS = 0V Parameter Symbol Ratings Conditions min Supply voltage (logic) VDD Supply voltage (LCD) VDD-VEE *2, 3 typ Unit max 2.7 - 5.5 8 - 20 V V Input high level voltage VIH DIO1, DIO64, CP, M, RS/LS, DISPOFF 0.8VDD - - V Input low level voltage VIL DIO1, DIO64, CP, M, RS/LS, DISPOFF - - 0.2VDD V CP (Shift clock) fCP CP - CP (pulse width) tWC CP 125 - - ns 100 - - ns - - Setup time tSETUP DIO1→CP, DIO64→CP Hold time tHOLD DIO1→CP, DIO64→CP - 100 1 MHz ns CP rise time tR CP - - 50 ns CP fall time tF CP - - 50 ns Note *2 The voltages V1, V2, and V5 must obey the relationships: VDD≥V1>V2>V5>VEE, VDD-V2≤7V, V5-VEE≤7V *3 When applying power, apply power to the LCD drive block after applying power to the logic block or apply power to both the blocks simultaneously. When turning off power, turn off power to the logic block after turning off power to the LCD drive block or turn off power to both the blocks simultaneously. No.A0575-5/8 LC7942KD Electrical Characteristics at Ta = 25±2°C, VSS = 0V, VDD= 2.7 to 5.5V Parameter Symbol Ratings Conditions Input high level current IIH VIN = VDD, VDD = 5.5V, DIO1, DIO64, CP, M, RS/LS, DISPOFF Input low level current IIL VIN = VSS, VDD = 5.5V, DIO1, DIO64, CP, M, RS/LS, DISPOFF min typ - - Unit max 1 -1 - - µA µA Output high level voltage VOH IOH = -0.4mA, DIO1, DIO64 VDD-0.4 - Output low level voltage VOL IOL = 0.4mA, DIO1, DIO64 - - 0.4 V Driver on resistance RON - - 1.5 kΩ VDD static Current IDD VDD-VEE = 18V. |VDE-VO| = 0.25V VDD = 4.5V *4; O1 to O64 VDD-VEE = 18V, CP = VDD - - 100 µA V Note *4 VDE = V1 or V2 or V5 or VEE, V1 = VDD, V2 = 10/11(VDD-VEE), V5 = 1/11(VDD-VEE) Switching Characteristics at Ta = 25±2°C, VSS = 0V, VDD = 2.7 to 5.5V Parameter Symbol Ratings Conditions min Output delay time typ Unit max tPLH CL=30pF; CP→DIO1, CP→DIO64 - - 250 ns tPHL CL=30pF; CP→DIO1, CP→DIO64 - - 250 ns Switching Characteristics Diagram tR twc tF 0.8VDD CP 0.2VDD tSETUP tHOLD DIO1 (DIO64) tPLH , tPHL DIO64 (DIO1) No.A0575-6/8 R R VEE + V5 4 4 V1 V3 V4 VEE 240 + 239 V1 V3 V4 VEE M V1 V3 V4 VEE LC7940KD-#2 160 M CDO 159 V4 4 161 LC7940KD-#3 CDI CDI CDO LCD Panel (240×100 Pixels) 81 7R 6 V1 V2 V5 VEE O36 100 M LOAD CP Serial Data V1 V3 V4 VEE LC7940KD-#1 80 V3 V2 CP #2 DIO1 O1 M LC7942KD 4 V1 V2 V5 VEE 79 + + V1 O1 LC7942KD CP #1 O64 DIO64 DIO1 2 R R VDD Serial Data CP LOAD M •••• •••• M •••• •••• FLM •••• •••• Controller LOAD CP SDI CDI LC7942KD Application Notes LCD Panel 1 No.A0575-7/8 LC7942KD Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2006. Specifications and information herein are subject to change without notice. PS No.A0575-8/8