SANYO LV4141W

Ordering number : EN8927A
Bi-CMOS LSI
For LCD Panel Drive
LV4141W
Single Chip IC
Overview
The LV4141W is single chip IC for LCD panel drive.
Functions
• Analog block RGB Decoder/Driver
• Digital block Timing Generator
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Allowable power dissipation
Symbol
Conditions
Ratings
Unit
VCC1 max
Analog LOW type
6
V
VCC2 max
Analog HIGH type
12
V
VDD max
Digital type
4.5
V
350
mW
Pd max
Ta ≤ 75°C * Mounted on a board.
Operating temperature
Topr
-15 to +75
°C
Storage temperature
Tstg
-40 to +125
°C
Input pin voltage
VINA
Analog input pin (other than pin 33)
-0.3 to VCC1
V
VINA
Analog input pin (33PIN)
VIND
Digital input pin (other than pins 6, 7, and 8)
VIND
Digital input pin (6, 7, 8PIN)
-0.3 to 10
V
-0.3 to VDD+0.3
V
-0.3 to +4.5
V
* : Mounted on a board : 30×30×1.6mm3, glass epoxy board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
41107 TI PC B8-6227, 6576 No.8927-1/27
LV4141W
Operating Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Operating voltage range
Symbol
Conditions
Ratings
Unit
VCC1
Analog LOW type
3.0
V
VCC2
Analog HIGH type
7.0
V
VDD
Digital type
4.5
V
VCC1op
Analog LOW type
2.7 to 3.6
V
VCC2op
Analog HIGH type
6 to 9.5
V
VDDop
Digital type
2.7 to 3.6
V
Input Signal Voltage
Parameter
Recommended input amplitude
Ratings
Conditions
min
typ
R, G, B input pin (RGB input mode)
Unit
max
0.35
0.42
Vp-p
Electrical DC Characteristics
Unless otherwise specified, the setting 2 must be made.
Unless otherwise specified, VCC1 = 3V, VCC2 = VCCCOM = 7V, GND1 = GND2 = GNDCON = 0,
VDD1 = VDD2 = VDD0 = 3V, VSS1 = VSS2 = VSS0 = 0, Ta = 25°C
[Current Characteristics]
Parameter
Symbol
Ratings
Conditions
min
Current dissipation VCC1
ICC11
Enter SIG4 (VL = 0mV) to (A).
Measure the current value of ICC1.
Normal
Current dissipation VCC2
ICC2
Enter SIG4 (VL = 0mV) to (A).
Normal
Measure the current value of ICC2.
Standby
Current dissipation VDD, logic
typ
9.5
14
Standby
Unit
max
18.5
mA
mA
1
1.5
2
1.5
2.8
3.5
mA
0
0.1
0.2
mA
IDD1
Enter SIG4 (VL = 0mV) to (A).
Normal
3.5
6.5
8.5
mA
IDD2
Measure the current value of IDD11
Standby
3
6
8
mA
and IDD22.
Sleep
1
1.6
2.5
mA
IDD3
IDD1, IDD2, IDD3 = IDD11+IDD22
[Digital block input/output characteristics]
Parameter
Symbol
Conditions
L-level input voltage
VIH
Digital block input pin (Note 1)
H-level input voltage
VIL
Digital block input pin (Note 1)
H-level output voltage
VOHT
VDD = 3.0V IOH = -1.0mA (Note 2)
Ratings
min
typ
Unit
max
0.3VDD
V
0.7VDD
V
2.8
V
L-level output voltage
VOL
IOL = 1.0mA (Note 2)
0.3
V
Output transition time
tTLH
Load 30pF (see Fig. 2)
30
ns
30
ns
10
ns
53
%
tTHL
Cross point time difference
ΔT
Load 30pF
Measure CKH1 and CKH2.(see Fig. 3)
CHK duty
DTYHC
Load 30pF
47
50
Measure the duty of CKH1 and CKH2.
(Note 1) Digital block input pins : LOAD, DATA, SCLK, VDIN, HDIN, CLPIN
(Note 2) Digital block output pin (pins 17 to 30)
No.8927-2/27
LV4141W
Electrical AC Characteristics (1)
Unless otherwise specified, the setting 1 and 2 must be made.
Unless otherwise specified, VCC1 = 3V, VCC2 = VCCCOM = 7V, GND1 = GND2 = GNDCON = 0,
VDD1 = VDD2 = VDD0 = 3V, VSS1 = VSS2 = VSS0 = 0, Ta = 25°C
Unless otherwise specified, measure non-inverted output for P TP40, TP43, TP45 outputs.
[RGB signal system]
Parameter
Input-output gain TYP
Symbol
GTP
Conditions
Enter SIG3 to (A) and measure the ratio between
Ratings
min
typ
Unit
max
14
16
18
dB
-2
1
4.5
dB
19.5
21.5
23.5
dB
the output amplitude (white to black) and input
amplitude of TP43.
Input-output gain MIN
GMN
Enter SIG3 to (A) and measure the ratio between
the output amplitude (white to black) and input
amplitude of TP43.
Input-output maximum gain,
GMX
MAX
Enter SIG3 to (A) and measure the ratio between
the output amplitude (white to black) and input
amplitude of TP43.
Frequency characteristics
FCH
Assume that the output amplitude of TP43 when
3.5
MHz
FCL
SIG1 (0dB, 100kHz) is entered to (A) is 0dB.
2.5
MHz
Change the input signal frequency to change and
determine the frequency at which the output
amplitude becomes -3dB.
FCH when the serial bus LPF = HIGH and FCL
when LPF = LOW
Input/output delay rate
TD
Enter SIG8 to (A). Measure the delay time from the
0
100
200
ns
input signal 2T pulse peak to the peak of TP43
non-inverted output.
Antipole output DC voltage
COMBMX
change amount
COMBMN
Measure TP38 output. DC IO = ±1m
ACOMBMX when COMB = 63 and COMBMN
3.55
V
2.6
V
when COMB = 0
Output DC voltage
VDSDH
VCC2 = 8.5V
Measure the TP50 voltage by setting VCC2 = 8,5V
and SIG center level changeover = low voltage
3.4
3.5
3.6
V
3.4
3.5
3.6
V
3.3
3.5
3.7
V
3.3
3.5
3.7
V
0
120
mV
mode.
Output DC voltage
VDSD
VCC2 = 7V
Measure the TP50 voltage by setting VCC2 = 7V
and SIG center level changeover = high voltage
mode.
RGB signal output DC voltage
VOUTH
VCC2 = 8.5V
Set VCC2 = 8.5V and SIG center level changeover
= low voltage mode and enter SIG4 (VL = 0mV)
into (A). Adjust the serial bus BRIGHT to set TP43
output to 3Vp-p and measure the DC voltage of
TP40, TP43, and TP45.
RGB signal output DC voltage
VOUT
VCC2 = 7V
Set VCC2 = 7V and SIG center level changeover =
high voltage mode, and enter SIG4 (VL = 0mV) to
(A). Adjust the serial bus BRIGHT to set the TP43
output to 3Vp-p and measure the DC voltage of
TP40, TP43, and TP45.
RGB signal output DC voltage
ΔVOUT
difference
Determine the maximum of differences among
measurements of TP40, TP43, and TP45 of VOUT
of previous item.
Brightness change rate
BRTMX
Measure the change rate of the black level of
2
2.5
V
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and BRT is changed from 128 to
255.
BRTMN
-2.5
Measure the change rate of the white level of
-2
V
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and BRT is changed from 128 to 0.
Antipole output change
COMWMX
amount
Measure the difference between non-inverted and
4.6
V
inverted levels of TP38 output when (A) = SIG2 is
entered and COMW is set to 255.
COMWMN
Measure the difference between non-inverted and
0.1
V
inverted levels of TP38 output when (A) = SIG2 is
entered and COMW is set to 0.
Continued on next page.
No.8927-3/27
LV4141W
Continued from preceding page.
Parameter
Sub-brightness R change
Symbol
SBBRTR
rates
Conditions
Measure the change amount of TP45 output black
Ratings
min
typ
Unit
max
±1.3
±1.7
V
±1.3
±1.7
V
-0.6
0
level when SIG2 is entered in (A) and COMW is
changed from 128 to 255 and that of TP45 output
white level change amount when COMW is
changed from 128 to 0.
Sub-brightness B change
SBBRTR
rates
Measure the change amount of TP40 output black
level when SIG2 is entered in (A) and COMW is
changed from 128 to 255 and that of TP45 output
white level when COMW is changed from 128 to 0.
Gain difference between RGB
ΔGRGB
signals
Determine the level difference of non-inverted
0.6
dB
output amplitude (white to black) of TP40, TP43,
and TP45 when SIG3 is entered to (A).
Sub-contrast R change rate
SBCNTR
Measure the non-inverted output (white to black) of
±2.0
dB
±2.0
dB
TP45 for the non-inverted output (white to black) of
TP43 when SIG3 is entered to (A) and when
R-CNT = 0 and R-CNT = 255.
Sub-contrast B change rate
SBCNTB
Measure the non-inverted output (white to black) of
TP40 for the non-inverted output (white to black) of
TP43 when SIG3 is entered to (A) and when
B-CNT = 0 and B-CNT = 255.
RGB inverted/non-inverted
ΔGINV
gain difference
Determine the difference of inverted output
-0.5
0
0.5
dB
amplitude for the non-inverted output amplitude
(white to black) of TP40, TP43, and TP45 when
SIG3 is entered to (A).
[RGB signal system]
Parameter
Symbol
Black level potential difference
ΔVBL
between RGB signals
Conditions
Ratings
min
typ
Unit
max
Determine the difference between highest and
300
mV
lowest black levels for inverted and non-inverted
outputs of TP40, TP43, and TP45 when SIG3 is
entered to (A).
Gamma gain
GγL
Enter SIG7 into (A) and set the non-inverted output
23
26
29
dB
GγM
amplitude (black and white) of TP43 at γ1 = 120, γ2
12
15
18
dB
23
26
29
dB
0
IRE
GγH
= 0 to 2.7Vp-p with CONT. Adjust the amplitude
(black and white) to 3.5Vp-p with γ2 and the black
level to 1.5V with BRT. Measure VG1, VG2 and
VG3 and calculate as follows :
GγL = 20log (VG1/0.0357)
GγM = 20log (VG2/0.0357)
GγH = 20log (VG3/0.0357)
(See Fig. 4.)
γ1 adjustment variable range
Vγ1MN
Enter SIG7 to (A) and set the TP43 output (black to
Vγ1MX
black) to 3Vp-p through BRIGHT adjustment.
100
IRE
Read the γ gain change point at γ2 = 0, γ2 = 255 by
referring to the IRE level of input signal :
Vγ1MN forγ1 = 0 Vγ1MX for γ1 = 255
γ2 adjustment variable range
Vγ2MN
Enter SIG7 to (A) and set the TP43 output (black to
Vγ2MX
black) to 3Vp-p through BRIGHT adjustment.
100
IRE
0
IRE
Read the γ gain change point atγ1 = 0, γ1 = 255 by
referring to the IRE level of input signal :
Vγ2MN forγ2 = 0 Vγ2MX for γ2 = 255
Antipole transition time
tCOMH
Enter SIG3 to (A) and set the output amplitude of
1
1.5
μs
tCOML
TP38 to 3Vp-p. Measure tCOMH for rise and
1
1.5
μs
tCOML for fall. Load : 1000pF
RGB output black limiter
VBLIMN
Enter SIG2 to (A) and measure the amplitude of
variablerange
VBLIMX
the black side limiter of inverted/non-inverted
4.5
Vp-p
2
Vp-p
TP38, 40, 43 and 45 output.
RGB output white limiter
VWLIMN
Enter SIG2 to (A) and measure the amplitude of
variablerange
VWLIMX
the white side limiter of inverted/non-inverted
4
Vp-p
2.2
Vp-p
TP38, 40, 43 and 45 output.
Continued on next page.
No.8927-4/27
LV4141W
Continued from preceding page.
Parameter
Symbol
Conditions
Black limiter Dcvoltage
DVBLIM
Enter SIG4 (VL = 0 mV) to (A) and adjust BLIM to
set the TP43 output to 3Vp-p. Measure the DC
White limiter Dcvoltage
DVWLIM
Enter SIG4 (VL = 350mV) into (A), measure the
Ratings
min
typ
Unit
max
3.3
3.5
3.7
V
3.3
3.5
3.7
V
voltage of TP40, Tp43, and TP45.
DC voltage of TP40, TP43, and TP45, and
determine the difference from the above VOUT.
[Sync. separation, TG]
Parameter
Input sync signal width
Symbol
Conditions
WSSEP
Enter SIG4 (VL = 0mV, VS = 143mV, WS variable)
to (A) and confirm synchronization with the
sensitivity
Ratings
min
typ
Unit
max
μs
2.0
TP15HD output. Narrow WS of SIG4 from 4.7μs
and determine WS at which synchronization
between the input and TP15HD output is lost.
Sync separation input
VSSEP
sensitivity
Enter SIG4 (VL = 0mV, WS = 4.7μs, VS variable)
to (A) and confirm synchronization with the
40
60
mV
TP15HD output. Reduce VS of SIG4 from 143mV
and determine VS at which synchronization
between the input and TP15HD output is lost.
Sync separation output delay
TDSY1
rate
TDSY2
Enter SIG4 (VL = 0mV, WS = 4.7μs, VS = 143mV)
into (A) and measure the delay amount from the
300
500
700
ns
150
300
550
ns
TP2RPD output. Assume that the period from fall
of input HSYNC to a front edge of RPD output is
TDSY1 and the period from rise of input HSYNC to
the rear edge of RPD output is TDSY2.
Horizontal pull-in range
HPLLN
Enter SIG4 (VL = 0mV, WS = 4.7μs, and VS =
±500
Hz
HPLLP
143mV, horizontal frequency variable) to (A) and
±500
Hz
confirm synchronization with TP15HD output.
Determine the horizontal frequency fH of SIG4 and
calculate
HPLLN = fH-15734
HPLLP = fH-15625.
Package Dimensions
unit : mm (typ)
3190A
12.0
0.5
10.0
33
32
64
17
10.0
49
1
12.0
48
16
0.5
0.18
0.15
0.1
1.7max
(1.5)
(1.25)
SANYO : SQFP64(10X10)
No.8927-5/27
LV4141W
Conditions of setting to measure the electric characteristic
Following settings must be made before measurement of electric characteristics.
Setting 1. System reset
Turn ON SW56 and start V56 from GND in order to perform system reset for MOS block.
(See fig. 1-1.)
The default value is set for the serial bus.
Setting 2. Horizontal AFC adjustment
Enter SIG4 (VL = 0mV) to (A) and adjust VR1 so that the width of WL and WH
becomes equal in the TP2 output waveform.(See fig 1-2.)
(Note) In order to measure the 2MHz or more band for measurement items, such as the RGB signal frequency
characteristics, etc., it is necessary to pass through the sample hold circuit via serial bus.
VDD1,VDD2
V56 (RESET)
Tr
Tr > 10μs
Fig.1-1 System reset
SIG4
V-sync
TP2
TP2
Approx.1/2VDD
Fig.1-2 Horizontal AFC adjustment
No.8927-6/27
LV4141W
Electric characteristics measurement method
tTHL
tTLH
90%
10%
Fig.2 Output transition time measurement conditions
ΔT
50%
ΔT
Fig.3 Cross point time difference measurement conditions
White
Non-inverted output
VG3
VG2
3.5V
VG1
Black
1.5V
Input
Fig.4 γ characteristics measurement conditions
No.8927-7/27
LV4141W
Block Diagram
No.8927-8/27
LV4141W
Pin Description
Pin No.
1
Pin Name
I/O
Pin Description
VDD1
-
Oscillation cell power supply (3V)
2
RPD
O
Phase comparison output
3
VSS1
-
GND for oscillation cell
4
TEST4
I
Oscillator cell input (also used for test)
5
TEST5
O
Oscillator cell output
6
LOAD
I
Load input for serial bus
7
DATA
I
Data input for serial bus
8
SCLK
I
Clock input for serial bus
9
TEST8
I
Test pin 8
10
TEST3
I
Test pin 3
11
VDD2
-
Digital system power supply (3V)
12
VDDO
-
Digital output system power supply (3V)
13
BLSW
O
Backlight control pulse output
14
BLHD
O
Backlight drive pulse output
15
HD
O
H-drive output
16
VSSO
-
Digital output system ground
17
XSTH
O
H-start pulse output (inverted)
18
STH
O
H-start pulse output
19
CKH2
O
H-clock 2 pulse output
20
CKH1
O
H-clock 1 pulse output
21
TEST6
O
Test pin 6
22
TEST7
O
Test pin 7
23
XDSG
O
Drain hold timing pulse output (inverted)
24
DSG
O
Drain hold timing pulse output
25
XSTV
O
V-start pulse output (inverted)
26
STV
O
V-start pulse output
27
CKV2
O
V-clock 2 pulse output
28
CKV1
O
V-clock 1 pulse output
29
XENB
O
Enable pulse output (inverted)
30
ENB
O
Enable pulse output
31
VD
O
V-drive pulse output(positive polarity)
32
VSS2
-
Digital system ground
33
SHIN
I
Input pin for test
34
CSVO
O
Open collector output for vertical scan changeover
35
CSHO
O
Open collector output for lateral scan changeover
36
FBCOM
O
Time constant pin for antipole output DC return
37
GNDCOM
-
Antipole output ground
38
COMOUT
O
Antipole output
39
VCCCOM
-
Power supply for antipole output (7V)
40
BOUT
O
B output
41
FBB
O
Time constant pin for B-output DC return
42
GND2
-
7V ground
43
GOUT
O
G output
44
FBG
O
Time constant pin for G-output DC return
45
ROUT
O
R output
46
FBR
O
Time constant pin for R-output DC return
47
VCC2
-
7V power supply
48
SIGCENT
I
Time constant pin for R, G, B, COM, and DSD output DC voltage
49
VCC1
-
Analog 3V power supply
50
DSDOUT
O
Drain hold data output
51
NC
-
NC
52
VREG
-
Reference power supply
53
RIN
I
R signal input
54
GIN
I
G signal input
55
BIN
I
B signal input
Continued on next page.
No.8927-9/27
LV4141W
Continued from preceding page.
Pin No.
Pin Name
I/O
Pin Description
56
RESET
I
System reset
57
SYNC IN
I
Sync signal input (composite)
58
VSEP TC
O
Time constant pin for separation of vertical sync
59
VDIN
I
VSYNC input
60
HDIN
I
CSYNC/HSYNC input
61
TEST1
I
Test pin 1
62
TEST2
I
Test pin 2
63
CLPIN
I
External clamp input
64
GND1
-
Analog 3V power supply
Analog pin function description
Pin No.
Pin Name
Pin Voltage
33
SHIN
-
Pin Description
Equivqlent Circuit
Input pin for test
Normally, connect to the ground for use.
VDD2 10kΩ
1kΩ
40kΩ
VSS2
34
CSVO
35
CSHO
-
10kΩ
100kΩ
33
Vertical and horizontal inversion control
output pin. Output is made from the open
VCC2
collector. Connect a resistor to CSVO and
CSHO pins of the panel power supply. The
resistance must comply with the panel
34
35
specification.
GND2
1.5V
Feedback circuit smoothing capacitor pin for
36
FBCOM
41
FBR
control of antipole output DC level and RGB
44
FBG
output DC level.
46
FBB
Because of high impedance, a capacitor with
VCC1
1kΩ
small leakage is used.
36
41
44
46 GND1
37
GNDCOM
0V
38
COMOUT
2.6 to 3.55V
1kΩ
1kΩ
100kΩ
Ground pin of antipole output
Antipole AC output pin that can adjust the
VCCCOM
output DC voltage with variable resistor of
serial bus. When the signal output DC voltage
150Ω
has been changed to VCC2/2 and
VCC2*21/51 with the serial bus and the
voltage has been applied to SIC.C from the
outside, the DC voltage of antipole output
38
20Ω
follows.
GNDCOM
39
VCCCOM
7V
Power pin of antipole output
Continued on next page.
No.8927-10/27
LV4141W
Continued from preceding page.
Pin Voltage
Pin Description
40
ROUT
GOUT
VCC2/2
VCC2*21/51
RGB elementary color signal output pin. Can
43
45
BOUT
Equivqlent Circuit
VCC2
be changed to VCC2/2 and VCC2*21/51 with
the serial bus.
40
43
20Ω
45
20Ω
GND2
42
GND2
0V
47
VCC2
7V
48
SIGCENT
VCC2/2
VCC2
output DC voltage is to be used with the
setting other than VCC2/2 and VCC2*21/51,
set to the SIG center level changeover: high
300Ω
48
150kΩ
voltage mode with the serial bus and apply the
voltage (3.3 - 3.7V) from the outside.
GND2
VCC1
3.0V
DSDOUT
VCC2/2
VCC2*21/51
150kΩ
7V power supply.
Pin to set the DC voltage of R/G/B/COM/DSD
between this pin and GND2. When the signal
50
1kΩ
VCC2 ground.
output. Connect a capacitor of 0.01μF
49
40μA
Pin Name
150kΩ
Pin No.
105kΩ
Analog 3V power supply.
Drain hold data power output pin. The output
DC voltage can be set to VCC2/2 and
VCC2
1kΩ
VCC2*21/51 with the serial bus. Connect a
capacitor of 1μF between this pin and GND2.
10Ω
1kΩ
50
20Ω
10kΩ
51
NC
-
52
VREG
2.0V
1kΩ
GND2
Pin not used
Regulator output pin. Connect an external
VCC1
capacitor of 1μF or more.
52
18.5kΩ
GND1
53
RIN
54
GIN
1.45V
input signal level is 0.5Vp-p (from sink chip to
55
BIN
white 100%). Pedestal clamp is made with an
30kΩ
Analog RGB signal input pin.The standard
external coupling capacitor.
VCC1
53
54
55
1kΩ
20μA
GND1
Continued on next page.
No.8927-11/27
LV4141W
Continued from preceding page.
Pin No.
Pin Name
Pin Voltage
56
RESET
-
Pin Description
Equivqlent Circuit
C-MOS circuit reset pin. Normally, this is used
VDD1
with the capacity connected to the ground.
(Threshold value = 2.0V)
2μA
300Ω
56
1kΩ
GND1
57
SYNCIN
1.6V
Input pin for sync separation.
VDD1
Input is made via the external capacitor.
1kΩ
1kΩ
57
500Ω
58
VSEPTC
1.7V
Time constant connection pin for vertical sync
VDD1
separation.
500Ω
1kΩ
58
1kΩ
20μA
GND1
64
GND1
-
12μA
0.6μA
GND1
20μA
Analog 3V power supply.
Digital pin function description
Pin No.
Pin Name
Pin Voltage
1
VDD1
-
Power supply dedicated for VCO
Pin Description
2
RPD
-
Phase comparator output pin
Equivqlent Circuit
VDD1
2
1kΩ
6kΩ
100kΩ
100kΩ
1.5V
VSS1
3
VSS1
0
Groud pin for VCO
4
TEST4
-
5
TEST5
TEST4 is an input pin for test.
TEST5 is an output pin for test.
Use while fixing TEST4 to the ground potential
and keeping TEST5 open.
VDD1
4
600Ω
5
VSS1
Continued on next page.
No.8927-12/27
LV4141W
Continued from preceding page.
Pin No.
Pin Name
Pin Voltage
Pin Description
6
LOAD
-
7
DATA
Input possible up to 4.5V regardless of the
8
SCLK
VDD2 power voltage.
Equivqlent Circuit
Serial bus input pin.
VDD2
2kΩ
6
7
8
VSS2
-
TEST8, TEST3, TEST1, and TEST2 are input
9
TEST8
10
TEST3
pins for test.
61
TEST1
Normally, this is used at the ground potential
62
TEST2
or in the open state. CLPIN is an input pin for
63
CLPIN
external clamp. Use after setting to the
external clamp input with the serial bus.
Connect the CLPIN pin to the ground in cases
other than external clamp input.
11
VDD2
-
Power pin for digital block
12
VDD0
-
Power pin for digital system output
13
BLSW
-
Digital output pin.
14
BLHD
15
HD
17
XSTH
18
STH
19
CKH2
20
CKH1
21
TEST6
22
TEST7
23
XDSG
24
DSG
25
XSTV
26
STV
27
CKV2
28
CKV1
29
XENB
30
ENB
31
VD
16
VSSO
VDD2
9
10
61
62
63
2kΩ
50kΩ
VSS2
VDD0
VSS0
-
Power pin for digital system output.
Ground
32
VSS2
0
Digital ground pin.
59
VDIN
-
External VD and HD input pins. When using,
60
HDIN
VDD2
set them to the external synchronous signal
input with the serial bus. Connect VDIN and
50kΩ
HDIN pins to the ground in cases other than
the external synchronous signal input.
2kΩ
59
60
VSS2
No.8927-13/27
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
(A)=SIG4(VL=0mV)
(A)=SIG4(VL=0mV)
HCK duty
Input-output gain TYP
Input-output gain MIN
Input-output gain MAX
Frequency characteristics
Input/output delay rate
Antipole output DC current change
amount
DSD output DC voltage VCC2=8.5V VDSDH
DSD output DC voltage VCC2=7V
RGB output DC voltage VCC2=8.5V VOUTH
VOUT
Cross point time difference
RGB output DC voltage VCC2=7V
RGB output DC voltage difference
Brightness change rate
9
10
11
12
13
14
15
16
17
18
19
20
21
22
OFF
Output transition time
8
OFF
OFF
OFF
(A)=SIG4(VL=0mV)
L-level output voltage
7
OFF
OFF
(A)=SIG4(VL=0mV)
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
(A)=SIG4(VL=0mV)
(A)=SIG3
TP12
TP43
(A)=SIG8
TP43
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
B
B
B
B
B
B
B
B
A
BRTMX
(A)=SIG2
B
OFF
OFF
OFF
ON
OFF
A
B
B
B
B
B
B
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
B
B
B
B
B
B
B
B
B
B
B
B
A
B
53
OFF
P43
(Calculate)
(A)=SIG4
(A)=SIG4
(A)=SIG4
(A)=SIG4
(A)=SIG2
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
45
SW set
OFF OFF OFF OFF
BRTMN P43
(A)=SIG2
(Note) PLL resetting necessary after change of the panel mode (- : arbitrary, ADJ : adjustment, SET : setting)
ΔVOUT
P50
P50
P38
COMBMN
VDSD
P38
COMBMX
(A)=SIG2
(A)=SIG6
TP43
FCL
TD
(A)=SIG6
(A)=SIG3
TP43
TP43
TP43
FCH
GMX
GMN
GTP
DTYHC
(A)=SIG3
OFF
OFF
OFF
TP12
(A)=SIG4(VL=0mV)
ΔT
OFF
OFF
(A)=SIG4(VL=0mV)
TP12
tTHL
OFF
OFF
OFF
(A)=SIG4(VL=0mV)
TP12
tTLH
VOL
VOH
OFF
OFF
OFF
OFF
(A)=SIG4(VL=0mV)
H-level output voltage
VIH
H-level input voltage
6
(A)=SIG4(VL=0mV)
5
OFF
OFF
OFF
(A)=SIG4(VL=0mV)
IDD
IDD3
Current dissipation, VDD(Sleep)
VIL
OFF
OFF
(A)=SIG4(VL=0mV)
IDD
IDD2
Current dissipation, VDD(Standby)
L-level input voltage
OFF
OFF
OFF
(A)=SIG4(VL=0mV)
IDD
OFF
OFF
OFF
ICC2
OFF
OFF
OFF
OFF
IDD1
ICC2
OFF
OFF
(A)=SIG4(VL=0mV)
OFF
OFF
43
ICC1
40
38
(A)=SIG4(VL=0mV)
(A)=SIG4(VL=0mV)
Input signal,
Conditions, etc.
ICC1
Pin
Test
Current dissipation, VDD(Normal)
Current dissipation, VCC2(Standby)
Current dissipation, VCC2(Normal)
ICC11
Symbol
4
3
2
Current dissipation, VCC1(Normal)
1
Current dissipation, VCC1(Standby)
(Setting 2, horizontal AFC
Parameter
0
No.
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
54
B
B
B
B
B
B
B
B
B
B
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A
B
55
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
56
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Panel System
Mode set
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S/H
0
255
ADJ
ADJ
ADJ
ADJ
ADJ
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
BRT
128
128
128
128
128
128
128
128
128
128
128
128
255
0
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
CNT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
R-B
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
B-B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ1
128
128
ADJ
ADJ
ADJ
ADJ
ADJ
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
COMW RCNT BCNT
DAC set
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BLM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WLM
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
51
51
51
51
51
51
51
0
63
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
VCO COMB
LV4141W
No.8927-14/27
Sub-brightness B change rate
Gain difference between RGB
Sub-contrast R change rate
Sub-contrast B change rate
RGB inverted/non-inverted gain
Black level potential difference between RGB signals
Gamma gain
γ1 adjustment variable range
γ2 adjustment variable range
Antipole transition time
RGB output black limiter operating
25
26
27
28
29
30
31
32
33
34
35
Input sync signal amplitude sensitivity
Sync separation input sensitivity
HD output delay rate
39
40
41
No.8927-15/27
P15
P15
HPLLN
HPLLP
TDSY2
TDSY1
VSSEP
P15
(A)=SIG4
ΔVWLIM
(A)=SIG4
(A)=SIG4
(A)=SIG4
(A)=SIG4
(A)=SIG4
(A)=SIG4
(A)=SIG4
WSSEP
(A)=SIG2
ΔVBLIM
(A)=SIG2
(A)=SIG2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
(A)=SIG2
ON
(A)=SIG3
OFF
(A)=SIG3
(A)=SIG7
OFF
OFF
(A)=SIG7
(A)=SIG7
OFF
(A)=SIG7
VWLIMX
VWLIMN
VBLIMX
P15
P38
VBLIMN
P38
tCOM
P43
Vγ2MX
tCOM
P43
P43
Vγ2MN
P43
Vγ1MX
(A)=SIG7
P43
GγH
Vγ1MN
OFF
(A)=SIG7
P43
GγM
OFF
OFF
(A)=SIG7
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
P43
(A)=SIG3
ΔVBL
38
OFF
GγL
(A)=SIG3
ΔGINV
(A)=SIG3
(A)=SIG3
(A)=SIG4
(A)=SIG3
P45
(A)=SIG4
(A)=SIG2
(A)=SIG2
Conditions, etc.
Input signal,
SBCNTB
SBCNTR
ΔGRGB
SBBRTB
P41
P38
COMWMN
SBBRTR
P38
Pin
Test
COMWMX
Symbol
40
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
43
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
B
B
OFF
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
53
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
45
SW set
(Note) PLL resetting necessary after change of the panel mode (- : arbitrary, ADJ : adjustment, SET : setting)
Horizontal pull-in range
White limiter DC voltage difference
38
42
Black limiter DC voltage difference
voltage
RGB output white limiter operating
37
36
Sub-brightness R change rate
24
voltage
Antipole output change amount
Parameter
23
No.
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
54
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
55
56
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PAL
NT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Panel System
Mode set
S/H
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
128
128
128
128
128
128
255
0
255
255
0
0
128
128
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
128
128
128
128
128
160
160
128
128
BRT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
60
60
60
60
ADJ
ADJ
ADJ
128
128
70
70
128
128
128
128
128
CNT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SET
128
128
R-B
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SET
128
128
128
B-B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
255
0
120
120
120
0
0
0
0
0
0
0
0
0
γ1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
255
0
0
0
180
ADJ
ADJ
0
0
0
0
0
0
0
0
0
γ2
128
128
128
128
128
128
128
128
128
128
128
128
ADJ
ADJ
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
255
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SET
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SET
128
128
128
128
128
128
COMW RCNT BCNT
DAC set
0
0
0
0
0
0
0
ADJ
0
0
255
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BLM
0
0
0
0
0
0
8
0
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WLM
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
VCO COMB
LV4141W
LV4141W
Input sine wave (1)
SG No.
Sine wave
SIG1
With/without sine wave video signal
(Amplitude and frequency variable)
150m
143m
← Value shown in the left 0dB
SIG2
357mV
143mV
SIG3
150
5-step staircase wave
143
SIG4
VL amplitude variable
VS variable:
143mV, unless otherwise specified.
VL
WS variable:
4.7μs, unless otherwise specified.
VS
fH variable :
WS
NTSC 15.734kHz
fH
PAL 15.625kHz
unless otherwise specified.
Input sine wave (2)
SG No.
Sine wave
SIG5
30μs
5μs
GND
VL
VL amplitude variable
SYNC
Timing
SIG6
75mV
Frequency variable
175mV
143mV
SIG7
10-step staircase wave
357mV
143mV
SIG8
357mV
2T pulse
143mV
No.8927-16/27
LV4141W
Serial bus communication specifications
(1) Conditions for serial transfer
DATA
D15 D14 D13 D12 D11 D10 D9
ts1
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
th1
50%
SCLK
tw1L
tw1H
LOAD
50%
ts0
Parameter
th0
Symbol
Conditions
min
tw2
typ
max
unit
Serial transfer
Data setup time
Data hold time
Pulse width
ts0
LOAD setup time to start SCLK.
150
ns
ts1
DATA setup time to start SCLK.
150
ns
th0
Hold time of LOAD for fall of SCLK.
150
ns
th1
Data hold time to start SCLK.
150
ns
tw1L
SCLK pulse width.
160
ns
tw1H
SCLK pulse width.
160
ns
tw2
LOAD pulse width.
1.0
μs
No.8927-17/27
LV4141W
(2) 3-wave serial format
DATA
SCLK
LOAD
Data length : 16bit
Clock frequency : 3MHz or less
DATA loaded at start of "LOAD" only when 16-clock of "SCLK" is entered in the "LOAD" "L" period.
(Note) Data not loaded in case of 15 or less clocks or 17 or more clocks in "LOAD" "L" period
(3) Data output timing
1. Various mode settings
Some items (with a circle in the V latch column of data specification) have data set at fall of the vertical
synchronous signal and some (without a mark in the V latch column) do not.
When data immediately before the vertical synchronous signal is transferred for multiple times, data immediately
before vertical synchronous signal becomes effective for items to be set with the vertical synchronous signal. For
items for whcih no setting is made, data becomes effective each time "DATA" is loaded.
2. Setting of the electric volume
D/A output data is changed at the same time with loading of "DATA."
No.8927-18/27
LV4141W
(4) Data specifications
(4-1) Various mode settings 1
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not used
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Not used
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LPF characteristic changeover : High
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
LPF characteristic changeover : Low
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not used
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Not used
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
System changeover NTSC
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
System changeover PAL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External VD input changeover OFF (used to
V latch
Default
○
○
○
○
○
separate IC sync)
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
External VD input changeover ON (with
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Normal mode
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
HD output polarity, positive
○
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
HD output polarity, negative
○
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
VD output polarity, positive
○
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
VD output polarity, negative
○
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Panel selection, 521×218 :L1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
Panel selection, 557×234 :L2
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Not used
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
Not used
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Field overlap method, odd number on even
external VD input)
○
○
○
○
○
○
○
number
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
Field overlap method, even number on odd
○
number
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Horizontal inversion, normal scan
○
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
Horizontal inversion, reverse scan
○
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Vertical inversion, from top to bottom
○
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
Vertical inversion, from bottom to top
○
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Not used
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
Not used
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Normal mode
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
For test. Do not set.
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
For test. Do not set.
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
For test. Do not set.
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
For test. Do not set.
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
External SYNC input polarity change, negative
○
○
○
○
○
polarity
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
External SYNC input polarity, positive polarity
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
External clamp input changeover OFF (IC
○
internal pulse used)
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
External clamp input changeover ON (external
pulse input)
HSYNC/CSYNC input changeover. SYNC IN
○
valid
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
HSYNC input changeover. HD IN valid
No.8927-19/27
LV4141W
(4-1) Various mode settings 2
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Description
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Normal mode
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
For test. Do not set.
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
VGATE function ON
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
VGATE function OFF
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Normal mode
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
For test. Do not set.
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
For test. Do not set.
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
SIG center level changeover Low voltage
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
SIG center level changeover High voltage
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Normal mode
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
1
0
0
×
×
×
0
0
0
0
0
1
0
1
×
×
×
0
0
0
0
0
1
1
0
×
×
×
0
0
0
0
0
1
1
1
×
×
×
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
HC5 HC4 HC3 HC2 HC1
V latch
Default
○
○
○
○
○
H-position setting, 2fh×31Step (Note 1)
○
V-position setting, 1H×4Step (Note 2)
○
010
HD6 HD5 HD4 HD3 HD2
HD phase setting, 4fh×31Step (Note 3)
○
00000
HW5 HW4 HW3 HW2 HW1
BLHD pulse setting, 2fh×31Step (Note 4)
○
10000
×
×
0
VP2 VP1 VP0
0
0
0
Not used
0
0
0
Normal mode
0
0
1
For test. Do not set.
1
0
For test. Do not set.
0
0
For test. Do not set.
0
0
0
For test. Do not set.
0
0
0
0
V blanking period CKH?STH stop OFF
○
0
0
0
0
V blanking period CKH/STH stop ON
○
0
0
0
0
0
H blanking period CKH stop OFF
○
0
0
0
0
0
H blanking period STH stop ON
○
0
0
0
0
0
0
Normal mode
1
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
0
0
HD/VD output ON
0
0
0
0
0
0
0
1
HD/VD output OFF (HD generation counter stop)
0
0
0
0
0
0
0
0
0
BLHD output ON
1
0
0
0
0
0
0
0
1
0
BLHD output OFF (BLHD generation counter
0
1
0
0
0
0
0
0
0
0
0
Backlight OFF (BLSW = 3V)
1
0
1
0
0
0
0
0
0
1
0
0
Backlight ON (BLSW = 0V)
0
1
0
1
0
0
0
0
0
0
0
0
0
Normal mode
0
0
1
0
1
0
0
0
0
0
1
0
0
0
For test. Do not set.
0
0
1
0
1
0
0
0
0
1
0
0
0
0
For test. Do not set.
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
For test. Do not set.
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
Horizontal system counter operation
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
Horizontal system counter stop
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
Not used
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Not used
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
Not used
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
Not used
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Not used
10000
○
○
○
○
○
○
stop)
○
○
○
(effective at standby only)
No.8927-20/27
LV4141W
(4-1) Various mode settings 3
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Description
V latch
Default
○
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Standby mode (Note 6)
Note 6
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
Sleep mode (Note 6)
Note 6
Note 6
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
Normal mode (Note 6)
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
Not used
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Blanking at transfer to normal ON
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
Blanking at transfer to normal OFF
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Blanking period at transfer to normal changed to 0.25
○
○
sec
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
Blanking period at transfer to normal changed to 0.5
sec
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Normal mode
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
○
1
0
0
0
0
For test. Do not set.
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
For test. Do not set.
0
0
0
0
0
0
Sample hold phase SHS1 (Note 5)
0
0
0
0
0
1
Sample hold phase SHS2 (Note 5)
0
0
0
0
0
1
0
Sample hold phase SHS3 (Note 5)
0
0
0
0
0
0
1
1
Sample hold phase SHS4 (Note 5)
0
0
0
0
0
1
0
0
Sample hold phase SHS5 (Note 5)
1
0
0
0
0
0
1
0
1
Sample hold phase SHS6 (Note 5)
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
×
Sample hold phase, ALL through (Note 5)
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
Normal mode
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
For test. Do not set.
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
For test. Do not set.
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
For test. Do not set.
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
For test. Do not set.
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
For test. Do not set.
D6
D5
D4
D3
D2
D1
D0
○
○
(4-2) Electronic volume setting
D15 D14 D13 D12 D11 D10 D9
D8
D7
Description
Default
1
0
0
0
0
0
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Not used
1
0
0
0
0
0
0
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Not used
1
0
0
0
0
0
1
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
BRIGHT adjustment
10010101
1
0
0
0
0
0
1
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
CONTRAST adjustment
10001100
1
0
0
0
0
1
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
R-BRIGHT adjustment
10000000
1
0
0
0
0
1
0
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
B-BRIGHT adjustment
10000000
1
0
0
0
0
1
1
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
γ-1 adjustment
01100100
1
0
0
0
0
1
1
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
γ-2 adjustment
00000000
1
0
0
0
1
0
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Not used
1
0
0
0
1
0
0
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
R-CONT adjustment
10000000
1
0
0
0
1
0
1
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
B-CONT adjustment
10000000
1
0
0
0
1
0
1
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
BLKLIMT adjustment
10101100
1
0
0
0
1
1
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Not used
1
0
0
0
1
1
0
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Not used
1
0
0
0
1
1
1
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Not used
1
0
0
0
1
1
1
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
VCO adjustment
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
1
0
1
1
1
0
0
0
0
0
×
×
×
×
DA3 DA2 DA1 DA0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
×
×
DA5 DA4 DA3 DA2 DA1 DA0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
WHTLIMT adjustment
COM amplitude adjustment
COM level adjustment
10000000
0000
10000000
100000
For test. Do not set.
No.8927-21/27
LV4141W
(Note 1) H-Position set
(1Step = 2×1/fh) : 1/fh = 90ns
CLK(fh)
10001(+1)
STH
10000(Default)
01111(-1)
Step 1
Step 1
Step 15
Step 16
Center
(Note 2) V-Position set
-2H
(VD)
-1H
(VD)
2H
(VD)
STV(Default)
+1H
(VD)
+2H
(VD)
(Note 3) HD phase set
(1Step = 4×1/fh)
HSYNC
Approx.6.5μs
Approx.2μs
HD
00000
(Default)
11111
HD
Step 31
No.8927-22/27
LV4141W
(Note 4) BLHD phase set
(1Step = 2×1/fh)
00000
Step 16
Approx.7μs
10000
BLHD
(Default)
Step 15
11111
(Note 5) Sample hold phase
S/H pulse timing
CKH
S/H3
B
S/H4
A
B
S/H2
R
S/H4
C
G
D
S/H4
S/H1
E
SH3
SH2
SH1
SH4
F
CSH = H (Normal)
SHS1
SHS2
SHS3
SHS4
SHS5
SHS6
SH1
B
C
D
E
F
A
SH2
F
A
B
C
D
E
SH3
D
E
F
A
B
C
SH4
C
D
E
F
A
B
SHS1
SHS2
SHS3
SHS4
SHS5
SHS6
SH1
D
E
F
A
B
C
SH2
F
A
B
C
D
E
SH3
B
C
D
E
F
A
SH4
C
D
E
F
A
B
CSH = L (Inverted)
SH1 : SH pulse for G signal
SH3 : SH pulse for B signal
SH2 : SH pulse for R signal
SH4 : SH pulse for RGB signal
No.8927-23/27
LV4141W
(Note 6) Powr save function
a) Signal output in each mode
Output Pin
Normal
Standb
Sleep
RGBout
DSD
Normal output
all OFF
COM
CKH1
CKH1 = H
CKH2
CKH2 = L
STH
STH = H
XSTH
XSTH = L
DSG
PCG1 = H
XDSG
ENB
PCG2 = L
Normal output
ENB = H
XENB
XENB = L
CKV1
CKV1 = H *
CKV2
CKV2 = L *
STV
STV = H *
XSTV
XSTV = L *
all “L”
HD
VD
Normal output
BLHD
BLSW
Normal output
* After transfer from normal to standby, the respective state becomes effective after normal output for the 1V period.
b) Transfer/return to each mode
• Transfer/return between normal and standby modes is acknowledged with the vertical synchronous signal.
• Transfer/return between standby and sleep modes is changed over each time the serial data is transmitted.
• Transfer/return between normal and sleep modes cannot be made directly.
Be sure to carry out changeover via the standby mode.
No.8927-24/27
LV4141W
Sampl Application Circuit (at input of internal synchronous separate signal)
0.01μF
0.47μF
46
45
44
43
42
41
40
39
38
37
36
35
34
VCC2
FBR
ROUT
FBG
GOUT
GND2
FBB
BOUT
VCCCOM
COMOUT
GNDCOM
FBCOM
CSHO
CSVO
VSS2 32
49 VCC1
+
1μF
VD 31
50 DSDOUT
ENB 30
51 NC
XENB 29
53 RIN
CKV1 28
54 GIN
CKV2 27
55 BIN
STV 26
56 RESET
DSG 24
58 VSEP TC
XDSG 23
59 VDIN
TEST7 22
60 HDIN
TEST6 21
47μF
+
BLSW
BLHD
HD
+3V
VDD0
XSTH 17
VDD2
64 GND1
TEST3
STH 18
TEST8
63 CLPIN
SCLK
CKH2 19
DATA
62 TEST2
LOAD
CKH1 20
TEST5
61 TEST1
TEST4
0.33μF
57 SYNC IN
VSS1
0.01μF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
10kΩ
+
1μF
To Serial
Controller
6800pF
To LCD
Panel
XSTV 25
LV4141W
22000pF
RPD
B
52 VREG
VDD1
G
+
1μF
+
1μF
+
1μF
+
1μF
0.01μF
R
33
SHIN
47
To LCD
Panel
VSS0
To LCD
Panel
48
SIGCENT
+
47μF
0.01μF
+3V
0.47μF
0.47μF
0.47μF
10kΩ
0.47μF
+
47μF
10kΩ
To LCD
Panel
+7V
16
+3V
47μF
+
0.01μF
No.8927-25/27
LV4141W
Sampl Application Circuit (at input of external synchronous separate signal)
0.01μF
0.47μF
0.47μF
0.47μF
0.47μF
10kΩ
0.47μF
+
47μF
10kΩ
To LCD
Panel
+7V
To LCD
Panel
G
B
45
44
43
42
41
40
39
38
37
36
35
34
+
VCC2
FBR
ROUT
FBG
GOUT
GND2
FBB
BOUT
VCCCOM
COMOUT
GNDCOM
FBCOM
CSHO
CSVO
VSS2 32
50 DSDOUT
+
1μF
+
1μF
+
1μF
+
1μF
22000pF
33
SHIN
46
49 VCC1
1μF
R
47
0.01μF
+
47μF
48
SIGCENT
+3V
VD 31
51 NC
ENB 30
52 VREG
XENB 29
53 RIN
CKV1 28
54 GIN
CKV2 27
55 BIN
STV 26
56 RESET
XSTV 25
LV4141W
57 SYNC IN
DSG 24
58 VSEP TC
XDSG 23
0.33μF *1
59 VDIN
(VD)
*2
60 HDIN
CSYNC,(HD)
61 TEST1
TEST7 22
62 TEST2
CKH2 19
63 CLPIN
STH 18
64 GND1
XSTH 17
+
DATA
SCLK
TEST8
TEST3
6
7
8
9
10
1μF
1kΩ
+
To Serial
Controller
6800pF
11
12
VSS0
LOAD
5
HD
TEST5
4
BLHD
TEST4
3
BLSW
VSS1
2
VDD0
RPD
1
VDD2
VDD1
CKH1 20
10kΩ
47μF
TEST6 21
0.01μF
+3V
To LCD
Panel
13
14
15
16
To LCD
Panel
+3V
47μF
+
0.01μF
*1 Delete (open) at input of external VD.
*2 Connect pin 59 to GND at input of composite sink
No.8927-26/27
LV4141W
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of April, 2007. Specifications and information herein are subject
to change without notice.
PS No.8927-27/27