CXA3503R Driver/Timing Generator for Color LCD Panels Description The CXA3503R is an IC designed to drive the color LCD panels LCX032 and LCX033. This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc. Features • Color LCD panel LCX032 and LCX033 driver • Supports NTSC and PAL systems • Supports 16:9 wide display (letter box and pulse elimination display) • Supports Y/color difference and RGB inputs • Supports OSD input (digital input) • Power saving function • Serial interface circuit • Electronic attenuators (D/A converter) • Trap and LPF (f0, fc variable) • COMMON output circuits • Sharpness function • 2-point γ correction circuit • R, G, B signal delay time adjustment circuit • D/A output pin (0 to 3V, 8 level output) • Output polarity inversion circuit • Supports AC drive for LCD panel during no signal 72 pin LQFP (Plastic) • Digital input pin voltage VIND (other than Pins 5, 10, 14, 15 and 16) VSS – 0.3 to VDD + 0.3 V VIND (Pins 5, 10) VSS – 0.3 to +5.5 V • Common input pin voltage VINAD (Pins 14, 15 and 16) GND, VSS – 0.3 to +5.5 V • Operating temperature Topr –15 to +75 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD (Ta ≤ 25°C) 737 mW Operating conditions • Supply voltage 2.7 to 3.6 V VCC1 – GND1 VCC2 – GND2 11.0 to 14.0 V VCC3 – GND3 11.0 to 14.0 V VDD – Vss 2.7 to 3.6 V • Input voltage SIG.C voltage VSIG.C 5.0 to 6.5 V RGB input signal voltage (Pins 70, 71 and 72)∗1 VRGB 0 to 0.7 (0.5 typ.) Vp-p Y input signal voltage (Pin 71)∗2 VY 0 to 0.5 (0.35 typ.) Vp-p R-Y input voltage (Pin 72)∗2 Applications Color LCD viewfinders Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC1 6 V VCC2 15 V VCC3 15 V 5.5 V VDD • Analog input pin voltage VINA (Pins 57, 58 and 59) GND – 0.3 to VCC1 + 0.3 V VINA (Pins 3, 69) VCC1 V V VINA (Pin 30) 1.5 to VCC2 – 4 VINA (Pin 71) 0.9 Vp-p VINA (Pins 70, 72) 0.8 Vp-p VR-Y 0 to 0.49 (0.245 typ.) Vp-p B-Y input voltage (Pin 70)∗2 VB-Y 0 to 0.622 (0.311 typ.) Vp-p ∗1 During RGB input ∗2 During Y/color difference input Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99733A98-PS CXA3503R POF TST8 47 46 45 44 43 42 GND3 41 40 39 38 +12.0V Vcc2 DWN 48 TST5 TST9 49 TST6 TST10 50 TST7 TST11 51 Vcc3 TST12 52 COM TST13 53 Vss GND3 TST14 54 Vss Vss Vss Block Diagram 37 +12.0V Buf VDD 55 +3.0V LPF FILTER USER-BRIGHT TST15 56 CONTRAST S/H GEN OSD B 57 CONT 35 G DC DET U-BRT FILTER BIAS TRAP OSD R 58 LPF GAMMA CLAMP OSD G 59 G R B 34 R OUT Buf γ1γ2 WHITLIM SUB-CONT R SUB-CONT B 33 R DC DET 32 B OUT Buf BLK-LIM BLK 60 31 B DC DET BLKLIM MODE SUB-BRIGHT HCK1 61 HCK GEN HCK2 62 G PIC-G R B PICTURE EN 66 29 GND2 COM-DC 28 TST4 DL1 PLL COUNTER DL1 PULSE ELM HUE PIC-F STB 67 30 SIG.C GND2 POL SW MATRIX HST 64 HCOUNTER HPULSE GEN SIG.C SUB-BRT R SUB-BRT B CLAMP Vcc1 63 +3.0V RGT 65 36 G OUT Buf S/H OSD RGB HUE COLOR CLAMP HDO GEN 27 HDO VDO GEN 26 VDO 25 XCLR V CONTROL V POSITION PHASE COMPARATOR CLP VCK 68 Vss 23 Vss HSYNC DET H SKEW DET V COUNTER FIL IN 69 24 RPD 22 CKI V SEP MODE CK CONTROL B/B-Y 70 CLK 21 CKO MCK G/Y 71 +3.0V 20 VDD DA +3.0V 19 VDD R/R-Y 72 H.FILTER SYNC SEP S/P CONV REGISTER DAC Buf SYNC OUT CSYNC/HD DA OUT TST1 F ADJ GND1 11 12 13 14 15 16 17 18 VSS SYNC IN Vss 10 R INJECT 9 SDAT 8 SEN 7 SCK 6 TST3 5 TST2 4 VST 3 VD 2 FIL OUT GND1 1 Vss Vss –2– CXA3503R Pin Description Pin No. Symbol I/O Description 1 VSS — Digital 3.0V GND 2 FIL OUT O H filter output (for using internal sync separation) 3 SYNC IN I Sync separation circuit input (for using internal sync separation) 4 SYNC OUT O Sync separation circuit output (for using internal sync separation) 5 CSYNC/HD I CSYNC/horizontal sync signal input 6 DA OUT O DAC output 7 TST1 — Test (Leave this pin open.) 8 F ADJ O Trap f0 adjusting resistor connection 9 GND1 — Analog 3.0V GND 10 VD I Vertical sync signal input 11 VST O V start pulse output 12 TST2 — Test (Leave this pin open.) 13 TST3 — Test (Leave this pin open.) 14 SCK I Serial clock input 15 SEN I Serial load input 16 SDAT I Serial data input 17 R INJECT O Serial block current controlling resistor connection 18 VSS — Digital 3.0V GND 19 VDD — Digital 3.0V power supply 20 VDD — Digital 3.0V power supply 21 CKO O Oscillation cell output 22 CKI I Oscillation cell input 23 VSS — Digital 3.0V GND 24 RPD O Phase comparator output 25 XCLR I Power-on reset capacitor connection (timing generator block) 26 VDO O VDO pulse output 27 HDO O HDO pulse output 28 TST4 — Test (Connect to GND.) 29 GND2 — Analog 12.0V GND 30 SIG.C I R, G and B output DC voltage adjustment 31 B DC DET O B signal DC voltage feedback circuit capacitor connection 32 B OUT O B signal output 33 R DC DET O R signal DC voltage feedback circuit capacitor connection 34 R OUT O R signal output 35 G DC DET O G signal DC voltage feedback circuit capacitor connection 36 G OUT O G signal output 37 VCC2 — Analog 12.0V power supply –3– Input pin for open status L H CXA3503R Pin No. Symbol I/O Description 38 TST5 — Test (Leave this pin open.) 39 TST6 — Test (Leave this pin open.) 40 TST7 — Test (Leave this pin open.) 41 VCC3 — Analog 12.0V COM power supply 42 COM O Common pad voltage for LCD panel output 43 GND3 — Analog 12.0V COM GND 44 TST8 — Test (Leave this pin open.) 45 POF O LCD panel power supply on/off (Leave this pin open when not using this function.) 46 DWN O Right/left inversion switching signal output 47 TST9 — Test (Connect to GND.) 48 TST10 — Test (Connect to GND.) 49 TST11 — Test (Leave this pin open.) 50 TST12 — Test (Leave this pin open.) 51 TST13 — Test (Leave this pin open.) 52 TST14 — Test (Leave this pin open.) 53 VSS — Digital 3.0V GND 54 VSS — Digital 3.0V GND 55 VDD — Digital 3.0V power supply 56 TST15 — Test (Connect to GND.) 57 OSD B I OSD B input 58 OSD R I OSD R input 59 OSD G I OSD G input 60 BLK O BLK pulse output 61 HCK1 O H clock pulse 1 output 62 HCK2 O H clock pulse 2 output 63 VCC1 — Analog 3.0V power supply 64 HST O H start pulse output 65 RGT O Right/left inversion switching signal output 66 EN O EN pulse output 67 STB O STB pulse output 68 VCK O V clock pulse output 69 FIL IN I H filter input (for using internal sync separation) 70 B/B-Y I B/B-Y signal input 71 G/Y I G/Y signal input 72 R/R-Y I R/R-Y signal input ∗ DWN: DOWN SCAN and UP SCAN, RGT: RIGHT SCAN and LEFT SCAN H: pull-up processing, L: pull-down processing –4– Input pin for open status CXA3503R Analog Block Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description VCC1 23k 2 FIL OUT Amplifies and outputs the sync portion of the video signal input to FIL IN (Pin 69). 2 2.15V 200 GND1 VCC1 3 SYNC IN 1.1V Sync separation circuit input. Inputs the FIL OUT (Pin 2) output signal via a capacitor. 200 3 GND1 VCC1 4 SYNC OUT Sync separation output. Positive polarity output in open collector format. — 4 GND1 VCC1 6 DA OUT — 50 6 50 DA output. Outputs the serial data converted to DC voltage. The current driving capacity is ±1.0mA (max.). GND1 VCC1 8 F ADJ 6.5k 1.1V 8 10 GND1 –5– Connect a resistor between this pin and GND1 to control the internal LPF and trap frequencies. Connect a 33kΩ resistor (tolerance ±2%, temperature characteristics ±200ppm or less). This pin is easily affected by external noise, so make the connection between the pin and external resistor, and between the GND side of the external resistor and the GND1 pin as close as possible. CXA3503R Pin No. 9 Symbol GND1 Pin voltage Equivalent circuit Description — Analog 3.0V GND. VCC1 14 15 16 SCK SEN SDAT 14 — Serial clock, serial load and serial data inputs for serial communication. 15 200 16 GND1 Connect a resistor for setting the injector current of the IIL logic circuit. Connect a 15kΩ resistor between this pin and GND1. Use a resistor with a deviation of ±2% and temperature characteristics of ±200ppm or less. VCC1 17 R INJECT 0.7V 200 17 GND1 29 GND2 Analog 12.0V GND. (for the RGB output circuits) — R, G and B output DC voltage setting. Connect a 0.01µF capacitor between this pin and GND1. When using a SIG.C of other than VCC2/2, input the SIG.C voltage from an external source. VCC2 Preset VCC2/2 30 SIG.C 140k 200 Variable range: 5.0 to 6.5V 30 10p 140k GND1 VCC2 31 33 35 B DC DET R DC DET G DC DET VCC1 31 1.8V 33 35 200 GND1 –6– Smoothing capacitor connection for the feedback circuit of R, G and B output DC level control. Connect a low-leakage capacitor. CXA3503R Pin No. Symbol Pin voltage Equivalent circuit Description VCC2 32 34 36 B OUT R OUT G OUT VCC2/2 (SIG.C = preset) 32 10 34 10 36 166k R, G and B signal outputs. The DC level is controlled to match the SIG.C pin voltage. Low output in power saving mode. VCC2/2V output when preset. GND2 37 VCC2 12.0V Analog 12.0V power supply. (for the RGB output circuits) 41 VCC3 12.0V Analog 12.0V power supply. (for COM output) VCC3 42 COM — 200 42 90k COMMON voltage output. The output voltage is controlled by serial communication. GND3 43 GND3 Analog 12.0V GND. (for COM output) — VCC1 57 58 59 OSD B OSD R OSD G Vth1 = VCC1 × 1/3 57 Vth2 = VCC1 × 2/3 50k 58 59 50k GND1 63 VCC1 OSD pulse inputs. When one of these input pins exceeds the Vth1 level, all of the outputs go to black limiter level; when an input pin exceeds the Vth2 level, only the corresponding output goes to white limiter level. Analog 3.0V power supply. — VCC1 69 FIL IN 1.2V H filter input. Input the video signal via a capacitor. 200 69 GND1 –7– CXA3503R Pin No. Symbol Pin voltage Equivalent circuit G/Y 1.8V In Y/color difference input mode, input the Y signal to Pin 71, the B-Y signal to Pin 70, and the R-Y signal to Pin 72. In RGB input mode, input the B signal to Pin 70, the G signal to Pin 71 and the R signal to Pin 72. Pedestal clamp these pins with external coupling capacitors. VDD1 70 71 72 B/B-Y G/Y R/R-Y R/R-Y, B/B-Y, RGB: 1.8V 70 Y/color difference: 2.0V GND1 Description 200 71 72 –8– CXA3503R Digital Block Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description 1 18 23 53 54 VSS — Digital 3.0V GND. 19 20 55 VDD — Digital 3.0V power supply. 5 14 15 16 CSYNC/HD SCK SEN SDAT Composite sync/horizontal sync signal input, and serial clock, serial load and serial data inputs for serial communication. 5 15 — 14 16 VSS 10 10 VD — Vertical sync signal input. VSS 21 CKO — Oscillation circuit output. 22 CKI — Oscillation circuit input. 24 RPD — Phase comparator output. VDD 25 XCLR — Digital block system reset. 25 VSS 11 26 27 45 46 61 62 64 65 66 67 68 VST VDO HDO POF DWN HCK1 HCK2 HST RGT EN STB VCK VDD 11 45 62 66 — Digital block outputs. 26 46 64 67 27 61 65 68 VSS –9– CXA3503R Test Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description 7 12 13 38 39 40 44 49 50 51 52 TST1 TST2 TST3 TST5 TST6 TST7 TST8 TST11 TST12 TST13 TST14 — Test. Leave these pins open. 28 47 48 56 TST4 TST9 TST10 TST15 — Test. Connect to GND. – 10 – CXA3503R Setting Conditions for Measuring Electrical Characteristics Use the Electrical Characteristics Measurement Circuit on page 22 when measuring electrical characteristics. For measurement, the digital block must be initialized and power saving must be canceled by performing Settings 1 and 2 below. In addition, the serial data must be set to the initial settings shown in the table below. Setting 1. Horizontal AFC adjustment Input a signal and adjust the VCO using V22 so that WL and WH of the TP24 output waveform are the same. Setting 2. Canceling power saving mode The power-on default is power saving mode, so clear (set all "0") serial data PS0, PS1, PS2, PS3, PS4 and SYNC GEN. Horizontal sync signal WS WS RPD (Pin 24) WL WH WL WH WL = WH Fig. 1. Horizontal AFC adjustment Serial data initial settings MSB ADDRESS LSB D15 D14 D13 D12 D11 D10 D9 ∗1 D8 MSB DATA D7 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 LSB D5 D4 D3 D2 D1 D0 (01000110/LSB) USER-BRIGHT (10001010/LSB) SUB-BRIGHT R (10001010/LSB) SUB-BRIGHT B (00111111/LSB) CONTRAST (10011111/LSB) SUB-CONTRAST R (10011111/LSB) SUB-CONTRAST B (11111111/LSB) γ-2 (11111111/LSB) γ-1 0 0 0 0 0 0 (10000000/LSB) COM-DC (00000000/LSB) COLOR (10000000/LSB) HUE WHITE-LIMITER (00/LSB) FILTER (00/LSB) 0 BLACK-LIMITER (11111/LSB) 0 0 0 PICTURE-GAIN (00000/LSB) LPF (000/LSB) PICTURE-F0 0 (00/LSB) 0 0 MODE (1) DA (000/LSB) SYNC GEN PS 4 PS 3 PS 2 PS 1 PS 0 (0) (0) (0) (0) (0) (0) SLRGT (0) SLSH2 (1) SLSH1 (1) SLSH0 (1) SLSYS2 (0) SLSYS (1) SLWD (0) SLPL (0) SLTST0 (0) SLFL (0) SLFR (0) SL4096 (0) SLCLP2 (0) SLCLP1 (0) SLVDP (0) SLHDP (0) SLTST5 (0) SLTST4 (0) SLTST3 (0) SLTST2 (0) SLDWN (0) SLSYP (1) SLTST1 (0) SLEXVD (0) 0 0 0 H-POSITION (10000) 0 0 0 HD-POSITION (00000) Note) If there is the possibility that data may be set at other than the above-noted addresses, set these data to "0". When using, the address data ∗1 must be set all "0". – 11 – CXA3503R Electrical Characteristics — DC Characteristics Analog Block Unless otherwise specified, Ta = 25°C, VCC1 = VDD =3.0V, VCC2/VCC3 = 12.0V, SW4 = off for the current consumption measurement, see page 11 for the DAC. Item Symbol Measurement conditions Min. Typ. Max. Unit Current consumption 1 (Y/color difference input) I1 Measure the inflow current to Pin 63. 27.0 37.0 mA Current consumption 2 (Y/color difference input) I2 Measure the inflow current to Pin 37. 3.8 5.0 mA Current consumption 3 (Y/color difference input) I3 Measure the inflow current to Pin 41. 0.90 1.3 mA Current consumption 1 (RGB input) IRGB1 Measure the inflow current to Pin 63. 23.0 30.0 mA Current consumption 2 (RGB input) IRGB2 Measure the inflow current to Pin 37. 3.8 5.0 mA Current consumption 3 (RGB input) IRGB3 Measure the inflow current to Pin 41. 0.90 1.3 mA Current consumption 1 (PS0 = 1) IPS01 Measure the inflow current to Pin 63. 7.5 10.0 mA Current consumption 2 (PS0 = 1) IPS02 Measure the inflow current to Pin 37. 0.18 0.35 mA Current consumption 3 (PS0 = 1) IPS03 Measure the inflow current to Pin 41. 1.00 Current consumption 1 (PS2 = 1) IPS21 Measure the inflow current to Pin 63. 26.5 36.5 mA Current consumption 1 (PS4 = 1) IPS41 Measure the inflow current to Pin 63. 26.5 36.5 mA Current consumption 1 (SYNC GEN = 1) ISG1 Measure the inflow current to Pin 63. 7.0 Current consumption 2 (SYNC GEN = 1) ISG2 Measure the inflow current to Pin 37. 0.18 0.35 mA Current consumption 3 (SYNC GEN = 1) ISG3 Measure the inflow current to Pin 41. 1.00 µA FIL OUT pin voltage V2 During no input 1.8 2.1 2.4 V SYNC IN pin voltage V3 During no input 1.8 1.1 1.4 V SYNC OUT pin voltage V4 During no input 0.2 0.4 V F ADJ pin voltage V8 0.8 1.1 1.4 V R INJECT pin voltage V17 0.4 0.7 1.0 V SIG.C pin voltage V30 5.8 6.0 6.2 V B DC DET pin voltage V31 1.5 1.8 2.1 V R DC DET pin voltage V33 1.5 1.8 2.1 V G DC DET pin voltage V35 1.5 1.8 2.1 V FIL IN pin voltage V69 0.9 1.2 1.5 V B/B-Y pin voltage 1 V70 During Y/color difference input 1.7 2.0 2.3 V B/B-Y pin voltage 2 V70 During RGB input 1.5 1.8 2.1 V G/Y pin voltage V71 1.5 1.8 2.1 V R/R-Y pin voltage 1 V70 During Y/color difference input 1.7 2.0 2.3 V R/R-Y pin voltage 2 V70 During RGB input 1.5 1.8 2.1 V OSD input resistance V57 V58 V59 80 100 120 – 12 – 9.5 µA mA kΩ CXA3503R Digital Block (including some analog block) Item Symbol High level input voltage VIH Low level input voltage VIL (Ta = –15 to +75°C, VDD = VCC1 = 3.7 to 3.6V) Measurement conditions Min. Typ. VDD × 0.7 Low level threshold voltage VT–1 VT+1 – VT–1 High level threshold voltage VT+2 Schmitt buffer Low level threshold voltage VT–2 Unit V High level threshold voltage VT+1 Hysteresis voltage Max. VDD × 0.3 V 2.6 V 0.6 V 0.4 V 2.6 V 0.2 V Hysteresis voltage VT+2 – VT–2 High level input current | IIH1 | VI = VDD 1.0 µA Low level input current | IIL1 | VI = 0V 1.0 µA High level input current | IIH2 | VI = VDD 3.0 µA Low level input current | IIL2 | VI = 0V 10 40 100 µA High level input current | IIH3 | VI = VDD 10 40 100 µA Low level input current | IIL3 | VI = 0V 3.0 µA High level input current | IIH4 | VI = VDD 1.0 µA Low level input current | IIL4 | VI = 0V 2.0 µA Low level output voltage VOL1 IOL = 1mA 0.3 V High level output voltage VOH1 IOH = –0.25mA Low level output voltage VOL2 IOL = 2mA High level output voltage VOH2 IOH = –0.5mA Low level output voltage VOL4 IOL = 1.5mA High level output voltage VOH4 IOH = –1.25mA Output leak current | IOZ | High impedance status ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 ∗9 ∗10 ∗11 ∗1 ∗2 V 0.6 2.6 Applicable pins ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 V 0.3 2.6 V ∗9 V 0.4 VDD – 0.5 V ∗10 V 1.0 µA ∗11 XCLR (Pin 25), CKI (Pin 22) CSYNC/HD (Pin 5), VD (Pin 10) SCK (Pin 14), SEN (Pin 15), SDAT (Pin 16) CSYNC/HD (Pin 5), CKI (Pin 22) XCLR (Pin 25) VD (Pin 10) SCK (Pin 14), SEN (Pin 15), SDAT (Pin 16) VST (Pin 11), DWN (Pin 46), BLK (Pin 60), RGT (Pin 65), EN (Pin 66), STB (Pin 67), VCK (Pin 68) RPD (Pin 24), VDO (Pin 26), HDO (Pin 27), POF (Pin 45), HCK1 (Pin 61), HCK2 (Pin 62), HST (Pin 64) CKO (Pin 21). However, when measuring the output pin (CKO), the input level of the input pin (CKI) should be 0V or VDD. RPD (Pin 24) – 13 – CXA3503R Electrical Characteristics AC Characteristics Unless otherwise specified, Settings 1 and 2, the serial data initial settings, and the following setting conditions are required. Ta = 25°C, VCC1 = 3.0V, VCC2 = VCC3 = 12V, GND1/2/3 = 0V, VSS = 0V, SW2 = ON, SW4 = ON, SW32/34/36 = OFF, no video input, SG1 input to TP5 Note: Serial data values in the table are HEX notation. Symbol Serial data setting (HEX) Maximum gain between input and output Y/color difference GMAX CONT FFh Input SG2 (50mVp-p) to TP71 and measure the output amplitude at TP36. 29 32 34 dB Maximum gain between input and output RGB GRGBMAX CONT FFh Input SG2 (50mVp-p) to TP71 and MODE 00h measure the output amplitude at TP36. 26 29 31 dB Amount of contrast Gcon attenuation Assume the output amplitude at TP36 when CONT 00h SG2 (0.5Vp-p) is input to TP71 as GMIN. ∆gcon = GMAX – GMIN 25 30 Inverted and non-inverted gain difference ∆GINV Assume the inverted output amplitude at TP36 when SG2 (0.35Vp-p) is input to TP71 CONT 2Fh as Vinv, and the non-inverted output amplitude as Vninv. ∆ginv = 20 log (Vninv/Vinv) Gain difference between R, G and B Input SG2 (0.35Vp-p) to TP71 (TP70, TP72), ∆GRGB1 CONT 2Fh measure the non-inverted output amplitude at TP32, TP34 and TP36, and obtain the MODE 00h maximum and minimum difference between ∆GRGB2 CONT 2Fh these values. Item ∆GSC1 Sub-contrast variable amount ∆GSC2 Sub-bright variable amount ∆VSB1 ∆VSB2 Set CONT = 26h, input SG2 (0.35Vp-p) to SUB-CONT TP71, and assume the non-inverted output 00h amplitude at TP32 and TP34 when SUBCONT R/B = 9Ah, 00h and FFh as V1, V2 SUB-CONT and V3, respectively. ∆Gsc1 = 20 log (V3/V1) FFh ∆Gsc2 = 20 log (V2/V1) SUB-BRT Set U-BRT = 1Ah and measure the nonR, B 00h inverted level at TP32 and TP34 relative to SUB-BRT the non-inverted black level at TP36 when R, B FFh SUB-BRT R/B = FFh and 00h. VBL1 BLK-LIM 00h VBL2 BLK-LIM 1Fh Black limiter variable amount Measurement conditions Min. Typ. Max. Unit dB ±0.3 dB 0.6 dB 0.6 –5.5 –4.5 dB 2.0 2.7 –1.5 –1.0 V 0.8 1.2 Set U-BRT = FFh, measure the inverted and non-inverted black limit level at TP36 when ±1.6 ±2.1 ±2.7 BLK-LIM = 00h and 1Fh, and assume the difference from the output DC voltage as ±4.7 ±5.1 ±5.4 VBL1 and VBL2, respectively. – 14 – V CXA3503R Item Symbol VWL1 White limiter variable amount VWL2 Serial data setting (HEX) Measurement conditions WHITE-LIM Set CONT = FFh, input SG2 (0.35Vp-p) to TP71, measure the inverted and non-inverted ±1.2 ±0.6 ±0 00h white limit level when WHITE-LIM = 00h and 03h, and assume the difference from the WHITE-LIM output DC voltage as VWL1 and VWL2, ±0.6 ±1.2 ±1.8 03h respectively. Black level difference between ∆VB R, G and B Measure the non-inverted black level at TP32, TP34 and TP36, and obtain the maximum and minimum difference between these values. RGB output DC voltage Measure the output DC level (average voltage) at TP32, TP34 and TP36 Vc ∆UB1 U-BRT 00h ∆UB2 U-BRT 7Ah θ1 Hue variable amount θ2 PIC-G 01h GP2 PIC-G 1Fh GC1 COLOR 00h GC2 COLOR FFh Picture variable amount Color variable amount 5.8 6.0 6.2 Measure the inverted and non-inverted black ±0.8 ±1.5 level at TP36 when U-BRT = 00h and 7Ah and assume the difference from the average ±4.5 ±4.9 voltage as ∆UB1 and ∆UB2, respectively. Set CONT = 2Fh, input SG3 to TP71, and measure the TP36 amplitude at f0 relative to –1.5 0 the TP36 amplitude at 100kHz when PIC-G = 01h and 1Fh. f0 at PIC-f0 = 00h, 01h, 02h and 03h is 2MHz, 2.2MHz, 2.6MHz and 10 12 2.9MHz, respectively. V ±200 mV Set U-BRT = 23h, CONT = 80h, COLOR = 40h, and assume the amplitude at TP32 HUE 00h when SG4 (56mVp-p) is input to TP72 as V1. –20 –25 Similarly, assume the amplitude at TP34 when SG4 (100mVp-p) is input to TP70 as V2. θ = tan – 1 (V1/V2). Assume the θ when HUE HUE FFh = 00h, 80h and FFh as θa, θb and θc, 20 25 respectively. θ1 = θa – θb, θ2 = θc – θb GP1 V 300 mV Measure the output average voltage difference at TP32 and TP34 relative to the output average voltage at TP36. DC voltage difference between ∆Vc RGB USER-BRT variable amount Min. Typ. Max. Unit V deg deg 1.5 dB Input SG4 (50mVp-p) to TP70 and TP72, –30 –20 and assume the output amplitude at TP32 and TP34 when COLOR = 00h, 80h and FFh dB as V1, V2 and V3, respectively. GC1 = 20 log (V1/V2) 5.0 6.0 GC2 = 20 log (V3/V2) – 15 – CXA3503R Item Symbol B-Y/ R-Y Matrix amplitude ratio G-Y/ R-Y G-Y/ B-Y fc1 LPF characteristics fc2 fo1 Trap characteristics fo2 Frequency response DA adjustment range f RGB VDA1 VDA2 Serial data setting (HEX) Measurement conditions Min. Typ. Max. Unit Assume the TP34 output when SG4 (0.1Vp-p) is input to TP72 as RR, the TP32 amplitude 0.85 1.00 1.15 when SG4 (0.1Vp-p) is input to TP70 as BB, CONT 63h the TP34 amplitude when SG5 (0.1Vp-p) is COLOR input to TP72 as RG, and the TP32 amplitude 0.41 0.51 0.61 when SG5 (0.1Vp-p) is input to TP70 as BG. 6Fh B-Y/R-Y = RR/BB, G-Y/R-Y = RG/RR, 0.15 0.19 0.23 G-Y/B-Y = BG/BB LPF 01h MODE 00h LPF 07h MODE 00h Input SG3 to TP71 and measure the frequency which results in –3dB relative to the TP36 amplitude at 100kHz when LPF = 01h and 07h. 2.0 2.5 MHz 5.0 6.4 Set U-BRT = 30h, CONT = DFh, input SG7 MODE 00h (13.5MHz) to TP70, TP71 and TP72, and –20 –27 measure the amount by which the output is attenuated when FILTER = 01h relative to FILTER = 00h. Similarly, input SG7 (14.5MHz) to TP70, TP71 and TP72, and measure the MODE 00h –20 –27 amount by which the output is attenuated when FILTER = 02h relative to FILTER = 00h. dB Set SW32, SW34 and SW36 = ON, input SG3 to TP70, TP71 and TP72, and measure the MODE 00h 5.5 frequency which results in –3dB relative to the TP32, TP34 and TP36 amplitude at 100kHz. DA 00h DA 07h Measure the DA output voltage when DA = 00h and 07h. MHz Output current 1.0mA Output current –1.0mA 0.3 V 2.7 Internal DAC differential non-linearity error SDL Measure under the measurement conditions –1.5 for each adjustment range. 1.5 LSB Internal DAC non-linearity error SL Measure under the measurement conditions –2.0 for each adjustment range. 2.0 LSB ∆γ1 Gamma characteristics ∆γ2 H FIL gain COMMON control range Input SG2 (0.35mVp-p) to TP71 and measure the amplitude at TP32, TP34 and TP36. 12 Assume the output amplitude when GAMMA1 CONT 41h = FFh as V1, when GAMMA1 = 3Fh as V2, and when GAMMA1 = GAMMA2 = 3Fh as V3. 12 ∆γ1 = 20 log (V1/V2) ∆γ2 = 20 log (V3/V2) 14 16 dB 14 16 Ghfil Input SG6 to TP69 and measure the output amplitude at TP2. 15.0 17.0 dB COMDC Measure the COM output DC voltage when COM-DC = 00h and FFh, and measure the difference from the COM output DC voltage when COM-DC = 80h. ±1.0 ±1.3 V – 16 – CXA3503R Serial data setting (HEX) Item Symbol Measurement conditions SYNC IN sensitivity current I SYNC Gradually increase the SYNC IN outflow current and measure the current at which SYNC OUT switches to high. SYNC OUT on voltage VOsync Measure the SYNC OUT pin voltage during SYNC IN no input. Input SG4 to TP57, TP58 and TP59, gradually raise the high level from 0V, and assume the high level voltage at which the output level goes to BLK-LIM level as Vth1OSD, and the high level voltage at which the output level goes to WHITE-LIM level as Vth2OSD. Vth1 OSD OSD threshold value Vth2 OSD Min. Typ. Max. Unit 20 0.8 0.2 0.4 1.0 1.2 V V 1.8 Propagation delay tLH1 time between input and output Y/color difference 1 tHL1 Set SW32, SW34 and SW36 = ON, 70 input SG4 (0.35Vp-p) to TP71, and measure the propagation delay time of the noninverted output rise and fall at TP32, TP34 80 and TP36 from TP71. Propagation delay tLH2 time between input and output RGB input tHL2 Set SW32, SW34 and SW36 = ON, input SG4 (0.35Vp-p) to TP70, TP71 and TP72, and measure the propagation delay time of the non-inverted output rise and fall at TP32, TP34 and TP36 from TP70, TP71 and TP72. MODE 00h µA 31 70 2.0 2.2 120 170 ns 130 180 110 160 ns 60 110 160 Set SW32, SW34 and SW36 = ON, input SG4 (0.35Vp-p) to TP71, and measure 270 330 390 the propagation delay time of the noninverted output rise and fall at TP32, TP34 270 330 390 and TP36 from TP71. ns Propagation delay tLH4 time between OSD input and output tHL4 Set SW32, SW34 and SW36 = ON, input SG4 (3Vp-p) to TP57, TP58 and TP59, 90 130 170 and measure the propagation delay time of the non-inverted rise and fall at TP70, TP71 170 210 250 and TP72 from TP57, TP58 and TP59. ns Propagation delay tLH7 time between H FIL tHL7 and FIL OUT Input SG6 to TP69 and measure the 500 700 900 propagation delay time of the rise and fall at 100 300 500 TP2 from TP69. ns Propagation delay time between SYNC IN and SYNC OUT Set SW2 = OFF, input SG8 to TP3, and measure the propagation delay time of the rise and fall at TP4 from TP3. Propagation delay tLH3 time between input and output Y/color difference 2 tHL3 tLH8 tHL8 PIC-G 01h 140 200 260 ns 40 ts0 SEN setup time, activated by the rising edge 150 of SCK. (See Fig. 4.) ts1 SDAT setup time, activated by the rising edge of SCK. (See Fig. 4.) Data setup time – 17 – 100 160 ns 150 CXA3503R Item Symbol Min. Typ. Max. Unit SEN hold time, activated by the rising edge of SCK. (See Fig. 4.) th1 SDAT hold time, activated by the rising edge 150 of SCK. (See Fig. 4.) tw1L SCK pulse width. (See Fig. 4.) 210 ns tw1H SCK pulse width. (See Fig. 4.) 210 ns tw2 SEN pulse width. (See Fig. 4.) 1 µs tTLH tTHL Output transition time Measurement conditions th0 Data hold time Minimum pulse width Serial data setting (HEX) tTLH tTHL 150 ns Measure the transition time of each output. 30pF load: VDO, HDO and POF output pins 40pF load: RPD, HCK1, HCK2 and HST output pins (See Fig. 2.) 30 ns 30 Measure the transition time of each output. 40pF load: VST, DWN, BLK, RGT, EN, STB and VCK output pins (See Fig. 2.) Cross-point time difference ∆T Measure HCK1/HCK2. 120pF load (See Fig. 3.) HCK duty DTYHC Measure the HCK1/HCK2 duty. 120pF load – 18 – 50 ns 50 47 50 10 ns 53 % CXA3503R Electrical Characteristic Measurement Method Diagrams ∆T 90% 50% 10% tTLH tTHL ∆T Fig. 2. Output transition time measurement conditions SDTA D15 D14 D13 D12 D11 D10 ts1 Fig. 3. Cross-point time difference measurement conditions D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 th1 50% SCK tw1H tw1L 50% SEN ts0 th0 Fig. 4. Serial transfer block measurement conditions – 19 – tw2 CXA3503R SG No. Waveform Horizontal sync signal (CSYNC) 4.7µs SG1 3.0Vp-p 1H Amplitude variable SG2 1H Horizontal sync signal Sine wave video signal; frequency and amplitude variable 0.1Vp-p SG3 0.1Vp-p 1H 25µs High level variable 10µs 0V SG4 Horizontal sync signal 3V 10µs SG5 Low level variable 25µs Horizontal sync signal – 20 – CXA3503R SG No. Waveform Horizontal sync signal (CSYNC) 50mVp-p 4.7µs SG6 1H Sine wave video signal 0.1Vp-p SG7 1H SG8 Horizontal sync signal (CSYNC) 4.7ns 0.15Vp-p 1H – 21 – CXA3503R Electrical Characteristics Measurement Circuit +12V A 47µ TP42 TP45 +12V 1µ A 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 47µ Vss TST14 TST13 TST12 TST11 TST10 TST9 DWN POF TST8 GND3 COM Vcc3 TST7 TST6 Vcc2 10 A 55 VDD 47µ TST5 54 Vss +3V 56 TST15 36 G OUT G DC DET 35 TP57 57 OSD B R OUT 34 TP58 58 OSD R R DC DET 33 0.01µ 1µ TP36 0.1µ TP34 0.1µ B DC DET 31 TP32 0.1µ 61 HCK1 SIG.C 30 TP62 62 HCK2 GND2 29 63 Vcc1 TST4 28 64 HST HDO 27 TP27 VDO 26 TP26 1µ TP64 TP65 65 RGT TP66 66 EN XCLR 25 TP67 67 STB RPD 24 68 VCK Vss 23 TP68 1µ TP69 69 FIL IN CKI 22 70 B/B-Y CKO 21 300P SW32 0.01µ TP61 TP30 0.1µ TP24 1k 0.01µ TP70 TST1 F ADJ GND1 VD VST TST2 TST3 SCK SEN SDAT R INJECT VSS 2 DA OUT 1 72 R/R-Y CSYNC/HD 71 G/Y 0.01µ TP72 SYNC OUT 0.01µ TP71 SYNC IN 47µ 60 BLK FIL OUT A TP60 B OUT 32 Vss +12V 59 OSD G 300P SW34 10 TP59 300P SW36 10 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1µ ∗1 39p V22 0.01µ 6800p 15k 47µ TP5 TP6 TP3 TP11 1k TP14 TP16 TP15 TP4 ∗1 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm or less Locate this resistor as close to the IC pin as possible to reduce the effects of external signals. ∗2 Varicap diode: 1T369 (SONY) – 22 – ∗2 +3V A SW2 SW4 10k VDD 19 ∗1 33k TP2 VDD 20 3.9µ 220p 33k 0.01µ 10k 3.3µ CXA3503R Description of Operation 1) RGB and Y/color difference signal processing block Signal processing is comprised of picture, hue, matrix, LPF/trap, contrast, OSD, sample-and-hold, γ correction, bright, sub-bright, sub-contrast and output circuits • Input signal mode switching The input mode (RGB input, Y/color difference input) can be switched by the serial communication settings. (During internal sync separation signal input) During RGB input: The G signal is input to Pins 71 and 69, the B signal to Pin 70, and the R-Y signal to Pin 72. During Y/color difference input: The Y signal is input to Pins 71 and 69, the B-Y signal to Pin 70, and the R-Y signal to Pin 72. (During external sync signal input) During RGB input: The G signal is input to Pin 71, the B signal to Pin 70, the R signal to Pin 72, CSYNC/HD to Pin 5, and VD to Pin 10. During Y/color difference input: The Y signal is input to Pin 71, the B-Y signal to Pin 70, the R-Y signal to Pin 72, CSYNC/HD to Pin 5, and VD to Pin 10. • NTSC/PAL switching The input system (NTSC/PAL) can be switched by the serial communication settings. • Picture circuit This performs aperture correction for the Y signal. The center frequency to be corrected and the correction amount are controlled by serial communication. In addition, when not using the picture circuit, it can be turned off by serial communication. • Hue circuit This is the hue adjustment circuit for the color difference signal. It is controlled by serial communication. • Matrix circuit This circuit converts Y, R-Y and B-Y signals into RGB signals. • LPF circuit This is the band limitation filter for the RGB signal. It is used to eliminate the noise component generated at the front end of this IC. The cut-off frequency can be controlled by serial communication. In addition, when not using the LPF, it can be turned off by serial communication. • Trap circuit This is used to eliminate the DSP clock and RGB decoder carrier leak generated at the front end of this IC. The center frequency can be switched between 13.5MHz and 14.3MHz by serial communication. In addition, when not using the trap, it can be turned off by serial communication. • Contrast adjustment circuit This adjusts the white-black amplitude to set the input RGB signal to the appropriate output level. • OSD This inputs the OSD pulses. There are two input threshold values: Vth1 (VCC1 × 1/3) and Vth2 (VCC1 × 2/3). When an input exceeds Vth1, the corresponding output falls to the level specified by BLACK-LIMITE. When an input exceeds Vth2, the corresponding output rises to the level specified by WHITE-LIMITER. Also, when one of the RGB inputs exceeds Vth1, any signal outputs not exceeding Vth1 also fall to the level specified by BLACK-LIMITER. – 23 – CXA3503R • Sample-and-hold circuit This circuit performs time axis correction for the RGB output signals in order to support the RGB simultaneous sampling systems of LCD panels. R S/H1 S/H4 R S/H4 G HCK1 A G S/H2 A' B S/H3 S/H4 B B B' SH1 SH2 SH3 SH4 C RGT = H (normal) SH1 SH2 SHS1 SHS2 SHS3 SHS4 SHS5 SHS6 B A' A C' C B' Through Through Through Through Through Through SH3 A C' C B' B A' SH4 C B' B A' A C' SHS1 SHS2 SHS3 SHS4 SHS5 SHS6 SH1 B A' A C' C B' SH2 A C' C B' B A' SH4 SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse SHS1, 2, 3, 4, 5, 6: Serial data settings RGT = L (right/left inversion) SH3 C' Through Through Through Through Through Through C B' B A' A C' The sample-and-hold circuit performs sample-and-hold by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation and other timing is also generated by the digital block. The sample-and-hold timing changes according to the phase relationship with the HCK pulse, so the timing should be set to the SHS1, 2 or 6 position in accordance with the actual board. • γ correction In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The γ1 gain transition point A voltage changes as shown in Fig. 2 by adjusting the serial bus register γ1, and the γ2 gain transition point B voltage changes as shown in Fig. 3 by adjusting γ2. Output B" Output Output B' A' B B B A A A Input Fig. 1 Input Fig. 2 – 24 – Input Fig. 3 CXA3503R • Bright circuit This is used to adjust the black-black amplitude of polarity-inverted RGB output signals. It is not interlinked with the γ transition points. • White balance adjustment circuit This is used to adjust the white balance. The black level is adjusted by SUB-BRIGHT, and the black-white amplitude is adjusted by SUB-CONTRAST. • Output circuit RGB output (Pins 70, 71, and 72) signals are inverted each horizontal line by the FRP pulse (internal pulse) supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage (SIG.C) of the output signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG.C (Pin 30)). In addition, the white level output is clipped at the limiter operation point that is set by the serial communication WHITE-LIMITER, and the black level output is clipped at the limiter operation point that is set by the serial communication BLACK-LIMITER. During 16:9 display the RGB output is specified by BLACK-LIMITER level at a certain timing and goes to BLACK-LIMITER level output. RGB IN 1H inverted signal (internal) 16:9 display signal (internal) BLACK-LIMITER WHITE-LIMITER SIG.C WHITE-LIMITER RGB OUT BLACK-LIMITER Set by BLACK-LIMITER – 25 – CXA3503R 2) Common voltage generation circuit block The common voltage circuit generates and supplies the common pad voltage to the LCD panel. The voltage is offset by serial communication using the SIG.C voltage as the reference and then output. 3) DAC output circuit There are two DAC output circuit systems. The DA OUT output circuit outputs DC 3.0V at equal divisions and is controlled by serial communication. 4) Sync system • H FIL This amplifies the sync signal of the input video signal and eliminates the noise with an internal LPF. The sync signal is clamped at the input, so be sure to input via a capacitor. • SYNC SEP This inputs the FIL OUT (Pin 2) output and performs sync separation. The signal is output from SYNC OUT (Pin 4) as a positive polarity pulse. 5) Power saving circuit (PS circuit) A power saving system can be realized together with the LCD panel by independently controlling (serial communication) the operation of each output block. This system is also effective for improving picture quality during power-on/off. The serial data PS0, PS1, PS2, PS3, PS4 and SYNC GEN must be set in order to use this IC. For details of the setting methods, see the "Description of Serial Control Operation" and "Power Supply and Power Saving Sequence" items. – 26 – CXA3503R 6) TG block • PLL and AFC circuits A PLL circuit can be comprised by connecting a PLL circuit phase comparator and frequency division counter and external VCO and LPF circuits. The PLL error detection signal is generated using the phase comparison output of the entire bottom of the horizontal sync signal and the internal frequency division counter as the RPD output. RPD output is converted to DC error voltage with the lag-lead filter, and then it changes the capacitance of the varicap diode to stabilize the oscillation frequency. The PLL of this system is adjusted by setting the reverse bias voltage of the varicap diode so that the point at which RPD changes is at the center of the horizontal sync signal window as shown in the figure below. Horizontal sync signal WS WS RPD (Pin 24) WL WH WL WH WL = WH • H-Position This adjusts the horizontal display position. Set this function so that the picture center matches the center of the LCD panel. • Right/left (RGT) and/or up/down inversion (DWN) The video display direction can be switched. The horizontal direction can be switched between right scan and left scan, and the vertical direction between down scan and up scan. Set the display direction in accordance with the LCD panel mounting position. • Wide mode 16:9 quasi-WIDE display can be achieved by converting the aspect ratio through pulse elimination processing. During wide mode, vertical pulse elimination scanning is performed for both NTSC and PAL display and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the display area, the black level set by BLACK-LIMITER (serial communication data) is wide-masked as the black signal within the limited vertical blanking period. This function achieves a quasi-display by simply pulse eliminating the video signal, so some video information is lost. Pulse elimination display 228 LINES Display area 4:3 display Black display Black display area 28 LINES Display area 172 LINES Black display area 28 LINES 16:9 display • AC driving of LCD panels during no signal The output signal runs freely so that the LCD panel is AC driven even when there is no sync signal from the FIL IN (Pin 69) pin or from the CSYNC/HD (Pin 5) and VD (Pin 10) pins. During this time, the sync separation circuit stops and the auxiliary counter is used to generate the free running output pulses after detecting that there is no vertical sync signal for approximately 3 fields (no signal state). – 27 – CXA3503R Description of Serial Control Operation 1) Control method Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCK. This loading operation starts from the falling edge of SEN and is completed at the next rising edge. Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator) block control data becomes valid each time the SEN signal is input. In addition, if 16 bits of more of SCK are not input while SEN is low, the transferred data is not loaded to the inside of the IC and is ignored. If 16 bits or more of SCK are input, the 16 bits of data before the rising edge of the SEN pulse are valid data. SDAT A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SCK SEN Serial transfer timing A: ADDRESS D: DATA 2) Serial data map The serial data map is as follows. Values inside parentheses are the default values. MSB ADDRESS LSB D15 D14 D13 D12 D11 D10 D9 0 0 0 ∗1 D8 MSB DATA D7 D6 (0) (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 (0) (0) 0 0 0 1 0 0 0 0 (0) (0) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 LSB D5 D4 D3 D2 D1 D0 (10000000/LSB) USER-BRIGHT (10000000/LSB) SUB-BRIGHT R (10000000/LSB) SUB-BRIGHT B (10000000/LSB) CONTRAST (10000000/LSB) SUB-CONTRAST R (10000000/LSB) SUB-CONTRAST B (00000000/LSB) γ-2 (00000000/LSB) γ-1 (0) (0) (0) (0) (0) (0) (10000000/LSB) COM-DC (00000000/LSB) COLOR (10000000/LSB) HUE WHITE-LIMITER (00/LSB) FILTER (00/LSB) (0) (0) BLACK-LIMITER (10000/LSB) (1) (1) PICTURE-GAIN (00000/LSB) LPF (000/LSB) PICTURE-F0 (0) (00/LSB) (0) (0) MODE (0) DA (000/LSB) SYNC GEN PS 4 PS 3 PS 2 PS 1 PS 0 (1) (1) (1) (1) (1) (1) SLRGT (0) SLSH2 (0) SLSH1 (0) SLSH0 (0) SLSYS2 (0) SLSYS1 (0) SLWD (0) SLPL (0) SLTST0 (0) SLFL (0) SLFR (0) SL4096 (0) SLCLP2 (0) SLCLP1 (0) SLVDP (0) SLHDP (0) SLTST5 (0) SLTST4 (0) SLTST3 (0) SLTST2 (0) SLDWN (0) SLSYP (0) SLTST1 (0) SLEXVD (0) (0) (0) (0) H-POSITION (10000/LSB) (0) (0) (0) HD-POSITION (00000/LSB) Note) If there is the possibility that data may be set at other than the above-noted addresses, set these data to "0". When using, the address data ∗1 must be set all "0". – 28 – CXA3503R 3) Description of control data • USER-BRIGHT This adjusts the brightness of the RGB output signals. Adjustment from LSB → MSB increases the amplitude (black-black). • SUB-BRIGHT R/B This adjusts the brightness of the R and B output signals using the G output signal as the reference. Adjustment from LSB → MSB increases the amplitude (black-black). • CONTRAST This adjusts the contrast of the RGB output signals. Adjustment from LSB → MSB increases the amplitude (black-white). • SUB-CONTRAST R/B This adjusts the contrast of the R and B output signals using the G output signal as the reference. Adjustment from LSB → MSB increases the amplitude (black-black). • γ-2 This sets the white side γ point level of the RGB output signals. Adjustment from MSB → LSB lowers the γ point. When not adjusting γ-2, set γ-2: 11111111 (LSB). Set the γ-2 point to the white side of the γ-1 point. • γ-1 This sets the black side γ point level of the RGB output signals. Adjustment from MSB → LSB lowers the γ point. When not adjusting γ-1, set γ-1: 11111111 (LSB). Set the γ-1 point to the black side of the γ-2 point. • COM-DC This adjusts the COMMON output voltage. Adjustment from LSB → MSB increases the output voltage. • COLOR This adjusts the color gain during Y/color difference input. Adjustment from LSB → MSB increases the gain. • HUE This adjusts the phase during Y/color difference input. Adjustment from LSB → MSB advances the phase. • WHITE-LIMITER This adjusts the white side limiter level of the RGB output signals. See the AC Characteristics for the output level. • BLACK-LIMITER This adjusts the black side limiter level of the RGB output signals. Adjustment from LSB → MSB lowers the limiter level. – 29 – CXA3503R • LPF This switches the frequency response of the low-pass filter. Set the fc/–3dB frequency relative to the amplitude 100kHz reference. See the AC Characteristics for the output level. D2 D1 D0 fc (RGB input/no load/typ.) 0 0 0 LPF OFF 0 0 1 2.0MHz 0 1 0 2.7MHz 0 1 1 3.4MHz 1 0 0 3.9MHz 1 0 1 4.9MHz 1 1 0 5.7MHz 1 1 1 6.4MHz • FILTER This sets the trap (f0) center frequency. See the AC Characteristics for the output level. D7 D6 Center frequency (f0) 0 0 TRAP OFF 0 1 13.5MHz 1 0 14.3MHz 1 1 — • PICTURE-F0 This sets the picture center frequency (f0) during Y/color difference input. See the AC Characteristics for the output level. D1 D0 Center frequency (f0) 0 0 2.0MHz (typ.) 0 1 2.2MHz (typ.) 1 0 2.6MHz (typ.) 1 1 2.9MHz (typ.) • PICTURE-VOLUME This adjusts the picture gain during Y/color difference input. Adjustment from LSB → MSB raises the gain. When not using the picture function (OFF), set PICTURE-VOLUME: 00000 (LSB). • DA This adjusts the DA output voltage. See the AC Characteristics for the output level. – 30 – CXA3503R • MODE This switches the input signal. D3 Input signal 0 RGB input 1 Y/color difference input • SYNC GEN This sync generator mode stops all output pulses other than the HDO and VDO output pulses. The PS0, PS1, PS2, PS3 and PS4 settings have priority over the SYNC GEN setting. Normally set to "0". Mode (SYNC GEN) D5 0 Normal operation 1 All output pulses and corresponding output blocks other than the HDO and VDO output pulses are stopped. • PS0, PS1, PS2, PS3, PS4 These perform the power saving settings for each input and output block. Be sure to use these settings as described in "Power Supply and Power Saving Sequence". The power-on default for this IC is power saving mode, so the settings should be canceled by serial communication after power-on. Mode (PS0, PS1, PS2, PS3, PS4) D0, 1, 2, 4 0 Normal operation 1 The respective outputs and corresponding output blocks are stopped. – 31 – CXA3503R Power Supply and Power Saving Sequence When using this IC, the power supply sequences described below must be followed during power-on/off to ensure reliability as a LCD driving system. Thoroughly study the function specifications of each control method (1), (2) and (3) before use. Control timing (1) Use this timing when not using the power saving (PS) function regardless of picture quality during poweron/off. Control timing (2) Use this timing when using the power saving (PS) function regardless of picture quality during power-on/off. Control timing (3) Use this timing when using the power saving (PS) function and placing priority on picture quality during power-on/off. Control timing (1) (1) IC power-on (3V, 12V), LCD power-on (HVDD, VVDD) (2) A settings: after the IC and LCD power supplies have risen (3) IC power-off (3V, 12V), LCD power-off (HVDD, VVDD): optional The LCD power supply (HVDD, VVDD) rise timing should adequately satisfy the panel specifications. Serial data settings other than PS should be made during the control period from the rise of the IC 3V power supply to (2). Default Status Supply voltage & output signal LCD display Power-on PS OFF LCD power supply IC 12V IC 3V SYNC GEN circuit PS4 circuit PS3 circuit PS1 circuit PS0 circuit Power-on/off & PS settings (serial data) ∗3 LCD display Power-on PS OFF Power-off ∗2 Power-off ∗2 ∗1 Operation Default ∗1 IC power-on A LCD power-on PS0 → 0 PS1 → 0 PS3 → 0 PS4 → 0 (1) IC power-off LCD power-off SYNC GEN →0 IC power-on A LCD power-on PS0 → 0 PS1 → 0 PS3 → 0 PS4 → 0 (1) IC power-off LCD power-off SYNC GEN →0 Fig. 1 ∗1 During IC power-on (default status), the PS mode is activated (the PS0, PS1, PS2, PS3, PS4 and SYNC GEN data are all set to "1"). Therefore, the PS settings should be canceled via serial communication in accordance with the sequence specifications. ∗2 When inputting the sync signal from an external source, set serial data PS4 = 1. ∗3 When using this control timing, set serial data PS2 = 0. VCC/VDD Power supply HVDD/ VVDD CXA3503R LCD Signal Fig. 2. System block diagram – 32 – CXA3503R Control timing (2) (1) IC power-on (3V, 12V), LCD power-on (HVDD, VVDD) (2) A settings: after the IC and LCD power supplies have risen (3) B settings: optional (4) IC power-off (3V, 12V), LCD power-off (HVDD, VVDD): optional It is possible to skip from step (2) to step (4) without making the B settings (dotted lines in the figure). The LCD power supply (HVDD, VVDD) rise timing should adequately satisfy the panel specifications. Serial data settings other than PS should be made during the control period from the rise of the IC 3V power supply to (2). PS (Default) LCD display PS LCD display PS Status Power-on PS OFF Supply voltage & output signal LCD power supply IC 12V IC 3V SYNC GEN circuit PS4 circuit PS3 circuit PS1 circuit PS0 circuit PS ON ∗2 PS OFF PS ON Power-off ∗2 ∗1 Operation Power-on/off & PS settings (serial data) ∗3 IC power-on A LCD power-on PS0 → 0 PS1 → 0 PS3 → 0 PS4 → 0 (1) SYNC GEN →0 B PS0 → 1 PS1 → 1 PS3 → 1 PS4 → 1 A PS0 → 0 PS1 → 0 PS3 → 0 PS4 → 0 (1) B PS0 → 1 PS1 → 1 PS3 → 1 PS4 → 1 IC power-off LCD power-off SYNC GEN →1 SYNC GEN →0 SYNC GEN →1 Fig. 1 ∗1 During IC power-on (default status), the PS mode is activated (the PS0, PS1, PS2, PS3, PS4 and SYNC GEN data are all set to "1"). Therefore, the PS settings should be canceled via serial communication in accordance with the sequence specifications. ∗2 When inputting the sync signal from an external source, set serial data PS4 = 1. ∗3 When using this control timing, set serial data PS2 = 0. VCC/VDD Power supply HVDD/ VVDD CXA3503R LCD Signal Fig. 2. System block diagram – 33 – CXA3503R Control timing (3) (1) IC power-on (3V) (2) IC power-on (12V), LCD power-on (HVDD, VVDD): after the IC power supply (3V) has completely risen (3) A settings: after the IC (12V) and LCD power supplies have risen (4) B settings: after the PLL has stabilized (stable RPD waveform) and the panel I/O power supply conditions have been satisfied. (5) C settings: optional (6) D settings: after COM and RGB have fallen (7) E settings: 100ms or more after the D settings (8) IC power-off (12V), LCD power-off (HVDD, VVDD): after the HVDD and VVDD pin voltages have fallen (9) IC power-off (3V): after the IC power supply (12V) has completely fallen Serial data settings other than PS should be made during the control period from the rise of the IC 3V power supply to (3). The LCD power supply (HVDD, VVDD) rise timing should adequately satisfy the panel specifications. PS (Default) LCD display Power-on Status Supply voltage & output signal LCD power supply IC 12V IC 3V SYNC GEN circuit PS4 circuit PS3 circuit PS1 circuit PS0 circuit PS OFF PS PS ON ∗2 LCD display PS OFF PS PS ON Power-off ∗2 ∗1 ∗3 Operation Power-on/off & PS settings (serial data) ∗5 IC power-on A LCD power-on PS0 → 0 PS1 → 0 PS3 → 0 PS4 → 0 SYNC GEN →1 B PS0 → 0 PS1 → 0 PS3 → 0 PS4 → 0 (1) SYNC GEN →0 ∗4 C PS0 → 1 PS1 → 0 PS3 → 0 PS4 → 0 (1) SYNC GEN →0 D PS0 → 1 PS1 → 1 PS3 → 0 PS4 → 0 (1) SYNC GEN →0 C A PS0 → 1 PS0 → 0 PS1 → 0 PS1 → 0 PS3 → 0 PS3 → 0 PS4 → 0 (1) PS4 → 0 SYNC GEN SYNC GEN →0 →1 E D B PS0 → 1 PS0 → 1 PS0 → 0 PS1 → 1 PS1 → 1 PS1 → 0 PS3 → 1 PS3 → 0 PS3 → 0 PS4 → 1 PS4 → 0 (1) PS4 → 0 (1) SYNC GEN SYNC GEN SYNC GEN →1 →0 →0 IC power-off LCD power-off E PS0 → 1 PS1 → 1 PS3 → 1 PS4 → 1 SYNC GEN →1 Fig. 1 ∗1 During IC power-on (default status), the PS mode is activated (the PS0, PS1, PS2, PS3, PS4 and SYNC GEN data are all set to "1"). Therefore, the PS settings should be canceled via serial communication in accordance with the sequence specifications. ∗2 When inputting the sync signal from an external source, set serial data PS4 = 1. ∗3 When raising the power supplies, first raise the IC 3V power supply, then raise the IC 12V and LCD power supplies. ∗4 When lowering the power supplies, first lower the LCD and IC 12V power supplies, then lower the IC 3V power supply. ∗5 When using this control timing, set serial data PS2 = 0. – 34 – VCC/VDD Power supply HVDD/ VVDD CXA3503R LCD Signal Fig. 2. System block diagram CXA3503R • SLPL This switches the display system. D0 Display system 0 NTSC 1 PAL • SLWD This switches the display aspect. D1 Supported aspect 0 4:3 display 1 16:9 display • SLSYS1, 2 These switch the supported panel. D3 D2 Supported panel 0 0 LCX032AK 0 1 LCX033AK 1 0 — 1 1 — • SLSH0, SLSH1, SLSH2 These switch the sample-and-hold timing. SLSH2 SLSH1 SLSH0 D6 D5 D4 Sample-and-hold position 0 0 0 SHS1 0 0 1 SHS2 0 1 0 SHS3 0 1 1 SHS4 1 0 0 SHS5 1 0 1 SHS6 1 1 0 Through (Sample-and-hold off) 1 1 1 Through (Sample-and-hold off) • SLRGT This is the right/left inversion function. This switches the horizontal scan direction of the LCD panel. D7 Scan mode 0 Normal display (right scan) 1 Right/left inverted display (left scan) – 35 – CXA3503R • SLHDP, SLVDP These switch the HDO output and VDO output polarity. D0 D1 Output polarity (HDO) Output polarity (VDO) 0 Positive polarity 0 Positive polarity 1 Negative polarity 1 Negative polarity • SLCP1, SLCP2 These switch the clamp position. D3 D2 Clamp position 0 0 A (Back porch position/when using the internal sync separation signals) 0 1 B (Sync position/when using the internal sync separation signals) 1 0 C (Back porch position/during external sync signal input) 1 1 D (Sync position/during external sync signal input) 2.35µs 2.35µs SYNC RPD 2µs A 1.3µs B 2.9µs 2µs XCLP 2µs C 3.6µs 1µs D 2µs Note) When clamp is performed at back porch and sync position, set back porch and sync period of Pins 69, 70, 71 and 72 input signals at pedestal level. • SL4096 This function inverts the output signal polarity every 4096 fields. This further inverts the polarity of the RGB output that is inverted every 1H for 4096 fields. Normally set to 1H inversion. D4 Mode 0 1H inversion 1 1H inversion + 4096 field inversion • SLFR This function inverts the output signal polarity every field. Normally set to 1H inversion. D5 Mode 0 1H inversion 1 1 field inversion • SLFL This function is used to stop output signal polarity inversion. Normally set to polarity inversion. D6 Mode 0 Polarity inversion 1 Polarity inversion stopped – 36 – CXA3503R • SLTST0, 1, 2, 3, 4, 5 These are the test functions. Set to normal mode. D0, 1, 2 Mode 0 Normal mode 1 Test mode • SLEXVD This switches the external vertical sync signal (VD/Pin 10) input. This is used when not performing sync separation with the internal sync separation circuit during external separate sync (VD, HD/Pins 10 and 5) input. Set to "0" during external CSYNC/Pin 5 input. D0 Mode 0 Other than during external vertical sync signal input 1 External vertical sync signal input • SLSYP This switches the input sync polarity. When using the Pin 4 (SYNC OUT) output as the sync signal (when using the internal sync separation signals), set this to "0". D2 Input polarity 0 Positive polarity 1 Negative polarity • SLDWN This is the up/down inversion function. This switches the vertical scan direction of the LCD panel. D3 Scan mode 0 Normal display (down scan) 1 Up/down inverted display (up scan) • HP1, 2, 3, 4, 5 These set the H position. The horizontal display position is switched by adjusting the HST pulse position using the input horizontal sync signal as the reference. Adjustment is possible in 1 bit = 2fH increments. (1fH = 1 dot) Horizontal sync signal HP: 11111 (LSB) HP: 10000 (LSB) HST HP: 00000 (LSB) 15 steps (30fH) – 37 – 16 steps (32fH) CXA3503R • HDP1, 2, 3, 4, 5 These set the HDO output pulse position. The HDO pulse output position is switched using the input horizontal sync signal as the reference. Adjustment is possible in 1 bit = 4fH increments. (1fH = 1 dot) Horizontal sync signal HDP: 00000 (LSB) HDO HDP: 11111 (LSB) 31 steps (124fH) – 38 – CXA3503R Application Circuit (RGB input/Y/color difference input, during internal sync separation signal input) +12V To LCD Panel 47µ 47µ 1µ 46 45 TST14 TST13 TST12 TST11 TST10 TST9 DWN POF 55 VDD 0.01µ 47µ 44 43 42 41 40 39 38 37 Vcc2 47 TST5 48 TST6 49 TST7 50 Vcc3 51 COM 52 TST8 53 GND3 54 Vss +3V Vss +12V 56 TST15 47µ 1µ 10 36 G OUT G DC DET 35 0.68µ 10 ∗3 57 OSD B R OUT 34 58 OSD R R DC DET 33 59 OSD G B OUT 32 To LCD Panel 0.68µ 10 To LCD Panel 1µ 0.68µ B DC DET 31 60 BLK 61 HCK1 SIG.C 30 62 HCK2 GND2 29 63 Vcc1 TST4 28 64 HST HDO 27 65 RGT VDO 26 66 EN XCLR 25 67 STB RPD 24 68 VCK Vss 23 69 FIL IN CKI 22 70 B/B-Y CKO 21 0.01µ 0.1µ ∗4 L 0.01µ B/B-Y Vss FIL OUT SYNC IN SYNC OUT CSYNC/HD DA OUT TST1 F ADJ GND1 VD VST TST2 TST3 SCK SEN SDAT R INJECT VSS 0.01µ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 71 G/Y G/Y 0.01µ R/R-Y 72 R/R-Y 1µ 1k ∗4 C VDD 20 +12V 10k VDD 19 ∗1 ∗1 33k 15k +3V 47k +3V 47µ 1k 220p 33k ∗2 0.01µ 6800p 0.01µ 270 47µ 1µ To LCD Panel To Serial Controller ∗1 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm or less Locate this resistor as close to the IC pin as possible to reduce the effects of external signals. ∗2 Varicap diode: 1T369 (SONY) ∗3 Connect to GND when not using OSD input. ∗4 L: 3.9µH C: 39pF (LCX033), L: 10µH C: 20pF (LCX032) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 39 – 10k 3.3µ CXA3503R Application Circuit (RGB input/Y/color difference input, during external sync signal input) +12V To LCD Panel 47µ 47µ 1µ 46 45 TST14 TST13 TST12 TST11 TST10 TST9 DWN POF 55 VDD 0.01µ 47µ 44 43 42 41 40 39 38 37 Vcc2 47 TST5 48 TST6 49 Vcc3 50 TST7 51 COM 52 TST8 53 GND3 54 Vss +3V Vss +12V 56 TST15 47µ 1µ 10 36 G OUT G DC DET 35 0.68µ 10 ∗3 57 OSD B R OUT 34 58 OSD R R DC DET 33 59 OSD G B OUT 32 To LCD Panel 0.68µ 10 0.68µ B DC DET 31 60 BLK 61 HCK1 SIG.C 30 62 HCK2 GND2 29 63 Vcc1 TST4 28 64 HST HDO 27 65 RGT VDO 26 0.01µ To LCD Panel 66 EN XCLR 25 67 STB RPD 24 68 VCK Vss 23 69 FIL IN CKI 22 70 B/B-Y CKO 21 0.1µ 0.01µ B/B-Y Vss FIL OUT SYNC IN SYNC OUT CSYNC/HD DA OUT TST1 F ADJ GND1 VD VST TST2 TST3 SCK SEN SDAT R INJECT VSS 0.01µ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 71 G/Y G/Y 0.01µ R/R-Y 72 R/R-Y 100k 47µ 1µ ∗4 VDD ∗1 33k 15k To LCD Panel ∗5 C VDD 20 ∗1 +3V ∗5 L 1k 220p 33k +12V 10k 19 47k +3V 47µ ∗2 0.01µ 6800p 0.01µ To Serial Controller CSYNC/HD VD ∗1 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm or less Locate this resistor as close to the IC pin as possible to reduce the effects of external signals. ∗2 Varicap diode: 1T369 (SONY) ∗3 Connect to GND when not using OSD input. ∗4 During CSYNC input, input to Pin 5 only (leave Pin 10 open). During separate sync (HD, VD) input, input to Pins 5 and 10. ∗5 L: 3.9µH C: 39pF (LCX033), L: 10µH C: 20pF (LCX032) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 40 – 10k 3.3µ CXA3503R Notes on Operation (1) This IC contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when designing the pattern. • The digital and analog IC power supplies should be separated, but the GND and VSS should not be separated and should use a plain GND (VSS) pattern in order to reduce impedance as much as possible. The power supplies should also use a plain pattern. • Use ceramic capacitors for the by-pass capacitors between the power supplies and GND, and connect these capacitors as close to the pins as possible. • The resistor connected to Pin 8 should be connected as close to the pin as possible, and the wiring from the pin to GND should be as short as possible. Also, do not pass other signal lines close to this pin or the connected resistor. • The resistor connected to Pin 17 should be located as close to the pin as possible. Also, do not pass other signal lines close to this pin. • The capacitors connected to Pin 42 should be located as close to the LCD panel as possible. • The PLL block (LPF/VCO) should be compact and located near the IC. (2) The R/R-Y (Pin 72), G/Y (Pin 71), B/B-Y (Pin 70) and FIL IN (Pin 69) pin input signals are clamped at the inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low impedance. (Input at an impedance of 1kΩ (max.) or less.) (3) The smoothing capacitor of the DC level control feedback circuit in the capacitor block connected to the RGB output pins should have a leak current with a small absolute value and variance. Also, when using the pulse elimination (PAL display, WIDE display) function, the picture quality should be thoroughly evaluated before deciding the capacitance value of the capacitor. (4) A thorough study of whether the capacitor connected to the COM output pin satisfies the LCD panel specifications should be made before deciding the capacitance value. (5) If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of using this IC with other circuits before deciding on its use. (6) Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up. (7) Be sure to observe the power supply and power saving sequence specifications specified for this IC. (8) Do not apply a voltage higher than VDD or lower than VSS to I/O pins. (9) Do not use this IC under operating conditions other than those given. (10) Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage the device, leading to eventual breakdown. (11) This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. (12) Always connect the VSS, GND1 and GND2/3 pins to the lowest potential applied to this IC; do not leave these pins open. The voltages applied to the power supply pins should be as follows. VSS = GND1 = GND2/3 ≤ VDD = VCC1 ≤ VCC2 = VCC3. – 41 – CXA3503R Package Outline Unit: mm 72PIN LQFP (PLASTIC) 12.0 ± 0.3 14.5 ± 0.2 10.0 ± 0.2 0.65 ± 0.2 54 39 38 72 19 11.0 ± 0.2 55 1 0.5 18 0.2 ± 0.08 0.08 M A 0.15 ± 0.05 0.1 0.1 ± 0.1 0° to 10° DETAIL A PACKAGE STRUCTURE SONY CODE LQFP-72P-L111 EIAJ CODE P-LQFP72-10X10-0.5 JEDEC CODE – 42 – PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.3g