SEMTECH SC453

SC453
Portable, VID Programmed Single
Phase Power Supply Controller
POWER MANAGEMENT
Description
Features
The SC453 IC is a single chip high-performance Hysteretic
PWM controller. With its integrated SmartDriver™, it powers advanced graphics and core processors. It provides
sleep mode and boot voltage support. Automatic "powersave" is present to prevent negative current flow in the
low-side FET during light loading conditions saving even
more power. The high side driver initially turns on with a
weak drive to reduce ringing, EMI, and capacitive turn-on
of the low side.
High Speed Hysteretic Controller
Single Phase Operation
Selectable Analog or VID Controlled Sleep Setting
6 Bit VID programmable Output
Integrated Drivers with Soft-High Side Turn-On
Programmable Soft-Start
Programmable Boot Voltage
Programmable Sleep Voltage with Sleep Mode
Under-Voltage Lockout on VCCA
Over-voltage Protection on CORE
Current Limit Protection on CORE
Thermal Protection
Power Good Flag with Blanking During
VCORE Changes
Automatic Power Save at Light Load
TSSOP-28 Package
A 6-bit DAC, accurate to 0.85%, sets the output voltage
reference, and implements the 0.700V to 1.708V range
required by the processor. The hysteretic converter uses a
comparator without an error amplifier, and therefore provides the fastest possible transient response, while avoiding the stability issues inherent to classical PWM controllers. The DAC is externally slew rate limited to minimize
transient currents and audible noise.
The SC453 operates from 5VDC and also features softstart, an open-drain PWRGD signal with power good blanking, and an enable input. Programmable current limiting
shuts down the SC453 after 32 current limit pulses.
Applications
Low Power Notebook and Laptop Computers
Embedded Applications
PowerStep IV™ and Smart Driver™ are trademarks
of Semtech Corporation.
Typical Application Circuit
V5
VIN
VCCA
VCORE
0.700V-1.708V
Smart
Driver
PWM
Controller
SC453 Single Phase
Power Supply
VID (5:0)
August 25, 2006
VID Logic
and DAC
1
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1
12
13
14
VID2
VID1
VID0
VID2
VID1
VID0
PG_DEL
11
VID3
VID3
8
10
36.5K
2
VID4
1
HY S
7
6
9
33.2K
1
R5
PG#
BOOTV
VID4
2
R4
4
SLP
5
3
BST
SLPV
2
1
TG
DRN
VID5
PG_DEL
54.9K
2
2
VID5
1nF
R3
1
C10
PG#
SLP
EN
VID0
VID1
VID2
VID3
VID4
VID5
HY S
PG#
BOOTV
SLPV
SLP
BST
TG
DRN
2
SC453
U1
1
SS
PG_DEL
CORE
DAC
GND
REFIN
VCCA
CLRF
CMP
CL
EN
PGND
BG
V5
15
16
17
18
19
20
21
22
23
24
25
26
27
28
BST_L
SS
CORE
DAC
VCCA
CLRF
CMP
CL
EN
BG
C21
15nF
1
2
1nF
C23
1
2
1
2
1
2
270pF
C11
DNP
R10
1uF
C9
330pF
C22
1
2
10
R1
1
DNP
1
2
332
R12
330pF
C12
R13
1
2
2
1nF
+VCORE
2
1.8K
C13
2
931
1
R8
R6 1.8K
2
1uF
1
R7
1
1
1
1
2
D1
Q3
4
4
IRF7821
MBR0530
IRF7832
1uF
C6
2
1
2
2
1
R2 0
2
1
D
8
7
6
5
1
2
Q1
D
4
IRF7832
Q4
5 L1
1
3
0.5uH
3
2
1
+5V
8
7
6
5
3
2
1
4
1
4
2
6
10uF
C3
D
1
4.7uF
CSH
2
C14
IRF7821
10uF
C2
2
8
7
6
5
C1
8
7
6
5
3
2
1
1
D
Q2
10uF
C4
2
MBRS140L
D2
0.001
R9
1
2
1
2
3
2
1
2
1
+
1
2
330uF
C15
10uF
C5
1
1
2
+
10uF
C7
0
R11
330uF
C18
1
2
1
2
2
+
330uF
C17
10uF
+VCORE
+V_IN
C8
330uF
2
+
C16
1
2
1
© 2006 Semtech Corp.
2
2
SC453
POWER MANAGEMENT
Reference Design
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SC453
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not implied.
Parameter
Symbol
Supply Voltages
VCCA, V5
Conditions
Min
Max
Units
-0.3
7
V
-0.3
VCCA +0.3
V
7
V
36
V
40
V
-0.3
7
V
VSLPV, V SLP, V VID [0.5], V DAC, V REFIN,
Input and Output Voltages
V CMP, V HYS, V CORE, V CL, V CLRF, V PG#,
V BOOTV, V SS, V GND, V BG, V CLSET
EN
VEN
BST to PGND
Static
-0.3
BST to PGND
Transicent < 100ns
BST to DRN
DRN to PGND
Static
-2
30
V
DRN to PGND
Transient < 100ns
-5
34
V
-2
BST
+0.3
V
-0.3
0.3
V
TG
TSTG
PGND to AGND
Thermal Resistance
Junction to Ambient
θJA
TSSOP-28
70
°C/W
Thermal Resistance
Junction to Case
θJC
TSSOP-28
20
°C/W
Lead Temperature
(Soldering) 10s
TLEAD
TSSOP-28
300
°C
Peak IR Reflow
Temperature 10 - 40s
TPKG
TSSOP-28
260
°C
NOTES:
(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB.
(2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Unless otherwise specified: VIN = 15V, VCCA = 5V, and V5 = 5V.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
25
V
Supply (VIN, VCCA, V5)
VIN Supply
Voltage Range
VIN
3.0
V5 Supply
Voltage Range
V5
4.3
5.0
6.0
V
VCCA Voltage Range
VCCA
4.5
5.0
6.0
V
VCCA Quiescent Current
ICCQ
10
μA
© 2006 Semtech Corp.
EN is low
EN is high in UVLO
3
400
μA
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SC453
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
VCCA Operating Current
Symbol
Conditions
Min
ICC
Typ
Max
5
Units
mA
Under-Voltage Lockout Circuits (VCCA, V5)
Threshold (VCCA falling)
VCCA Hysteresis
Threshold (V5 falling)
V5 Hysteresis
VHCCA
3.47
VHYST CCA
3.70
3.93
190
VHV5
3.85
VHYST V5
4.00
V
mV
4.25
210
V
mV
Fixed Over-Voltage Protection (CORE)
Threshold
(CORE Rising)
VTH CORE
1.95
2.00
2.05
V
FIXED
Enable Input (EN)
Input High
ViH (EN)
Input Low
ViL (EN)
2
V
0.8
V
VCORE Power Good Generator (PG_DEL, PG#)
VDAC = 0.6 - 1.75V
Core Input Threshold
VTH CORE
Note: during
UVLO, the
output level of
this signal is
undefined
Upper Threshold
1.1×
VDAC
1.15×
VDAC
Lower Threshold
0.86×
VDAC
0.9×
VDAC
Hysteresis
PG# Output Voltage
VPG#
Pulled up with
external 680Ω
resistor to
VPULL-UP
PG_DEL
Output Voltage
PG_DEL Delay
(at start-up)
© 2006 Semtech Corp.
VPG_DEL
0.4
Either VCORE < 0.88*VDAC,
or, VCORE > 1.12*VDAC
0.95×
VPULL-UP
EN is low or EN is high
but UVLO condition
0.95×
VPULL-UP
VCORE = VDAC pulled-up with external
680Ω resistor to VPULL-UP 1.2V
%
1
VCORE = VDAC
V
0.95×
VPULL-UP
Either VCORE < 0.88*VDAC,
or, VCORE > 1.12*VDAC
0.4
EN is low or EN is high
but UVLO condition
0.8
Measured from PG# assertion
4
V
1007
V
Clocks
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SC453
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Symbol
Conditions
Min
Typ
Max
Discharge (sink) Current
5
10
Soft-Start transition 0 < TA < 85°C,
- 40 < TA < 85° C
7.5
10.5
16
Sleep Exit, 0 < TA < 85°C
204
256
310
Sleep Exit, -40 < TA < 85°C
180
240
320
VID Transition, 0 < TA < 85°C
102
128
155
VID Transition, -40 < TA < 85°C
90
120
160
40
100
Units
Soft-Start & DAC Slew (SS)
Soft-Start/DAC
Slew Current
Note:
SS cap is not discharged
until EN goes low or
UVLO cuts in. To enable
the converter, SS has to
drop below VSS_EN.
Soft-Start
Enable Threshold
ISS
VSS_EN
mA
μA
mV
DAC (VID [5:0])
VID Input Threshold
ViH_VID
0.55
V
ViL_VID
DAC Output
Voltage Accuracy
VDAC_ERR
0.45
0° < TA < 85°C, VID [5:0] = 000000
"111111(1.708V" 0.812V)
-0.85
+0.85
%
-25°C < TA < 85°C, VID [5:0] = 000000
"111111 (1.708V" 0.700V)
-2.0
+2.0
%
|±3|
%
Boot Voltage (BOOTV)
Input Voltage Offset
VBOOTVVDAC
BOOT Delay Time(1)
TBOOT
BOOTV = 1.2V
10
35
μs
Sleep (SLP, SLPV)
Input Voltage Offset
SLP Logic Threshold
VSLPV-VDAC
SLPV = 0.8V
ViH_SLP
|±3|
%
2
V
ViL_SLP
0.8
CORE Comparator (CMP, REFIN, HYS)
Input Bias Current
IREFIN
Input Voltage Offset
VCMP VREFIN
© 2006 Semtech Corp.
VREFIN = 1.3V
|±1.5|
5
|±2|
μA
|±3|
mV
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SC453
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Symbol
Conditions
Min
Typ
Max
VCMP < VREFIN
-110
-100
-90
VCMP > VREFIN
90
100
110
VCMP < VREFIN
-7
-10
-13
VCMP > VREFIN
7
10
13
VCMP < VREFIN
-83
-73
-63
VCMP > VREFIN
63
73
83
Units
CORE Comparator (CMP, REFIN, HYS) (Cont.)
RHYS = 17K
Hysteresis Setting
Current SLP = low
ICMP
RHYS = 170K
Hysteresis Setting
Current SLP = high
ISLP_ ICMP
RHYS = 17K
μA
μA
Current Limit Comparator (CL, CLRF, HYS)
Input Bias Current
Input Voltage Offset
ICL
VCL1, 2 = 1.3V
VCL- VCLRF
RHYS = 17K
Current Limit Setting
Current SLP = low
ICLRF
RHYS = 170K
Current Limit Setting
Current SLP = high
ISLP_CLRF
RHYS = 17K
|±2|
μA
|±3|
|±5|
mV
VCL < VCLRF
150
200
250
VCL > VCLRF
250
300
350
VCL < VCLRF
15
20
25
VCL > VCLRF
25
30
35
VCL < VCLRF
120
150
180
VCL > VCLRF
195
230
265
μA
μA
Zero-Crossing (Powersave) Comparators (CL, CORE)
Offset
VCL- VCORE
|±5|
mV
High Side Driver (TG)
Peak Output Current(1)
Output Resistance
Ipkh
RSRC_TG
1.5
I = 100mA,
VBST-VDRN = 5V
A
VDRN < 1V
4.2
VDRN > 1V
1
4
1.4
Ω
RSINK_TG
I = 100mA, VBST-VDRN = 5V
0.7
Rise Time(1)
trTG
CTG = 3nF, VBST-VDRN = 5V
60
ns
Fall Time(1)
tfTG
CTG = 3nF, VBST-VDRN = 5V
36
ns
© 2006 Semtech Corp.
6
Ω
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SC453
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
High Side Driver (Cont.)
Propagation Delay TG
Going High(1)
tpdhTG
CMP crossing REFIN to 10%
point of TG, CTG = 3nF, BG = 0V
45
ns
Propagation Delay TG
Going Low(1)
tpdlTG
CMP crossing REFIN to 90%
point of TG, CTG = 3nF
45
ns
Shoot-thru Protection
Delay Time(1)
tspd
21
30
39
ns
Low Side Driver (BG)
Peak Output Current(1)
Output Resistance
Ipkl
RSRC_BG
3
A
1.0
2.6
0.5
1.2
I = 100mA, V5 = 5V
RSINK_BG
Ω
Rise Time(1)
trBG
CBG = 3nF, V5 = 5V
25
ns
Fall Time(1)
tfBG
CTG = 3nF, V = 5V
15
ns
Propagation Delay TG
Going High(1)
tpdhBG
CMP crossing REFIN to 10%
point of BG, CBG = 3nF, DRN = 0V
35
ns
Propagation Delay TG
Going Low(1)
tpdlBG
CMP crossing REFIN to 90%
point of TG, CTG = 3nF, DRN = 0V
35
ns
Notes:
1) Guaranteed by design.
© 2006 Semtech Corp.
7
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SC453
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device
Package
Temp Range(TJ)
SC453TSTRT
TSSOP-28
-40°C to + 125°C
TOP VIEW
DRN
1
28
V5
TG
2
27
BG
BST
3
26
PGND
SLP
4
25
EN
SLPV
5
24
CL
BOOTV
6
23
CMP
PG#
7
22
CLRF
HYS
8
21
VCCA
VID5
9
20
REFIN
VID4
10
19
GND
VID3
11
18
DAC
VID2
12
17
CORE
VID1
13
16
PG_DEL
VID0
14
15
SS
SC453EVB
EVALUATION BOARD
Notes:
1. Only available in tape and reel packaging. A reel contains
2500 devices.
2. Lead-free package compliant with J-STD-020B. Qualified
to support maximum IR reflow temperature of 260°C for 30
seconds.
3. This device is ESD sensitive. Use of standard ESD handling
precautions is required.
4. All parameters subject to change without notice.
5. Lead-free product. This product is fully WEEE and RoHS
compliant.
(28 Pin TSSOP)
Pin Descriptions
Pin#
Pin Name
1
DRN
2
TG
3
BST
Bootstrap pin. A capacitor is connected between BST and DRN pins to develop
the floating bootstrap voltage for the high-side MOSFET.
4
SLP
Sleep logic input signal.
5
SLPV
6
BOOTV
7
PG#
Start clock indicator - open drain output. Active low.
8
HYS
Core Comparator Hysteresis. Connect to ground thru an external resistor called RHYS.
Hysteresis current is established by an internal VREF voltage, 1.7V, divided by RHYS.
9
VID5
VID most significant bit main controller voltage programming DAC input.
10
VID4
VID input.
© 2006 Semtech Corp.
Pin Function
This pin connects to the junction of the switching and synchronous MOSFETs.
Output gate drive for the switching (high-side) MOSFET.
Connect this pin to VCCA to select "VID Sleep Mode". Otherwise, "SLPV Sleep Mode"
is selected and the voltage on this pin sets the DAC output during sleep.
The voltage on this pin sets the BOOT-Up voltage.
8
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SC453
POWER MANAGEMENT
Pin Confi
guration(Cont.)
Descriptions
Pin#
Pin Name
11
VID3
VID input.
12
VID2
VID input.
13
VID1
VID input.
14
VID0
VID least significant bit main controller voltage programming DAC input.
15
SS
16
PG_DEL
17
CORE
18
DAC
Main controller digital-to-analog output.
19
GND
Analog ground.
20
REFIN
Core Comparator reference input pin. Connect to DAC.
21
VCCA
5V supply for precision analog circuitry.
22
CLRF
Current limit reference input pin
23
CMP
Core Comparator input pin.
24
CL
Current limit input pin.
25
EN
Enable - active high. This is capable of accepting a 5.0V signal level.
26
PGND
27
BG
Output drive for the synchronous (low-side) FET.
28
V5
5VDC supply for the driver. A capacitor should be connected from V5 to GND.
© 2006 Semtech Corp.
Pin Function
Soft-start. An external cap defines the soft-start ramp.
Delayed power good - open drain output. When the Main Converter Output approaches
and stays within ± 14% of the VID_DAC setting, and the tCPU_PWRGD period has terminated.
This signal is pulled high by an external resistor.
Main CORE converter output feedback to the power good generator. A small RC filter
should be used to filter out any HF component to prevent faulty trip condition.
Power ground. Connect to the synchronous FET power ground.
9
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SC453
POWER MANAGEMENT
Block Diagram
```
`
`
SLPV
BOOTV
SLP
VID/SLPV Sleep Mode Detect
REFIN
PG#
PG_DEL
© 2006 Semtech Corp.
10
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
SUPPLY, BIAS, UVLO, POWER GOOD GENERATOR
VID
Supply
The chip is optimized to operate from a 5V ± 5% rail but
also designed to work up to 6V maximum supply voltage.
Under-Voltage Lock-Out Circuit
The Under-Voltage Lock-Out Circuit consists of comparators which monitor the VCCA and V5 voltage levels. The
SC453 is in UVLO mode while either supply has not
ramped above the upper threshold or has dropped below
the lower threshold. During UVLO, the external FETs are
held off, tri-stating the output (DRN).
Over-Voltage Protection
If the CORE voltage is greater than +14% of the DAC (i.e.,
out of the power good window), the SC453 will latch off
and hold the low-side driver on permanently. Either the
power or EN must be recycled to clear the latch. The latch
is disabled during soft-start and VID/Sleep transitions.
For safety, the latch is enabled if the CORE voltage exceeds 2V even during VID/Sleep transitions.
Thermal Shutdown
The device will be disabled and latched off when the internal junction temperature reaches approximately 160°C.
Either the power or EN must be recycled to clear the
latch.
Band Gap Reference
A ± 0.85% precision Band Gap reference acts as the internal reference voltage standard of the chip, which all
critical biasing voltages and currents are derived from. All
references to VREF in the equations to follow will assume
VREF = 1.7V.
Precision DAC
This 6-bit digital-to-analog converter (DAC) serves as the
programmable reference source of the Core Comparator.
Programming is accomplished by logic voltage levels applied to the DAC inputs. The VID code vs. the DAC output
is shown in the following table. The accuracy of the VID
/DAC is maintained on the same level as the Band Gap
reference.
© 2006 Semtech Corp.
11
VDAC
VID
VDAC
5
4
3
2
1
0
V
5
4
3
2
1
0
V
0
0
0
0
0
0
1.708
1
0
0
0
0
0
1.196
0
0
0
0
0
1
1.692
1
0
0
0
0
1
1.180
0
0
0
0
1
0
1.676
1
0
0
0
1
0
1.164
0
0
0
0
1
1
1.660
1
0
0
0
1
1
1.148
0
0
0
1
0
0
1.644
1
0
0
1
0
0
1.132
0
0
0
1
0
1
1.628
1
0
0
1
0
1
1.116
0
0
0
1
1
0
1.612
1
0
0
1
1
0
1.100
0
0
0
1
1
1
1.596
1
0
0
1
1
1
1.084
0
0
1
0
0
0
1.580
1
0
1
0
0
0
1.068
0
0
1
0
0
1
1.564
1
0
1
0
0
1
1.052
0
0
1
0
1
0
1.548
1
0
1
0
1
0
1.036
0
0
1
0
1
1
1.532
1
0
1
0
1
1
1.020
0
0
1
1
0
0
1.516
1
0
1
1
0
0
1.004
0
0
1
1
0
1
1.500
1
0
1
1
0
1
0.988
0
0
1
1
1
0
1.484
1
0
1
1
1
0
0.972
0
0
1
1
1
1
1.468
1
0
1
1
1
1
0.956
0
1
0
0
0
0
1.452
1
1
0
0
0
0
0.940
0
1
0
0
0
1
1.436
1
1
0
0
0
1
0.924
0
1
0
0
1
0
1.420
1
1
0
0
1
0
0.908
0
1
0
0
1
1
1.404
1
1
0
0
1
1
0.892
0
1
0
1
0
0
1.388
1
1
0
1
0
0
0.876
0
1
0
1
0
1
1.372
1
1
0
1
0
1
0.860
0
1
0
1
1
0
1.356
1
1
0
1
1
0
0.844
0
1
0
1
1
1
1.340
1
1
0
1
1
1
0.828
0
1
1
0
0
0
1.324
1
1
1
0
0
0
0.812
0
1
1
0
0
1
1.308
1
1
1
0
0
1
0.796
0
1
1
0
1
0
1.292
1
1
1
0
1
0
0.780
0
1
1
0
1
1
1.276
1
1
1
0
1
1
0.764
0
1
1
1
0
0
1.260
1
1
1
1
0
0
0.748
0
1
1
1
0
1
1.244
1
1
1
1
0
1
0.732
0
1
1
1
1
0
1.228
1
1
1
1
1
0
0.716
0
1
1
1
1
1
1.212
1
1
1
1
1
1
0.700
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
CORE CONVERTER CONTROLLER
DAC Slew Control
The output of the DAC will slew at a rate defined by the
current in the SS pin and the capacitor applied externally
to the SS pin. The slew rate (charge current) applied depends on which mode (soft-start, VID or sleep transition)
is in effect. The SS capacitor together with the DAC capacitor will determine the stability of the DAC, a 1nF capacitor is recommended for the DAC pin.
Core Comparator
This is an ultra-fast hysteretic comparator with a typical
propagation delay of about 20ns at a 20mV overdrive.
Hysteresis is generated by the current set at the HYS pin
impressed upon an external resistor connected to the
CMP pin.
Current Limit Comparator
The Current Limit Comparator monitors the core converter
output current and turns off the high side FETs when the
current exceeds the upper current limit threshold, VHCL
and is re-enabled only if the phase current drops below
the lower current limit threshold, VLCL. The current is
sensed by monitoring the voltage drop across the current
sense resistor, RCS connected in series with the core converter inductor. VHCL and VLCL are fixed by the current
set at the HYS pin impressed upon an external resistor
connected to the CLRF pin.
Blanking During VID Changes
On any VID change or Sleep change, the PG# and PG_
DEL signals are blanked for 62 switching cycles to prevent
glitching during the transition.
Sleep Function
In sleep mode, the DAC output is set by the voltage on
the SLPV pin when the SLP pin is held high. In "VID Sleep"
mode, the DAC output is set by the VID bits when SLP is
held high. During sleep, the hysteresis and current limit
hysteresis currents are reduced to 70% of their nominal
values.
Current Limit Latch
If the CORE voltage goes lower than 14% below the VID
(i.e., out of the power good window), then sustained current limiting (32 current limit pulses) will cause the part
to permanently latch off. The latch is inhibited during softstart.
SLPV/VID Sleep Mode
By default, the controller is in "SLPV controlled Sleep"
mode. In this mode, the voltage applied to the SLPV pin
appears at the DAC output when SLP is asserted.
By holding the SLPV pin at VCCA during start-up, "VID controlled sleep" mode is engaged. In this mode, the DAC output continues to be set by the VID inputs even when SLP
is asserted.
Core Converter Soft-Start Timer
This block controls the start-up ramp time of the CORE
voltage up to the boot voltage. The primary purpose is to
reduce the initial in-rush current on the core input voltage
(battery) rail.
Cycle-by-Cycle Power-Save
A zero crossing comparator detects when the currents
through the external sense resistor reduces to zero. When
the current in the external sense resistor reaches zero,
the bottom FET is latched off. The latch is reset when the
controller decides to switch on the top FET. This prevents
excessive switching at light loads and hence saves switching power losses.
© 2006 Semtech Corp.
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
PG# Output
This is an open-drain output and should be pulled up externally. This signal is asserted (pulled low) by the SC453
whenever the core voltage is within ±14% of the VID
programmed value. If the chip is disabled or enabled in
UVLO, then PG# is de-asserted. During start-up PG# remains de-asserted until the core voltage has reached the
defined boot voltage and remains there for the BOOT period (10μS minimum). This signal is forced low (asserted)
during VID and sleep transitions.
and should be pulled up externally. This signal is asserted
(open drain) by the SC453 whenever the core is within
±14% of the VID programmed value. If the chip is disabled
or enabled in UVLO, then PG_DEL is de-asserted. The signal is forced high (open drain) during VID and sleep transitions.
Start-Up and Sequencing
On start-up, VCORE ramps to the boot voltage set by the
BOOTV pin irrespective of the status of the VID pins. After
a minimum of 10μs, PG# asserts, and VCORE responds to
the VID inputs. The controller will then count 1007 switching cycles before asserting PG_DEL.
PG_DEL Output
This signal is delayed a minimum of 3mS from first assertion of the PG# signal. This is an open drain output
Summary of Fault Conditions
Protection Mode
Latched?
When Active
Driver Status
SS Pin Status
Supply UVLO (VCCA, V5)
32 Cycle Current Limit
No
Yes
Always
SS has terminated and PGDEL is low
All low
TG low
Low
Sawtooth
114% VCORE OVP
Yes
SS has terminated and PGDEL is low
BG high
High
2.0VCORE OVP
Yes
Always
BG high
High
Thermal Shutdown
Yes
Always
BG, TG low
High
Driver Timing Diagram
CMPRF
CMP
REFIN
(4)
tpdlTG tfTG
tpdhTG
tr TG
TG
(4)
tpdhBG
trBG
tpdlBG
tfBG
tspd
BG
Note (4): subtract a typical value of 17ns for the core comparator delay since this parameter is specified from a CMP edge.
© 2006 Semtech Corp.
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
Step 2: Output Inductor and Capacitor Selection
The SC453 has "passive" droop. The voltage at full load is
less than the DAC voltage by the voltage drop across the
current sense resistor and any PCB copper losses from
the sense resistor to the processor socket. The steadystate voltage at full load is:
DESIGN PROCEDURE
Step 1: Define Constants
VINMAX := 20V
Maximum input voltage
VINMIN := 8V
Minimum input voltage
IMAX_FL := 20A
Maximum load current,
highest output voltage
ILKGMAX := 5A
Leakage current, highest
output voltage
VMAX_NL := 1.212V
The highest VCORE voltage
VMIN_NL := 0.956 ⋅ V
The lowest VCORE voltage
VREF := 1.7V
SC453 Internal reference voltage
C OUT := 330 ⋅ μF
Output capacitance per cap
RESR := 6m ⋅ Ω
ESR per cap
RCS := 1m ⋅ Ω
Current sense resistor
RCU := 0.5m ⋅ Ω
Parasitic resistance from the
current sense resistor to the
processor
VPOS_TRANS := 50mV
Voltage droop allowed for a low
current to high current transient
VNEG_TRANS := 50mV
Voltage rise allowed for a high
current to low current transient
VRIPPLE := 20m V
(
)
VMAX_FL := VMAX_NL − RCS + RCU ⋅ IMAX_FL
VMAX_FL = 1.182 V
Output capacitance and ESR values are a function of
transient requirements and output inductor value. Figure
1 illustrates the response of a hysteretic converter to a
positive transient. In a hysteretic converter with passive
droop, like the SC453, two conditions determine if you
meet the positive transient requirements.
VPOS_TRANS
A.
ESR ≤
B.
VNEG_TRANS ≥ deltaV C OUT
(IMAX_FL − ILKGMAX)
(
)
Desired maximum output ripple
Figure 1 - Hysteretic Converter Response to a
Positive Transient
The first condition is easy to see; if the ESR is too high, the
transient response will fail.
© 2006 Semtech Corp.
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
In the second condition, because the hysteretic converter
responds in < 100ns, the capacitor does not droop very
far before the inductor current starts ramping up. (This is
not true of control schemes where time constants in the
error amplifier cause delays.) Once the inductor current
starts to rise, the increasing ∆V of the capacitor is offset
by reduced ∆V from the ESR, so ∆V is constant. If the ∆V
due to the charge taken from the capacitor before the inductor current reaches the load current (note the shaded
area on the graph) is less than VPOS_TRANS, then the
transient response passes.
Based on the following four factors: 1) minimum inductance requirement; 2) device availability at the time we
designed the evaluation board; 3) low DCR ; 4) height and
package size consideration. Keep in mind, the choice you
make should be based upon the requirement of the converter design, including minimum inductance, minimum
saturation current, efficiency, foot area, maximum allowable height, and of course, device availability. In the current demo board design,
Since the highest output voltage has the most severe requirements, any other modes are satisfied by a design optimized for the highest output voltage.
This value of inductance is required up to maximum load.
Inductors with a “swinging choke” characteristic, where
the zero current value of inductance is much less than the
full load current inductance can be used, as long as the
above restriction is met. Then, the worst-case (low input
voltage) response time (the time for the current to reach
the new transient value) is:
C.
ESRMAX :=
VPOS_TRANS
(IMAX_FL − ILKGMAX)
ESRMAX = 3.333 × 10
−3
Ω
dT :=
For the second condition, we need to know the inductor
value, which is a function of the highest desired switching
frequency. The maximum frequency occurs at the highest input voltage. As a reasonable compromise between
efficiency and component size, a maximum switching frequency of 350kHz is desired.
D.
F S := 350K⋅ Hz
E.
dMIN :=
F.
LMIN := dMIN ⋅
H.
VINMAX
I.
⎛ ESRMAX + RCS ⎞
ESRMAX
⎝
LMIN = 5.422 × 10
−7
)
VINMIN − VMAX_NL
−6
s
Add ~100ns for the propagation delay from a change at
the output to the MOSFET switch turning on in reaction.
Since the shaded area is triangular, the total charge taken
out of the capacitor = (dI / dt) / 2. Q = C / dV = (dI / dt) /
2, therefore;
VMAX_NL
F S⋅ VRIPPLE ⋅ ⎜
(
L1⋅ IMAX_FL − ILKGMAX
dT = 1.326 × 10
(VINMAX − VMAX_NL)⋅ (ESRMAX + RCS)
© 2006 Semtech Corp.
L1 := 0.60 ⋅ μH
G.
C MINP :=
(IMAX_FL − ILKGMAX)⋅ (dT + 1⋅ 10 − 7⋅ sec)
VPOS_TRANS
C MINP = 4.278 × 10
⎠
−4
F
This condition applies only to the positive transient.
H
15
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
LOAD RELEASE
The worst-case for the transient load release to happen is
when the hysteresis has just reached the maximum, (i.e.,
the high-side switch has just turned of); at this time the
inductor has reached its peak current.
IRIPPLE :=
(VINMAX − VMAX_FL)⋅ dMIN
L1⋅ F S
⋅
t := 0 , 10n⋅ s .. 10μ ⋅ s
⎛
IL( t) := ⎜ It0 −
⎠
ICAP( t) := IL( t) − ILKGMAX
LMIN
Since the output inductor is discharging at a fixed rate,
there are two terms contributing to the increase of the
voltage on the output capacitors: 1) is due to the ESR of
the output capacitor; 2) is due to the added charge contributed by the inductor current.
IRIPPLE
2
It0 = 23.005 A
RDS
RCU
Rds_ON
BG
ESR_eq
IMAX
IMIN
(
)
(
)
(
)
RESR
J.
VESR t , N CAP := ICAP( t) ⋅
K.
dVCAP t , N CAP :=
L.
VTOTAL t , N CAP := VESR t , N CAP + dVCAP t , N CAP
Load is stepping from high to low.
L
L1
⎝
L1
IRIPPLE = 6.01 A
It0 := IMAX_FL +
VMAX_FL⋅ t ⎞
N CAP
ICAP( t) ⋅ t
C OUT⋅ N CAP
(
)
(
)
R_LOAD
Cout_eq
Rcu_rt
Immediately after the load steps down from IMAX to IMIN, the
high side FET is turned off, and the bottom FET is turned
on after the dead time. We assume for the worst-case
condition, at t = 0, the output inductor is sitting at its maximum; after t = 0, the inductor discharges at a rate equal
to VFL / L. (without the consideration of the secondary order effect, such as, Rds_on drop, current sense resistor
and copper losses). The energy released from the output
inductor during load step-down, charges the output capacitors and is dissipated through the following means:
Rds_on, Rcs, Rcu, Rcu_rt, ESR of the output capacitors
and load.
© 2006 Semtech Corp.
The chart above shows the system response for the capacitors defined in Step 1 and the chart to follow shows
the details of the response for the chosen number of output capactors.
16
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
VHYS is created by a current source, IHYS, through R9 (see
the diagram below). The current source value is controlled via RHYS. For simplicity it is easier to select a value
for R7 (the resistor in series with the CMP pin) first, and
then calculate RHYS, as follows:
R7 := 1K⋅ Ω
N.
RHYS :=
.
2⋅ VREF
⎛ VHYS ⎞
⎜
⎝ R7 ⎠
In the SC453 application circuit, RHYS consists of three resistors (R3, R4 and R5). These resistors also form the
dividers for BOOTV and SLPV. Note also that depending
on circuit layout and parasitics, RHYS may have to be adjusted slightly to obtain optimum performance. (We will
come back to calculate the above resistors after we set
the PBOOT and Deeper Sleep voltages). To increase hysteresis without having to change the divider resistors, a
fourth resistor (R14), can be added. Additional hysteresis
is needed when inductances in the current sense paths
cause additional signal that add to the resistive signal,
limiting the accuracy of the calculations.
Step 3: Setting RHYS
The next step is to calculate RHYS. Since the SC453 is a
hysteretic controller, it regulates the amount of output
ripple according to a hysteresis value set by RHYS. The designer must therefore decide upon the amount of desired
output ripple, and then set RHYS accordingly.
The hysteresis controls the amount of ripple at the point
of regulation, which is the point between the inductor and
the current sense resistor. The amount of ripple at the
output is defined by the current sense resistor and the
output cap, ESR. This factor is taken into account in the
equation shown below relating VRIPPLE to VHYS.
SC453
To achieve tight accuracy, it is recommended that the output ripple be set to 20mV peak-to-peak.
HYS
R14
ESR :=
RESR
N CAP
ESR = 1.5 × 10
−3
RHYS = 102.0 KΩ
R5
Ω
BOOTV
R4
VRIPPLE = 0.02 V
M.
VHYS := VRIPPLE ⋅
SLPV
(RCS + ESR)
R3
ESR
VHYS = 0.033 V
© 2006 Semtech Corp.
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
⎛⎜ R14⋅ RHYS
⎜ R14 − RHYS
v := ⎜
0
⎜
⎜⎝
0
Step 4: BOOTV Design
The boot-up voltage for VCORE is set at 1.2V. For the SC453
typical application circuit, R3, R4, and R5 form a voltage
divider off VREF and are used to set the boot voltage. For
simplicity, we define RBOOT : = R3 + R4.
O.
VBOOT := 1.2V
(
soln := lsolve M x , v
1
RHYS :=
1
R25
+
1
RBOOT + R5
P.
RBOOT :=
)
⎞
⎟
⎟
⎟
⎟⎠
⎛ 5.011 × 10 4 ⎞
⎜
soln = ⎜ 3.007 × 10 4 ⎟ Ω
⎜
⎟
⎜
4⎟
⎝ 3.341 × 10 ⎠
4
VBOOT ⋅ R5
R3 := ( 1 0 0 ) ⋅ soln
R3 = 5.011 × 10 Ω
VREF − VBOOT
R4 := ( 0 1 0 ) ⋅ soln
R4 = 3.007 × 10 Ω
R5 := ( 0 0 1 ) ⋅ soln
R5 = 3.341 × 10 Ω
4
4
Step 5: Sleep Voltage Design
The sleep voltage is set at 0.750V nominally using the R3
- R4 - R5 divider.
From the standard 1% resistor value table, we choose
the following values according to the calculation results:
Q.
R5 = 33.2KΩ.
R4 = 30.1KΩ
R3 = 49.9KΩ
VSLP := 0.750V
R3 := VSLP ⋅
(R4 + R5)
VREF − VSLP
Step 6: Current Limit Calculation
Setting the threshold for current limit is a relatively
straightforward process. To do this we must calculate the
peak current based on the maximum DC value plus the
worst-case ripple current. The following calculations apply
for a single phase. Worst-case ripple occurs at the highest input voltage. Since ripple is also inversely proportional to inductance, it is recommended that the minimum
inductance value be used based on the manufacturer’s
specified tolerance:
R3, R4 and R5 are calculated using a matrix to solve the
simultaneous equations. R14 is set at 1MΩ as a placeholder:
R14 := 1000 KΩ
1
1
⎛1
⎜
VBOOT
⎜
−
1
1
VREF − VBOOT
M x := ⎜
⎜
⎜
−1
−1
VSLP ⋅
⎜ 1 VSLP ⋅ V
VREF − VSLP
REF − VSLP
⎝
⎞
LLOW := L1⋅ ( 1 − 20%)
⎟
⎟
⎟
⎟
⎟
⎠
LLOW = 4.8 × 10
−7
H
R.
IRIPPLE_MAX :=
(VINMAX − VMAX_NL)⋅ dMIN
LLOW ⋅ F S
IRIPPLE_MAX = 6.777 A
© 2006 Semtech Corp.
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
We set the current limit at ICLIM = ICLMAX, and then solve
for RCL, which is R6 in the typical applications circuit. For
balance, R8, in series with the CLRF pin is kept the same
value as R6.
To calculate the maximum DC value of current we must
add the maximum DC current and the maximum ripple
value to obtain peak current:
S.
IPEAK := IMAX_FL +
IRIPPLE_MAX
2
V.
IPEAK = 23.389 A
RCL :=
ICLIM ⋅ RHYS⋅ RCS
2.5 ⋅ VREF
It is recommended that the current limit be set at 120%
of the peak value to allow for inductor current overshoot
during load transients:
RCL = 673.59 Ω
T.
R8 := R6
ICLIM := 120%⋅ IPEAK
ICLIM = 28.066 A
C11, which filters the output voltage feedback, is sized to
provide filtering beyond the 5th harmonic of the fundamental.
Current limiting will cycle from ICLMAX to ICLMIN for 32 switching cycles to allow for short term transients, then the converter is latched off. ICLMAX and ICLMIN are set according to
the following equations:
ICLMAX := 3⋅ VREF⋅
ICLMIN := 2⋅ VREF⋅
R8 = 681 Ω
Step 7: Small Capacitors/Resistor Selection
Several small capacitors are required for signal filtering.
Use SMT ceramic capacitors with an X7R or better temperature coefficient. COG is preferred.
The Current Limit Comparator internal to the SC453 monitors the output current and turns the high side switch off
when the current exceeds the upper current limit threshold, ICLMAX and re-enables only if the load current drops below the lower current limit threshold, ICLMIN. The current is
sensed by monitoring the voltage drop across the current
sense resistor RCS.
U.
R6 := 681Ω
C11 :=
W.
1
2⋅ Π ⋅ R7⋅ F S⋅ 5
C11 = 9.095 × 10
F
RCL
RHYS⋅ RCS
In the evaluation board design, we use 100pF, 603, X7R
ceramic caps for C11. The DAC output requires a 1nF,
X7R or COG capacitor (C23) for high frequency noise filtering. The values for C12 and C13 are calculated in a
similar manner, though they are returned to the CORE pin
because that is the reference point for the current limit
comparator.
RCL
RHYS⋅ RCS
X.
C 12 :=
1
19
C 13 := C 12
2⋅ Π ⋅ R6⋅ F S⋅ 5
C 12 = 1.335 × 10
© 2006 Semtech Corp.
− 11
− 10
F
C 13 = 1.335 × 10
− 10
F
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
Step 8: Calculate Input RMS Current
In order to calculate the worst-case input RMS current, we
need to assume the efficiency at VIN_MIN and full load. From
the measurement result, we are safe to assume 80%,
(this number is very conservative, actual efficiency should
be much higher). The actual converter efficiency depends
on component selection, layout, airflow, etc.
POUT := IMAX_FL⋅ VMAX_FL
PIN :=
dVin := 250mV
DMAX := 0.5
Tin :=
POUT = 23.64 W
IPEAK
2
2 ⎞ Tin
⋅ ⎛⎝ DMAX − DMAX
C IN_MIN = 3.341 × 10
−5
⋅
dVin
F
C IN := 10μF
85%
IRMS :=
FS
C IN_MIN :=
POUT
IIN_DC :=
1
⎛ CIN_MIN ⎞
PIN
VINMIN
D :=
VMAX_FL
VINMIN
N IN_MIN_RIPPLE := ceil⎜
⎝
IIN_DC = 3.476 A
Based on the above calculations, we choose N = 4 for the
input capacitor.
Step 9: OVP
No calculations are necessary for Over-Voltage Protection.
If VCORE is greater than +14% of the DAC (i.e., out of the
power good window), the SC453 will latch off and hold the
low-side driver on permanently (for each phase). Either
the power or EN must be recycled to clear the latch. The
latch is disabled during soft-start and VID/DeeperSleep
transitions. The latch is enabled if VCORE exceeds 2V even
during VID/DeeperSleep transitions to ensure that the
processor maximum is not exceeded. The table on Page
13 is a summary of fault conditions using SC453.
IRMS = 7.116 A
C I_RMS := 2A
10μF@25V, MLCC cap from Panasonic is rated 2A RMS.
⎛ IRMS ⎞
⎝ CI_RMS ⎠
⎠
N IN_MIN_RIPPLE = 4
2
2
⎡⎣(IMAX_FL) − IIN_DC⎤ ⋅ D + ⎡⎣IIN_DC ⋅ ( 1 − D)⎤
C I_NUM := ceil⎜
C IN
C I_NUM = 4
The calculation indicates four of these MLCC caps satisfy
the worst-case RMS current requirement.
Step 10: Soft-Start/DAC Slew Control
The soft-start cap C21 in the SC453 design serves three
conditions: 1) to define the soft-start ramp; 2) to define
the DAC slew rate during sleep and VID transitions (during VID transitions the SS current is nominally +/- 120μA.
During sleep transitions the SS current increases to +/240μA); 3) during start-up, the SS current is normally +/6.5μA.
Input Capacitance Calculation:
(based on ripple voltage)
dVin is the allowable input ripple voltage contributed by
the amount of input capacitance. For this exercise, we
use 250mV as the allowable input ripple voltage. The
maximum value occurs at D = 0.5
We will be doing three soft-start exercises based on the
above three conditions for SC453 application:
© 2006 Semtech Corp.
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SC453
POWER MANAGEMENT
Applications Information (Cont.)
1. Start-Up:
ISS := 6.5 μA
dtSU := 3 m s
dVdacSU := VMAX_NL
C SS_max_startup :=
ISS⋅ dtSU
dVdacSU
C SS_max_startup = 1.609 × 10
−8
F
2. VID Change:
ISSV := 120 μA
dtV := 100 μs
dVdacV := VMAX_NL − VMIN_NL
C SS_max_VID :=
ISSV⋅ dtV
dVdacV
C SS_max_VID = 4.687 × 10
−8
F
3. Sleep Entry/Exit:
ISSS := 240 μA
dtS := 33 μs
dVdacS := VMAX_NL − VSLP
C SS_max_drs :=
ISSS ⋅ dtS
dVdacS
C SS_max_drs = 1.714 × 10
−8
F
Exercise #1 predicts the max capacitance allowed. In
order to allow tolerance, we choose C22 = 15nF.
© 2006 Semtech Corp.
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SC453
POWER MANAGEMENT
Outline Drawing - TSSOP-28
A
DIM
D
e
N
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
2X E/2
E1
E
PIN 1
INDICATOR
ccc C
1 2 3
e/2
2X N/2 TIPS
B
D
aaa C
SEATING
PLANE
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.002
.031
.007
.003
.378
.169
.382
.173
.252 BSC
.026 BSC
.018 .024
(.039)
28
0°
.047
.006
.042
.012
.007
.386
.177
.030
8°
0.05
0.80
0.19
0.09
9.60
4.30
9.70
4.40
6.40 BSC
0.65 BSC
0.45 0.60
(1.0)
28
0°
.004
.004
.008
1.20
0.15
1.05
0.30
0.20
9.80
4.50
0.75
8°
0.10
0.10
0.20
A2 A
C
bxN
bbb
H
A1
C A-B D
c
GAGE
PLANE
0.25
L
(L1)
SEE DETAIL
SIDE VIEW
A
DETAIL
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4.
REFERENCE JEDEC STD MO-153, VARIATION AE.
-A- AND
-B- TO BE DETERMINED AT DATUM PLANE
-H-
Marking Information
© 2006 Semtech Corp.
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SC453
POWER MANAGEMENT
Land Pattern - TSSOP-28
X
DIM
(C)
G
Z
Y
C
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
© 2006 Semtech Corp.
23
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