SC4605 Low Input, High Efficiency Synchronous, Step Down Controller POWER MANAGEMENT Description Features The SC4605 is a voltage mode step down (buck) regulator controller that provides accurate high efficiency power conversion from a input supply range of 2.8V to 5.5V. A high level of integration reduces external component count, and makes it suitable for low voltage applications where cost, size and efficiency are critical. The SC4605 drives external N-channel MOSFETs with 1A peak current. A non-overlap protection is provided for the gate drive signals to prevent shoot through of the MOSFET pair. The voltage drop across the high side MOSFET during its conduction is sensed for lossless short circuit current limiting. BICMOS voltage mode PWM controller 2.8V to 5.5V Input voltage range Output voltages as low as 0.8V +/-1% Reference accuracy Sleep mode (Icc = 10µA typ) Lossless adjustable short circuit current limiting Combination pulse by pulse & hiccup mode current limit High efficiency synchronous switching 0% to 97% Duty cycle range 1A Peak current driver 10-Pin MSOP package Applications The quiescent supply current in sleep mode is typically lower than 10µA. A 1.8ms soft start is internally provided to prevent output voltage overshoot during start-up. The SC4605 is an ideal choice for 3.3V, 5V or other low input supply systems. It’s available in 10 pin MSOP pack- age. Distributed power architecture Servers/workstations Local microprocessor core power supplies DSP and I/O power supplies Battery powered applications Telecommunications equipment Data processing applications Typical Application Circuit Vin = 2.8V - 5.5V D2 R3 C14 2 4.7u 3 4 C1 C20 C2 2.2n 220u C11 C12 22u 22u U1 1 C3 1u C71 M1 R13 1 0.1u C10 5 BST DRVH VCC PHASE ISET DRVL COMP FS/SYNC FSET GND VSENSE 10 L1 9 Vout = 1.5V (as low as 0.8V * ) / 12A 1.8u 8 7 C6 C5 C4 6 330u 22u 22u M2 C9 4.7n 470pF 180p SC4605 R7 10k R8 200 R1 14.3k R9 11.5k * External components can be modified to provide a Vout as low as 0.8V. Revision: October 14, 2004 1 www.semtech.com SC4605 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units 7 V +/-0.25 A +/-1.00 A -0.3 to 7 V -0.3 to 5.5 V -2 to 7 V TA -40 to +85 °C Storage Temperature Range TSTG -65 to +150 °C Junction Temperature Range TJ -55 to +150 °C TLEAD +300 °C Supply Voltage (VCC) Output Drivers (DRVH, DRVL) Currents Continuous P eak Inputs (VSENSE, COMP, FS/SYNC, ISET) PHASE PHASE Pulse tpulse < 100ns Operating Ambient Temperature Range Lead Temperature (Soldering) 10 Sec. All voltages with respect to GND. Currents are positive into, negative out of the specified terminal. Electrical Characteristics Unless otherwise specified, VCC = 5V, CT = 470pF, TA = -40°C to 85°C, TA = TJ. Parameter Test Conditions Min Typ Max Unit 5.5 V Overall Supply Voltage 2.8 Supply Current, Sleep FS/SYNC = 0V 10 15 µA Supply Current, Bias VCC = 5.5V 1 3 mA VCC Turn-on Threshold 2.7 2.8 V VCC Turn-off Hysteresis 125 mV Error Amplifier Input Voltage (Internal Reference) TA = 25°C 0.792 0.8 0.808 VCC = 2.8V ~ 5.5V, TA = 25°C 0.788 0.8 0.812 Temperature 0.786 0.8 0.814 VSENSE Bias Current V 25 nA 80 dB Unity Gain Bandwidth (1) 4 MHz Slew Rate 2 V/µs VCC - 0.2 V Open Loop Gain (1) VCOMP = 0.5 to 2.5V (1) VOUT High ICOMP = -2mA VOUT Low ICOMP = 2mA 2004 Semtech Corp. VCC - 0.5 0.1 2 0.25 V www.semtech.com SC4605 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise specified, VCC = 5V, CT = 470pF, TA = -40°C to 85°C, TA = TJ. Parameter Test Conditions Min Typ Max Unit TA = 25°C 255 300 345 kHz Oscillator Initial Accuracy Minimum Operation Frequency (1) 100 kHz Maximum Operation Frequency (1) 600 kHz Ramp Peak to Valley (1) 1.5 V Ramp Peak Voltage 2.0 V 0.5 V (1) Ramp Valley Voltage (1) Sleep, Soft Start, Current Limit Sleep Threshold Soft Start Time Measured at FS 0.2 1.8 (1) ISET Bias Current TJ = 25°C Current Limit Blank Time -43 -50 ms -57 150 (1) V µA ns Gate Drive Duty Cycle 0 97 % Vgs = 5V, ISOURCE = 100mA 3 Ω Vgs = 5V, ISINK = 100mA 3 Ω Vgs = 5V, ISOURCE = 100mA 3 Ω Peak Sink (DRVL) (2) Vgs = 5V, ISINK = 100mA 3 Ω Output Rise Time Vgs = 5V, COUT = 4.7nF 35 ns Vgs = 5V, COUT = 4.7nF 35 ns 40 ns Peak Source (DRVH) (2) Peak Sink (DRVH) (2) Peak Source (DRVL) (2) Output Fall Time (2) (2) Minimum Non-Overlap 30 (1) Notes: (1). Guaranteed by design. (2). Guaranteed by characterization. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required. 2004 Semtech Corp. 3 www.semtech.com SC4605 POWER MANAGEMENT Pin Configuration Ordering Information TOP VIEW Part Number (1) SC4605IMSTR BST 1 10 DRVH VCC 2 9 PHASE ISET 3 8 DRVL COMP 4 7 GND FS/SYNC 5 6 VSENSE SC4605IMSTRT (2) Device MSOP-10 Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (MSOP-10) Pin Descriptions VCC: Positive supply rail for the IC. Bypass this pin to GND with a 0.1 to 4.7µF low ESL/ESR ceramic capacitor. ISET / PHASE: PHASE is connected to the junction between the two external power MOSFET transistors. The voltage drop across the high side MOSFET during its conduction is compared with the voltage drop generated by the internal 50µA current source and the external current limit resistor connected between PHASE and Vin, and forms the current limit comparator and logic sets the PWM latch and terminates the output pulse. If the converter output voltage drops below 68.75% of its nominal voltage, the controller stops switching and goes through a soft start sequence. This prevents excess power dissipation in the low side MOSFET during a short circuit. The current limit threshold is set by the external resistor between VCC and ISET. GND: All voltages are measured with respect to this pin. All bypass and timing capacitors connected to GND should have leads as short and direct as possible. FS/SYNC: A capacitor from FS pin to GND sets the PWM oscillator frequency. Use a high quality ceramic capacitor with low ESL and ESR for best result. A minimum capacitor value of 200pF ensures good accuracy and less susceptibility to circuit layout parasitics. When the FS is pulled and held below 0.2V, its sleep mode operation is invoked. The Sleepmode supply current is 10µA typical. The oscillator and PWM are designed to provide practical operation up to 600kHz. In synchronous mode operation, a low value resistor has to be connected between ground and the timing capacitor. An external clock is then feed into the resistor capacitor junction to override the internal clock. BST: This pin connects the external charge pump, and powers the high side MOSFET gate drive. DRVH, DRVL: The output drivers are rated for 1A peak currents. The PWM circuitry provides complementary drive signals to the output stages. The cross conduction of the external MOSFETs is prevented by monitoring the voltage on the driver pins of the MOSFET pair in conjunction with a time delay optimized for FET turn-off characteristics. VSENSE: This pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the Buck converter. It senses the output voltage through an external divider. COMP: This is the output of the voltage amplifier. The voltage at this output is inverted internally and connected to the non-inverting input of the PWM comparator. A leadlag network around the voltage amplifier compensates for the two pole LC filter characteristic inherent to voltage mode control and is required in order to optimize the dynamic performance of the voltage mode control loop. 2004 Semtech Corp. 4 www.semtech.com SC4605 POWER MANAGEMENT Block Diagram Marking Information yyww = Datecode (Example: 0012) xxxx = Semtech Lot # (Example: E901 xxxx 01-1) 2004 Semtech Corp. 5 www.semtech.com SC4605 POWER MANAGEMENT Applications Information Enable Soft Start Pulling and holding the FS/SYNC pin below 0.2V initializes the SLEEP mode of the SC4605 with its typical SLEEP mode supply current of 10µA. During the SLEEP mode, the high side and low side MOSFETs are turned off and the internal soft start voltage is held low. The soft start function is required for step down controllers to prevent excess inrush current through the DC bus during start up. Generally this can be done by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up the error amp reference. The closed loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady state duty cycle as the output voltage reaches its regulated value. With this, the inrush current from the input side is controlled. The duration of the soft start in the SC4605 is controlled by an internal timing circuit which is used during start up and over current to set the hiccup time. The soft start time can be calculated by: Oscillator The oscillator uses an external capacitor between FS and GND to set the oscillation frequency. The ramp waveform is a triangle at the PWM frequency with a peak voltage of 2V and a valley voltage of 0.5V. The PWM duty ratio is limited to a maximum of 97%, which allows the bootstrap capacitor to be charged during each cycle. The capacitor tolerance adds to the accuracy of the oscillator frequency. The approximate operating frequency is determined by the external capacitor connected to the FS/SYNC pin as shown below: fs = TSOFT _ START = As can be seen here, the soft start time is switching frequency dependant. For example, if fs = 300kHz, TSOFT_START = 720/300k = 2.4ms. But if fs = 600kHz, TSOFT_START = 720/600k = 1.2ms. 1.55 ⋅ 10 −4 CT In its synchronous mode, a low value resistor needs to be connected between ground and the frequency setting capacitor, CT. Then an external clock connects to the junction of the resistor and the capacitor to activate its synchronous mode. The frequency of the clock can be used up to 700kHz. This external clock signal should have a duty cycle from 5% to 10% and the peak voltage at the junction from the clock signal should be about 0.2V. The SC4605 implements its soft start by ramping up the error amplifier reference voltage providing a controlled slew rate of the output voltage, then preventing overshoot and limiting inrush current during its start up. Over Current Protection Over current protection for the SC4605 is implemented by detecting the voltage drop of the high side N-MOSFET during its conduction, also known as high side RDS(ON) detection. This loss-less detection eliminates the sense resistor and its loss. The overall efficiency is improved and the number of components and cost of the converter are reduced. RDS(ON) sensing is by default inaccurate and is mainly used to protect the power supply during a fault case. The over current trigger point will vary from unit to unit as the RDS(ON) of N-MOSFET varies. Even for the same unit, the over current trigger point will vary as the junction temperature of N-MOSFET varies. The SC4605 provides a built-in 50µA current source, which is combined with RSET (connected between VCC and ISET) to determine the current limit threshold. The value of RSET can be properly selected according to the desired current limit point IMAX and the internal 50µA pull down current available on the ISET pin based on the following expression: UVLO When the FS/SYNC pin is not pulled and held below 0.2V, the voltage on the Vcc pin determines the operation of the SC4605. As Vcc increases during start up, the UVLO block senses Vcc and keeps the high side and low side MOSFETs off and the internal soft start voltage low until Vcc reaches 2.8V. If no faults are present, the SC4605 will initiate a soft start when Vcc exceeds 2.8V. A hysteresis (150mV) in the UVLO comparator provides noise immunity during its start up. 2004 Semtech Corp. 720 fs 6 www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) R SET = Power MOSFET Drivers IMAX ⋅ R DS( ON) The SC4605 has two drivers for external power NMOSFETs. The driver block consists of one high side NMOSFET, 1A driver, DRVH, and one low side 1A, N-MOSFET driver, DRVL, which are optimized for driving external power MOSFETs in a synchronous buck converter. The output drivers also have gate drive non-overlap mechanism that gives a dead time between DRVH and DRVL transitions to avoid potential shoot through problems in the external MOSFETs. By using the proper design and the appropriate MOSFETs, a 12A converter can be achieved. As shown in Figure 2, td1, the delay from the top MOSFET off to the bottom MOSFET on is adaptive by detecting the voltage of the phase node. td2, the delay from the bottom MOSFET off to the top MOSFET on is fixed, is 50ns for the SC4605. This control scheme guarantees avoiding the cross conduction or shoot through between two MOSFETs and minimizes the conduction loss in the bottom diode for high efficiency applications. 50µA Kelvin sensing connections should be used at the drain and source of N-MOSFET. R needs to be adjusted if SET the input of the application changes significantly, say from 3.3V to 5V for the same load and same output voltage. A 0.1µA ceramic capacitor paralled to this resistor should be used to decouple the noise. The RDS(ON) sensing used in the SC4605 has an additional feature that enhances the performance of the over current protection. Because the RDS(ON) has a positive temperature coefficient, the 50µA current source has a positive coefficient of about 0.17%/C° providing first order correction for current sensing vs temperature. This compensation depends on the high amount of thermal transferring that typically exists between the high side NMOSFET and the SC4605 due to the compact layout of the power supply. TOP MOSFET Gate Drive When the converter detects an over current condition (I > IMAX) as shown in Figure 1, the first action the SC4605 takes is to enter the cycle by cycle protection mode (Point B to Point C), which responds to minor over current cases. Then the output voltage is monitored. If the over current and low output voltage (set at 68.75% of nominal output voltage) occur at the same time, the Hiccup mode operation (Point C to Point D) of the SC4605 is invoked and the internal soft start capacitor is discharged. This is like a typical soft start cycle. BOTTOM MOSFET Gate Drive Ground Phase node td1 td2 Figure 2. Timing Waveforms for Gate Drives and Phase Node Inductor Selection The factors for selecting the inductor include its cost, efficiency, size and EMI. For a typical SC4605 application, the inductor selection is mainly based on its value, saturation current and DC resistance. Increasing the inductor value will decrease the ripple level of the output voltage while the output transient response will be degraded. Low value inductors offer small size and fast transient responses while they cause large ripple currents, poor efficiencies and more output capacitance to smooth out the large ripple currents. The inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss. A good tradeoff among its size, loss and cost is to set the inductor ripple current to be within 15% to 30% of the maximum output current. A B VO − nom 0.6875 ⋅ VO − nom VO C D 0.125 ⋅ VO − nom IMAX IO Figure 1. Over current protection characteristic of SC4605 2004 Semtech Corp. 7 www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) the additional current needed by the load. The ESR and ESL of the output capacitor, the loop parasitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. Surface mount speciality polymer aluminum electrolytic chip capacitors in UE series from Panasonic provide low ESR and reduce the total capacitance required for a fast transient response. POSCAP from Sanyo is a solid electrolytic chip capacitor that has a low ESR and good performance for high frequency with a low profile and high capacitance. Above mentioned capacitors are recommended to use in SC4605 applications. The inductor value can be determined according to its operating point and the switching frequency as follows: L= VO ⋅ ( VI − VO ) VI ⋅ fs ⋅ ∆I ⋅ IOMAX Where: fs = switching frequency and DI = ratio of the peak to peak inductor current to the maximum output load current. The peak to peak inductor current is: IP −P = ∆I • IOMAX Boost Capacitor Selection After the required inductor value is selected, the proper selection of the core material is based on the peak inductor current and efficiency requirements. The core must be able to handle the peak inductor current IPEAK without saturation and produce low core loss during the high frequency operation. IPEAK = IOMAX + The boost capacitor selection is based on its discharge ripple voltage, worst case condition time and boost current. The worst case conduction time T can be estimated W as follows: Tw = Ip −p 2 Where: f = the switching frequency and S Dmax = maximum duty ratio, 0.97 for the SC4605. The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should be minimized to reduce inductor’s copper loss. The core loss can be found in the manufacturer’s datasheet. The inductor’ copper loss can be estimated as follows: The required minimum capacitance for boost capacitor will be: PCOPPER = I2LRMS ⋅ R WINDING Cboost = Where: ILRMS is the RMS current in the inductor. This current can be calculated as follows: ILRMS IB ⋅ TW VD Where: I = the boost current and B V = discharge ripple voltage D 1 = IOMAX ⋅ 1 + ⋅ ∆I2 3 With f = 300kH, V = 0.3V and I = 50mA, the required S D B capacitance for the boost capacitor is: Output Capacitor Selection Cboost = Basically there are two major factors to consider in selecting the type and quantity of the output capacitors. The first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes. The second one is the required capacitance, which should be high enough to hold up the output voltage. Before the SC4605 regulates the inductor current to a new value during a load transient, the output capacitor delivers all 2004 Semtech Corp. 1 ⋅ Dmax fs IB 1 0.05 1 ⋅ ⋅ Dmax = ⋅ ⋅ 0.97 = 540nF VD fs 0.3 300k Input Capacitor Selection The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This capacitor must be able to provide the ripple current by the switching actions. For the continuous conduction 8 www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) PTOP _ TOTAL = I2 TOP _ RMS ⋅ R TOP _ ON + mode, the RMS value of the input capacitor can be calculated from: ICIN (RMS ) = IOMAX ⋅ (Q GD + Q GS 2 ) + Q GT ⋅ VGATE ⋅ fs + (Q OSS + Q rr ) ⋅ VI ⋅ fs VO ⋅ ( VI − VO ) V 2I Where: RG = gate drive resistor, QGD = the gate to drain charge of the top MOSFET, QGS2 = the gate to source charge of the top MOSFET, QGT = the total gate charge of the top MOSFET, QOSS = the output charge of the top MOSFET and Qrr = the reverse recovery charge of the bottom diode. This current gives the capacitor’s power loss as follows: PCIN = I2 CIN(RMS ) ⋅ R CIN(ESR ) This capacitor’s RMS loss can be a significant part of the total loss in the converter and reduce the overall converter efficiency. The input ripple voltage mainly depends on the input capacitor’s ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calculated by: CIN = IOMAX ⋅ For the top MOSFET, it experiences high current and high voltage overlap during each on/off transition. But for the bottom MOSFET, its switching voltage is the bottom diode’s forward drop during its on/off transition. So the switching loss for the bottom MOSFET is negligible. Its total power loss can be determined by: D ⋅ (1 − D) fs ⋅ ( ∆VI − IOMAX ⋅ R CIN(ESR ) ) PBOT _ TOTAL = I2 BOT _ RMS ⋅ R BOT _ ON + Q GB ⋅ VGATE ⋅ fs + ID _ AVG ⋅ VF Where: D = VO/VI , duty ratio and DVI = the given input voltage ripple. Because the input capacitor is exposed to the large surge current, attention is needed for the input capacitor. If tantalum capacitors are used at the input side of the converter, one needs to ensure that the RMS and surge ratings are not exceeded. For generic tantalum capacitors, it is wise to derate their voltage ratings at a ratio of 2 to protect these input capacitors. Where: QGB = the total gate charge of the bottom MOSFET and VF = the forward voltage drop of the bottom diode. For a low voltage and high output current application such as the 3.3V/1.5V@12A case, the conduction loss is often dominant and selecting low RDS(ON) MOSFETs will noticeably improve the efficiency of the converter even though they give higher switching losses. The gate charge loss portion of the top/bottom MOSFET’s total power loss is derived from the SC4605. This gate charge loss is based on certain operating conditions (fs, VGATE, and IO). Power Mosfet Selection The SC4605 can drive an N-MOSFET at the high side and an N-MOSFET synchronous rectifier at the low side. The use of the high side N-MOSFET will significantly reduce its conduction loss for high current. For the top MOSFET, its total power loss includes its conduction loss, switching loss, gate charge loss, output capacitance loss and the loss related to the reverse recovery of the bottom diode, shown as follows: The thermal estimations have to be done for both MOSFETs to make sure that their junction temperatures do not exceed their thermal ratings according to their total power losses PTOTAL, ambient temperature Ta and their thermal resistance Rθja as follows: Tj(max) < Ta + 2004 Semtech Corp. ITOP _ PEAK ⋅ VI ⋅ fs ⋅ VGATE RG 9 PTOTAL R θja www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) Loop Compensation Design Where: R = load resistance and RC = C4’s ESR. For a DC/DC converter, it is usually required that the converter has a loop gain of a high cross-over frequency for fast load response, high DC and low frequency gain for low steady state error, and enough phase margin for its operating stability. Often one can not have all these properties at the same time. The purpose of the loop compensation is to arrange the poles and zeros of the compensation network to meet the requirements for a specific application. The compensation network will have the characteristic as follows: s s 1+ ω ωZ1 ωZ 2 ⋅ GCOMP (s) = I ⋅ s s s 1+ ⋅1+ ωP1 ωP 2 1+ The SC4605 has an internal error amplifier and requires the compensation network to connect among the COMP pin and VSENSE pin, GND, and the output as shown in Figure 3. The compensation network includes C1, C2, R1, R7, R8 and C9. R9 is used to program the output voltage according to: VO = 0.8 ⋅ (1 + Where; ωI = 1 R 7 ⋅ ( C1 + C 2 ) ωZ1 = R7 ) R9 ωZ 2 = 1 (R 7 + R 8 ) ⋅ C 9 SC4605 1 2 3 4 C1 5 C2 BST DRVH VCC PHASE ISET COMP FSET DRVL GND VSENSE 10 L1 ωP1 = +VO 9 1 R1 ⋅ C 2 C1 + C 2 R 1 ⋅ C1 ⋅ C 2 8 7 C4 6 C9 ωP 2 = R7 After the compensation, the converter will have the following loop gain: R8 R1 1 R 8 ⋅ C9 R9 T(s) = GPWM ⋅ GCOMP (s) ⋅ G VD (s) = s 1 s s 1 ⋅ ωI ⋅ VI 1 + 1+ RC ⋅ C4 ω Z1 ωZ 2 VM ⋅ ⋅ ⋅ s s L s ⋅1+ 1+ 1 + s + s 2LC ωP1 ωP 2 R 1+ Figure 3. Compensation network provides 3 poles and 2 zeros. For voltage mode step down applications as shown in Figure 3, the power stage transfer function is: 1+ G VD (s) = VI 2004 Semtech Corp. 1+ s Where: GPWM = PWM gain VM = 1.5V, ramp peak to valley voltage of SC4605 s 1 RC ⋅ C4 L1 + s 2L 1C 4 R 10 www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) Layout Guideline The design guidelines for the SC4605 applications are as following: In order to achieve optimal electrical, thermal and noise performance for high frequency converters, special attention must be paid to the PCB layouts. The goal of layout optimization is to identify the high di/dt loops and minimize them. The following guideline should be used to ensure proper functions of the converters. 1. A ground plane is recommended to minimize noises and copper losses, and maximize heat dissipation. 2. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. Put all the connections on one side of the PCB with wide copper filled areas if possible. 3. The Vcc bypass capacitor should be placed next to the Vcc and GND pins. 4. The trace connecting the feedback resistors to the output should be short, direct and far away from the noise sources such as switching node and switching components. 5. Minimize the traces between DRVH/DRVL and the gates of the MOSFETs to reduce their impedance to drive the MOSFETs. 6. Minimize the loop including input capacitors, top/bottom MOSFETs. This loop passes high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. 7. ISET and PHASE connections to the top MOSFET for current sensing must use Kelvin connections. 8. Maximize the trace width of the loop connecting the inductor, bottom MOSFET and the output capacitors. 9. Connect the ground of the feedback divider and the compensation components directly to the GND pin of the SC4605 by using a separate ground trace. Then connect this pin to the ground of the output capacitor as close as possible. 1. Set the loop gain crossover corner frequency ωC for given switching corner frequency ωS =2πfs, 2. Place an integrator at the origin to increase DC and low frequency gains, 3. Select ωZ1 and ωZ2 such that they are placed near ωO to damp the peaking and the loop gain has a -20dB/dec rate to go across the 0dB line for obtaining a wide bandwidth, 4. Cancel the zero from C4’s ESR by a compensator pole ωP1 ( ωP1 = ωESR = 1/( RCC4)), 5. Place a high frequency compensator pole ωp2 ( ωp2 = πfs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate phase lag at ωC. The compensated loop gain will be as given in Figure 4: T ωZ1 Loop gain T(s) ωo ωZ2 Gvd -20dB/dec ωc 0dB ωp1 ω p2 Power stage GVD(s) ω ESR -40dB/dec Figure 4. Asymptotic diagrams of power stage and its loop gain 2004 Semtech Corp. 11 www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) Design Example 1: 3.3V to 1.5V @ 12A application with SC4605 (NH020 footprint) GND 1 2 3 +VIN C10 D2 R13 1 C14 R3 2.26k R6 1 C3 2 4.7u 3 2.2n C20 R12 100 BST DRVH VCC PHASE ISET 4 C2 330u DRVL COMP 5 FSET GND VSENSE 10 M1 6 J1 1.0 L1 9 7 C7 C6 C5 C4 6 150u 150u 22u 22u R5 M2 C9 4.7n 1.0 SC4605 1 2 3 4 5 +VOUT 1.8u 8 470pF 180p 5 ON/OFF 22u U1 0.1u C1 1u C71 4 C12 R7 10k J2 R8 200 R1 R10 14.3k TRIM 100 R9 11.5k R11 100 ON/OFF Figure 5. Schematic for 3.3V/1.5V@12A with SC4605 application Design Example 2: 5V to 1.5V @ 12A application with SC4605 (NH020 footprint) GND 1 2 3 +VIN C10 D2 R13 1 C14 R3 2.8k 0.1u R6 U1 1 C3 2 4.7u 3 4 C1 C2 2.2n R12 100 180p C20 1u C71 5 BST DRVH VCC PHASE ISET DRVL COMP FSET GND VSENSE 470pF SC4605 10 M1 330u 5 ON/OFF 22u 6 J1 1.0 L1 9 1 2 3 4 5 +VOUT 1.8u 8 7 6 4 C12 R5 M2 1.0 C7 C6 C5 C4 150u 150u 22u 22u C9 4.7n R7 10k J2 R8 200 R1 R10 14.3k R9 11.5k R11 TRIM 100 100 ON/OFF Figure 6. Schematic for 5V/1.5V@12A with SC4605 application 2004 Semtech Corp. 12 www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) Design Example 3: 3.3V to 1.5V @ 15A application with SC4605 and its typical efficiency characteristics. U3 V in= 3.3V D2 C18 R3 2.43k C11 C12 C13 C14 330u 330u 22u 22u 22u 1u C17 Vin Vin GND GND Vin Vin GND GND 8 7 6 5 J8 R13 1 M12 M11 0.1u 4.7u 2 3 4 C2 2.2n C16 5 DRVH VCC PHASE ISET DRVL COMP GND FSET VSENSE 10 9 8 7 R6 V o ut= 1.5V 15 A M21 C7 M22 470u 6 C5 C4 22u 22u C9 8.2n R7 5.62k 470pF 270p 1 2 3 4 5 6 2.2u R5 1 U2 H C 2-2R 2 1 P C3 BST N U1 1 C1 C10 1 2 3 4 R8 115 S C 4605 R1 Vout Vout Vout GND GND GND Vout Vout Vout GND GND GND 12 11 10 9 8 7 J12 4 x S i78 82 15.8k R9 6.49k Figure 7. Schematic for 3.3V/1.5V @ 15A with SC4605 application Efficiency vs Load current 0.93 Efficiency 0.92 0.91 Vin=3.3V 0.9 0.89 Vo=1.5V 0.88 3 6 9 12 15 Load current (A) 2004 Semtech Corp. 13 www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) Design Example 4: 5V to 3.3V @ 5A application with SC4605 and its typical efficiency characteristics. GND 1 2 3 2 x S i7882 D2 R3 2.87k C14 R13 1 0.1u R6 U1 1 C3 2 4.7u 3 4 C1 C2 2.2n R12 100 220p C20 1u C71 5 BST DRVH VCC PHASE ISET DRVL COMP FSET GND VSENSE V IN = 5 V 4 C10 C12 5 22u 22u ON/OFF6 M1 J1 1.0 10 E T Q P 6F 2R 5 9 1 2 3 4 5 V O U T = 3 .3 V /5 A 2.5u 8 7 6 R5 470pF M2 C7 C6 C5 C4 150u 150u 22u 22u R8 1.0 S C 4605 C9 10n R7 4.7k J2 97.6 R1 R10 14.3k R9 1.5k R11 TRIM 100 100 ON/OFF Figure 8. Schematic for 5V/3.3V@ 5A with SC4605 application Efficiency vs Load current 0.98 0.97 Efficiency 0.96 0.95 0.94 Vin=5V 0.93 0.92 0.91 Vo=3.3V 0.9 1 2 3 4 5 Load current (A) 2004 Semtech Corp. 14 www.semtech.com SC4605 POWER MANAGEMENT Bill of Materials - 3.3V to 1.5V @ 12A Item Qty Reference Value Part No./Manufacturer 1 1 C1 180pF 2 1 C2 2.2nF 3 1 C3 4.7uF, 0805 4 1 C 71 1uF 5 3 C 4, C 5, C 12 22uF, 1210 TDK P/N: C3225X5R0J226M 6 2 C 6, C 7 150uF, 2870 Sanyo P/N: 4TPB150ML 7 1 C9 4.7nF 8 1 C 10 330uF, 2870 9 1 C 14 0.1uF 10 1 C 20 470pF 11 1 D2 MBR0520LT1, SOD-123 ON Semiconductor 14 1 L1 Inductor, 1.8uF Panasonic. P/N: ETQP6F1R8BFR 15 2 M1, M2 Powerpack, SO-8 Vishay P/N: Si7858DP 16 1 R1 14.3k 17 1 R3 2.32k 18 2 R5, R6 1.0 19 1 R7 10k 20 1 R8 200 21 1 R9 11.5k 22 3 R10, R11, R12 100 23 1 R13 1 24 1 U1 S C 4605 Sanyo P/N: 6TPB330ML Semtech P/N: SC4605IMSTR Unless specified, all resistors have 1% precision with 0603 package. Capacitors will have 20% percision with 0603 package. For R9, there are 3 kinds of values for different output cases. 2004 Semtech Corp. 15 www.semtech.com SC4605 POWER MANAGEMENT PCB Layout - 3.3V to 1.5V @ 12A Top Bottom Top Bottom 2004 Semtech Corp. 16 www.semtech.com SC4605 POWER MANAGEMENT Applications Information (Cont.) Over current protection characteristic of SC4605 for 3.3V to 1.5V @12A application The over current protection curve below is obtained by applying a gradually increased load while the load current and the output voltage are monitored and measured. When the load current is increased from 0 to 16.2A (over current trigger point), the output voltage is 1.5V, corresponding from Point A to Point B. As the load current increases further from 16.2A to 16.3A, the output voltage drops significantly from 1.5V (Point B) to 0.88V (Point C). Because an over current and a lower output voltage (0.88V<68.75%*1.5V=1.03V) are present at Point C, the SC4605 enters its HICCUP mode. Then the locus of the output current and the output voltage follows Line CD as shown in the curve. Due to the over current applied, the HICCUP protection will go back and forth on Line CD. This prevents excess power dissipation in the TOP MOSFET during a short output condition. Over current protection 3 2.5 A B Vo (V) 2 1.5 D 1 0.5 C 0 0 5 10 15 20 Io (A) 2004 Semtech Corp. 17 www.semtech.com SC4605 POWER MANAGEMENT Typical Characteristics 318 316 314 312 310 308 306 304 Oscillator Internal Accuracy vs Temperature Internal Accuracy (kHz) Internal Accuracy (kHz) Oscillator Internal Accuracy vs Input Voltage TA = 25°C 2.5 3 3.5 4 4.5 5 314 312 310 308 306 304 302 300 298 Vcc = 5V -40 5.5 -20 0 20 Sense Voltage (V) Sense Voltage (V) 0.804 TA = 25°C 0.803 0.803 0.802 0.802 80 100 120 80 100 120 80 100 120 Vcc = 5V 0.802 0.800 0.798 0.796 0.794 0.792 0.801 2.5 3 3.5 4 4.5 5 -40 5.5 -20 0 40 60 Current Limit Bias Current vs Temperature Current Limit Bias Current vs Input Voltage 60.0 TA = 25°C Current Limit Bias Current (uA) 51.0 50.5 50.0 49.5 49.0 48.5 48.0 47.5 20 Temperature (°C) Vcc (V) Current Limit Bias Current (uA) 60 Sense Voltage vs Temperature Sense Voltage vs Input Voltage 0.804 40 Temperature (°C) Vcc (V) 55.0 Vcc = 5V 50.0 45.0 40.0 35.0 30.0 2.5 3 3.5 4 4.5 5 5.5 -40 Vcc (V) 2004 Semtech Corp. -20 0 20 40 60 Temperature (°C) 18 www.semtech.com SC4605 POWER MANAGEMENT Outline Drawing - MSOP-10 DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX e A DIM D 2X E/2 ccc C 2X N/2 TIPS E E1 PIN 1 INDICATOR .043 .000 .006 .030 .037 .007 .011 .003 .009 .114 .118 .122 .114 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 0° 8° .004 .003 .010 A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc N 12 B 1.10 0.00 0.15 0.95 0.75 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0° 8° 0.10 0.08 0.25 D aaa C SEATING PLANE A2 H A bxN bbb c GAGE PLANE A1 C C A-B D 0.25 L (L1) DETAIL SEE DETAIL SIDE VIEW 01 A A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA. Land Pattern - MSOP-10 X DIM (C) G Y Z C G P X Y Z DIMENSIONS INCHES MILLIMETERS (.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 2OO Flynn Road, Camarillo, CA. 93012 Phone: (805)498-2111 FAX (805)498-3804 2004 Semtech Corp. 19 www.semtech.com