SEMTECH SX1211I084TRT

SX1211 Transceiver
Lowest Power Integrated UHF Transceiver
Short Range Devices
ADVANCED COMMUNICATIONS & SENSING
General Description
Features
The SX1211 is a low cost single-chip transceiver
operating in the frequency ranges from 863-870, 902928 MHz and 950-960 MHz. The SX1211 is optimized
for very low power consumption (3mA in receiver
mode). It incorporates a baseband modem with data
rates up to 100 kb/s. Data handling features include a
sixty-four byte FIFO, packet handling, automatic CRC
generation and data whitening. Its highly integrated
architecture allows for minimum external component
count whilst maintaining design flexibility. All major RF
communication parameters are programmable and
most of them may be dynamically set. It complies with
European (ETSI EN 300-220 V2.1.1) and North
American (FCC part 15) regulatory standards.
Applications
Wireless alarm and security systems
Wireless sensor networks
Automated Meter Reading
Home and building automation
Industrial monitoring and control
Low Rx power consumption: 3mA
Low Tx power consumption: 25 mA @ +10 dBm
Good reception sensitivity: down to -104 dBm at
25 kb/s in FSK, -111 dBm at 2kb/s in OOK
Programmable RF output power: up to +12.5 dBm
in 8 steps
Packet handling feature with data whitening and
automatic CRC generation
RSSI (Received Signal Strength Indicator) range
from noise floor to 0 dBm
Bit rates up to 100 kb/s, NRZ coding
On-chip frequency synthesizer
FSK and OOK modulation
Incoming sync word recognition
Built-in Bit-Synchronizer for incoming data and
clock synchronization and recovery
5 x 5 mm TQFN package
Ordering Information
Table 1: Ordering Information
Part number
Temperature Range
SX1211I084TRT
-40 °C to +85 °C
Package
Lead Free
TQFN-32
TR refers to Tape and Reel delivery
T refers to Lead Free packaging
This device is WEEE and RoHS compliant
Block Diagram
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
Table of Contents
1. Block Diagram and General Description ........................ 5
1.1. Simplified Block Diagram ............................................ 5
1.2. Pin Diagram ................................................................ 6
1.3. Pin Description............................................................ 7
2. Electrical Characteristics................................................ 8
2.1. ESD Notice ................................................................. 8
2.2. Absolute Maximum Ratings ........................................ 8
2.3. Operating Range......................................................... 8
2.4. Chip Specification ....................................................... 8
2.4.1. Power Consumption................................................. 8
2.4.2. Frequency Synthesis................................................ 9
2.4.3. Transmitter............................................................... 9
2.4.4. Receiver................................................................. 10
2.4.5. Digital Specification................................................ 11
3. Architecture Description............................................... 12
3.1. Power Supply Strategy.............................................. 12
3.2. Frequency Synthesis Description.............................. 12
3.2.1. Crystal Resonator Specification ............................. 12
3.2.2. CLKOUT Output..................................................... 13
3.2.3. PLL Architecture .................................................... 13
3.2.4. PLL Tradeoffs ........................................................ 14
3.2.5. Voltage Controlled Oscillator.................................. 14
3.2.6. PLL Loop Filter....................................................... 15
3.2.7. PLL Lock Detection Indicator ................................. 16
3.2.8. Frequency Calculation ........................................... 16
3.2.9. Software for Frequency Calculation ....................... 16
3.3. Transmitter Description ............................................. 18
3.3.1. Architecture Description ......................................... 18
3.3.2. Bit Rate Setting ...................................................... 19
3.3.3. Fdev Setting in FSK Mode ..................................... 19
3.3.4. Fdev Setting in OOK Mode .................................... 19
3.3.5. Suggested Interpolation Filter Setting .................... 19
3.3.6. Power Amplifier...................................................... 20
3.3.7. Transmitter Spectral Purity..................................... 22
3.3.8. Common Input and Output Front-End.................... 22
3.4. Receiver Description................................................. 24
3.4.1. Architecture............................................................ 24
3.4.2. LNA and First Mixer ............................................... 25
3.4.3. IF Gain and Second I/Q Mixer................................ 25
3.4.4. Channel Filters....................................................... 25
3.4.5. Channel Filters Setting in FSK Mode ..................... 27
3.4.6. Channel Filters Setting in OOK Mode .................... 27
3.4.7. RSSI....................................................................... 27
3.4.8. Fdev Setting in Receive Mode ............................... 28
3.4.9. FSK Demodulator .................................................. 29
3.4.10. OOK Demodulator................................................ 29
3.4.11. Bit Synchronizer................................................... 31
3.4.12. Data Output.......................................................... 32
4. Data Processing........................................................... 33
4.1. Overview ................................................................... 33
4.1.1. Block Diagram........................................................ 33
4.1.2. Data Operation Modes ........................................... 33
4.2. Building Blocks Description....................................... 34
4.2.1. SPI Interface .......................................................... 34
4.2.2. FIFO....................................................................... 37
V3.0 – august 15th, 2007
4.2.3. Sync Word Recognition ..........................................39
4.2.4. Packet Handler .......................................................39
4.2.5. Control ....................................................................39
4.3. Continuous Mode ......................................................40
4.3.1. General Description ................................................40
4.3.2. Tx Processing.........................................................40
4.3.3. Rx Processing ........................................................40
4.3.4. Interrupt Signals Mapping.......................................41
4.3.5. uC Connections ......................................................41
4.3.6. Example of Usage ..................................................42
4.4. Buffered Mode ...........................................................42
4.4.1. General Description ................................................42
4.4.2. Tx Processing.........................................................43
4.4.3. Rx Processing ........................................................44
4.4.4. Interrupt Signals Mapping.......................................45
4.4.5. uC Connections ......................................................46
4.4.6. Example of Usage ..................................................46
4.5. Packet Mode..............................................................47
4.5.1. General Description ................................................47
4.5.2. Packet Format ........................................................48
4.5.3. Tx Processing.........................................................49
4.5.4. Rx Processing ........................................................49
4.5.5. Packet Filtering.......................................................50
4.5.6. DC-Free Data Mechanisms ....................................51
4.5.7. Interrupt Signal Mapping.........................................52
4.5.8. uC Connections ......................................................53
4.5.9. Example of Usage ..................................................53
4.5.10. Additional Information ...........................................54
5. Operating Modes ..........................................................55
5.1. Modes of Operation ...................................................55
5.2. Digital Pin Configuration vs. Chip Mode ....................55
5.3. Switching Times and Procedures ..............................55
5.3.1. Optimized Receive Cycle........................................56
5.3.2. Optimized Transmit Cycle.......................................57
5.3.3. Transmitter Frequency Hop Optimized Cycle .........58
5.3.4. Receiver Frequency Hop Optimized Cycle .............59
5.3.5. RxTx and TxRx Jump Cycles ..........................60
5.4. Power-On Reset ........................................................60
6. Configuration and Status Registers ..............................61
6.1. General Description...................................................61
6.2. Main Configuration Register - MCParam ...................61
6.3. Interrupt Configuration Parameters - IRQParam .......63
6.4. Receiver Configuration parameters - RXParam ........65
6.5. Sync Word Parameters - SYNCParam ......................66
6.6. Transmitter Parameters - TXParam...........................67
6.7. Oscillator Parameters - OSCParam...........................67
6.8. Packet Handling Parameters – PKTParam................68
7. Reference Design.........................................................69
7.1. Schematics ................................................................69
7.2. PCB Layout ...............................................................69
7.3. Bill Of Material ...........................................................70
7.4. SAW Filter Plot ..........................................................71
8. Packaging Information..................................................72
9. Contact Information ......................................................73
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SX1211
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Index of Figures
Figure 1: SX1211 Block Diagram....................................... 5
Figure 2: SX1211 Pin Diagram .......................................... 6
Figure 3: Power Supply Breakdown................................. 12
Figure 4: Frequency Synthesizer Description .................. 13
Figure 5: LO Generator.................................................... 14
Figure 6: Loop Filter......................................................... 15
Figure 7: Transmitter Architecture.................................... 18
Figure 8: I(t), Q(t) Overview ............................................. 18
Figure 9: PA Control ........................................................ 20
Figure 10: Optimal Load Impedance Chart ...................... 21
Figure 11: Suggested PA Biasing and Output Matching .. 21
Figure 12: 869MHz Spectral Purity DC-1GHz.................. 22
Figure 13: 869MHz Spectral Purity 1-6GHz ..................... 22
Figure 14: Front-end Description ..................................... 23
Figure 15: Receiver Architecture...................................... 24
Figure 16: FSK Receiver Setting...................................... 24
Figure 17: OOK Receiver Setting..................................... 24
Figure 18: Active Channel Filter Description.................... 26
Figure 19: Butterworth Filter's Actual BW ........................ 27
Figure 20: Polyphase Filter's Actual BW .......................... 27
Figure 21: RSSI IRQ Timings........................................... 28
Figure 22: OOK Demodulator Description........................ 29
Figure 23: Floor Threshold Optimization.......................... 30
Figure 24: BitSync Description......................................... 31
Figure 25: SX1211’s Data Processing Conceptual View . 33
Figure 26: SPI Interface Overview and uC Connections.. 34
Figure 27: Write Register Sequence ................................ 35
Figure 28: Read Register Sequence................................ 36
Figure 29: Write Bytes Sequence (ex: 2 bytes)................ 36
Figure 30: Read Bytes Sequence (ex: 2 bytes)................ 37
V3.0 – august 15th, 2007
Figure 31: FIFO and Shift Register (SR)...........................37
Figure 32: FIFO Threshold IRQ Source Behavior.............38
Figure 33: Sync Word Recognition ...................................39
Figure 34: Continuous Mode Conceptual View.................40
Figure 35: Tx Processing in Continuous Mode .................40
Figure 36: Rx Processing in Continuous Mode.................41
Figure 37: uC Connections in Continuous Mode ..............41
Figure 38: Buffered Mode Conceptual View .....................43
Figure 39: Tx processing in Buffered Mode ......................44
Figure 40: Rx Processing in Buffered Mode .....................45
Figure 41: uC Connections in Buffered Mode...................46
Figure 42: Packet Mode Conceptual View........................47
Figure 43: Fixed Length Packet Format ...........................48
Figure 44: Variable Length Packet Format .......................49
Figure 45: CRC Implementation .......................................51
Figure 46: Manchester Encoding/Decoding......................52
Figure 47: Data Whitening ................................................52
Figure 48: uC Connections in Packet Mode .....................53
Figure 49: Optimized Rx Cycle .........................................56
Figure 50: Optimized Tx Cycle .........................................57
Figure 51: Tx Hop Cycle ...................................................58
Figure 52: Rx Hop Cycle...................................................59
Figure 53: Rx Tx Rx Cycle.......................................60
Figure 54: Reference Design’s Schematics......................69
Figure 55: Reference Design‘s Stackup ...........................70
Figure 56: Reference Design’s Layout (top view) .............70
Figure 57: 915 MHz SAW Filter Plot.................................71
Figure 58: 869 MHz SAW Filter Plot.................................71
Figure 59: Package Information........................................72
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Index of Tables
Table 1: Ordering Information ............................................ 1
Table 2: SX1211 Pinouts ................................................... 7
Table 3: Absolute Maximum Ratings ................................. 8
Table 4: Operating Range.................................................. 8
Table 5: Power Consumption Specification........................ 8
Table 6: Frequency Synthesizer Specification ................... 9
Table 7: Transmitter Specification...................................... 9
Table 8: Receiver Specification........................................ 10
Table 9: Digital Specification............................................ 11
Table 10: Crystal Resonator Specification ....................... 13
Table 11: MCParam_Freq_band Setting ......................... 15
Table 12: PA Rise/Fall Times........................................... 20
Table 13: Data Operation Mode Selection ....................... 34
Table 14: Config vs. Data SPI Interface Selection ........... 35
Table 15: Status of FIFO when Switching Between
Different Modes of the Chip ............................................. 38
Table 16: Interrupt Mapping in Continuous Rx Mode....... 41
Table 17: Interrupt Mapping in Continuous Tx Mode ....... 41
Table 18: Relevant Configuration Registers in Continuous
Mode (data processing related only)................................ 42
Table 19: Interrupt Mapping in Buffered Rx and Stby
Modes...............................................................................45
Table 20: Interrupt Mapping in Buffered Tx Mode ............45
Table 21: Relevant Configuration Registers in Buffered
Mode (data processing related only) ................................46
Table 22: Interrupt Mapping in Rx and Stby in Packet Mode
52
Table 23: Interrupt Mapping in Tx Packet Mode ...............53
Table 24: Relevant Configuration Registers Relevant in
Packet Mode (data processing related only).....................54
Table 25: Operating Modes ..............................................55
Table 26: Pin Configuration vs. Chip Mode ......................55
Table 27: Registers List....................................................61
Table 28: MCParam Register Description ........................61
Table 29: IRQParam Register Description........................63
Table 30: RXParam Register Description.........................65
Table 31: SYNCParam Register Description ....................66
Table 32: TXParam Register Description .........................67
Table 33: OSCParam Register Description ......................67
Table 34: PKTParam Register Description .......................68
Table 35: Reference Design’s BOM .................................70
Acronyms
BOM
BR
BW
CCITT
CP
CRC
DAC
DDS
DLL
ETSI
FCC
Fdev
FIFO
FS
FSK
GUI
IC
ID
IF
IRQ
ITU
LFSR
LNA
Bill Of Materials
Bit Rate
Bandwidth
Comité Consultatif International
Téléphonique et Télégraphique - ITU
Charge Pump
Cyclic Redundancy Check
Digital to Analog Converter
Direct Digital Synthesis
Dynamically Linked Library
European Telecommunications Standards
Institute
Federal Communications Commission
Frequency Deviation
First In First Out
Frequency Synthesizer
Frequency Shift Keying
Graphical User Interface
Integrated Circuit
IDentificator
Intermediate Frequency
Interrupt ReQuest
International Telecommunication Union
Linear Feedback Shift Register
Low Noise Amplifier
V3.0 – august 15th, 2007
LO
LSB
MSB
NRZ
NZIF
OOK
PA
PCB
PFD
PLL
RBW
RF
RSSI
Rx
SAW
SPI
SR
Stby
Tx
uC
VCO
XO
XOR
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Local Oscillator
Least Significant Bit
Most Significant Bit
Non Return to Zero
Near Zero Intermediate Frequency
On Off Keying
Power Amplifier
Printed Circuit Board
Phase Frequency Detector
Phase-Locked Loop
Resolution BandWidth
Radio Frequency
Received Signal Strength Indicator
Receiver
Surface Acoustic Wave
Serial Peripheral Interface
Shift Register
Standby
Transmitter
Microcontroller
Voltage Controlled Oscillator
Crystal Oscillator
eXclusive OR
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SX1211
ADVANCED COMMUNICATIONS & SENSING
1. Block Diagram and General Description
The SX1211 is a single chip FSK and OOK transceiver capable of operation in the 863-870 MHz and 902-928 MHz
license free ISM frequency bands, and 950 - 960 MHz frequency bands. It complies with both European and North
American standards, EN 300-220 V2.1.1 (June 2006 release) and FCC Part 15 (10-1-2006 edition). A unique
feature of this circuit is its extremely low current consumption in receiver mode of 3mA (typ).
The SX1211 comes in a 5x5 mm TQFN-32 package.
1.1. Simplified Block Diagram
VR_PA
PA
I
Q
LO2 Tx
I
Q
LO2 Tx
Waveform
generator
I
RFIO
LO1 Tx
Q
RSSI
OOK
demod
BitSync
LNA
Control
FSK
demod
LO2 Rx
IRQ_0
IRQ_1
MOSI
MISO
SCK
NSS_CONFIG
NSS_DATA
CLKOUT
DATA
LO1 Rx
TEST(8:0)
LO1 Rx
PLL_LOCK
XTAL_P
XO
I LO2 Rx
Q
Frequency Synthesizer
LO
Generator
XTAL_M
I LO1 Tx
Q
I LO2 Tx
Q
VR_1V
VR_DIG
VCO_P
VCO_M
VR_VCO
LF_M
LF_P
Figure 1: SX1211 Block Diagram
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
1.2. Pin Diagram
The following diagram shows the pins arrangement on the QFN package, top view.
Figure 2: SX1211 Pin Diagram
Notes:
yyww refers to the date code
------ refers to the lot number
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ADVANCED COMMUNICATIONS & SENSING
1.3. Pin Description
Table 2: SX1211 Pinouts
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
GND
TEST5
TEST1
VR_VCO
VCO_M
VCO_P
LF_M
LF_P
TEST6
TEST7
XTAL_P
XTAL_M
TEST0
TEST8
NSS_CONFIG
NSS_DATA
MISO
MOSI
SCK
CLKOUT
DATA
Type
I
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
I
O
I
I
O
I/O
Description
Exposed ground pad
Connect to GND
Connect to GND
Regulated supply of the VCO
VCO tank
VCO tank
PLL loop filter
PLL loop filter
Connect to GND
Connect to GND
Crystal connection
Crystal connection
Connect to GND
Do not connect
SPI CONFIG enable
SPI DATA enable
SPI data output
SPI data input
SPI clock input
Clock output
NRZ data input and output
(Continuous mode)
21
22
23
24
25
26
27
IRQ_0
IRQ_1
PLL_LOCK
TEST2
TEST3
VDD
VR_1V
O
O
O
I/O
I/O
I
O
Interrupt output
Interrupt output
PLL lock detection output
Connect to GND
Connect to GND
Supply voltage
Regulated supply of the analog
circuitry
28
VR_DIG
O
Regulated supply of digital
circuitry
29
30
31
32
VR_PA
TEST4
RFIO
NC
O
I/O
I/O
-
Regulated supply of the PA
Connect to GND
RF input/output
Connect to GND
Note: pin 13 (Test 8) should be left unconnected on any design.
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SX1211
ADVANCED COMMUNICATIONS & SENSING
2. Electrical Characteristics
2.1. ESD Notice
The SX1211 is a high performance radio frequency device. It satisfies general ESD quality rules, except on pins 34-5-27-28-29-31. It should thus be handled with all the necessary ESD precautions to avoid any permanent
damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Table 3: Absolute Maximum Ratings
Symbol
VDDmr
Tmr
Pmr
Description
Supply voltage
Storage temperature
Input level
Min.
-0.3
-55
-
Max.
3.7
125
0
Min.
2.1
-40
-
Max.
3.6
+85
0
Unit
V
°C
dBm
2.3. Operating Range
Table 4: Operating Range
Symbol
VDDop
Trop
ML
Description
Supply Voltage
Temperature
Input Level*
Unit
V
°C
dBm
Note: above -10 dBm input power, the receive current can increase over the specification.
2.4. Chip Specification
Conditions: Temp = 25 °C, VDD = 3.3 V, crystal freq uency = 12.8 MHz, carrier frequency = 869 or 915 MHz,
modulation FSK, data rate = 25 kb/s, Fdev = 50 kHz, fo = 50 kHz, fc-fo = 100 kHz, unless otherwise specified.
2.4.1. Power Consumption
Symbol
IDDSL
IDDST
IDDFS
IDDR
IDDT
Description
Supply current in sleep
mode
Supply current in standby
mode, CLKOUT disabled
Supply current in FS mode
Supply current in receiver
mode
Supply current in
transmitter mode
Conditions
Min
Typ
Max
Unit
-
0.3
-
µA
Crystal oscillator running
-
55
80
µA
Frequency synthesizer
running
-
1.3
1.7
mA
-
3.0
3.5
mA
-
25
16
30
21
mA
mA
Output power = 10 dBm
Output power = 1dBm
Table 5: Power Consumption Specification
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
2.4.2. Frequency Synthesis
Table 6: Frequency Synthesizer Specification
Symbol
Description
Conditions
FR
Frequency ranges
Programmable but requires
a specific BOM.
BR_F
BR_O
FDA
XTAL
Bit rate (FSK)
Bit rate (OOK)
Frequency deviation (FSK)
Crystal oscillator frequency
Frequency synthesizer
step
Oscillator wake-up time
FSTEP
TS_OSC
TS_FS
TS_HOP
Frequency synthesizer
wake-up time
Frequency synthesizer hop
time
NRZ
NRZ
Min
863
902
950
1.56
1.56
33
12
Variable, depending on the
frequency.
From sleep mode.
From Stby to frequency at
most 10 kHz away from the
target.
200 kHz step at most
10 kHz away from the
target
1MHz step at most 10 kHz
away from the target
10 MHz step at most
10 kHz away from the
target
Typ
50
12.8
Max
870
928
960
100
32
200
15
Unit
MHz
MHz
MHz
kb/s
kb/s
kHz
MHz
-
2
-
kHz
-
1.5
5
ms
-
500
800
µs
-
200
-
µs
-
220
-
µs
-
350
-
µs
2.4.3. Transmitter
Table 7: Transmitter Specification
Symbol
Description
Conditions
RF output power,
programmable with 8 steps
of typ. 3dB
Maximum power setting
-
12.5
-
RFOP
Minimum power setting
-
-8.5
-
-
-112
-
-
-
-47
dBc
Measured with a 600 kHz
offset, at the transmitter
output.
At any offset between
200 kHz and 600 kHz,
unmodulated carrier, Fdev
= 50 kHz.
Min
Typ
Max
Unit
dBm
PN
Phase noise
SPT
Transmitted spurious
TS_TR
Transmitter wake-up time
From FS to Tx ready.
-
120
500
µs
TS_TR2
Transmitter wake-up time
From Stby to Tx ready.
-
600
900
µs
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dBc/Hz
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ADVANCED COMMUNICATIONS & SENSING
2.4.4. Receiver
Table 8: Receiver Specification
Symbol
RFS_F
RFS_O
CCR
ACR
BI
RXBW_F
RXBW_O
IIP3
TS_RE
TS_RE2
TS_RSSI
Description
Sensitivity (FSK)
Sensitivity (OOK)
Conditions
869 MHz, BR=25 kb/s,
Fdev =50 kHz, fc=100 kHz
869 MHz, BR=66.7 kb/s,
Fdev=100 kHz, fc=200 kHz
915 MHz, BR=25 kb/s,
Fdev=50 kHz, fc=100 kHz
915 MHz, BR = 66.7 kb/s,
Fdev=100 kHz, fc=200 kHz
869 MHz, 2kb/s NRZ
fc=50 kHz, fo=50 kHz
869 MHz, 16.7 kb/s NRZ
fc=100 kHz, fo=100 kHz
915 MHz, 2kb/s NRZ
fc=50 kHz, fo=50 kHz
915 MHz, 16.7 kb/s NRZ
fc=100 kHz, fo=100 kHz
Co-channel rejection
Adjacent channel rejection
Blocking immunity
Receiver bandwidth in FSK
mode
Receiver bandwidth in OOK
mode
rd
Input 3 order intercept
point
Receiver wake-up time
Receiver wake-up time
RSSI sampling time
Offset = 600 kHz, same
modulation as wanted
signal
Offset = 300 kHz, same
modulation as wanted
signal
Offset = 1.2 MHz, same
modulation as wanted
signal
Offset = 1 MHz,
unmodulated
Offset = 2 MHz,
unmodulated, no SAW
Offset = 10 MHz,
unmodulated, no SAW
Single side BW
Polyphase Off
Single side BW
Polyphase On
Interferers at 1MHz and
1.950 MHz offset
From FS to Rx ready
From Stby to Rx ready
From Rx ready
Min
Typ
Max
Unit
-
-104
-
dBm
-
-100
-
dBm
-
-102
-
dBm
-
-98
-
dBm
-
-110
-
dBm
-
-102
-
dBm
-
-108
-
dBm
-
-102
-
dBm
-
-12
-
dBc
-
42
-
dBc
-
24
-
dBc
-
57
-
dBc
-
53
-
dBc
-
-37
-
dBm
-
-33
-
dBm
50
-
250
kHz
50
-
400
kHz
-
-28
-
dBm
-
280
600
-
500
900
1/Fdev
µs
µs
s
Notes:
fc and fo describe the bandwidth of the active channel filters as described in section 3.4.4.2
All sensitivities are measured receiving a PN15 sequence, for a BER of 0.1%
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SX1211
ADVANCED COMMUNICATIONS & SENSING
2.4.5. Digital Specification
Conditions: Temp = 25 °C, VDD = 3.3 V, crystal freq uency = 12.8 MHz, unless otherwise specified.
Table 9: Digital Specification
Symbol
VIH
VIL
VOH
VOL
SCK_CONFIG
SCK_DATA
T_DATA
T_MOSI_C
T_MOSI_D
T_NSSC_L
T_NSSD_L
T_NSSC_H
T_NSSD_H
Description
Digital input level high
Digital input level low
Digital output level high
Digital output level low
SPI config clock frequency
SPI data clock frequency
DATA hold and setup time
MOSI setup time for SPI Config.
MOSI setup time for SPI Data.
NSS_CONFIG low to SCK rising edge.
SCK falling edge to NSS_CONFIG high.
NSS_DATA low to SCK rising edge.
SCK falling edge to NSS_DATA high.
NSS_CONFIG rising to falling edge.
NSS_DATA rising to falling edge.
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Conditions
Imax=1mA
Imax=-1mA
Page 11 of 73
Min
0.8*VDD
0.9*VDD
2
250
312
Typ
Max
Unit
V
V
V
V
MHz
MHz
µs
ns
ns
-
0.2*VDD
0.1*VDD
2
1.6
-
500
-
-
ns
625
-
-
ns
500
625
-
-
ns
ns
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SX1211
ADVANCED COMMUNICATIONS & SENSING
3. Architecture Description
This section describes in depth the architecture of this ultra low-power transceiver.
3.1. Power Supply Strategy
To provide stable sensitivity and linearity characteristics over a wide supply range, the SX1211 is internally
regulated. This internal regulated power supply structure is described below:
1ųF
Y5V
Vbat
VDD – Pin 26
2.1 – 3.6V
External Supply
Reg_top
1.4 V
Biasing :
-SPI
-Config. Registers
-POR
Reg_ana
1.0 V
Biasing analog
blocks
Reg_dig
1.0 V
Biasing digital
blocks
Biasing :
-VCO circuit
-Ext. VCO
tank
VR_DIG
Pin 28
VR_1V
Pin 27
1ųF
Y5V
Reg_VCO
0.85 V
220nF
X7R
Reg_PA
1.80 V
Biasing :
-PA Driver
-PA choke
(ext)
VR_PA
Pin 29
VR_VCO
Pin 3
100nF
X7R
47nF
X7R
Figure 3: Power Supply Breakdown
To ensure correct operation of the regulator circuit, the decoupling capacitor connection shown in Figure 3 is
required. These decoupling components are mandatory for any design.
3.2. Frequency Synthesis Description
The frequency synthesizer of the SX1211 is a fully integrated integer-N type PLL. The PLL circuit requires only six
external components - the reference oscillator crystal, the PLL loop filter and the VCO tank circuit.
3.2.1. Crystal Resonator Specification
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Table 10: Crystal Resonator Specification shows the crystal resonator specification for the crystal reference
oscillator circuit of the SX1211. This specification covers the full range of operation of the SX1211 and is employed
in the reference design (see section 7),
Name
Fxtal
Cload
Rm
Co
∆Fxtal
∆Fxtal(∆T)
∆Fxtal(∆t)
Description
Nominal frequency
Load capacitance for Fxtal
Motional resistance
Shunt capacitance
Calibration tolerance at 25+/-3°C
Stability over temperature range
[-40°C ; +85°C]
Aging tolerance in first 5 years
Min. value
12
13.5
1
-15
-20
Typ. value
12.800
15
-
-2
Max. value
15
16.5
100
7
+15
+20
-
+2
Unit
MHz
pF
ohms
pF
ppm
ppm
ppm/
year
Table 10: Crystal Resonator Specification
Note that the initial frequency tolerance, temperature stability and ageing performance should be chosen in
accordance with the target operating temperature range and the receiver bandwidth selected.
3.2.2. CLKOUT Output
The reference frequency, or a sub-multiple of it, can be provided on CLKOUT (pin 19) by activating the bit
OSCParam_Clkout_on. The division ratio is programmed through bits OSCParam_Clkout_freq. The two
applications of the CLKOUT output are:
To provide a clock output for a companion uC, thus saving the cost of an additional oscillator. CLKOUT can be
made available in any operation mode, except Sleep mode, and is automatically enabled at power-up.
To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software
trimming of the initial crystal tolerance.
Note: To minimize the current consumption of the SX1211, ensure that the CLKOUT signal is disabled when
unused.
3.2.3. PLL Architecture
The crystal oscillator (XO) forms the reference oscillator of an Integer-N Phase Locked Loop (PLL), whose
operation is discussed in the following section. Figure 4 shows a block schematic of the SX1211 PLL. Here the
crystal reference frequency and the software controlled dividers R, P and S determine the output frequency of the
PLL.
÷75.(Pi+1)+Si
LO
PFD
÷(Ri+1)
XO
Vtune
Fcomp
XT_M
XT_P
LF_M
LF_P
VCO_P
VCO_M
VR_VCO
Figure 4: Frequency Synthesizer Description
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ADVANCED COMMUNICATIONS & SENSING
The VCO tank inductors are connected on an external differential input. Similarly, the loop filter is also located
externally. However, there is an internal 8 pF capacitance at VCO input that should be subtracted from the desired
loop filter capacitance.
The output signal of the VCO is used as the input to the local oscillator (LO) generator stage, illustrated in Figure 5.
The VCO frequency is subdivided and used in a series of up (down) conversions for transmission (reception).
LO1 Rx
Receiver
LOs
I
LO2 Rx
÷8
90°
Q
LO
VCO Output
I
LO1 Tx
90°
Q
Transmitter
LOs
I
LO2 Tx
÷8
90°
Q
Figure 5: LO Generator
3.2.4. PLL Tradeoffs
With an integer-N PLL architecture, the following criterion must be met, to ensure correct operation:
The comparison frequency Fcomp of the Phase Frequency Detector (PFD) input must remain higher than six
times the PLL bandwidth (PLLBW) to guarantee loop stability and to reject harmonics of the comparison
frequency Fcomp. This is expressed in the inequality:
PLLBW ≤
Fcomp
6
However the PLLBW has to be sufficiently high to allow adequate PLL lock times
Because the divider ration R determines Fcomp, it should be set close to 119, leading to Fcomp≈100 kHz
which will ensure suitable PLL stability and speed.
With the recommended Bill Of Materials (BOM) of the reference design of section 7, the PLL prototype is the
following:
64 ≤ R ≤ 169
S < P+1
PLLBW = 15 kHz nominal
Startup times and reference frequency spurs as specified.
3.2.5. Voltage Controlled Oscillator
The integrated VCO requires only two external tank circuit inductors. As the input is differential, two components of
the same value should be used. The performance of these inductors is key to both the phase noise and the power
consumption of the PLL. Thus, a pair of high Q factor inductances mounted orthogonally to other inductors (in
particular the PA choke) is advised to reduce spurious coupling between the PA and VCO. Furthermore such
measures may reduce radiated pulling effects and undesirable transient behavior, thus minimizing spectral
occupancy. Note that ensuring a symmetrical layout of the VCO inductors will further improve PLL spectral purity.
For best performance wound type inductors, with tight tolerance, should be used as described in the reference
design section.
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ADVANCED COMMUNICATIONS & SENSING
3.2.5.1. SW Settings of the VCO
To guarantee the best operation of the VCO over the SX1211’s frequency and temperature ranges, the following
settings should be programmed into the SX1211:
Target channel
(MHz)
Freq_band
863870
10
902915
00
915928
01
950960
10
Table 11: MCParam_Freq_band Setting
3.2.5.2. Trimming the VCO Tank by Hardware and Software
To ensure that the whole band may be accurately addressed by the R, P and S dividers of the synthesizer, it is
necessary to ensure that the VCO is correctly centered. Note that for the reference design (see section 7) no
centering is necessary. However, any deviation from the reference design may require the optimization procedure,
outlined below, to be performed. This procedure is simplified thanks to the built in VCO trimming feature which is
controlled over the SPI interface. Moreover, this tuning does not require any RF test equipment, simply by
measuring the voltage between pins 6 (LFM) and 7 (LFP) - herein referred to as Vtune - the VCO is in tune if the
voltage is within the range:
100 ≤ Vtune( mV ) ≤ 200
Note that this measurement should be conducted when in transmit mode at the center frequency of the desired
band (for example 869 MHz in the 868-870 MHz band), with the appropriate MCParam_Freq_band setting.
If this inequality is not satisfied then, starting from 00, iteratively adjust the MCParam_VCO_trim bits whilst
monitoring Vtune. This allows the VCO voltage to be trimmed in 60 mV increments. Should the desired voltage
range be inaccessible, the voltage may be adjusted further by changing the tank circuit inductance value,
remembering that an increase in inductance will increase Vtune.
Note for mass production: The VCO capacitance is piece to piece dependant. As such, the optimization proposed
above should be verified on several prototypes, to ensure that the population is centered on 150 mV.
3.2.6. PLL Loop Filter
To adequately reject spurious components arising from the comparison frequency Fcomp, an external 2
loop filter is employed.
nd
order
RL1
LF_M
CL2
CL1
LF_P
Figure 6: Loop Filter
Following the recommendations made in section 3.2.4, the loop filter proposed in the reference design’s bill of
material on section 7.3 should be used. The loop filter settings are frequency band independent and are hence
relevant to all implementations of the SX1211.
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ADVANCED COMMUNICATIONS & SENSING
3.2.7. PLL Lock Detection Indicator
The SX1211 also features a PLL lock detect indicator. This is useful for optimizing power consumption, by adjusting
the synthesizer wake up time (TS_FS), since the PLL startup time is lower than specified under nominal conditions.
The lock status can be read on bit IRQParam_PLL_lock, and must be cleared by writing a “1” to this same register.
In addition, the lock status can be reflected in pin 23 PLL_LOCK, by setting the bit IRQParam_Enable_lock_detect.
3.2.8. Frequency Calculation
As shown in
Figure 4, the PLL structure comprises three different dividers, R, P and S, which set the output frequency through
the LO. A second set of dividers is also available to allow rapid switching between a pair of frequencies: R1/P1/S1
and R2/P2/S2. These six dividers are programmed by six bytes of the register MCParam from addresses 6 to 11.
3.2.8.1. FSK Mode
The following formula gives the relationship between the local oscillator, and R, P and S values, when using FSK
modulation.
9
Flo
8
9 Fxtal
[75(P + 1) + S )]
Frf , fsk =
8 R +1
Frf , fsk =
3.2.8.2. OOK Mode
Due to the manner in which the baseband OOK symbols are generated, the signal is always offset by the FSK
frequency deviation (Fdev - as programmed in MCParam_Freq_dev). Hence, the center of the transmitted OOK
signal is:
9
Flo − Fdev
8
9 Fxtal
[75(P + 1) + S )] − Fdev
Frf , ook , tx =
8 R +1
Frf , ook , tx =
Consequently, in receive mode, the local oscillator frequency also needs to be offset, due to the SX1211 Low
Intermediate Frequency (Low-IF) architecture. To ensure that this low IF (denote IF2) is at the baseband receiver
center frequency of 100 kHz, as suggested in section 3.4.4, the user must ensure:
9
Flo − IF 2
8
9 Fxtal
Frf , ook , tx =
[75(P + 1) + S )] − IF 2
8 R +1
Frf , ook , rx =
3.2.9. Software for Frequency Calculation
The R1, P1 and S1, and R2, P2, S2 dividers, are configured over the SPI interface and programmed by 8 bits each,
at addresses 6 to 11. The frequency pairs may hence be switched in a single SPI cycle
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ADVANCED COMMUNICATIONS & SENSING
3.2.9.1. GUI Software
To aid the user with calculating appropriate R, P and S values, software is available to perform the frequency
calculation. Please refer to its user guide for assistance on its use.
3.2.9.2. SW .dll for Automatic Production Bench
The Dynamically Linked Library (DLL) used by the software to perform these calculations is also provided, free of
charge, to users, for inclusion in automatic production testing. Key benefits of this are:
No hand trimming of the reference frequency required: the actual reference frequency of the Device Under Test
(DUT) can be easily measured (e.g. from the CLKOUT output of the SX1211) and the tool will calculate the
best frequencies to compensate for the crystal initial error.
Channel plans can be calculated and stored in the application’s memory, then adapted to the actual crystal
oscillation frequency.
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SX1211
ADVANCED COMMUNICATIONS & SENSING
3.3. Transmitter Description
The SX1211 is set to transmit mode when MCParam_Chip_mode = 100.
Amplification
Second
up-conversion
Interpolation
filters
First up-conversion
DACs
DDS
Data
I
Waveform
generator
LO2 Tx
Q
Clock
I
RFIO
LO1 Tx
PA
Q
I
LO2 Tx
Q
Baseband
IF
RF
Figure 7: Transmitter Architecture
3.3.1. Architecture Description
The baseband I and Q signals are digitally generated by a DDS whose digital to analog converters (DAC) followed
by two anti-aliasing low-pass filters transform the digital signal into analog in-phase (I) and quadrature (Q)
components whose frequency is the selected frequency deviation (Fdev).
1
Fdev
I(t)
Q(t)
Figure 8: I(t), Q(t) Overview
In FSK mode, the relative phase of I and Q is switched by the input data between -90° and +90° with co ntinuous
phase. The modulation is therefore performed at this initial stage, since the information contained in the phase
difference will be converted into a frequency shift when the I and Q signals are up-converted in the first mixer
stage. This first up-conversion stage is duplicated to enhance image rejection. The FSK convention is such that:
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ADVANCED COMMUNICATIONS & SENSING
DATA =' '1' ' ⇒ Frf + Fdev
DATA =' '0' ' ⇒ Frf − Fdev
In OOK mode, the phase difference between the I and Q channels is kept constant (independent of the transmitted
data). Thus, the first stage of up-conversion creates a fixed frequency signal at the low IF = Fdev (This explains
why the transmitted OOK spectrum is offset by Fdev). OOK Modulation is accomplished by switching on and off the
PA and PA regulator stages. By convention:
DATA =' '1' ' ⇒ PAon
DATA =' '0' ' ⇒ PAoff
After the interpolation filters, a set of four mixers combines the I and Q signals and converts them into a pair of
complex signals at the second intermediate frequency, equal to 1/8 of the LO frequency, or 1/9 of the RF
frequency. These two new I and Q signals are then combined and up-converted to the final RF frequency by two
quadrature mixers fed by the LO signal. The signal is pre-amplified, then the transmitter output is driven by a final
power amplifier stage.
3.3.2. Bit Rate Setting
In Continuous transmit mode, setting the Bit Rate is useful to determine the frequency of DCLK. As explained in
section 4.3.2, DCLK will trigger an interrupt on the uC each time a new bit has to be radiated.
BR =
FXTAL
64 * [1 + val ( MCParam _ BR)]
3.3.3. Fdev Setting in FSK Mode
The frequency deviation, Fdev, of the FSK transmitter is programmed through bits MCParam_Freq_dev:
Fdev =
FXTAL
32 * [1 + val ( MCParam _ Freq _ dev)]
For correct operation the modulation index ß should be such that:
β = 2*
Fdev
≥2
BR
Furthermore, assuming communication between a pair of SX1211s, then Fdev > 33 kHz - to ensure a correct
sensitivity at receiver side. If the SX1211 is transmitting to any other FM receiver, there is no restriction on Fdev.
3.3.4. Fdev Setting in OOK Mode
Fdev has no physical meaning in OOK transmit mode. However, as has been shown - due to the DDS baseband
signal generation, the OOK tone is always offset by “-Fdev” (see formulas is section 3.2.8). It is hence suggested
that Fdev retains its default value of 100 kHz in OOK mode.
3.3.5. Suggested Interpolation Filter Setting
After digital to analog conversion, both I and Q signals are smoothed by interpolation filters. This block low-pass
filters the digitally generated signal, and prevents the alias signals from entering the modulators. Its bandwidth can
be programmed with the register RXParam_InterpFiltTx, and should be set to:
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ADVANCED COMMUNICATIONS & SENSING
BR 

BW ≅ 3 *  Fdev +
2 

Where Fdev is the programmed frequency deviation as set in MCParam_Freq_dev, and BR is the physical Bit Rate
of transmission.
Note: low interpolation filter bandwidth will attenuate the baseband I/Q signals thus reducing the power of the FSK
signal. Conversely, excessive bandwidth will degrade spectral purity.
3.3.6. Power Amplifier
The Power Amplifier (PA) integrated in the SX1211 operates under a regulated voltage supply of 1.8 V. The
external PA choke inductor is biased by an internal regulator output made available on pin 29 (VR_PA). Thanks to
these features, the PA output power is consistent over the power supply range. This is important for mobile
applications where this allows both predictable RF performance and battery life.
3.3.6.1. Rise and Fall Times Control
As the SX1211 is also an OOK device, the PA ramp times can be accurately controlled through the
TParam_PA_ramp bits. Those bits directly control the slew rate of VR_PA output (pin 29).
Table 12: PA Rise/Fall Times
MCParam_PA_ramp
00
01
10
11
tVR_PA
3 us
8.5 us
15 us
23 us
tPA_OUT (rise / fall)
2.5 / 2 us
5 / 3 us
10 / 6 us
20 / 10 us
DATA
VR_PA
[V]
95 %
95 %
tVR_PA
PA Output
power
tVR_PA
60 dB
60 dB
tPA_OUT
tPA_OUT
Figure 9: PA Control
3.3.6.2. Optimum Load Impedance
As the PA and the LNA front-ends in the SX1211 share the same Input/Output pin, they are internally matched to
impedances close to 50 Ω.
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ADVANCED COMMUNICATIONS & SENSING
Pmax-1dB circle
Max Power
Zopt = 30+j25 Ω
Figure 10: Optimal Load Impedance Chart
Please refer to the reference design section for an optimized PA load setting.
3.3.6.3. Suggested PA Biasing and Matching
The matching proposed is the following one:
VR_PA
47nF
100nH
Antenna
port
SAW
PA
RFIO
DC block
Low-pass and DC block
Figure 11: Suggested PA Biasing and Output Matching
Please refer to section 7 of this document for the optimized matching arrangement for frequency band.
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ADVANCED COMMUNICATIONS & SENSING
3.3.7. Transmitter Spectral Purity
Figure 12: 869 MHz Spectral Purity DC-1GHz
Figure 13: 869 MHz Spectral Purity 1-6GHz
3.3.8. Common Input and Output Front-End
The receiver and the transmitter share the same RFIO pin (pin 31). Figure 14 below shows the configuration of the
common RF front-end.
In transmit mode, the PA and the PA regulator are active, with the voltage on the VR_PA pin equal to the nominal
voltage of the regulator (1.8 V). The external inductance is used to bias the PA.
In receive mode, both PA and PA regulator are off and VR_PA is tied to ground. The external inductance LT1 is
then used to bias the LNA.
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VR_PA
Reg_PA
Rx_on
PA
To
Antenna
RFIO
LNA
Figure 14: Front-end Description
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ADVANCED COMMUNICATIONS & SENSING
3.4. Receiver Description
The SX1211 is set to receive mode when MCParam_Chip_mode = 011.
Second downconversion
First downconversion
RSSI
OOK
demod
Control logic
-Pattern recognition
-FIFO handler
-SPI interface
-Packet handler
Bit
synchronizer
FSK
demod
LO2 Rx
LNA
LO1 Rx
Baseband, IF2 in OOK
IF1
RF
Figure 15: Receiver Architecture
3.4.1. Architecture
th
The SX1211 receiver employs a super-heterodyne architecture. Here, the first IF is 1/9 of the RF frequency
(approximately 100MHz). The second down-conversion mixes the I and Q signals to base band in the case of the
FSK receiver (Zero IF) and to a low-IF (IF2) for the OOK receiver.
Second
down-conversion
LO2
Rx
First
down-conversion
0
IF1
≈100MHz
IF2=0
in FSK
mode
Image
frequency
LO1 Rx
Channel
Image
frequency
LO1 Rx
Channel
Frequencyl
Figure 16: FSK Receiver Setting
First
down-conversion
Second
down-conversion
0
IF2<0
in FSK
mode
equal to fo
IF1
≈100MHz
LO2 Rx
Frequency
Figure 17: OOK Receiver Setting
After the second down-conversion stage, the received signal is channel-select filtered and amplified to a level
adequate for demodulation. Both FSK and OOK demodulation are available. Finally, an optional Bit Synchronizer
(BitSync) is provided, to be supply a synchronous clock and data stream to a companion uC in Continuous mode,
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ADVANCED COMMUNICATIONS & SENSING
or to fill the FIFO buffers with glitch-free data in Buffered mode. The operation of the receiver is now described in
detail.
Note: Receiver image rejection is achieved by the SAW filter.
3.4.2. LNA and First Mixer
In receive mode, the RFIO pin is connected to a fixed gain, common-gate, Low Noise Amplifier (LNA). The
performance of this amplifier is such that the Noise Figure (NF) of the receiver can be estimated to be ≈7 dB.
3.4.3. IF Gain and Second I/Q Mixer
Following the LNA and first down-conversion, there is an IF amplifier whose gain can be programmed from 13.5 dB to 0 dB in 4.5 dB steps, via the register MCParam_IF_gain. The default setting corresponds to 0 dB gain,
but lower values can be used to increase the RSSI dynamic range. Refer to section 3.4.7 for additional information.
3.4.4. Channel Filters
The second mixer stages are followed by the channel select filters. The channel select filters have a strong
influence on the noise bandwidth and selectivity of the receiver and hence its sensitivity. Each filter comprises a
passive and active section.
3.4.4.1. Passive Filter
Each channel select filter features a passive second-order RC filter, with a bandwidth programmable through the
bits RXParam_PassiveFilt. As the wider of the two filters, its effect on the sensitivity is negligible, but its bandwidth
has to be setup instead to optimize blocking immunity. The value entered into this register sets the single side
bandwidth of this filter. For best performance it must be set to 3 to 4 times the cutoff frequency of the active
Butterworth (or polyphase) filter described in the next section.
3 * Fc ButterfFilt ≤ BW passive, filter ≤ 4 * Fc ButterFilt
3.4.4.2. Active Filter
The ’fine’ channel selection is performed by an active, third-order, Butterworth filter, which acts as a low-pass filter
for the zero-IF configuration (FSK), or a complex poly-phase filter for the Low-IF (OOK) configuration. The
RXParam_PolypFilt_on bit enables/disables the polyphase filter.
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Low-pass filter for FSK ( RXParam_PolyFilt_on=’’0’’)
-fC
frequency
fC
0
Polyphase filter for OOK ( RXParam_PolyFilt_on=’’1’’ )
Canceled side of
polyphase filter
-fC
-fo
frequency
0
Figure 18: Active Channel Filter Description
As can be seen from Figure 18, the required bandwidth of this filter varies between the two demodulation modes.
FSK mode: The 99% energy bandwidth of an FSK modulated signal is approximated to be:
BR 

BW99%, FSK = 2 *  Fdev +
2 

The bits RXParam_ButterFilt set fc, the cutoff frequency of the filter. As we are in a Zero-IF configuration, the FSK
lobes are centered around the virtual “DC” frequency. The choice of fc should be such that the modulated signal
falls in the filter bandwidth, anticipating the Local Oscillator drift over the operating temperature and lifespan of the
device:
2 * fc > BW99%,FSK + LOdrifts
Please refer to the charts in section 3.4.5 for an accurate overview of the filter bandwidth vs. setting.
OOK mode: The bits RXParam_PolypFilt_center set fo, the center frequency of the polyphase filter when
activated. fo should always be chosen to be equal to the low Intermediate Frequency of the receiver. This is
why, in the GUI described in section 3.2.9.1 of this document, the low IF frequency of the OOK receiver
denoted IF2 has been replaced by fo. The following setting is recommended:
fo = 100kHz
RXParam _ PolypFilt ="0011"
Then, the 99% energy bandwidth of an OOK modulated signal is approached by:
BW99%,OOK =
2
= 2.BR
Tbit
The value stored in RXParam_ButterFilt determines fc, the filter cut-off frequency. So the user should set fc
according to:
2 * ( fc − fo ) > BW 99 %,OOK + LO drifts
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ADVANCED COMMUNICATIONS & SENSING
Again, fc as a function of RXParam_ButterFilt is given in the section 3.4.6.
N.B. In the specific case where the frequency of the companion transmitter is not well controlled (i.e. it can drift by
more than +/-100kHz), the user can artificially set the fo to a higher value (such as 150kHz), and increase the filter
bandwidth. This, of course, leads to a concomitant decrease in sensitivity.
3.4.5. Channel Filters Setting in FSK Mode
Fc, the 3dB cutoff frequency of the Butterworth filter used in FSK reception, is programmed through the bit
RXParam_ButterFilt. However, the whole receiver chain influences this cutoff frequency. Thus the channel select
and resultant filter bandwidths are summarized in the following chart:
Theoretical
BW (kHz)
Actual
BW (kHz)
450
400
350
fc (kHz)
300
250
200
150
100
50
0
0
2
4
6
8
10
12
14
16
Val(RXParam_ButterFilt)
Figure 19: Butterworth Filter's Actual BW
3.4.6. Channel Filters Setting in OOK Mode
The center frequency, fo, is always set to 100kHz. The following chart shows the receiver bandwidth when
changing RXParam_Butterfilt bits, while the polyphase filter is activated.
Theoretical BW=fc-fo
Actual
BW (kHz)
450
400
350
fc-fo (kHz)
300
250
200
150
100
50
0
0
2
4
6
8
10
Val(RXParam_ButterFilt)
RXParam_PolypFilt="0011"
12
14
16
Figure 20: Polyphase Filter's Actual BW
3.4.7. RSSI
3.4.7.1. General Description
After filtering, the I and Q signals are amplified by a chain of 11 amplifiers, each with 6 dB gain. The outputs of
these amplifiers are used to evaluate the Received Signal Strength (RSSI). A limiting amplifier is located after the I
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and Q amplifiers chains to provide the input signal to the FSK demodulator. Conversely, the OOK demodulator
derives its output from the RSSI block.
The overall accuracy of the RSSI is dependent upon both process and external components. So although the RSSI
resolution is 0.5 dB, its absolute accuracy is not expected to be better than +/-3 dB. Reliable absolute RSSI
measurement will require additional calibration.
3.4.7.2. Performance
The RSSI evaluates the signal strength by sampling I(t) and Q(t) signals 16 times in each Fdev period. An average
is then performed over a sliding window of 16 samples. Hence, the RSSI output register RXParam_RSSI is
updated 16 times in each Fdev period and outputs one correct value per Fdev. For accurate timing information on
the RSSI, please refer to Figure 49.
The dynamic range of the RSSI is over 70 dB, from the sensitivity level.
3.4.7.3. RSSI IRQ Source
The SX1211 can also be used to detect a RSSI level above a threshold. This function can be activated by bit
IRQParam_RSSI_irq, while the threshold level is selected by bits IRQParam_RSSI_thresh. This interrupt can be
mapped to the pins IRQ0 or IRQ1 by bits IRQParam_Rx_stby_irq0 or IRQParan_Rx_stby_irq1. The IRQ is
eventually cleared by writing a “1” to IRQ_Param_RSSI_irq.
The following figure shows the timing diagram of RSSI in interrupt mode.
IRQParam_RSSI_int
RXParam_RSSI(7:0)
24 26 27 30 25 20 20 20 18 22 33 20 22 34 33
IRQParam_RSSI_signal_detect
Clear interrupt
RSSI_irq
Figure 21: RSSI IRQ Timings
3.4.8. Fdev Setting in Receive Mode
The effect of the Fdev setting is different between FSK and OOK modes:
3.4.8.1. FSK Rx Mode
In FSK mode the Fdev setting has no impact on the circuit architecture. The user should leave it set to the default
value.
3.4.8.2. OOK Rx Mode
The frequency deviation Fdev, as described above, sets the sampling rate of the RSSI block. It is therefore
necessary to set Fdev to the recommended IF2 frequency of 100 kHz:
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Fdev = IF 2 = 100 kHz
MCParam _ Freq _ dev ="00000011"
3.4.9. FSK Demodulator
The FSK demodulator provides data polarity information, based on the relative phase of the input I and Q signals at
baseband. Its outputs can be fed to the Bit Synchronizer to recover the timing information. The user can also use
the raw, unsynchronized, output of the FSK demodulator in Continuous mode.
The FSK demodulator of the SX1211 operates most effectively for FSK signals with a modulation index greater
than or equal to two:
β=
2 * Fdev
≥2
BR
3.4.10. OOK Demodulator
The OOK demodulator performs a comparison of the RSSI output and a threshold. Three different threshold modes
are available, programmed through bits RXParam_OOK_thresh_type.
The recommended “Peak” threshold mode is described on Figure 22:
RSSI
(dB)
‘’Peak -6dB’’ Threshold
‘’Floor’’ threshold as in
MCParam_OOK_floor_thresh
Noise floor of
receiver
Time
Zoom
Decay in dB as defined in
RXPAram_OOK_thresh_step
Fixed 6dB difference
Period as defined in
RXParam_OOK_thresh_dec_period
Figure 22: OOK Demodulator Description
In peak threshold mode the comparison threshold used is the peak value of the RSSI, lowered by 6dB. In the
absence of an input signal or, equivalently, during the reception of a logical “0”, the acquired peak value is
decremented by one RXPAram_OOK_thresh_step every RXParam_OOK_thresh_dec_period.
When the RSSI output is null for a long time (for instance after a long string of “0” received, or if no transmitter is
present), the peak threshold level will continue falling until it reaches the “Floor Threshold” that is programmed
through the register MCParam_OOK_floor_thresh.
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The default settings of the OOK demodulator lead to the performance stated in the electrical specification.
However, in applications in which sudden signal drops are awaited during a reception, the three parameters shall
be optimized accordingly.
3.4.10.1. Optimizing the Floor Threshold
This threshold determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input
signals (i.e. close to the noise floor). Significant sensitivity improvements can be generated if configured correctly.
The noise floor of the receiver depends on:
The noise figure of the receiver.
The gain of the receive chain from antenna to base band.
The matching - including SAW filter.
The bandwidth of the channel filters.
It is therefore important to note that the setting of MCParam_OOK_Floor_thresh will be application dependant. The
following procedure is proposed to optimise MCParam_OOK_Floor_thresh.
Set SX1211 in OOK Rx mode
Adjust Bit Rate, Channel filters’ BW
Default RXParam_OOK_thresh setting
No input signal
Continuous Mode
Monitor DATA pin (pin 20)
MCParam_OOK_thres
Increment (x  x+1)
Glitch activity
on DATA ?
Optimization complete
Figure 23: Floor Threshold Optimization
The new floor threshold value found during this test should be the value used for OOK reception with those receiver
settings.
3.4.10.2. Optimizing OOK Demodulator Response for Fast Dropping Signals
As shown in Figure 22, a sudden drop in signal strength will cause the bit error rate to rise. For applications where
the expected signal drop can be estimated the OOK demodulator parameters: RXParam_OOK_thresh_step and
RXParam_OOK_thresh_dec_period can be tuned as shown below for a given number of drops per bit
RXParam_OOK_thresh_dec_period given by
000 once in each chip period (d)
001 once in 2 chip periods
010 once in 4 chip periods
011 once in 8 chip periods
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100 twice in each chip period
101 4 times in each chip period
110 8 times in each chip period
111 16 times in each chip period
With each drop of size RXParam_OOK_thresh_step given by:
000 0.5 dB (d)
001 1.0 dB
010 1.5 dB
011 2.0 dB
100 3.0 dB
101 4.0 dB
110 5.0 dB
111 6.0 dB
3.4.10.3. Alternative Threshold Types
In addition to the “Peak” type of threshold, the user can alternatively select two other types of threshold:
Fixed threshold: its value is selected through bits MCParam_OOK_floor_thresh.
Average threshold: the data supplied by the RSSI block is averaged with the following cutoff frequency:
RXParam _ OOK _ cutoff = 00 ⇒ Fcutoff =
BR
8 *π
In this case, the cutoff frequency is higher, and a sequence of up to 8 consecutive “0s” or “1s” can be supported.
RXParam _ OOK _ cutoff = 11 ⇒ Fcutoff =
BR
32 * π
With the second setting, the cutoff frequency is four times smaller, allowing the reception up to 32 consecutive “1”s
or “0”s.
3.4.11. Bit Synchronizer
The Bit Synchronizer (BitSync) is a block that provides a clean and synchronized digital output, free of glitches.
Rough
demodulator
output
(FSK or OOK)
DATA
BitSync
Output
To pin DATA and
DCLK in
continuous mode
DCLK
IRQ1
Figure 24: BitSync Description
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The BitSync can be disabled through the bits RXParam_Bitsync_off, and by holding pin IRQ1 low. However, for
optimum receiver performance, its use when running Continuous mode is strongly advised. With this option a
DCLK signal is present on pin IRQ_1.
BitSync is automatically activated in Buffered and Packet modes. The bit synchronizer bit-rate is controlled by
MCParam_BR. For a given bit rate, this parameter is determined by:
BR =
FXTAL
64 * [1 + MCParam _ BR ]
For proper operation, the Bit Synchronizer must first receive three bytes of alternating logic value preamble, i.e.
“0101” sequences. After this startup phase, the rising edge of DCLK signal is centered on the demodulated bit.
Subsequent data transitions will preserve this centering.
This has two implications:
Firstly, if the Bit Rates of Transmitter and Receiver are known to be the same, the SX1211 will be able to
receive an infinite unbalanced sequence (all “0s” or all ”1s”) with no restriction.
If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the
BitSync can withstand can be estimated as:
NumberOfBits =
1 BR
*
2 ∆BR
This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily
achievable (crystal tolerance is in the range of 50 to 100 ppm).
3.4.12. Data Output
After OOK or FSK demodulation, the baseband signal is made available to the user on pin 20, DATA, when
Continuous mode is selected.
In Buffered and Packet modes, the data can of course be retrieved from the FIFO through the SPI interface.
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4. Data Processing
4.1. Overview
4.1.1. Block Diagram
As illustrated below, the SX1211’s data processing is built around several blocks which are described in the
following paragraphs.
Its role is to interface the data to/from the modulator/demodulator and the uC access points (SPI, IRQ and DATA
pins). It also controls all the configuration registers.
SX1211
Tx/Rx
DATA
IRQ_0
CONTROL
IRQ_1
Data
Rx
SPI
SYNC
RECOG.
CONFIG
PACKET
HANDLER
FIFO
(+SR)
Tx
DATA
NSS_DATA
SCK
MOSI
MISO
Figure 25: SX1211’s Data Processing Conceptual View
As explained below, the SX1211 implements several data operation modes, each with their own data path through
the data processing section. Depending on which data operation mode is selected, some blocks are active while
others remain inactive.
4.1.2. Data Operation Modes
The SX1211 has three different data operation modes selectable by the user:
Continuous mode: each bit transmitted or received is accessed in real time at the DATA pin. This mode may be
used if adequate external signal processing is available.
Buffered mode: each byte transmitted or received is stored in a FIFO and accessed via the SPI bus. uC
processing overhead is hence significantly reduced compared to Continuous mode operation. The packet
length is unlimited.
Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is
automatically built with preamble, Sync word, and optional CRC, DC free encoding and the reverse operation is
performed in reception. The uC processing overhead is hence reduced further compared to Buffered mode.
The payload length is limited to 64 bytes (maximum FIFO size).
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Table 13: Data Operation Mode Selection
MCParam_Data_mode
00
01
1x
Data Operation Mode
Continuous
Buffered
Packet
Each of these data operation modes is described fully in the following sections.
4.2. Building Blocks Description
4.2.1. SPI Interface
4.2.1.1. Overview
As illustrated in the figure below, the SX1211’s SPI interface is actually made of two sub blocks:
SPI Config: used in all data operation modes to read and write the configuration registers which control all the
parameters of the chip (operating mode, bit rate, etc...)
SPI Data: used in Buffered and Packet mode to write and read data bytes to and from the FIFO. (FIFO
interrupts can be used to manage the FIFO content.)
SX1211
Config.
Registers
SPI
CONFIG
(slave)
NSS_CONFIG
MOSI
MISO
SCK
NSS_CONFIG
MOSI
MISO
SCK
NSS_DATA
µC
FIFO
SPI
DATA
(slave)
(master)
NSS_DATA
Figure 26: SPI Interface Overview and uC Connections
Both interfaces are configured in slave mode while the uC is the master. They have separate selection pins
(NSS_CONFIG and NSS_DATA) but share the remaining pins:
SCK (SPI Clock): clock signal provided by the uC
MOSI (Master Out Slave In): data input signal provided by the uC
MISO (Master In Slave Out): data output signal provided by the SX1211
As described below, only one interface can be selected at a time (NSS_CONFIG has the priority):
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Table 14: Config vs. Data SPI Interface Selection
NSS_DATA
0
0
1
1
NSS_CONFIG
0
1
0
1
SPI Interface
Config
Data
Config
None
Following paragraphs describe how to use each of these interfaces.
4.2.1.2. SPI Config
Write Register
To write a value into a configuration register the timing diagram below should be carefully followed by the uC.
The register’s new value is effective from the rising edge of NSS_CONFIG.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NSS_CONFIG (In)
SCK (In)
New value at
address A1
MOSI (In)
start
rw
A(4) A(3) A(2) A(1) A(0) stop D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Current value at
address A1*
Address = A1
MISO (Out)
HZ
x
x
x
x
x
x
x
x
D(7) D(6) D(5) D(4) D(3) D(2) D(1)
D(0)
HZ
* when writing the new value at address A1, the current content of A1 can be read by the uC.
(In)/(Out) refers to SX1211 side
Figure 27: Write Register Sequence
Note that when writing more than one register successively, it is not compulsory to toggle NSS_CONFIG back high
between two write sequences. The bytes are alternatively considered as address and value. In this instance, all
new values will become effective on rising edge of NSS_CONFIG.
Read Register
To read the value of a configuration register the timing diagram below should be carefully followed by the uC.
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1
2
start
rw
3
4
5
6
7
8
9
10
11
12
13
14
15
16
x
x
x
x
x
x
x
x
NSS_CONFIG (In)
SCK (In)
MOSI (In)
A(4) A(3) A(2) A(1) A(0) stop
Current value at
address A1
Address = A1
MISO (Out)
HZ
x
x
x
x
x
x
x
D(7) D(6) D(5) D(4) D(3) D(2) D(1)
x
HZ
D(0)
Figure 28: Read Register Sequence
Note that when reading more than one register successively, it is not compulsory to toggle NSS_CONFIG back
high between two read sequences. The bytes are alternatively considered as address and value.
4.2.1.3. SPI Data
Write Byte (before/during Tx)
To write bytes into the FIFO the timing diagram below should be carefully followed by the uC.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
NSS_DATA (In)
SCK (In)
st
nd
1 byte written
MOSI (In)
MISO (Out) HZ
D1(7) D1(6)
x
x
D1(5)
x
D1(4) D1(3)
x
x
x
2
D1(2)
x
D1(1)
x
D1(0)
x
D2(7)
HZ
x
D2(6)
x
D2(5)
x
byte written
D2(4)
D2(3) D2(2)
x
x
x
D2(1)
x
D2(0)
x
x
HZ
Figure 29: Write Bytes Sequence (ex: 2 bytes)
Note that it is compulsory to toggle NSS_DATA back high between each byte written.
The byte is pushed into the FIFO on the rising edge of NSS_DATA
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Read Byte (after/during Rx)
To read bytes from the FIFO the timing diagram below should be carefully followed by the uC.
1
2
3
4
5
6
7
8
x
x
x
x
x
1
2
3
x
x
x
4
5
6
7
8
x
x
x
x
NSS_DATA (In)
SCK (In)
x
MOSI (In)
x
x
x
2nd byte read
st
1 byte read
MISO (Out) HZ
D1(7)
D1(6) D1(5)
D1(4) D1(3)
x
D1(2) D1(1) D1(0)
HZ
D2(7) D2(6)
D2(5)
D2(4)
D2(3)
D2(2)
D2(1)
D2(0)
HZ
Figure 30: Read Bytes Sequence (ex: 2 bytes)
Note that it is compulsory to toggle NSS_DATA back high between each byte read.
4.2.2. FIFO
4.2.2.1. Overview and Shift Register (SR)
The SX1211 contains a FIFO (First In First Out) which is used in Buffered and Packet mode, to store both data to
be transmitted and that has been received. It is accessed via the SPI Data interface and provides several interrupts
for transfer management.
The FIFO is 1 byte (8 bits) wide hence it only performs byte (parallel) operations, whereas the demodulator
functions serially. A shift register is therefore employed to interface the two devices. In transmit mode it takes bytes
from the FIFO and outputs them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the
shift register gets bit by bit data from the demodulator and writes them byte by byte to the FIFO. This is illustrated in
figure below.
FIFO
byte1
byte0
8
Data Tx/Rx
SR (8bits)
1
MSB
LSB
Figure 31: FIFO and Shift Register (SR)
4.2.2.2. Size Selection
The FIFO width is programmable, to 16, 32, 48 or 64 bytes via MCParam_Fifo_size
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4.2.2.3. Interrupt Sources and Flags
Except for Fifo_threshold, all interrupt sources and flags are configured in the IRQParam section of the
configuration register.
/Fifoempty: /Fifoempty interrupt source is low when byte0, i.e. whole FIFO, is empty. Otherwise it is high.
Write_byte: Write_byte interrupt source goes high for 1 bit period each time a new byte is transferred from the
SR to the FIFO (i.e. each time a new byte is received)
Fifofull: Fifofull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
Fifo_overrun_clr: Fifo_overrun_clr flag is set when a new byte is written by the user (in Tx or Standby modes)
or the SR (in Rx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1,
note that the FIFO will also be cleared.
Tx_done: Tx_done interrupt source goes high when FIFO is empty and the SR’s last bit has been send to the
modulator (i.e. the last bit of the packet has been sent).
One bit period must be waited after the rising edge of Tx_done for effective RF transmission of last bit.
Practically this may not require special care in the uC software due to IRQ processing time.
Fifo_threshold: Fifo_threshold interrupt source’s behavior depends on the running mode (Tx, Rx or Stby mode)
and the threshold itself can be programmed via MCParam_Fifo_thresh (B value).
Full behavior is described in Figure 32.
IRQ source
1
0
B
B+1 B+2
# of bytes in FIFO
Tx
Rx & Stby
Figure 32: FIFO Threshold IRQ Source Behavior
4.2.2.4. FIFO Clearing
Table 15 below summarizes the status of the FIFO when switching between different modes
Table 15: Status of FIFO when Switching Between Different Modes of the Chip
From
To
Stby
Tx
Stby
Rx
Rx
Tx
Tx
Any
Rx
Tx
Stby
Rx
Stby
Sleep
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FIFO Status
Cleared
Not cleared
Cleared
Cleared
Not cleared
Cleared
Not cleared
Cleared
Comments
In Buffered mode, FIFO cannot be written in Stby before Tx
In Packet mode, FIFO can be written in Stby before Tx
In Packet & Buffered modes FIFO can be read in Stby after Rx
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4.2.3. Sync Word Recognition
4.2.3.1. Overview
Sync word recognition (also called Pattern recognition in previous products) is activated by setting
RXParam_Sync_on. The bit synchronizer must also be activated.
The block behaves like a shift register; it continuously compares the incoming data with its internally programmed
Sync word and asserts the Sync IRQ source when a match is detected. This is illustrated in Figure 33.
Rx DATA
Bit N-x =
(NRZ)
Sync_value[x]
Bit N-1 =
Bit N =
Sync_value[1] Sync_value[0]
DCLK
SYNC
Figure 33: Sync Word Recognition
During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of byte at
address 22 and the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by
the length of the Sync word.
When the programmed Sync word is detected the user can assume that this incoming packet is for him and can be
processed accordingly.
4.2.3.2. Configuration
Size: Sync word size can be set to 8, 16, 24 or 32 bits via RXParam_Sync_size. In Packet mode this field is
also used for Sync word generation in Tx mode.
Error tolerance: The number of errors tolerated in the Sync word recognition can be set to 0, 1, 2 or 3 via
RXParam_Sync_tol.
Value: The Sync word value is configured in SYNCParam_Sync_value. In Packet mode this field is also used
for Sync word generation in Tx mode.
4.2.4. Packet Handler
The packet handler is the block used in Packet mode. Its functionality is fully described in section 4.5.
4.2.5. Control
The control block configures and controls the full chip’s behavior according to the settings programmed in the
configuration registers.
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4.3. Continuous Mode
4.3.1. General Description
As illustrated in Figure 34, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by
the uC on the bidirectional DATA pin (20). The SPI Data, FIFO and packet handler are thus inactive.
SX1211
Tx/Rx
DATA
IRQ_0
IRQ_1(DCLK)
CONTROL
Data
Rx
SPI
SYNC
RECOG.
NSS_CONFIG
CONFIG
SCK
MOSI
MISO
Datapath
Figure 34: Continuous Mode Conceptual View
4.3.2. Tx Processing
In Tx mode, a synchronous data clock for an external uC is provided on IRQ_1 pin. Its timing with respect to the
data is illustrated in Figure 35. DATA is internally sampled on the rising edge of DCLK so the uC can change logic
state anytime outside the greyed out setup/hold zone.
The use of DCLK is compulsory in FSK and optional in OOK.
T_DATA
T_DATA
DATA (NRZ)
DCLK
Figure 35: Tx Processing in Continuous Mode
4.3.3. Rx Processing
If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK
signal is provided.
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Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively
on DATA and IRQ_1 pins. DATA is updated by SX1211 on DCLK’s falling edge as illustrated in Figure 36.
DATA (NRZ)
DCLK
Figure 36: Rx Processing in Continuous Mode
Note that in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal
even if the DCLK signal is not used by the uC. (bit synchronizer is automatically enabled in Buffered and Packet
mode).
4.3.4. Interrupt Signals Mapping
The tables below give the description of the interrupts available in Continuous mode.
IRQ_0
Rx_stby_irq_0
00 (d)
01
Rx
Sync
RSSI
1x
DCLK
IRQ_1
Table 16: Interrupt Mapping in Continuous Rx Mode
Note: In Continuous mode, no interrupt is available in Stby mode
IRQ_0
Tx
-
IRQ_1
DCLK
Table 17: Interrupt Mapping in Continuous Tx Mode
4.3.5. uC Connections
SX1211
DATA
IRQ_0
IRQ_1 (DCLK)
NSS_CONFIG
uC
SCK
MOSI
MISO
Figure 37: uC Connections in Continuous Mode
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Note that some connections may not be needed depending on the application:
IRQ_0: if Sync and RSSI interrupts are not used
IRQ_1: if the chip is never used in Tx mode (DCLK connection is not compulsory in Rx).
MISO: if no read register access is needed.
Please refer to Table 26 for SX1211’s pins configuration
4.3.6. Example of Usage
On both sides:
Configure all data processing related registers listed below appropriately. In this example we assume that both
Bit synchronizer and Sync word recognition are on.
Table 18: Relevant Configuration Registers in Continuous Mode (data processing related only)
MCParam
IRQParam
RXParam
SYNCParam
Data_mode_x
Rx_stby_irq_0
Sync_on
Sync_size
Sync_tol
Sync_value
Tx
X
Rx
X
X
X
X
X
X
Description
Defines data operation mode ( Continuous)
Defines IRQ_0 source in Rx mode
Enables Sync word recognition
Defines Sync word size
Defines the error tolerance on Sync word recognition
Defines Sync word value
On Tx side:
Go to Tx mode (and wait for Tx to be ready, see Figure 50)
Send all packet’s bits on DATA pin synchronously with DCLK signal provided on IRQ_1
Go to Sleep mode
On Rx side:
Program Rx interrupts: IRQ_0 mapped to Sync (Rx_stby_irq_0=”00”) and IRQ_1 mapped to DCLK (Bit
synchronizer enabled)
Go to Rx mode (note that Rx is not ready immediately, see Figure 49)
Wait for Sync interrupt
Get all packet bits on DATA pin synchronously with DCLK signal provided on IRQ_1
Go to Sleep mode
4.4. Buffered Mode
4.4.1. General Description
As illustrated in Figure 38, in Buffered mode the NRZ data to (from) the (de)modulator is not directly accessed by
the uC but stored in the FIFO and accessed via the SPI Data interface. This frees the uC for other tasks between
processing data from the SX1211, furthermore it simplifies software development and reduces uC performance
requirements (speed, reactivity). Note that in this mode the packet handler stays inactive.
An important feature is also the ability to empty the FIFO in Stby mode, ensuring low power consumption and
adding greater software flexibility.
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ADVANCED COMMUNICATIONS & SENSING
SX1211
IRQ_0
CONTROL
IRQ_1
Data
Rx
SPI
SYNC
RECOG.
NSS_CONFIG
CONFIG
FIFO
(+SR)
Tx
DATA
NSS_DATA
SCK
MOSI
MISO
Datapath
Figure 38: Buffered Mode Conceptual View
Note that Bit Synchronizer is automatically enabled in Buffered mode.
activated by the user if needed.
The Sync word recognition must be
4.4.2. Tx Processing
After entering Tx in Buffered mode, the chip expects the uC to write into the FIFO, via the SPI Data interface, all the
data bytes to be transmitted (preamble, Sync word, payload...).
Actual transmission of first byte will start either when the FIFO is not empty (i.e. first byte written by the uC) or when
the FIFO is full depending on bit IRQParam_Tx_start_irq_0.
In Buffered mode the packet length is not limited, i.e. as long as there are bytes inside the FIFO they are sent.
When the last byte is transferred to the SR, /Fifoempty IRQ source is asserted to warn the uC, at that time FIFO
can still be filled with additional bytes if needed.
When the last bit of the last byte has left the SR (i.e. 8 bit periods later), the Tx_done interrupt source is asserted
and the user can exit Tx mode after waiting at least 1 bit period from the last bit processed by modulator.
If the transmitter is switched off (for example due to entering another chip mode) during transmission it will stop
immediately, even if there is still unsent data.
Figure 39 illustrates Tx processing with a 16 byte FIFO depth and Tx_start_irq_0=0. Please note that in this
example the packet length is equal to FIFO size, but this does not need to be the case, the uC can use the FIFO
interrupts anytime during Tx to manage FIFO contents and write additional bytes.
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Start condition
(Cf. Tx_start_irq_0)
Fifofull
/Fifoempty
Tx_done
from
SPI Data
15
FIFO
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Data Tx
(from SR)
XXX
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11 b12 b13 b14 b15
XXX
Figure 39: Tx processing in Buffered Mode (FIFO size = 16, Tx_start_irq_0=0)
4.4.3. Rx Processing
After
entering
Rx
in
Buffered
mode,
the
chip
requires
the
uC
to
retrieve
the
received data from the FIFO. The FIFO will actually start being filled with received bytes either; when a Sync word
has been detected (in this case only the bytes following the Sync word are filled into the FIFO) or when the Fifo_fill
bit is asserted by the user - depending on the state of bit, IRQParam_Fifo_fill_method.
In Buffered mode, the packet length is not limited i.e. as long as Fifo_fill is set, the received bytes are shifted into
the FIFO.
The uC software must therefore mediate the transfer of the FIFO contents by interrupt and ensure reception of the
correct number of bytes. (In this mode, even if the remote transmitter has stopped, the demodulator will output
random bits from noise)
When the FIFO is full, Fifofull IRQ source is asserted to alert the uC, that at that time, the FIFO can still be unfilled
without data loss. If the FIFO is not unfilled, once the SR is also full (i.e. 8 bits periods later) Fifo_overrun_clr is
asserted and SR’s content is lost.
Figure 40 illustrates an Rx processing with a 16 bytes FIFO size and Fifo_fill_method=0. Please note that in the
illustrative example of section 4.4.6, the uC does not retrieve any byte from the FIFO through SPI Data, causing
overrun.
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ADVANCED COMMUNICATIONS & SENSING
Data Rx
(to SR) “noisy” data
Preamble
Sync
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11 b12 b13 b14 b15 b16
Start condition
(Cf. Fifo_fill_method)
/Fifoempty
Fifofull
Fifo_overrun_clr
Write_byte
15
b9
FIFO
b4
0
b0
b1
b2
b5
b6
b7
b10
b11
b12
b13
b14
b15
b8
b3
Figure 40: Rx Processing in Buffered Mode (FIFO size=16, Fifo_fill_method=0)
4.4.4. Interrupt Signals Mapping
The tables below describe the interrupts available in Buffered mode.
IRQ_0
IRQ_1
Rx_stby_irq_x
00 (d)
01
10
11
00 (d)
01
10
11
Rx
Write_byte
/Fifoempty
Sync
Fifofull
RSSI
Fifo_threshold
Stby
/Fifoempty
Fifofull
Fifo_threshold
Table 19: Interrupt Mapping in Buffered Rx and Stby Modes
Tx
/Fifoempty
IRQ_0
IRQ_1
Tx_irq_1=0 (d)
Fifofull
Tx_irq_1=1
Tx_done
Table 20: Interrupt Mapping in Buffered Tx Mode
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4.4.5. uC Connections
SX1211
IRQ_0
IRQ_1
uC
NSS_CONFIG
NSS_DATA
SCK
MOSI
MISO
Figure 41: uC Connections in Buffered Mode
Note that depending upon the application, some uC connections may not be needed:
IRQ_0: if none of the relevant IRQ sources are used.
IRQ_1: if none of the relevant IRQ sources are used.
MISO: if no read register access is needed and the chip is used in Tx mode only.
Please refer to Table 26 for the SX1211’s pin configuration.
4.4.6. Example of Usage
On both sides:
Configure all data processing related registers listed below appropriately. In this example we assume Sync
word recognition is on and Fifo_fill_method=0.
MCParam
IRQParam
RXParam
SYNCParam
Data_mode_x
Fifo_size
Fifo_thresh
Rx_stby_irq_0
Rx_stby_irq_1
Tx_irq_1
Fifo_fill_method
Fifo_fill
Tx_start_irq_0
Sync_size
Sync_tol
Sync_value
Tx
X
X
X
Rx
X
X
X
X
X
X
X
X
X
X
X
X
Description
Defines data operation mode (Buffered)
Defines FIFO size
Defines FIFO threshold
Defines IRQ_0 source in Rx & Stby modes
Defines IRQ_1 source in Rx & Stby modes
Defines IRQ_1 source in Tx mode
Defines FIFO filling method
Controls FIFO filling status
Defines Tx start condition and IRQ_0 source
Defines Sync word size
Defines the error tolerance on Sync word detection
Defines Sync word value
Table 21: Relevant Configuration Registers in Buffered Mode (data processing related only)
Tx side:
Program Tx start condition and IRQs: Start Tx when FIFO is not empty (Tx_start_irq_0=1) and IRQ_1 mapped
to Tx_done (Tx_irq_1=1)
Go to Tx mode (and wait for Tx to be ready, see Figure 50)
Write packet bytes into FIFO. Tx starts when the first byte is written (Tx_start_irq_0=1). We assume the FIFO is
being filled via SPI Data faster than being unfilled by SR.
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Wait for Tx_done interrupt (+1 bit period)
Go to Sleep mode
Rx side:
Program Rx/Stby interrupts: IRQ_0 mapped to /Fifoempty (Rx_stby_irq_0=10) and IRQ_1 mapped to
Fifo_threshold (Rx_stby_irq_1=01). Configure Fifo_thresh to an appropriate value (ex: to detect packet end if
its length is known)
Go to Rx mode (note that Rx is not ready immediately, Cf section 5.3.1).
Wait for Fifo_threshold interrupt (i.e. Sync word has been detected and FIFO filled up to the defined threshold).
If it is packet end, go to Stby (SR’s content is lost).
Read packet bytes from FIFO until /Fifoempty goes low (or correct number of bytes is read).
Go to Sleep mode.
4.5. Packet Mode
4.5.1. General Description
Similarly to Buffered mode, in Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by
the uC but stored in the FIFO and accessed via the SPI Data interface.
Additionally, the SX1211’s packet handler performs several packet oriented tasks like Preamble and Sync word
generation, CRC calculation/check, whitening/dewhitening of data, address filtering, etc. This simplifies software
even more and reduces uC overhead by performing these repetitive tasks on the RF chip itself.
Another important feature is ability to fill and empty the FIFO in Stby mode, ensuring optimum power consumption
and adding more flexibility for the software.
SX1211
IRQ_0
CONTROL
IRQ_1
Data
Rx
SPI
SYNC
RECOG.
NSS_CONFIG
CONFIG
PACKET
HANDLER
FIFO
(+SR)
Tx
DATA
NSS_DATA
SCK
MOSI
MISO
Datapath
Figure 42: Packet Mode Conceptual View
Note that Bit Synchronizer and Sync word recognition are automatically enabled in Packet mode.
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4.5.2. Packet Format
Two types of packet formats are supported: fixed length and variable length, selectable by the
PKTParam_Pkt_format bit. The maximum size of the payload is limited by the size of the FIFO selected (16, 32, 48
or 64 bytes).
4.5.2.1. Fixed Length Packets
In applications where the packet length is fixed in advance, this mode may be of interest to minimize RF overhead
(no length field to be sent). All nodes, whether Tx only, Rx only, or Tx/Rx should be programmed with the same
packet length value.
The length of the payload is set by the PKTParam_Payload_length register and is limited by the size of the FIFO
selected.
The length stored in this register relates only to the payload which includes the message and the optional address
byte. In this mode, the payload must contain at least one byte, i.e. address or message byte.
An illustration of a fixed length packet is shown in Figure 43. It is made up of the following fields:
Preamble (1010...).
Sync word (Network ID).
Optional Address byte (Node ID).
Message data.
Optional 2-bytes CRC checksum.
Optional DC free data coding
CRC checksum calculation
Preamble
1 to 4 bytes
Sync Word
1 to 4 bytes
Address
byte
Message
0 to (FIFO size) bytes
CRC
2-bytes
Payload/FIFO
Fields added by the packet handler in Tx and processed and removed in Rx
Optional User provided fields which are part of the payload
Message part of the payload
Figure 43: Fixed Length Packet Format
4.5.2.2. Variable Length Packets
This mode is necessary in applications where the length of the packet is not known in advance and can vary over
time. It is then necessary for the transmitter to send the length information together with each packet in order for
the receiver to operate properly.
In this mode the length of the payload, indicated by the length byte of Figure 44, is given by the first byte of the
FIFO and is limited only by the width of the FIFO selected. In this mode, the payload must contain at least 2 bytes,
i.e. length + address or message byte.
An illustration of a variable length packet is shown in Figure 44. It is made up of the following fields:
Preamble (1010...).
Sync word (Network ID).
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Length byte
Optional Address byte (Node ID).
Message data.
Optional 2-bytes CRC checksum.
Optional DC free data coding
CRC checksum calculation
Preamble
1 to 4 bytes
Sync Word
1 to 4 bytes
Length
byte
Address
byte
Message
0 to (FIFO size - 1) bytes
CRC
2-bytes
Payload/FIFO
Fields added by the packet handler in Tx and processed and removed in Rx
Optional User provided fields which are part of the payload
Message part of the payload
Figure 44: Variable Length Packet Format
4.5.3. Tx Processing
In Tx mode the packet handler dynamically builds the packet by performing the following operations on the payload
available in the FIFO:
Add a programmable number of preamble bytes
Add a programmable Sync word
Optionally calculating CRC over complete payload field (optional length byte + optional address byte +
message) and appending the 2 bytes checksum.
Performing optional DC-free encoding of the data (Manchester or whitening).
Only the payload (including optional address and length fields) is to be provided by the user in the FIFO.
Assuming that the chip is already in Tx mode then, depending on IRQParam_Tx_start_irq_0 bit, packet
transmission (starting with programmed preamble) will start either after the first byte is written into the FIFO
(Tx_start_irq_0=1) or after the number of bytes written reaches the user defined threshold (Tx_start_irq_0=0).
The FIFO can also be fully or partially filled in Stby mode via PKTParam_Fifo_stby_access. In this case, the start
condition will only be checked when entering Tx mode.
At the end of the transmission (Tx_done = 1), the user must explicitly exit Tx mode if required. (e.g. back to Stby)
Note that while in Tx mode, before and after actual packet transmission (not enough bytes or Tx_done), additional
preamble bytes are automatically sent to the modulator. When the start condition is met, the current additional
preamble byte is completely sent before the transmission of the next packet (i.e. programmed preamble) is started.
4.5.4. Rx Processing
In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations:
Receiving the preamble and stripping it off.
Detecting the Sync word and stripping it off.
Optional DC-free decoding of data.
Optionally checking the address byte.
Optionally checking CRC and reflecting the result on CRC_status bit and CRC_OK IRQ source.
Only the payload (including optional address and length fields) is made available in the FIFO.
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Payload_ready and CRC_OK interrupts (the latter only if CRC is enabled) can be generated to indicate the end of
the packet reception.
By default, if the CRC check is enabled and fails for the current packet, then the FIFO is automatically cleared and
neither of the two interrupts are generated and new packet reception is started. This autoclear function can be
disabled via PKTParam_CRC_autoclr bit and, in this case, even if CRC fails, the FIFO is not cleared and only
Payload_ready IRQ source is asserted.
Once fully received, the payload can also be fully or partially retrieved in Stby mode via
PKTParam_Fifo_stby_access. At the end of the reception, although the FIFO automatically stops being filled, it is
still up to the user to explicitly exit Rx mode if required. (e.g. go to Stby to get payload).
4.5.5. Packet Filtering
SX1211’s packet handler offers several mechanisms for packet filtering ensuring that only useful packets are made
available to the uC, reducing significantly system power consumption and software complexity.
4.5.5.1. Sync Word Based
Sync word filtering/recognition is automatically enabled in Packet mode. It is used for identifying the start of the
payload and also for network identification
As previously described, the Sync word recognition block is configured (size, error tolerance, value) via
RXParam_Sync_size, RXParam_Sync_tol and SYNCParam configuration registers. This information is used, both
for appending Sync word in Tx, and filtering packets in Rx.
Every received packet which does not start with this locally configured Sync word is automatically discarded and no
interrupt is generated.
When the Sync word is detected, payload reception automatically starts and Sync IRQ source is asserted.
4.5.5.2. Address Based
Address filtering can be enabled via the PKTParam_Adrs_filt bits. It adds another level of filtering, above Sync
word, typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and
each node has its own ID (address).
Three address based filtering options are available:
Adrs_filt = 01: Received address field is compared with internal register Node_Adrs. If they match then the
packet is accepted and processed, otherwise it is discarded.
Adrs_filt = 10: Received address field is compared with internal register Node_Adrs and the constant 0x00. If
either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional
check with a constant is useful for implementing broadcast in a multi-node networks.
Adrs_filt = 11: Received address field is compared with internal register Node_Adrs and the constants 0x00 &
0xFF. If any of the three matches, then the received packet is accepted and processed, otherwise it is
discarded. These additional checks with constants are useful for implementing broadcast commands of all
nodes.
Please note that the received address byte, as part of the payload, is not stripped off the packet and is made
available in the FIFO.
Also note that Node_Adrs and Adrs_filt only apply to Rx. On Tx side, if address filtering is expected, the address
byte should simply be put into the FIFO like any other byte of the payload.
4.5.5.3. Length Based
In variable length Packet mode, PKTParam_Payload_length must be programmed with the maximum length
permitted. If received length byte is smaller than this maximum then the packet is accepted and processed,
otherwise it is discarded.
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Please note that the received length byte, as part of the payload, is not stripped off the packet and is made
available in the FIFO.
To disable this function the user should set the value of the PKTParam_Payload_length to the value of the FIFO
size selected.
4.5.5.4. CRC Based
The CRC check is enabled by setting bit PKTParam_CRC_on. It is used for checking the integrity of the message.
On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end
of the message.
On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes
received. The result of the comparison is stored in the PKTParam_CRC_status bit and CRC_OK IRQ source.
By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering
function can be disabled via PKTParam_CRC_autoclr bit and in this case, even if CRC fails, the FIFO is not
cleared and only Payload_ready interrupt goes high. Please note that in both cases, the two CRC checksum bytes
are stripped off by the packet handler and only the payload is made available in the FIFO.
The CRC is based on the CCITT polynomial as shown in Figure 45. This implementation also detects errors due to
leading and trailing zeros.
data input
CRC Polynomial =X16 + X12 + X5 + 1
X15
X14
X13
X12
X11
***
X5
X4
***
X0
Figure 45: CRC Implementation
4.5.6. DC-Free Data Mechanisms
The payload to be transmitted may contain long sequences of 1’s and 0’s, which introduces a DC bias in the
transmitted signal. The radio signal thus produced has a non uniform power distribution over the occupied channel
bandwidth. It also introduces data dependencies in the normal operation of the demodulator. Thus it’s useful if the
transmitted data is random and DC free.
For such purposes, two techniques are made available in the packet handler: Manchester encoding and data
whitening. Please note that only one of the two methods should be enabled at a time.
4.5.6.1. Manchester Encoding
Manchester encoding/decoding is enabled by setting bit PKTParam_Manchester_on and can only be used in
Packet mode.
The NRZ data is converted to Manchester code by coding ‘1’ as “10” and ‘0’ as “01”.
In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit
rate is half the chip rate.
Manchester encoding and decoding is only applied to the payload and CRC checksum while preamble and Sync
word are kept NRZ. However, the chip rate from preamble to CRC is the same and defined by MCParam_BR (Chip
Rate = Bit Rate NRZ = 2 x Bit Rate Manchester).
Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from
the FIFO.
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1/BR
RF chips @ BR
User/NRZ bits
Manchester OFF
User/NRZ bits
Manchester ON
...Sync
1 0
...
1
1
...
1
1
1
...
1
1
1
1/BR
1
0
0
1
0
0
1
Payload...
0
1
1
0
1
0
...
0
1
0
0
1
0
0
1
0
0
1
0
...
0
1
0
0
1
0
1
0
1
1
1
t
...
Figure 46: Manchester Encoding/Decoding
4.5.6.2. Data Whitening
Another technique called whitening or scrambling is widely used for randomizing the user data before radio
transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using
the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ datarate i.e. actual
bit rate is not halved.
The whitening/de-whitening process is enabled by setting bit PKTParam_Whitening_on. A 9-bit LFSR is used to
generate a random sequence. The payload and 2-byte CRC checksum is then XORed with this random sequence
as shown in Figure 47. The data is de-whitened on the receiver side by XORing with the same random sequence.
Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from
the FIFO.
L F S R P o ly n o m ia l = X 9 + X 5 + 1
X8
X7
X6
X5
X4
X3
X2
X1
X0
W h ite n e d da ta
T ra n sm it d a ta
Figure 47: Data Whitening
4.5.7. Interrupt Signal Mapping
Tables below give the description of the interrupts available in Packet mode.
Table 22: Interrupt Mapping in Rx and Stby in Packet Mode
IRQ_0
IRQ_1
Rx_stby_irq_x
00 (d)
01
10
11
00 (d)
01
10
11
Rx
Payload_ready
Write_byte
/Fifoempty
Sync or Adrs_match*
CRC_OK
Fifofull
RSSI
Fifo_threshold
Stby
/Fifoempty
Fifofull
Fifo_threshold
*The latter if Address filtering is enabled
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IRQ_0
IRQ_1
Tx_start_irq_0=0 (d)
Tx
Fifo_threshold
Tx_start_irq_0=1
/Fifoempty
Tx_irq_1=0 (d)
Fifofull
Tx_irq_1=1
Tx_done
Table 23: Interrupt Mapping in Tx Packet Mode
4.5.8. uC Connections
SX1211
IRQ_0
IRQ_1
uC
NSS_CONFIG
NSS_DATA
SCK
MOSI
MISO
Figure 48: uC Connections in Packet Mode
Note that some connections may not be needed depending on the application.
IRQ_0: if none of the relevant IRQ sources is used
IRQ_1: if none of the relevant IRQ sources is used
MISO: if no read register access is needed and chip is used in Tx only.
Please refer to Table 26 for the SX1211’s pin configuration.
4.5.9. Example of Usage
On both sides:
Configure all data processing related registers listed below appropriately. In this example we assume CRC is
enabled with autoclear on.
MCParam
IRQParam
RXParam
SYNCParam
PKTParam
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Data_mode_x
Fifo_size
Fifo_thresh
Rx_stby_irq_0
Rx_stby_irq_1
Tx_irq_1
Tx_start_irq_0
Sync_size
Sync_tol
Sync_value
Manchester_on
Payload_length
Node_adrs
Tx
X
X
X
X
X
X
X
X
(1)
X
Rx
X
X
X
X
X
X
X
X
X
X
X
Description
Defines data operation mode (Packet)
Defines FIFO size
Defines FIFO threshold
Defines IRQ_0 source in Rx & Stby modes
Defines IRQ_1 source in Rx & Stby modes
Defines IRQ_1 source in Tx mode
Defines Tx start condition and IRQ_0 source
Defines Sync word size
Defines the error tolerance on Sync word detection
Defines Sync word value
Enables Manchester encoding/decoding
Length in fixed format, max Rx length in variable format
Defines node address for Rx address filtering
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Pkt_format
Preamble_size
Whitening_on
CRC_on
Adrs_filt
CRC_autoclr
Fifo_stby_access
(1)
X
X
X
X
X
X
X
X
X
X
X
Defines packet format (fixed or variable length)
Defines the size of preamble to be transmitted
Enables whitening/de-whitening process
Enables CRC calculation/check
Enables and defines address filtering
Enables FIFO autoclear if CRC failed
Defines FIFO access in Stby mode
fixed format only
Table 24: Relevant Configuration Registers Relevant in Packet Mode (data processing related only)
On Tx side:
Program Tx start condition and IRQs: Start Tx when FIFO not empty (Tx_start_irq_0=1) and IRQ_1 mapped to
Tx_done (Tx_irq_1=1)
Go to Stby mode
Write all payload bytes into FIFO (Fifo_stby_access=0, Stby interrupts can be used if needed)
Go to Tx mode. When Tx is ready (automatically handled) Tx starts (Tx_start_irq_0=1).
Wait for Tx_done interrupt (+1 bit period)
Go to Sleep mode
On Rx side:
Program Rx/Stby interrupts: IRQ_0 mapped to /Fifoempty (Rx_stby_irq_0=10) and IRQ_1 mapped to CRC_OK
(Rx_stby_irq_1=00)
Go to Rx (note that Rx is not ready immediately, see section 5.3.1
Wait for CRC_OK interrupt
Go to Stby
Read payload bytes from FIFO until /Fifoempty goes low. (Fifo_stby_access =1)
Go to Sleep mode
4.5.10. Additional Information
If the number of bytes filled for transmission is greater than the actual length of the packet to be transmitted and
Tx_start_irq_0 = 1, then the FIFO is cleared after the packet has been transmitted. Thus the extra bytes in the
FIFO are lost. On the other hand if Tx_start_irq_0 = 0 then the extra bytes are kept into the FIFO. This opens up
the possibility of transmitting more than one packet by filling the FIFO with multiple packet messages.
It is not possible to receive multiple packets. Once a packet has been received and filled into the FIFO all its
content needs to be read i.e. the FIFO must be empty for a new packet reception to be initiated.
The Payload_ready interrupt goes high when the last payload byte is available in the FIFO and remains high until
all its data are read. Similar behavior is applicable to Adrs_match and CRC_OK interrupts.
The CRC result is available in the CRC_status bit as soon as the CRC_successful and Payload_ready interrupt
sources are triggered. In Rx mode, CRC_status is cleared when the complete payload has been read from the
FIFO. If the payload is read in Stby mode, then CRC_status is cleared when the user goes back to Rx mode and a
new Sync word is detected.
The Fifo_fill_method and Fifo_fill bits don’t have any meaning in the Packet mode and should be set to their default
values only.
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
5. Operating Modes
This section summarizes the settings for each operating mode of the SX1211, and explains the functionality
available and the timing requirements for switching between modes.
5.1. Modes of Operation
Table 25: Operating Modes
Mode
Sleep
Standby
MCParam_Chip_mode
000
001
FS
Receive
010
011
Transmit
100
Active blocks
SPI, POR
SPI, POR, Top regulator, digital regulator, XO, CLKOUT (if activated through
OSCParam_Clkout)
Same + VCO regulator, all PLL and LO generation blocks
Same as FS mode + LNA, first mixer, IF amplifier, second mixer set, channel
filters, baseband amplifiers and limiters, RSSI, OOK or FSK demodulator,
BitSync and all digital features if enabled
Same as FS mode + DDS, Interpolation filters, all up-conversion mixers, PA
driver, PA and external VR_PA pin output for PA choke.
5.2. Digital Pin Configuration vs. Chip Mode
Table 26 describes the state of the digital IOs in each of the above described modes of operation.
Table 26: Pin Configuration vs. Chip Mode
Chip
……….Mode
Sleep
mode
Standby
mode
FS mode
Receive
mode
Transmit
mode
Comment
NSS_CONFIG
INPUT
INPUT
INPUT
INPUT
INPUT
NSS_CONFIG
has
the
priority over NSS_DATA
NSS_DATA
IRQ_0
IRQ_1
DATA
CLKOUT
INPUT
High-Z
High-Z
High-Z
High-Z
OUTPUT if
NSS_CON
FIG=’0’ or
NSS_DAT
A = ‘0’
INPUT
INPUT
INPUT
OUTPUT(1)
OUTPUT(1)
High-Z
OUTPUT
OUTPUT if
NSS_CONFI
G=’0’
or
NSS_DATA
= ‘0’
INPUT
INPUT
INPUT
OUTPUT(1)
OUTPUT(1)
High-Z
OUTPUT
OUTPUT if
NSS_CONFI
G=’0’
or
NSS_DATA
= ‘0’
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT if
NSS_CON
FIG=’0’ or
NSS_DAT
A = ‘0’
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
OUTPUT if
NSS_CON
FIG=’0’ or
NSS_DAT
A = ‘0’
INPUT
INPUT
Pin
MISO
MOSI
SCK
Notes:
(1): High-Z if Continuous mode is activated
(2): valid logic states must be applied to inputs at all times to avoid unwanted leakage currents.
5.3. Switching Times and Procedures
As an ultra-low power device, the SX1211 can be configured for low minimum average power consumption. To
minimize consumption the following optimized transitions between modes are shown.
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
5.3.1. Optimized Receive Cycle
The lowest-power Rx cycle is the following:
SX1211
Icc
IDDR
3.0mA typ.
IDDFS
1.3mA typ.
IDDST
55uA typ.
IDDSL
300nA typ.
Time
Rx
time
SX1211 can be put in
Any other mode
Wait
TS_RE
Receiver is ready :
-RSSI sampling is valid after a 1/Fdev period
-Received data is valid
Wait
TS_FS
Set SX1211 in Rx mode
Wait for Receiver settling
Wait
TS_OS
Set SX1211 in FS mode
Wait for PLL settling
Set SX1211 in Standby mode
Wait for XO settling
Figure 49: Optimized Rx Cycle
Note: If the lock detect indicator is available on an external interrupt pin of the companion uC, it can be used to
optimize TS_FS, without having to wait the maximum specified TS_FS.
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
5.3.2. Optimized Transmit Cycle
SX1211
Icc
IDDT
16mA typ. @1dBm
IDDFS
1.3mA typ.
IDDST
55uA typ.
IDDSL
300nA typ.
Time
Tx
time
SX1211 can be put in
Any other mode
Wait
TS_TR
Data transmission can start in
Continuous and Buffered
modes
Wait
TS_FS
Set SX1211 in Tx mode
Packet mode starts its operation
Wait
TS_OS
Set SX1211 in FS mode
Wait for PLL settling
Set SX1211 in Standby mode
Wait for XO settling
Figure 50: Optimized Tx Cycle
Note: As stated in the preceding section, TS_FS time can be improved by using the external lock detector pin as
external interrupt trigger.
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
5.3.3. Transmitter Frequency Hop Optimized Cycle
SX1211
Icc
IDDT
16mA typ. @1dBm
IDDFS
1.3mA typ.
Time
Wait
TS_TR
SX1211 is now ready
for data transmission
Wait
TS_HOP
Set SX1211 back in Tx mode
1. Set R2/P2/S2
2. Set SX1211 in FS mode, change
MCParam_Band if needed, then switch
from R1/P1/S1 to R2/P2/S2
SX1211 is in Tx mode
On channel 1 (R1/P1/S1)
Figure 51: Tx Hop Cycle
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
5.3.4. Receiver Frequency Hop Optimized Cycle
SX1211
Icc
IDDR
3mA typ
IDDFS
1.3mA typ.
Time
Wait
TS_RE
SX1211 is now ready
for data reception
Wait
TS_HOP
Set SX1211 back in Rx mode
1. Set R2/P2/S2
2. Set SX1211 in FS mode, change
MCParam_Band if needed, then switch
from R1/P1/S1 to R2/P2/S2
SX1211 is in Rx mode
On channel 1 (R1/P1/S1)
Figure 52: Rx Hop Cycle
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
5.3.5. RxTx and TxRx Jump Cycles
SX1211
Icc
IDDT
16mA typ. @1dBm
IDDR
3.0mA typ.
Time
Wait
TS_RE
SX1211 is ready to
receive data
Set SX1211 in
Rx mode
Wait
TS_TR
SX1211 is now ready
for data transmission
SX1211 is in
Rx mode
Set SX1211 in
Tx mode
Figure 53: Rx Tx Rx Cycle
5.4. Power-On Reset
If the application requires the disconnection of VDD from the SX1211, despite of the extremely low Sleep Mode
current, the user should wait for 10 ms before the device is actually able to communicate through the SPI port.
V3.0 – august 15th, 2007
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SX1211
ADVANCED COMMUNICATIONS & SENSING
6. Configuration and Status Registers
6.1. General Description
Table 27 sums-up the control and status registers of the SX1211:
Table 27: Registers List
Name
MCParam
IRQParam
RXParam
SYNCParam
TXParam
OSCParam
PKTParam
Size
13 x 8
3x8
6x8
4x8
1x8
1x8
3x8
Address
0 - 12
13 - 15
16 - 21
22 – 25
26
27
28 - 31
Description
Main parameters common to transmit and receive modes
Interrupt registers
Receiver parameters
Pattern
Transmitter parameters
Crystal oscillator parameters
Packet handler parameters
6.2. Main Configuration Register - MCParam
The detailed description of the MCParam register is given in Table 28.
Table 28: MCParam Register Description
Name
Bits
Address
(dec)
RW
Chip_mode
7-5
0
r/w
Freq_band
4-3
0
r/w
VCO_trim
2-1
0
r/w
RPS_select
0
0
r/w
Modul_select
7-6
1
r/w
Data_mode_0
5
1
r/w
OOK_thresh_type
4-3
1
r/w
V3.0 – august 15th, 2007
Description
Transceiver mode:
000 sleep mode - Sleep
001 stand-by mode - Stby (d)
010 frequency synthesizer mode - FS
011 receive mode - Rx
100 transmit mode - Tx
Frequency band:
00 902 – 915 MHz
01 915 – 928 MHz (d)
10 950 – 960 MHz and 863 - 870 MHz (with another VCO tank)
Fine VCO trimming:
00 Vtune as set by tank inductors values (d)
01 Vtune + 1 x 60 mV typ.
10 Vtune + 2 x 60 mV typ.
11 Vtune + 3 x 60 mV typ.
Selection between the two sets of frequency dividers of the PLL, Ri/Pi/Si
0 R1/P1/S1 used (d)
1 R2/P2/S2 used
Type of modulation:
01 OOK
10 FSK (d)
Data operation mode LSB.
Data_mode(1:0):
00 Continuous (d)
01 Buffered
1x Packet
OOK demodulator threshold type:
00 fixed threshold mode
01 peak mode (d)
10 average mode
11 reserved
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ADVANCED COMMUNICATIONS & SENSING
Data_mode_1
2
1
r/w
IF_gain
1-0
1
r/w
Freq_dev
7-0
2
r/w
Res
BR
7
3
r/w
Data operation mode’s MSB.
Cf Data_mode_0
Gain on the IF chain:
00 maximal gain (0dB) (d)
01 -4.5 dB
10 -9dB
11 -13.5 dB
Single side frequency deviation:
Fdev =
f XTAL , 0 ≤ D ≤ 255, where D is the value in the register.
32 ⋅ (D + 1)
(d): D = “00000011” => Fdev = 100 kHz
Reserved
(d): “0”
Bit Rate =
6-0
3
r/w
f XTAL
64 ⋅ (C + 1)
, 0 ≤ C ≤ 127, where C is the value in the register.
(d): C = “0000111” => Bit Rate = 25 kb/s NRZ
OOK_
floor_thresh
7-0
4
r/w
Floor threshold in OOK Rx mode. By default 6 dB.
(d): “00001100” assuming 0.5 dB RSSI step
Fifo_size
7:6
5
r/w
FIFO size selection:
00 16 bytes (d)
01 32 bytes
10 48 bytes
11 64 bytes
Fifo_thresh
5-0
5
r/w
FIFO threshold for interrupt source (Cf section 4.2.2.3)
(d): B = “001111”
R1
7-0
6
r/w
P1
7-0
7
r/w
S1
7-0
8
r/w
R2
7-0
9
r/w
P2
7-0
10
r/w
S2
7-0
11
r/w
Res
7-5
12
r/w
PA_ramp
4-3
12
r/w
Res
2-0
12
r/w
V3.0 – august 15th, 2007
R counter, active when RPS_select=”0”
(d):77h; default values of R1, P1, S1 generate (915.0 MHz-Fdev)
P counter, active when RPS_select=”0”
(d): 64h; default values of R1, P1, S1 generate (915.0 MHz-Fdev)
S counter, active when RPS_select=”0”
(d): 32h; default values of R1, P1, S1 generate (915.0 MHz-Fdev)
R counter, active when RPS_select=”1”
(d): 74h; default values of R2, P2, S2 generate (920.0 MHz-Fdev)
P counter, active when RPS_select=”1”
(d): 62h; default values of R2, P2, S2 generate (920.0 MHz-Fdev)
S counter, active when RPS_select=”1”
(d): 32h; default values of R2, P2, S2 generate (920.0 MHz-Fdev)
Reserved
(d): “001”
Controls the ramp times of the PA regulator output voltage in OOK mode:
00 3us
01 8.5 us
10 15 us
11 23 us (d)
Reserved
(d):”000”
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SX1211
ADVANCED COMMUNICATIONS & SENSING
6.3. Interrupt Configuration Parameters - IRQParam
The detailed description of the IRQParam register is given in Table 29.
Table 29: IRQParam Register Description
Name
Bits
Address
(dec)
RW
Description
IRQ_0 source in Rx and Standby modes:
Rx_stby_irq_0
7-6
13
r/w
If Data_mode(1:0) = 00 (Continuous mode):
00 Sync (d)
01 RSSI
10 Sync
11 Sync
If Data_mode(1:0) = 01 (Buffered mode):
00 - (d)
01 Write_byte
10 /Fifoempty*
11 Sync
If Data_mode(1:0) = 1x (Packet mode):
00 Payload_ready (d)
01 Write_byte
10 /Fifoempty*
11 Sync or Adrs_match (the latter if address filtering is enabled)
*also available in Standby mode (Cf sections 4.4.4 and 4.5.7)
IRQ_1 source in Rx and Standby modes:
Rx_stby_irq_1
5-4
13
r/w
If Data_mode(1:0) = 00 (Continuous mode):
xx DCLK
If Data_mode(1:0) = 01 (Buffered mode):
00 - (d)
01 Fifofull*
10 RSSI
11 Fifo_threshold*
If Data_mode(1:0) = 1x (Packet mode):
00 CRC_ok (d)
01 Fifofull*
10 RSSI
11 Fifo_threshold*
*also available in Standby mode (Cf sections 4.4.4 and 4.5.7)
IRQ_1 source in Tx mode:
Tx_irq_1
3
13
r/w
Fifofull
2
13
r
/Fifoempty
1
13
r
Fifo_overrun_clr
0
13
Fifo_fill_method
7
14
V3.0 – august 15th, 2007
r/w/
c
r/w
If Data_mode(1:0) = 00 (Continuous mode):
x DCLK
If Data_mode(1:0) = 01 (Buffered mode) or 1x (Packet mode):
0 Fifofull (d)
1 Tx_done
Fifofull IRQ source
Goes high when FIFO is full.
/Fifoempty IRQ source
Goes low when FIFO is empty
Goes high when an overrun error occurred. Writing a 1 clears flag and FIFO
FIFO filling method (Buffered mode only):
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ADVANCED COMMUNICATIONS & SENSING
Fifo_fill
6
14
r/w/
c
Tx_done
5
14
r
Tx_start_irq_0
4
14
r/w
Res
3
14
r/w
RSSI_irq
2
14
r/w/
c
PLL_locked
1
14
r/w/
c
PLL_lock_en
0
14
r/w
RSSI_irq_thresh
7-0
15
V3.0 – august 15th, 2007
0 Automatically starts when a sync word is detected (d)
1 Manually controlled by Fifo_fill
FIFO filling status/control (Buffered mode only):
If Fifo_fill_method = ‘0’: (d)
Goes high when FIFO is being filled (sync word has been detected)
Writing ‘1’ clears the bit and waits for a new sync word (if Fifo_overrun_clr=0)
If Fifo_fill_method = ‘1’:
0 Stop filling the FIFO
1 Start filling the FIFO
Tx_done IRQ source
Goes high when the last bit has left the shift register.
Tx start condition and IRQ_0 source:
If Data_mode(1:0) = 01 (Buffered mode):
0 Tx starts if FIFO is full, IRQ_0 mapped to /Fifoempty (d)
1 Tx starts if FIFO is not empty, IRQ_0 mapped to /Fifoempty
If Data_mode(1:0) = 1x (Packet mode):
0 Start transmission when the number of bytes in FIFO is greater than or
equal to the threshold set by MCParam_Fifo_thresh parameter (Cf section
4.2.3), IRQ_0 mapped to Fifo_threshold (d)
1 Tx starts if FIFO is not empty, IRQ_0 mapped to /Fifoempty
(d): “0”, should be set to “1”
RSSI IRQ source:
Goes high when a signal above RSSI_irq_thresh is detected
Writing ‘1’ clears the bit
PLL status:
0 not locked
1 locked
Writing a ‘1’ clears the bit
PLL_locked mapped to pin 23:
0 no, pin 23 is HI
1 yes (d)
RSSI threshold for interrupt (coded as RSSI)
(d): “00000000”
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ADVANCED COMMUNICATIONS & SENSING
6.4. Receiver Configuration parameters - RXParam
The detailed description of the RXParam register is given in Table 30.
Table 30: RXParam Register Description
Name
Bits
Address (d)
RW
PassiveFilt
7-4
16
r/w
ButterFilt
3-0
16
r/w
PolypFilt_center
7-4
17
r/w
Res
3-0
17
r/w
PolypFilt_on
7
18
r/w
Bitsync_off
6
18
r/w
Sync_on
5
18
r/w
Sync_size
4-3
18
r/w
Sync_tol
2-1
18
r/w
Res
0
18
r/w
Res
7-0
19
r/w
V3.0 – august 15th, 2007
Description
Typical single side bandwidth of the passive low-pass filter.
PassiveFilt = 0000 65 kHz
0001 82 kHz
0010 109 kHz
0011 137 kHz
0100 157 kHz
0101 184 kHz
0110 211 kHz
0111 234 kHz
1000 262 kHz
1001 321 kHz
1010 378 kHz (d)
1011 414 kHz
1100 458 kHz
1101 514 kHz
1110 676 kHz
1111 987 kHz
Sets the receiver bandwidth. For BW information please refer to
sections 3.4.5 (FSK) and 3.4.6 (OOK).
(d): “0011”
Central frequency of the polyphase filter (100kHz recommended):
f 0 = 200kHz.
Fxtal MHz 1 + Val ( PolypFilt _ center )
.
12.8MHz
8
(d):“0011” => f0 = 100 kHz
Reserved
(d): “1000”
Enable the polyphase filter, in OOK Rx mode:
0 off (d)
1 on
Bit synchronizer: control in Continuous Rx mode:
0 on (d)
1 off
Sync word recognition:
0 off (d)
1 on
Sync word size:
00 8 bits
01 16 bits
10 24 bits
11 32 bits (d)
Number of errors tolerated in the Sync word recognition:
00 0 error (d)
01 1 error
10 2 errors
11 3 errors
Reserved
(d):”0”
Reserved
(d): “00000111”
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ADVANCED COMMUNICATIONS & SENSING
Name
Bits
Address (d)
RW
RSSI_val
7-0
20
r
OOK_thresh_step
7-5
21
r/w
OOK_thresh_dec
_period
4-2
21
r/w
OOK_avg_thresh
_cutoff
1-0
21
r/w
Description
RSSI output, 0.5 dB / bit
Caution: not to be written
Size of each decrement of the RSSI threshold in the OOK demodulator
000 0.5 dB (d)
100 3.0 dB
101 4.0 dB
001 1.0 dB
110 5.0 dB
010 1.5 dB
011 2.0 dB
111 6.0 dB
Period of decrement of the RSSI threshold in the OOK demodulator:
000 once in each chip period (d)
001 once in 2 chip periods
010 once in 4 chip periods
011 once in 8 chip periods
100 twice in each chip period
101 4 times in each chip period
110 8 times in each chip period
111 16 times in each chip period
Cutoff frequency of the averaging for the average mode of the OOK
threshold in demodulator
00 fC ≈ BR / 8.π (d)
01 Reserved
10 Reserved
11 fC ≈ BR / 32.π
6.5. Sync Word Parameters - SYNCParam
The detailed description of the SYNCParam register is given in Table 31.
Table 31: SYNCParam Register Description
Name
Sync_value(31:2
4)
Sync_value(23:1
6)
Sync_value(15:8)
Bits
7-0
Address (d)
22
7-0
23
7-0
24
Sync_value(7:0)
7-0
25
V3.0 – august 15th, 2007
RW
r/w
Description
st
Sync word’s 1 byte
(d): “00000000”
nd
Sync word’s 2 byte (only used if Sync_size ≠ 00)
(d): “00000000”
rd
Sync word’s 3 byte (only used if Sync_size = 1x)
(d): “00000000”
th
Sync word’s 4 byte (only used if Sync_size = 11)
(d): “00000000”
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ADVANCED COMMUNICATIONS & SENSING
6.6. Transmitter Parameters - TXParam
The detailed description of the TXParam register is given in Table 32.
Table 32: TXParam Register Description
Name
InterpFilt
Bits
7-4
Address (d)
26
RW
r/w
Description
Interpolation filter cut off frequency:
fc = 200kHz.
Pout
3-1
26
r/w
Res
0
26
r/w
Fxtal MHz 1 + Val ( InterpFiltTx )
.
12.8MHz
8
(d): “0111” => fC = 200 kHz
Tx output power (1 step ≈ 3 dB):
000 13 dBm
001 13 dBm -1 step (d)
010 13 dBm – 2 steps
011 13 dBm – 3 steps
100 13 dBm – 4 steps
101 13 dBm – 5 steps
110 13 dBm – 6 steps
111 13 dBm – 7 steps
Reserved
(d): “0”
6.7. Oscillator Parameters - OSCParam
The detailed description of the OSCParam register is given in Table 33.
Table 33: OSCParam Register Description
Name
Bits
RW
Description
7
Address
(dec)
27
Clkout_on
r/w
6-2
27
r/w
Clkout control
0 off
1 on, frequency given by Clkout_freq (d)
Frequency of the signal provided on CLKOUT:
fclkout = f xtal if Clkout_freq = “00000”
Clkout_freq
fclkout =
Res
V3.0 – august 15th, 2007
1-0
27
r/w
f xtal
otherwise
2 ⋅ Clkout _ freq
(d): 01111 (= 427 kHz)
Reserved
(d): “00”
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ADVANCED COMMUNICATIONS & SENSING
6.8. Packet Handling Parameters – PKTParam
The detailed description of the PKTParam register is given in Table 34.
Table 34: PKTParam Register Description
Name
Bits
RW
Description
7
Address
(dec)
28
Manchester_on
r/w
Payload_length
6-0
28
r/w
Node_adrs
7-0
29
r/w
Pkt_format
7
30
r/w
Preamble_size
6-5
30
r/w
Whitening_on
4
30
r/w
CRC_on
3
30
r/w
Adrs_filt
2-1
30
r/w
CRC_status
0
30
r
CRC_autoclr
7
31
r/w
Fifo_stby_access
6
31
r/w
Res
5-0
31
r/w
Enable Manchester encoding/decoding:
0 off (d)
1 on
If Pkt_format=0, payload length.
If Pkt_format=1, max length in Rx, not used in Tx.
(d): “0000000”
Node’s local address for filtering of received packets.
(d): 00h
Packet format:
0 fixed length (d)
1 variable length
Size of the preamble to be transmitted:
00 1 byte
01 2 bytes
10 3 bytes (d)
11 4 bytes
Whitening/dewhitening process:
0 off (d)
1 on
CRC calculation/check:
0 off
1 on (d)
Address filtering of received packets:
00 off (d)
01 Node_adrs accepted, else rejected.
10 Node_adrs & 0x00 accepted, else rejected.
11 Node_adrs & 0x00 & 0xFF accepted, else rejected.
CRC check result for current packet:
0 failed
1 ok
FIFO auto clear if CRC failed for current packet:
0 on (d)
1 off
FIFO access in standby mode:
0 Write (d)
1 Read
Reserved
(d): “000000”
V3.0 – august 15th, 2007
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ADVANCED COMMUNICATIONS & SENSING
7. Reference Design
The SX1211 results presented in the preceding sections have been measured on the SM1211 two-layer reference
design detailed below.
It is strongly recommended that this reference design (i.e. schematics, placement, layout, BOM,) is copied verbatim
in the final application board to guarantee optimum performance, short development time and the least design
effort.
7.1. Schematics
Figure 54: Reference Design’s Schematics
The reference design area is represented by the dashed rectangle. C12 is a DC blocking capacitor which protects
the SAW filter. It has been added for debug purposes only so is not required for a direct antenna connection.
Please note that C10 and C11 are not used.
7.2. PCB Layout
As illustrated in figures below, the layout has the following characteristics:
very compact (9x19mm) => can be easily inserted even on very small PCBs
standard PCB technology (2 layers, 1.6mm, std via & clearance) => low cost
Its performance is quasi-insensitive to dielectric thickness => quasi-zero effort portability to other PCB
technology (thickness, # of layers, etc...)
The layers description is illustrated in Figure 55:
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SX1211
ADVANCED COMMUNICATIONS & SENSING
Signal (35um)
Isolation (FR4, 1.6mm)
Ground plane
Figure 55: Reference Design‘s Stackup
The layout itself is illustrated in Figure 56. Please contact Semtech for gerber files.
19mm
9mm
Figure 56: Reference Design’s Layout (top view)
7.3. Bill Of Material
Table 35: Reference Design’s BOM
Ref
U1
U2
Q1
Value
868MHz
915MHz
SX1211
869 MHz
915 MHz
12.8 MHz
Tol (+/-)
Techno
Transceiver IC
SAW Filter
15 ppm at 25°C
AT-cut
20 ppm over -40/+85°C
2ppm/year max
R1
1Ω
1%
R2
6.8 kΩ
1%
C1
1uF
15%
X5R
C2
1uF
15%
X5R
C3
220 nF
10%
X7R
C4
47 nF
10%
X7R
C5
100 nF
10%
X7R
C6
10 nF
10%
X7R
C7
680 pF
5%
NPO
C8
1.8 pF
0.25 pF
NPO
C9
22 pF
5%
NPO
L1, L2
8.2 nH
6.8 nH
0.2 nH
Wire wound
L3
100 nH
5%
Wire wound
L4
8.2 nH
5%
Multilayer
C10,C11
NC
C12*
47pF
5%
NPO
*Not part of the ref. design (not required for direct antenna connection).
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Size
Comment
TQFN-32
3.8*3.8 mm
5.0*3.2 mm
Plotted in section 6.4
Fundamental, Cload=15 pF
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
0402
PA regulator
Loop filter
VDD decoupling
Top regulator decoupling
Digital regulator decoupling
PA regulator decoupling
VCO regulator decoupling
Loop Filter
Loop Filter
Matching
DC block and L4 adjust
VCO tank inductors
PA Choke
Matching
DC block
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SX1211
ADVANCED COMMUNICATIONS & SENSING
7.4. SAW Filter Plot
The following screenshot shows the plot of the SAW filter used on the reference design:
0
-10
Attenuation (dB)
-20
-30
-40
-50
-60
-70
-80
400
600
800
1000
1200
1400
1600
1800
2000
1800
2000
Frequency (MHz)
Figure 57: 915 MHz SAW Filter Plot
0
-10
Attenuation (dB)
-20
-30
-40
-50
-60
-70
-80
400
600
800
1000
1200
1400
1600
Frequency (MHz)
Figure 58: 869 MHz SAW Filter Plot
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SX1211
ADVANCED COMMUNICATIONS & SENSING
8. Packaging Information
SX1211 is available in a 32-lead TQFN package as shown in Figure 59 below.
Figure 59: Package Information
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SX1211
ADVANCED COMMUNICATIONS & SENSING
9. Contact Information
Semtech Corporation
Advanced Communication and Sensing Products Division
200 Flynn Road, Camarillo, CA 93012
Phone (805) 498-2111 Fax: (805) 498-3804
© Semtech 2007
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