SPANSION S70GL02GP11FAIR10

S70GL-P MirrorBitTM Flash
S70GL02GP
2 Gigabit, 3.0 Volt-only Page Mode Flash Memory featuring
90 nm MirrorBit Process Technology
S70GL-P MirrorBitTM Flash Cover Sheet
Data Sheet (Advance Information)
Notice to Readers: This document contains information on one or more products under development at
Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this
proposed product without notice.
Publication Number S70GL-P_00
Revision 01
Issue Date December 4, 2006
Data
Sheet
(Advan ce
Infor m a tio n)
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
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places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
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require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
ii
S70GL-P MirrorBitTM Flash
S70GL-P_00_01 December 4, 2006
S70GL-P MirrorBitTM Flash Family
S70GL02GP
2 Gigabit, 3.0 Volt-only Page Mode Flash Memory featuring
90 nm MirrorBit Process Technology
Data Sheet (Advance Information)
General Description
The Spansion S70GL02GP 2 Gigabit Mirrorbit™ Flash memory device is fabricated on 90 nm process technology. This device
offers a fast page access time of 25 ns with a corresponding random access time of 120 ns. It features a Write Buffer that
allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than
standard programming algorithms. This makes the device an ideal product for today’s embedded applications that require
higher density, better performance and lower power consumption.
Distinctive Characteristics
„ Two 1024 Megabit (S29GL01GP) in a single 64-ball FortifiedBGA package (see publication S29GL-P_00 for full
specifications)
„ Single 3V read/program/erase (2.7-3.6 V)
„ Enhanced VersatileI/O™ control
– All input levels (address, control, and DQ input levels) and outputs
are determined by voltage on VIO input. VIO range is 1.65 to VCC
„ Offered Packages
– 64-ball Fortified BGA
„ Suspend and Resume commands for Program and Erase
operations
„ Write operation status bits indicate program and erase
operation completion
„ 90 nm MirrorBit process technology
„ Unlock Bypass Program command to reduce programming
time
„ 8-word/16-byte page read buffer
„ Support for CFI (Common Flash Interface)
„ 32-word/64-byte write buffer reduces overall programming
time for multiple-word updates
„ Persistent and Password methods of Advanced Sector
Protection
„ Secured Silicon Sector region
„ WP#/ACC input
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
– Can be programmed and locked at the factory or by the customer
– Accelerates programming time (when VACC is applied) for greater
throughput during system production
– Protects first or last sector of each die, regardless of sector
protection settings
„ Uniform 64Kword/128KByte Sector Architecture
„ Hardware reset input (RESET#) resets device
– S70GL02GP: two thousand forty-eight sectors
„ Ready/Busy# output (RY/BY#) detects program or erase
cycle completion
„ 100,000 erase cycles per sector typical
„ 20-year data retention typical
Performance Characteristics
Max. Read Access Times (ns)*
Current Consumption (typical values)
2 Gb
Random Access Read
30 mA
Parameter
V1
V2
V3
8-Word Page Read
1 mA
Random Access Time (tACC)
110
120
130
Program/Erase
50 mA
Page Access Time (tPACC)
25
25
25
Standby
CE# Access Time (tCE)
110
120
130
OE# Access Time (tOE)
25
25
30
Program & Erase Times (typical values)
* Access times are dependent on VCC and VIO operating ranges. See Ordering
Information page for further details.
V1: VCC = 3.0–3.6 V. V2: VCC = VIO = 2.7–3.6 V.
V3: VIO = 1.65–VCC, VCC = 3 V.
** Contact a sales representative for availability.
Publication Number S70GL-P_00
1 µA
Single Word Programming
60 µs
Effective Write Buffer Programming (VCC) Per Word
15 µs
Effective Write Buffer Programming (VACC) Per Word
15 µs
Sector Erase Time (64 Kword Sector)
0.5 s
Revision 01
Issue Date December 4, 2006
This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.
Data
Sheet
(Advan ce
Infor m a tio n)
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Recommended Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.
Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Special Handling Instructions for BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
LSE064—64 ball Fortified Ball Grid Array, 13 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.
Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.
Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.
BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.
Common Flash Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8.
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of Figures
Figure 2.1
Figure 2.2
64-ball Fortified Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LSE064—64-ball Fortified Ball Grid Array (FBGA), 13 x 11 mm . . . . . . . . . . . . . . . . . . . . . . .6
List of Tables
Table 2.1
Table 3.1
Table 4.1
Table 5.1
Table 7.1
Table 7.2
Table 7.3
Table 7.4
2
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
S70GL02GP Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Autoselect Addresses in System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Erase And Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
S70GL-P MirrorBitTM Flash Family
S70GL-P_00_01 December 4, 2006
D at a
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S hee t
(Adva nce
In for m ation)
Ordering Information
The ordering part number is formed by a valid combination of the following:
S70GL02GP
10
F
A
I
01
0
PACKING TYPE
0 = Tray (standard; see (Note 1)
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER (VIO range, protection when WP# =VIL)
01 = VIO = VCC = 2.7 to 3.6 V, highest address sector protected
02 = VIO = VCC = 2.7 to 3.6 V, lowest address sector protected
V1 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6 V, highest address sector protected
V2 = VIO = 1.65 to VCC, VCC = 2.7 to 3.6 V, lowest address sector protected
R1 = VIO = VCC = 3.0 to 3.6 V, highest address sector protected
R2 = VIO = VCC = 3.0 to 3.6 V, lowest address sector protected
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
PACKAGE MATERIALS SET
A = Pb (Note 3)
F = Pb-free
PACKAGE TYPE
F = Fortified Ball Grid Array, 1.0 mm pitch package
SPEED OPTION
11 = 110 ns
12 = 120 ns
13 = 130 ns
DEVICE NUMBER/DESCRIPTION
S70GL02GP
3.0 Volt-only, 2048 Megabit (256 M x 16-Bit/512 M x 8-Bit) Page-Mode Flash Memory
Manufactured on 90 nm MirrorBitTM process technology
S70GL02GP Valid Combinations
Base Part Number
Speed (ns)
Package &
Temperature
12
S70GL02GP
Model Number
Pack Type
Package Description
0, 2, 3 (Note 1)
LSE064 (Fortified BGA) (Note 2)
R1, R2
11
FAI , FFI
(Note 3)
13
01 (Note 3), 02
V1 (Note 3), V2
Notes
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S70” and packing type designator from ordering part number.
3. Contact local sales representative for availability.
1.1
Recommended Combinations
Recommended Combinations list configurations planned to be supported in volume for this device. Consult
your local sales office to confirm availability of specific recommended combinations and to check on newly
released combinations.
December 4, 2006 S70GL-P_00_01
S70GL-P MirrorBitTM Flash Family
3
Data
2.
Sheet
(Advan ce
Infor m a tio n)
Input/Output Descriptions & Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
4
Symbol
Type
Description
A26–A0
Input
DQ14–DQ0
I/O
Address lines for GL02GP
DQ15
I/O
CE#
Input
Chip Enable.
Data input/output.
DQ15: Data input/output in word mode .
A-1: LSB address input in byte mode.
OE#
Input
Output Enable.
WE#
Input
Write Enable.
VCC
Supply
Device Power Supply.
VIO
Supply
Versatile IO Input.
VSS
Supply
Ground.
NC
No Connect
RY/BY#
Output
BYTE#
Input
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0DQ7 are active. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15
are active.
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#/ACC
Input
Write Protect/Acceleration Input. At VIL, disables program and erase functions in the
outermost sectors. At VHH, accelerates programming; automatically places device in
unlock bypass mode. Should be at VIH for all other conditions.
RFU
Reserved
Not connected internally.
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
VIL, the device is actively erasing or programming. At High Z, the device is in ready.
Reserved for future use.
S70GL-P MirrorBitTM Flash Family
S70GL-P_00_01 December 4, 2006
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2.1
S hee t
(Adva nce
In for m ation)
Special Handling Instructions for BGA Package
Special handling is required for Flash Memory products in BGA packages.
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning m ethods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Figure 2.1 64-ball Fortified Ball Grid Array
64-ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
H8
RFU
A22
A23
VIO
VSS
A24
A25
RFU
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
BYTE#
DQ15/A-1
VSS
A6
B6
C6
D6
E6
F6
G6
H6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
DQ4
WE#
RESET#
A21
A19
DQ5
DQ12
VCC
A4
B4
C4
D4
E4
F4
G4
H4
A18
A20
DQ2
DQ10
DQ11
DQ3
RY/BY# WP#/ACC
December 4, 2006 S70GL-P_00_01
A3
B3
C3
D3
E3
F3
G3
H3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A2
B2
C2
D2
E2
F2
G2
H2
A3
A4
A2
A1
A0
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
RFU
A26
RFU
RFU
RFU
VIO
RFU
RFU
S70GL-P MirrorBitTM Flash Family
5
Data
2.2
Sheet
(Advan ce
Infor m a tio n)
LSE064—64 ball Fortified Ball Grid Array, 13 x 11 mm
Figure 2.2 LSE064—64-ball Fortified Ball Grid Array (FBGA), 13 x 11 mm
NOTES:
PACKAGE
LSE 064
JEDEC
N/A
DxE
13.00 mm x 11.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.40
A1
0.40
---
---
A2
0.79
---
0.91
D
13.00 BSC.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BODY THICKNESS
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY SIZE
BODY SIZE
MATRIX FOOTPRINT
E1
7.00 BSC.
MD
8
MATRIX SIZE D DIRECTION
ME
8
MATRIX SIZE E DIRECTION
MATRIX FOOTPRINT
64
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL COUNT
0.70
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
1.00 BSC.
BALL PITCH
eD
1.00 BSC
BALL PITCH
SD / SE
0.50 BSC.
---
BALL POSITION DESIGNATION PER JEP95,
SECTION 4.3, SPP-010.
4.
7.00 BSC.
0.60
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
PROFILE
11.00 BSC.
0.50
2.
BALL HEIGHT
E
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
NOTE
D1
Øb
1.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SOLDER BALL PLACEMENT
8.
"+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
DEPOPULATED SOLDER BALLS
3611 \ 16-038.15 \ 11.13.6
6
S70GL-P MirrorBitTM Flash Family
S70GL-P_00_01 December 4, 2006
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3. Memory Map
The S70GL02GP consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 3.1.
Table 3.1 S70GL02GP Sector & Memory Address Map
Uniform Sector
Size
Sector
Count
64 Kword/128 Kb
Sector
Range
Address Range (16-bit)
Notes
SA00
0000000h–000FFFFh
Sector Starting Address
2048
:
:
SA2047
7FF0000H–7FFFFFFh
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges
that are not explicitly listed (such as SA001-SA1022) have sector starting and ending addresses that form the same pattern as all other
sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
4. Autoselect
Table 4.1 provides the device identification codes for the S70GL02GP. For more information on the
autoselect function, refer to the S29GL-P data sheet (pulication number S29GL-P_00).
Table 4.1 Autoselect Addresses in System
Description
Address
Read Data (word/byte mode)
Manufacturer ID
(Base) + 00h
xx01h/1h
Device ID, Word 1
(Base) + 01h
227Eh/7Eh
Device ID, Word 2
(Base) + 0Eh
2248h/48h
Device ID, Word 3
(Base) + 0Fh
2201h/01h
Secure Device Verify
(Base) + 03h
Sector Protect Verify
(SA) + 02h
For S70GL02GPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked.
For S70GL02GPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked.
xx01h/01h = Locked, xx00h/00h = Unlocked
5. Erase And Programming Performance
Table 5.1 Erase And Programming Performance
Typ
(Note 1)
Parameter
Sector Erase Time
Chip Erase Time
S70GL02GP
Max
(Note 2)
Unit
0.5
3.5
sec
1024
4096
sec
Total Write Buffer Time (Note 3)
480
µs
Total Accelerated Write Buffer Programming Time
(Note 3)
432
µs
1968
sec
Chip Program Time (Note 4)
S70GL02GP
Comments
Excludes 00h programming
prior to erasure (Note 5)
Excludes system level
overhead (Note 6)
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V VCC, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of -40°C, VCC = 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 32-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum
program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
December 4, 2006 S70GL-P_00_01
S70GL-P MirrorBitTM Flash Family
7
Data
Sheet
(Advan ce
Infor m a tio n)
6. BGA Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
12
20
pF
COUT
Output Capacitance
VOUT = 0
20
24
pF
CIN2
Control Pin Capacitance
VIN = 0
16
20
pF
RESET#, WP#/ACC
Separated Control Pin
VIN = 0
84
90
pF
CE#
Separated Control Pin
VIN = 0
44
50
pF
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
8
S70GL-P MirrorBitTM Flash Family
S70GL-P_00_01 December 4, 2006
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Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h any time the device is ready to read array data. The system can read CFI infomation at the addresses
given in Tables 7.2–7.4). All reads outside of the CFI address range, returns non-valid data. Reads from other
sectors are allowed, writes are not. To terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 7.2–7.4. The
system must write the reset command to return the device to reading array data.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion
Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash
memory software development guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)base_addr + 0x55 ) = 0x0098;
/* Example: CFI Exit command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
/* write CFI entry command
/* write cfi exit command
*/
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and
JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents.
Table 7.1 CFI Query Identification String
Addresses (x16)
Addresses (x8)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
December 4, 2006 S70GL-P_00_01
Description
S70GL-P MirrorBitTM Flash Family
9
Data
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Table 7.2 System Interface String
Addresses (x16)
Addresses (x8)
Data
Description
1Bh
36h
0027h
VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 mV
1Ch
38h
0036h
VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 mV
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0006h
Typical timeout per single byte/word write 2N µs
20h
40h
0006h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
0009h
Typical timeout per individual block erase 2N ms
22h
44h
0013h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0003h
Max. timeout for byte/word write 2N times typical
24h
48h
0005h
Max. timeout for buffer write 2N times typical
25h
4Ah
0003h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0002h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7.3 Device Geometry Definition
Addresses (x16)
Addresses (x8)
Data
Description
N
10
Device Size = 2 byte
27h
4Eh
001Bh
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0006h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0001h
Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
0000h
000xh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FFh, 0003h, 0000h, 0002h =1 Gb
00FFh, 0001h, 0000h, 0002h = 512 Mb
00FFh, 0000h, 0000h, 0002h = 256 Mb
007Fh, 0000h, 0000h, 0002h = 128 Mb
31h
32h
33h
34h
60h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
1Bh = 1 Gb
S70GL-P MirrorBitTM Flash Family
S70GL-P_00_01 December 4, 2006
D at a
S hee t
(Adva nce
In for m ation)
Table 7.4 Primary Vendor-Specific Extended Query
Addresses (x16)
Addresses (x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII
44h
88h
0033h
Minor version number, ASCII
45h
8Ah
0014h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Process Technology (Bits 7-2) 0101b = 90 nm MirrorBit
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
90h
0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0008h
Sector Protect/Unprotect scheme
0008h = Advanced Sector Protection
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0002h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
00B5h
4Eh
9Ch
00C5h
4Fh
9Eh
00xxh
50h
A0h
0001h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
WP# Protection
December 4, 2006 S70GL-P_00_01
04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP#
protect
Program Suspend
00h = Not Supported, 01h = Supported
S70GL-P MirrorBitTM Flash Family
11
Data
8.
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Revision Summary
Section
Description
Revision A0 (December 4, 2006)
Initial Release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
12
S70GL-P MirrorBitTM Flash Family
S70GL-P_00_01 December 4, 2006