S71NS-N MCP Products MirrorBitTM 1.8 Volt-only Simultaneous Read/Write, Burst-mode Multiplexed Flash Memory: 256 Mb (16 Mb x 16-bit), 128 Mb (8 Mb x 16-bit) and 64 Mb (4 Mb x 16-bit) with Burst-mode Multiplexed pSRAM: 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit) and 16 Mb (1 Mb x 16-bit) ADVANCE INFORMATION Data Sheet Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. Publication Number S71NS-N_00 Revision A Amendment 3 Issue Date October 10, 2006 A d v a n c e I n f o r m a t i o n Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office. ii S71NS-N_00_A3 October 10, 2006 S71NS-N MCP Products MirrorBitTM 1.8 Volt-only Simultaneous Read/Write, Burst-mode Multiplexed Flash Memory: 256 Mb (16 Mb x 16-bit), 128 Mb (8 Mb x 16-bit) and 64 Mb (4 Mb x 16-bit) with Burst-mode Multiplexed pSRAM: 64 Mb (4 Mb x 16-bit), 32 Mb (2 Mb x 16-bit) and 16 Mb (1 Mb x 16-bit) ADVANCE INFORMATION General Description The S71NS-N Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of the following items: One or more S29NS-N flash memory die Mux burst-mode pSRAM The products covered by this document are listed in the table below. For details about their specifications, please refer to their individual datasheet for further details. pSRAM Flash Density 16 Mb 64 Mb S71NS064NA0 128 Mb S71NS128NA0 256 Mb 32 Mb 64 Mb S71NS128NB0 S71NS128NC0 S71NS256NB0 S71NS256NC0 Distinctive Characteristics MCP Features Power supply voltage of 1.7 V to 1.95 V Burst Speed: 66 MHz Package - MCP BGA: 0.5 mm ball pitch — 8.0 x 9.2 mm, 56 ball for NS064N and NS128N based MCPs — 10.0 x 11.0 mm, 60 ball for NS256N based MCPs Operating Temperature — Wireless, –25°C to +85°C For detailed specifications, please refer to the individual data sheets: Document Publication Identification Number S29NS-N S29NS-N_00 16 M Multiplexed pSRAM Type 2 muxpsram_05 16 M Multiplexed pSRAM Type 3 muxpsram_03 32 M Multiplexed pSRAM Type 3 muxpsram_04 64 M Multiplexed pSRAM Type 3 muxpsram_01 Publication Number S71NS-N_00 Revision A Amendment 3 Issue Date October 10, 2006 A d v a n c e 1 I n f o r m a t i o n Ordering Information The ordering part number is formed by a valid combination of the following: S71NS 128 N C 0 BJ W R N 0 Packing 0 = 2 = 3 = Type Tray 7-inch Tape and Reel 13-inch Tape and Reel RAM Supplier and Speed Combinations N = pSRAM Type 3, 70 ns, 66 MHz T = pSRAM Type 2, 70 ns, 66 MHz Package Modifier R = 1.2 mm, 8.0 x 9.2, 56-ball VFBGA V = 1.2 mm, 11 x 10 mm, 60-ball VFBGA Temperature Range W = Wireless (-25°C to +85°C) Package Type BJ = Very Thin Fine-Pitch Ball Grid Array (VFBGA) Lead (Pb)-free Package (LF35) Chip Contents—2 No content pSRAM Density C = 64 Mb B = 32 Mb A = 16 Mb Process Technology N = 110 nm MirrorBit Technology Flash 256 128 064 Density = 256 Mb = 128 Mb = 64 Mb Device Family S71NS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst Mode Multiplexed Flash Memory + pSRAM Table 1.1 Base Ordering Part Number (Note 2) Package & Temperature S71NS064NA0 S71NS128NA0 S71NS128NB0 MCP Configurations and Valid Combinations Model Number Packing Type S71NS128NC0 Flash Speed Options pSRAM Speed Options RT pSRAM Type 2 66 MHz 66 MHz RN pSRAM Type 3 66 MHz 66 MHz 66 MHz RN BJW pSRAM Type RN 0, 1, 2 RN pSRAM Type 3 66 MHz pSRAM Type 3 66 MHz 66 MHz pSRAM Type 3 66 MHz 66 MHz S71NS256NB0 VN pSRAM Type 3 66 MHz 66 MHz S71NS256NC0 VN pSRAM Type 3 66 MHz 66 MHz Package Marking Note: The package marking omits the leading S from the ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 2 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006 A d v a n c e 2 I n f o r m a t i o n Input/Output Descriptions Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Symbol Input/Output Descriptions Flash RAM AMAX – A16 Address inputs Description X X ADQ15 – ADQ0 Multiplexed Address/Data X X OE# Output Enable input. Asynchronous relative to CLK for the Burst mode. X X WE# Write Enable input. X X VSS Ground X X NC No Connect; not connected internally X X RDY Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY. X X CLK Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode X X AVD# Address Valid input. Indicates to device that the valid address is present on the address inputs. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs X X F-RST# Hardware reset input. Low = device resets and returns to reading array data X F-WP# Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. X F-ACC Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. X R-CE1# Chip-enable input for pSRAM. F-CE# Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. R-CRE Control Register Enable (pSRAM). F-VCC Flash 1.8 Volt-only single power supply. X X X X R-VCC pSRAM Power Supply. X R-UB# Upper Byte Control (pSRAM). X R-LB# Lower Byte Control (pSRAM) X DNU Do Not Use October 10, 2006 S71NS-N_00_A3 S71NS-N MCP Products 3 A d v a n c e 3 I n f o r m a t i o n MCP Block Diagram Figure 3.1 F-RST# RST# F-ACC F-WP# F-CE # OE# WE# AVD # CLK ACC WP# CE# OE# WE# AVD # CLK Amax-A16 MCP Block Diagram NS RDY AD15-AD0 RDY/ WAIT AD15-AD0 Amax-A16 R-CE# OE# WE# AVD # CLK CE # R-CRE R-UB # R-LB # CRE UB # LB# pSRAM WAIT AD15-AD0 Amax-A16 Note: The CLK and WAIT signals on the pSRAM are not present on the pSRAM Type 2; therefore, for those MCP's, those signals will only be connected to the NS flash, but not to the pSRAM. Also, on this pSRAM, the CRE signal will not be present at all. 4 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006 A d v a n c e 4 I n f o r m a t i o n Connection Diagrams/Physical Dimensions This section contains the I/O designations and package specifications for the S71NS-N. 4.1 Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 4.2 Connection Diagrams 4.2.1 pSRAM Based Pinout, 56-Ball, VFBGA 56-ball Fine-Pitch Ball Grid Array pSRAM-Based Pinout (Top View, Balls Facing Down) Legend A1 A14 NC NC C3 C4 C7 C8 C11 C12 NC RFU R-LB# R-UB# RFU NC D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 F-RDY/ R-WAIT A21 VSS CLK VCC WE# F-ACC A19 A17 A22 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 VCCQ A16 A20 AVD# DNU F-RST# F-WP# A18 F-CE# VSSQ F6 F7 F3 F4 F5 VSS A/DQ7 A/DQ6 G3 G4 A/DQ15 A/DQ14 A/DQ13 A/DQ12 G5 G6 G7 VSSQ A/DQ5 A/DQ4 F8 F9 F10 F11 F12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# G8 G9 A/DQ11 A/DQ10 G10 G11 G12 VCCQ A/DQ1 A/DQ0 H3 H4 H7 H8 H11 H12 NC RFU R-CE# R-CRE RFU NC No Connect (Distance between outer NC balls is 2x pitch) Reserved for Future Use Flash/RAM Shared Only Flash Only RAM Only K3 K14 NC NC Notes: 1. 2. Addresses are shared between Flash and RAM depending on the density of the pSRAM. CLK and WAIT signals are Flash only for the S71NS064NA0-RT, while on that MCP, the CRE signal won't exist. MCP Flash-Only Addresses Shared Addresses S71NS128NC0 A22 A21-A16 ADQ15 – ADQ0 S71NS128NB0 A22-A21 A20-A16 ADQ15 – ADQ0 S71NS128NA0 A22-A20 A19-A16 ADQ15 – ADQ0 S71NS064NA0 A21-A20 A19-A16 ADQ15 – ADQ0 Figure 4.1 October 10, 2006 S71NS-N_00_A3 Shared ADQ Pins pSRAM Based Pinout, 56-Ball, VFBGA S71NS-N MCP Products 5 A d v a n c e 4.2.2 I n f o r m a t i o n pSRAM Based Pinout, 60-Ball, VFBGA A1 A18 NC NC C3 C16 NC NC E5 E6 E9 E10 E13 E14 NC RFU R-LB# R-UB# RFU NC F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F-RDY/ R-WAIT A21 VSS CLK VCC WE# F-ACC A19 A17 A22 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 VCCQ A16 A20 AVD# A23 F-RST# F-WP# A18 F-CE# VSSQ H8 H9 H5 H6 H7 VSS A/DQ7 A/DQ6 J5 J6 J7 J8 J9 VSSQ A/DQ5 A/DQ4 A/DQ15 A/DQ14 A/DQ13 A/DQ12 H10 H11 H12 H13 H14 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# J10 J11 J12 J13 J14 VCCQ A/DQ1 A/DQ0 A/DQ11 A/DQ10 K5 K6 K9 K10 K13 K14 NC RFU R-CE# R-CRE RFU NC Legend No Connect (Distance between outer NC balls is 2x pitch) Reserved for Future Use Flash/RAM Shared Only Flash Only RAM Only M3 M16 NC NC P1 P18 NC NC Note: Addresses are shared between Flash and RAM depending on the density of the pSRAM. MCP Flash-Only Addresses Shared Addresses S71NS256NC0 A23-A22 A21–A16 Shared ADQ Pins ADQ15 – ADQ0 S71NS256NB0 A23-A21 A20-A16 ADQ15 – ADQ0 Figure 4.2 pSRAM Based Pinout, 60-Ball, VFBGA 6 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006 A d v a n c e 4.2.3 I n f o r m a t i o n Look Ahead Connection Diagram 112-ball x16 MUX NOR Flash + x16 MUX pSRAM on Shared Bus and x16 NAND Interface ORNAND on Bus 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Legend A NC NC NC NC NOR Flash/pSRAM Shared Only B No Connect C NC NC NC NC NC NC Do Not Use D NC NC DNU DNU N-IO7 N-IO15 NC N-IO5 N-IO13 N-IO6 N-IO14 A17 A22 N-IO4 N-IO12 NC NOR Flash 1 Only E DNU N-RDY N2-CE# F2-CE# R-LB# R-UB# WE# pSRAM Only F N1-CE# N-RE# F-RDY/ R-WAIT A21 VSS CLK VCC N-VCC N-VCC VCCQ A16 A20 AVD# A23 VSS A/DQ7 F-ACC A19 F-RST# F-WP# A18 G ORNAND Flash Only F1-CE# VSSQ N-IO11 N-PRE H NOR Flash 2 Only N-VSS N-VSS A/DQ6 A/DQ13 A/DQ12 A/DQ3 N-CLE N-ALE A/DQ15 A/DQ14 VSSQ A/DQ2 A/DQ9 A/DQ8 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 OE# VCC VSS J A/DQ5 NOR Flash Shared Only A/DQ0 N-IO18 N-IO3 N-IO1 N-IO9 N-IO2 N-IO0 N-IO8 NC NC NC NC NC K DNU N-WE# N-WP# A24 R-CE# R-CRE VSS L NC NC DNU NC NC NC DNU M N NC NC NC NC P Figure 4.3 Look Ahead Connection Diagram 112-ball x16 MUX NOR Flash + x16 MUX pSRAM on Shared Bus and x16 NAND Interface ORNAND on Bus 2 October 10, 2006 S71NS-N_00_A3 S71NS-N MCP Products 7 A d v a n c e 4.3 I n f o r m a t i o n Physical Dimensions 4.3.1 NLB056—9.2 x 8.0 mm, 56-ball VFBGA D1 A D eD 0.10 C (2X) 14 13 12 11 10 9 8 7 6 5 4 3 E eE SE 7 E1 2 1 K J H G F E D C B A INDEX MARK PIN A1 CORNER B 9 TOP VIEW PIN A1 CORNER 7 SD 0.10 C (2X) BOTTOM VIEW 0.20 C A A2 A1 C 56X 0.08 C SIDE VIEW 6 b 0.15 M C A B 0.08 M C NOTES: PACKAGE NLB 056 JEDEC N/A DxE 9.20 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.20 --- --- A2 0.85 --- 0.97 NOTE PROFILE 9.20 BSC. BODY SIZE 8.00 BSC. BODY SIZE D1 4.50 BSC. MATRIX FOOTPRINT E1 6.50 BSC. MATRIX FOOTPRINT MD 10 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION 56 0.25 ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.30 0.35 eE 0.50 BSC. BALL PITCH 0.50 BSC BALL PITCH 0.25 BSC. SOLDER BALL PLACEMENT A2 ~ A13,B1 ~ B14 C1,C2,C5,C6,C9,C10,C13,C14 D1,D2,D13,D14,E1,E2,E13,E14,F1,F2,F13,F14 G1,G2,G13,G14,H1,H2,H5,H6,H9,H10,H13,H14 J1 ~ J14, K2 ~ K13 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eD SD / SE 2. BALL HEIGHT E n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BODY THICKNESS D Øb 1. DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3507\ 16-038.22 \ 7.14.5 Figure 4.4 Physical Dimensions, NLB056—56-ball VFBGA 8 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006 A d v a n c e 4.3.1 I n f o r m a t i o n NLA060—11.0 x 10.0 mm, 60-ball VFBGA A D D1 eD 0.15 C (2X) E eE 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 E1 P N ML K J H GF E D C B A INDEX MARK PIN A1 CORNER SE B 9 TOP VIEW PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW 0.20 C A A2 A1 C 0.08 C SIDE VIEW 6 b 60X 0.15 M C A B 0.08 M C NOTES: PACKAGE NLA 060 JEDEC N/A DxE 10.95 mm x 9.95 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.20 --- --- A2 0.85 --- 0.97 e REPRESENTS THE SOLDER BALL GRID PITCH. BALL HEIGHT SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BODY THICKNESS SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. E 9.95 BSC. BODY SIZE 6.50 BSC. MATRIX FOOTPRINT E1 8.50 BSC. MD 14 MATRIX SIZE D DIRECTION MATRIX FOOTPRINT ME 18 MATRIX SIZE E DIRECTION 60 n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.35 eE 0.50 BSC. BALL PITCH 0.50 BSC BALL PITCH 0.25 BSC. A2~A17,B1~B18,C1,C2,C4~C15,C17,C18 D1~D18,E1,E2,E3,E4,E7,E8,E11,E12,E15,E16,E17,E18 F1,F2,F3,F4,F15,F16,F17,F18,G1,G2,G3,G4,G15,G16,G17,G18 H1,H2,H3,H4,H15,H16,H17,H18,J1,J2,J3,J4,J15,J16,J17,J18 K1,K2,K3,K4,K7,K8,K11,K12,K15,K16,K17,K18 L1 ~L18,M1,M2,M4~M15,M17,M18,N1~N18,P2~P17 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eD SD / SE BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 5. D1 0.30 ALL DIMENSIONS ARE IN MILLIMETERS. 3. 4. BODY SIZE 0.25 2. PROFILE 10.95 BSC. n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. NOTE D Øb 1. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 SOLDER BALL PLACEMENT 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. DEPOPULATED SOLDER BALLS 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3483 \ 16-038.22 \ 3.11.5 Figure 4.5 Physical Dimensions, NLA060—60-ball VFBGA October 10, 2006 S71NS-N_00_A3 S71NS-N MCP Products 9 A d v a n c e 5 I n f o r m a t i o n Revisions Revision A0 (January 3, 2006) Initial Release under Publication Identification Number S71NS128NC0_01 Revision A1 (March 1, 2006) Changed the Publication Identification Number from S71NS128NC0_01 to S71NS-N_00 Added the MCP S71NS064NA0 Revision A2 (June 13, 2006) Corrected the grid reference for 56-ball connection diagram Revision A3 (October 10, 2006) Added the S71NS064NA0-RT - the one using pSRAM Type 2 Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion Inc. product under development by Spansion Inc. Spansion Inc. reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion Inc. assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. 10 S71NS-N MCP Products S71NS-N_00_A3 October 10, 2006