SPANSION S71PL129JC0_06

S71PL129JC0/S71PL129JB0/S71PL129JA0
Stacked Multi-Chip Product (MCP) Flash Memory and
pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only
Simultaneous Operation, Page Mode Flash Memory with
64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM
ADVANCE
INFORMATION
Data Sheet
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S71PL129Jxx_00
Revision A
Amendment 8
Issue Date October 28, 2005
A d v a n c e
I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product
may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO range. Changes
may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
S71PL129JC0/S71PL129JB0/S71PL129JA0
Stacked Multi-Chip Product (MCP) Flash Memory and
pSRAM 128 Megabit (8M x 16-bit) CMOS 3.0 Volt-only
Simultaneous Operation, Page Mode Flash Memory with
64/32/16 Megabit (4M/2M/1M x 16-bit) Pseudo-Static RAM
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
MCP Features
„
„
Power supply voltage of 2.7 to 3.1 volt
„
High performance
„
Package
— 8 x 11.6 x 1.2 mm 64 ball FBGA
Operating Temperature
— –25°C to +85°C (Wireless)
— 65ns (65ns Flash, 70ns pSRAM)
— –40°C to +85°C (Industrial)
„ Dual CE# Flash memory
General Description
The S71PL129J series is a product line of stacked Multi-Chip Product (MCP) packages and consists of:
„ One S29PL129J Flash memory die
„ One 16M, 32M, or 64M pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheets for
further details.
Flash Memory Density
128Mb
pSRAM
Density
64Mb
S71PL129JC0
32Mb
S71PL129JB0
16Mb
S71PL129JA0
Publication Number S71PL129Jxx_00
Revision A
Amendment 8
Issue Date October 28, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
Product Selector Guide
128 Mb Flash Memory
2
Device-Model#
pSRAM density
Flash Access time (ns) (p)SRAM Access time (ns) pSRAM type
S71PL129JA0-9P
16M pSRAM
65
70
Type 7
TLA064
S71PL129JB0-9Z
32M pSRAM
65
70
Type 7
TLA064
S71PL129JB0-9B
32M pSRAM
65
70
Type 2
TLA064
S71PL129JB0-9U
32M pSRAM
65
70
Type 6
TLA064
S71PL129JC0-9B
64M pSRAM
65
70
Type 2
TLA064
S71PL129JC0-9Z
64M pSRAM
65
70
Type 7
TLA064
S71PL129JC0-9U
64M pSRAM
65
70
Type 6
TLA064
S71PL129JC0/S71PL129JB0/S71PL129JA0
Package
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
S71PL129JC0/S71PL129JB0/S71PL129JA0
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information .......................................................................................ii
Preliminary ..........................................................................................................ii
Combination .......................................................................................................ii
Full Production (No Designation on Document) ...................................ii
S71PL129JC0/S71PL129JB0/S71PL129JA0
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
128 Mb Flash Memory ..........................................................................................2
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7
Input/Output Description . . . . . . . . . . . . . . . . . . . 8
Pin Description ......................................................................................................8
Logic Symbol ...........................................................................................................8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 11
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ............................................................................................ 11
Password Protection Mode . . . . . . . . . . . . . . . . . 35
Password and Password Mode Locking Bit ................................................ 36
64-bit Password .................................................................................................. 36
Write Protect (WP#) ....................................................................................... 36
Persistent Protection Bit Lock ................................................................... 37
High Voltage Sector Protection ..................................................................... 37
Figure 1. In-System Sector Protection/Sector Unprotection
Algorithms........................................................................ 38
Temporary Sector Unprotect ........................................................................ 39
Figure 2. Temporary Sector Unprotect Operation ................... 39
Secured Silicon Sector Flash Memory Region ........................................... 39
Factory-Locked Area (64 words) ..............................................................40
Customer-Lockable Area (64 words) ......................................................40
Secured Silicon Sector Protection Bits ....................................................40
Figure 3. Secured Silicon Sector Protect Verify ...................... 41
Hardware Data Protection ..............................................................................41
Low VCC Write Inhibit .................................................................................41
Write Pulse “Glitch” Protection ................................................................ 41
Logical Inhibit ....................................................................................................41
Power-Up Write Inhibit ................................................................................ 41
Common Flash Memory Interface (CFI) . . . . . . 42
S29PL129J for MCP
General Description . . . . . . . . . . . . . . . . . . . . . . . . 14
Simultaneous Read/Write Operation with Zero Latency ...................... 14
Page Mode Features ........................................................................................... 14
Standard Flash Memory Features ................................................................... 14
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 19
Table 1. PL129J Device Bus Operations ................................ 19
Requirements for Reading Array Data ......................................................... 19
Random Read (Non-Page Read) ............................................................... 20
Page Mode Read ............................................................................................. 20
Table 2. Page Select .......................................................... 20
Simultaneous Read/Write Operation .......................................................... 20
Writing Commands/Command Sequences ................................................. 21
Accelerated Program Operation ............................................................... 21
Autoselect Functions ..................................................................................... 21
Standby Mode ........................................................................................................21
Automatic Sleep Mode ..................................................................................... 22
RESET#: Hardware Reset Pin ........................................................................ 22
Output Disable Mode ....................................................................................... 22
Table 3. S29PL129J Sector Architecture ............................... 23
Table 4. Secured Silicon Sector Addresses ............................ 29
Autoselect Mode ................................................................................................ 29
Table 5. Autoselect Codes for PL129J ................................... 30
Table 6. PL129J Boot Sector/Sector Block Addresses for Protection/
Unprotection ..................................................................... 31
Selecting a Sector Protection Mode ..............................................................32
Table 7. Sector Protection Schemes ..................................... 32
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 32
Persistent Sector Protection ...........................................................................32
Password Sector Protection ............................................................................32
WP# Hardware Protection .............................................................................32
Selecting a Sector Protection Mode ..............................................................32
Persistent Sector Protection . . . . . . . . . . . . . . . . 33
October 28, 2005 S71PL129Jxx_00_A8
Persistent Protection Bit (PPB) .......................................................................33
Persistent Protection Bit Lock (PPB Lock) ..................................................33
Dynamic Protection Bit (DYB) ........................................................................33
Persistent Sector Protection Mode Locking Bit ....................................... 35
Table 8. CFI Query Identification String ................................ 42
Table 9. System Interface String ......................................... 43
Table 10. Device Geometry Definition ................................... 43
Table 11. Primary Vendor-Specific Extended Query ................ 43
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 45
Reading Array Data ........................................................................................... 45
Reset Command ................................................................................................. 45
Autoselect Command Sequence ....................................................................46
Enter Secured Silicon Sector/Exit Secured Silicon
Sector Command Sequence ............................................................................46
Word Program Command Sequence ...........................................................46
Unlock Bypass Command Sequence ........................................................ 47
Figure 4. Program Operation ............................................... 48
Chip Erase Command Sequence ...................................................................48
Sector Erase Command Sequence ................................................................49
Figure 5. Erase Operation ................................................... 50
Erase Suspend/Erase Resume Commands ..................................................50
Password Program Command ........................................................................ 51
Password Verify Command .............................................................................. 51
Password Protection Mode Locking Bit Program Command ............... 51
Persistent Sector Protection Mode Locking Bit Program Command 52
Secured Silicon Sector Protection Bit Program Command .................. 52
PPB Lock Bit Set Command ............................................................................ 52
DYB Write Command ...................................................................................... 52
Password Unlock Command .......................................................................... 52
PPB Program Command .................................................................................. 53
All PPB Erase Command .................................................................................. 53
DYB Write Command ...................................................................................... 53
PPB Lock Bit Set Command ............................................................................ 53
Command ............................................................................................................. 54
Command Definitions Tables ......................................................................... 54
Table 12. Memory Array Command Definitions ...................... 54
Table 13. Sector Protection Command Definitions .................. 55
Write Operation Status . . . . . . . . . . . . . . . . . . . . 56
DQ7: Data# Polling ............................................................................................ 56
Figure 6. Data# Polling Algorithm ........................................ 58
S71PL129JC0/S71PL129JB0/S71PL129JA0
3
A d v a n c e
RY/BY#: Ready/Busy# .......................................................................................58
DQ6: Toggle Bit I ............................................................................................... 58
Figure 7. Toggle Bit Algorithm.............................................. 60
DQ2: Toggle Bit II .............................................................................................. 60
Reading Toggle Bits DQ6/DQ2 ..................................................................... 60
DQ5: Exceeded Timing Limits ........................................................................ 61
DQ3: Sector Erase Timer ................................................................................. 61
Table 14. Write Operation Status ......................................... 62
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 63
Figure 8. Maximum Overshoot Waveforms............................. 63
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .64
Industrial (I) Devices ......................................................................................... 64
Extended (E) Devices ........................................................................................ 64
Supply Voltages ................................................................................................... 64
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 15. CMOS Compatible ................................................ 65
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .66
Test Conditions .................................................................................................. 66
Figure 9. Test Setups......................................................... 66
Table 16. Test Specifications ............................................... 66
I n f o r m a t i o n
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 81
AC Characteristics and Operating Conditions . 82
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 83
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Read Timings ........................................................................................................84
Figure 24. Read Cycle ........................................................ 84
Figure 25. Page Read Cycle (8 Words Access) ....................... 85
Write Timings ......................................................................................................86
Figure 26. Write Cycle #1 (WE# Controlled) (See Note 8)....... 86
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 87
Deep Power-down Timing ..............................................................................87
Figure 28. Deep Power Down Timing .................................... 87
Power-on Timing ................................................................................................87
Figure 29. Power-on Timing ................................................ 87
Provisions of Address Skew ............................................................................88
Read ....................................................................................................................88
Figure 30. Read................................................................. 88
Write ..................................................................................................................88
Figure 31. Write ................................................................ 88
pSRAM Type 1
Switching Waveforms ....................................................................................... 66
Table 17. Key to Switching Waveforms ................................. 66
Figure 10. Input Waveforms and Measurement Levels............. 67
VCC RampRate ...................................................................................................67
Read Operations .................................................................................................67
Table 18. Read-Only Operations .......................................... 67
Figure 11. Read Operation Timings ....................................... 68
Figure 12. Page Read Operation Timings ............................... 68
Reset ...................................................................................................................... 69
Table 19. Hardware Reset (RESET#) .................................... 69
Figure 13. Reset Timings..................................................... 69
Erase/Program Operations ............................................................................. 70
Table 20. Erase and Program Operations .............................. 70
Timing Diagrams ...................................................................................................71
Figure 14. Program Operation Timings .................................. 71
Figure 15. Accelerated Program Timing Diagram .................... 71
Figure 16. Chip/Sector Erase Operation Timings ..................... 72
Figure 17. Back-to-back Read/Write Cycle Timings ................. 73
Figure 18. Data# Polling Timings
(During Embedded Algorithms) ............................................ 73
Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 74
Figure 20. DQ2 vs. DQ6 ...................................................... 74
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 21. Temporary Sector Unprotect ................................. 75
Figure 21. Temporary Sector Unprotect Timing Diagram.......... 75
Figure 22. Sector/Sector Block Protect and Unprotect Timing
Diagram............................................................................ 76
Controlled Erase Operations ..........................................................................77
Table 22. Alternate CE# Controlled Erase and
Program Operations ........................................................... 77
Table 23. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ............................................................. 78
Table 24. CE1#/CE2# Timing ............................................. 78
Figure 23. Timing Diagram for Alternating Between CE1# and CE2#
Control ............................................................................. 79
Table 25. Erase And Programming Performance .................... 79
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 79
pSRAM Type 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Functional Description . . . . . . . . . . . . . . . . . . . . . 81
4
Functional Description . . . . . . . . . . . . . . . . . . . . . 89
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 89
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 90
Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 95
Output Load Circuit ..........................................................................................96
Figure 32. Output Load Circuit............................................. 96
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 96
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 97
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 108
Read Cycle .......................................................................................................... 108
Figure 33. Timing of Read Cycle
(CE# = OE# = VIL, WE# = ZZ# = VIH) .............................. 108
Figure 34. Timing Waveform of Read Cycle
(WE# = ZZ# = VIH)......................................................... 109
Figure 35. Timing Waveform of Page Mode Read Cycle
(WE# = ZZ# = VIH)......................................................... 110
Write Cycle ...........................................................................................................111
Figure 36. Timing Waveform of Write Cycle
(WE# Control, ZZ# = VIH)................................................ 111
Figure 37. Timing Waveform of Write Cycle
(CE# Control, ZZ# = VIH)................................................. 111
Figure 38. Timing Waveform of Page Mode Write Cycle
(ZZ# = VIH) ................................................................... 112
Partial Array Self Refresh (PAR) ....................................................................112
Temperature Compensated Refresh (for 64Mb) .....................................113
Deep Sleep Mode ...............................................................................................113
Reduced Memory Size (for 32M and 16M) ..................................................113
Other Mode Register Settings (for 64M) ....................................................113
Figure 39. Mode Register .................................................. 114
Figure 40. Mode Register Update Timings (UB#, LB#, OE# are
Don’t Care)..................................................................... 114
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)... 115
Figure 42. Deep Sleep Mode - Entry/Exit Timings
(for 32M and 16M)........................................................... 115
Type 2 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Product Information . . . . . . . . . . . . . . . . . . . . . . 119
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . 120
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 121
(Under Recommended Conditions Unless Otherwise Noted) ..........136
Power Up ............................................................................................................. 121
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 43. Power Up 1 (CS1# Controlled) ............................ 121
Figure 44. Power Up 2 (CS2 Controlled) .............................. 121
(Under Recommended Operating Conditions
Unless Otherwise Noted) .............................................................................. 137
Read Operation ................................................................................................. 137
Functional Description . . . . . . . . . . . . . . . . . . . . . 121
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 122
DC Recommended Operating Conditions . . . . 122
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DC and Operating Characteristics . . . . . . . . . . 123
Common .............................................................................................................. 123
16M pSRAM ......................................................................................................... 124
32M pSRAM ........................................................................................................ 124
64M pSRAM ........................................................................................................ 125
128M pSRAM ....................................................................................................... 125
AC Operating Conditions . . . . . . . . . . . . . . . . . 126
Figure 45. Output Load ..................................................... 126
AC Characteristics ........................................................................................... 127
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 128
Read Timings ......................................................................................................128
Figure 46. Timing Waveform of Read Cycle(1)...................... 128
Figure 47. Timing Waveform of Read Cycle(2)...................... 128
Figure 48. Timing Waveform of Page Cycle (Page Mode Only) 129
Write Timings .................................................................................................... 129
Figure 49. Write Cycle #1 (WE# Controlled) ........................
Figure 50. Write Cycle #2 (CS1# Controlled) .......................
Figure 51. Timing Waveform of Write Cycle(3)
(CS2 Controlled) ..............................................................
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB#
Controlled) ......................................................................
129
130
130
131
pSRAM Type 7
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 138
Write Operation ...............................................................................................138
Power Down Parameters ...............................................................................139
Other Timing Parameters ...............................................................................139
AC Test Conditions .........................................................................................140
AC Measurement Output Load Circuits ...................................................140
Figure 53. AC Output Load Circuit – 16 Mb.......................... 140
Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb .......... 140
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 141
Read Timings ........................................................................................................141
Figure 55. Read Timing #1 (Basic Timing) .......................... 141
Figure 56. Read Timing #2 (OE# Address Access................. 141
Figure 57. Read Timing #3 (LB#/UB# Byte Access) ............. 142
Figure 58. Read Timing #4 (Page Address Access after CE1#
Control Access for 32M and 64M Only) ............................... 142
Figure 59. Read Timing #5 (Random and Page Address Access for
32M and 64M Only) ......................................................... 143
Write Timings .....................................................................................................143
Figure 60. Write Timing #1 (Basic Timing) ..........................
Figure 61. Write Timing #2 (WE# Control)..........................
Figure 62. Write Timing #3-1
(WE#/LB#/UB# Byte Write Control) ..................................
Figure 63. Write Timing #3-3
(WE#/LB#/UB# Byte Write Control) ..................................
Figure 64. Write Timing #3-4
(WE#/LB#/UB# Byte Write Control) ..................................
144
145
145
Read/Write Timings ..........................................................................................146
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Functional Description . . . . . . . . . . . . . . . . . . . . . 133
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 133
Power Down .......................................................................................................133
Power Down Program Sequence ..................................................................133
Address Key ....................................................................................................... 134
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 135
Recommended Operating Conditions . . . . . . . 135
(See Warning Below) ........................................................................................135
Figure 65. Read/Write Timing #1-1 (CE1# Control) .............
Figure 66. Read / Write Timing #1-2
(CE1#/WE#/OE# Control) ................................................
Figure 67. Read / Write Timing #2 (OE#, WE# Control) .......
Figure 68. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control) ........................................
Figure 69. Power-up Timing #1 .........................................
Figure 70. Power-up Timing #2 .........................................
Figure 71. Power Down Entry and Exit Timing .....................
Figure 72. Standby Entry Timing after Read or Write............
Figure 73. Power Down Program Timing (for 32M/64M Only).
Package Capacitance . . . . . . . . . . . . . . . . . . . . . 135
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 136
October 28, 2005 S71PL129Jxx_00_A8
143
144
S71PL129JC0/S71PL129JB0/S71PL129JA0
146
146
147
147
148
148
148
149
149
Revision Summary
5
A d v a n c e
I n f o r m a t i o n
MCP Block Diagram
VCCf
VCC
V
CC
CE1#f
CE2#f
WP#/ACC
RESET#
Flash-only Address
Flash 1
Shared Address
OE#
WE#
VSS
RY/BY#
VCCS
DQ15 to DQ0
VCC
pSRAM
IO15-IO0
CE#s
CE#
UB#s
UB#
LB#s
LB#
CE2#ps
CEM1#ps
6
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Connection Diagram
64-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A10
NC
NC
B5
B6
RFU
RFU
C3
C4
C5
C6
C7
C8
Legend
A7
LB#
WP/ACC
WE#
A8
A11
D2
D3
D4
D5
D6
D7
D8
D9
A3
A6
UB#
RST#f
CE2s
A19
A12
A15
E2
E3
E4
E5
E6
E7
E8
E9
A2
A5
A18
RY/BY#
A20
A9
A13
A21
F2
F3
F4
F7
F8
F9
A1
A4
A17
A10
A14
CE2#f
G2
G3
G4
G7
G8
G9
A0
VSS
DQ1
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
CE1#f
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J2
J3
J4
J5
J6
J7
J8
J9
CE1#s
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
K3
K4
K5
K6
K7
K8
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
L5
L6
RFU
RFU
Shared
(Note 1)
Flash only
RAM only
Reserved for
Future Use
M1
M10
NC
NC
Note: May be shared depending on density:
— A21 is shared for the 64M pSRAM configuration.
— A20 is shred for the 32M pSRAM configuration.
— A19 is shared for the 16M pSRAM configuration.
MCP
Flash-only Addresses
Shared Addresses
S71PL129JC0
A22
A21-A0
S71PL129JB0
A22-A21
A20-A0
S71PL129JA0
A22-A20
A19-A0
Note: It is advised to tie J5 and L5 together on the board.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
7
A d v a n c e
I n f o r m a t i o n
Input/Output Description
Pin Description
A21–A0
DQ15–DQ0
CE1#f
CE2#f
CE1#ps
CE2ps
OE#
WE#
RY/BY#
UB#
LB#
RESET#
WP#/ACC
VCCf
=
=
=
=
=
=
=
=
=
=
=
=
=
=
VCCps
VSS
NC
=
=
=
22 Address Inputs (Common)
16 Data Inputs/Outputs (Common)
Chip Enable 1 (Flash)
Chip Enable 2 (Flash)
Chip Enable 1 (pSRAM)
Chip Enable 2 (pSRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Hardware Reset Pin, Active Low (Flash 1)
Hardware Write Protect/Acceleration Pin (Flash)
Flash 3.0 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
pSRAM Power Supply
Device Ground (Common)
Pin Not Connected Internally
Logic Symbol
22
A21–A0
16
CE1#f
DQ15–DQ0
CE2#f
CE1#ps
CE2ps
RY/BY#
OE#
WE#
WP#/ACC
RESET#
UB#
LB#
8
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Ordering Information
The order number is formed by a valid combinations of the following:
S71PL
129
J
B0
BA
W
9
Z
0
PACKING TYPE
0
= Tray
2
= 7” Tape and Reel
3
= 13” Tape and Reel
MODEL NUMBER
See valid combinations table.
PACKAGE MODIFIER
9
= 8 x 11.6 mm, 1.2 mm height, 64 balls (TLA064)
TEMPERATURE RANGE
W
= Wireless (-25°C to +85°C)
I
= Industrial (-40°C to +85°C)
PACKAGE TYPE
BA
= Fine-pitch BGA Lead (Pb)-free compliant package
BF
= Fine-pitch BGA Lead (Pb)-free package
pSRAM
C0
=
B0
=
A0
=
DENSITY
64 Mb pSRAM
32 Mb pSRAM
16 Mb pSRAM
PROCESS TECHNOLOGY
J
= 110 nm, Floating Gate Technology
FLASH DENSITY
129 = 128Mb, dual CE#
PRODUCT FAMILY
S71PL Multi-chip Product (MCP)
3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
9
A d v a n c e
I n f o r m a t i o n
S71PL129J Valid Combinations
Base Ordering
Part Number
Package &
Temperature
Package Modifier/
Model Number
(p)SRAM
Type/Access
Time (ns)
S71PL129JA0
9P
pSRAM 7 / 70
S71PL129JB0
9Z
pSRAM 7 / 70
S71PL129JB0
9B
S71PL129JB0
BAW
9U
65
pSRAM 6 / 70
9B
pSRAM 2 / 70
S71PL129JC0
9Z
pSRAM 7 / 70
S71PL129JC0
9U
pSRAM 6 / 70
S71PL129JA0
9P
pSRAM 7 / 70
S71PL129JB0
9Z
pSRAM 7 / 70
S71PL129JB0
9B
pSRAM 2 / 70
BFW
9U
0, 2, 3 (Note 1)
65
(Note 2)
pSRAM 6 / 70
S71PL129JC0
9B
pSRAM 2 / 70
S71PL129JC0
9Z
pSRAM 7 / 70
S71PL129JC0
9U
pSRAM 6 / 70
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
3. Contact factory for availability of any of the above OPNs. RAM
type availability may vary over time.
Package
Marking
pSRAM 2 / 70
0, 2, 3 (Note 1)
S71PL129JC0
S71PL129JB0
10
Packing Type
Speed Options
(ns)
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Physical Dimensions
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package
D1
A
D
eD
0.15 C
10
(2X)
9
8
SE
7
7
6
E
E1
5
4
eE
3
2
1
M
INDEX MARK
PIN A1
CORNER
L
J
K
B
10
TOP VIEW
H
G
F
E
D
C B
A
PIN A1
CORNER
7
SD
0.15 C
(2X)
BOTTOM VIEW
A A2
0.20 C
A1
C
SIDE VIEW
6
0.08 C
b
64X
0.15
0.08
M C A B
M C
NOTES:
PACKAGE
TLA 064
JEDEC
N/A
DxE
11.60 mm x 8.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.17
---
---
A2
0.81
---
0.97
NOTE
PROFILE
11.60 BSC.
BODY SIZE
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
n
64
0.40
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
DEPOPULATED SOLDER BALLS
B1,B2,B3,B4,B7,B8,B9,B10
C1,C2,C9,C10,D1,D10,E1,E10,
F1,F5,F6,F10,G1,G5,G6,G10
H1,H10,J1,J10,K1,K2,K9,K10
L1,L2,L3,L4,L7,L8,L9,L10
M2,M3,M4,M5,M6,M7,M8,M9
October 28, 2005 S71PL129Jxx_00_A8
2.
BALL HEIGHT
E
0.35
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BODY THICKNESS
D
φb
1.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
S71PL129JC0/S71PL129JB0/S71PL129JA0
3352 \ 16-038.22a
11
S29PL129J for MCP
128 Megabit (8 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIOTM Control
Datasheet
ADVANCE
INFORMATION
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
„
128 Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
random locations within the page
„
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
„
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operations for battery-powered applications
„
„
Dual Chip Enable inputs (only in PL129J)
— Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 µA typical standby mode current
„
„
„
„
FlexBank Architecture
— 4 separate banks, with up to two simultaneous
operations per device
— CE#1 controlled banks:
Bank 1A:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B:
- 48Mbit (32Kw x 96)
— CE#2 controlled banks:
Bank 2A:
- 48 Mbit (32Kw x 96)
Bank 2B:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Enhanced VersatileI/OTM (VIO) Control
— Output voltage generated and input voltages
tolerated on all control inputs and I/Os is determined
by the voltage on the VIO pin
Software Features
„
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV,
Am29DL, and AM29PDL families and MBM29QM/RM,
MBM29LV, MBM29DL, MBM29PDL families
„
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
„
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or
program operations in other sectors of same bank
„
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
Hardware Features
„
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Secured Silicon Sector region
— Up to 128 words accessible through a command
sequence
„
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
— Up to 64 factory-locked words
„
WP#/ ACC (Write Protect/Acceleration) input
— At VIL, hardware level protection for the first and
last two 4K word sectors.
— At VIH, allows removal of sector protection
— At VHH, provides accelerated programming in a
factory setting
— Up to 64 customer-lockable words
„
Both top and bottom boot blocks in one device
„
Manufactured on 110 nm process technology
„
Data Retention: 20 years typical
„
Cycling Endurance: 1 million cycles per sector
typical
Publication Number S71PL129Jxx_00
Revision A
Amendment 8
Issue Date October 28, 2005
A d v a n c e
„
I n f o r m a t i o n
Persistent Sector Protection
— A command sector protection method to lock combinations of individual sectors and sector groups to prevent program
or erase operations within that sector
— Sectors can be locked and unlocked in-system at VCC level
„
Password Sector Protection
— A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent
program or erase operations within that sector using a user-defined 64-bit password
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
13
A d v a n c e
I n f o r m a t i o n
General Description
The PL129J is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write
Flash memory device organized as 8 Mwords.
The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not
required for write or erase operations.
The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed
microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Bank
PL129J Sectors
CE# Control
1A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE1#
1B
48 Mbit (32 Kw x 96)
CE1#
2A
48 Mbit (32 Kw x 96)
CE2#
2B
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE2#
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode
operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both
read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC 42.4 singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs
to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The
Unlock Bypass mode facilitates faster programming times by requiring only two
14
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
write cycles to program data instead of four. Device erasure occurs by executing
the erase command sequence.
The host system can detect whether a program or erase operation is complete by
reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector that
is not selected for erasure. True background erase can thus be achieved. If a read
is needed from the Secured Silicon Sector area (One Time Program area) after
an erase suspend, then the user must use the proper command sequence to
enter and exit this region.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consumption
is greatly reduced in both these modes.
The device electrically erases all bits within a sector simultaneously via FowlerNordheim tunneling. The data is programmed using hot electron injection.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
15
A d v a n c e
I n f o r m a t i o n
Block Diagram
DQ15–DQ0
RY/BY# (See Note)
VCC
VSS
Sector
Switches
VIO
RESET#
Input/Output
Buffers
Erase Voltage
Generator
WE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
Y-Gating
Timer
Address Latch
VCC Detector
Data Latch
Amax–A3
X-Decoder
Cell Matrix
A2–A0
Notes:
1. RY/BY# is an open drain output.
2. For PL129J there are two CE# (CE1# and CE2#)
16
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Simultaneous Read/Write Block Diagram (PL129J)
VCC
VSS
OE#
CE1#=L
CE2#=H
Mux
Bank 1A
Bank 1B
X-Decoder
A21–A0
RESET#
WE#
CE1#
CE2#
WP#/ACC
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ15–DQ0
Control
Mux
DQ15–DQ0
CE1#=H
CE2#=L
X-Decoder
Bank 2A Address
Bank 2A
X-Decoder
Bank 2B Address
Y-gate
A21–A0
DQ0–DQ15
A21–A0
DQ15–DQ0
Bank 1B Address
DQ15–DQ0
RY/BY#
DQ15–DQ0
A21–A0
X-Decoder
Y-gate
Bank 1A Address
A21–A0
Bank 2B
Mux
Notes:
1. Amax = A21 (PL129J)
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
17
A d v a n c e
I n f o r m a t i o n
Pin Description
Amax–A0
DQ15–DQ0
CE#
OE#
WE#
VSS
NC
RY/BY#
=
=
=
=
=
=
=
=
WP#/ACC
=
VIO
VCC
=
=
RESET#
CE1#, CE2#
=
=
Address bus
16-bit data inputs/outputs/float
Chip Enable Inputs
Output Enable Input
Write Enable
Device Ground
Pin Not Connected Internally
Ready/Busy output and open drain.
When RY/BY#= VIH, the device is ready to accept
read operations and commands. When RY/BY#=
VOL, the device is either executing an embedded
algorithm or the device is executing a hardware
reset operation.
Write Protect/Acceleration Input.
When WP#/ACC= VIL, the highest and lowest two
4K-word sectors are write protected regardless of
other sector protection configurations. When WP#/
ACC= VIH, these sector are unprotected unless the
DYB or PPB is programmed. When WP#/ACC= 12V,
program and erase operations are accelerated.
Input/Output Buffer Power Supply 2.7 V to 3.6 V
Chip Power Supply
(2.7 V to 3.6 V or 2.7 to 3.3 V)
Hardware Reset Pin
Chip Enable Inputs.
CE1# controls the 64Mb in Banks 1A and 1B. CE2#
controls the 64 Mb in Banks 2A and 2B.
Notes:
1. Amax = A21
Logic Symbol
max+1
Amax–A0
16
DQ15–DQ0
CE#
OE#
WE#
WP#/ACC
RESET#
RY/BY#
VIO (VCCQ)
18
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels required, and the resulting output. The following subsections describe each of these
operations in further detail.
Table 1.
PL129J Device Bus Operations
OE#
WE#
RESET#
WP#/ACC
Addresses
(A21–A0)
DQ15–
DQ0
L
H
H
X
AIN
DOUT
H
L
H
X
(Note 2)
AIN
DIN
VIO ±
0.3 V
X
X
VIO ±
0.3 V
X
X
High-Z
L
L
H
H
H
X
X
High-Z
Reset
X
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect
(High Voltage)
X
X
X
X
VID
X
AIN
DIN
Operation
CE1#
CE2#
L
H
H
L
L
H
H
L
VIO±
0.3 V
Output Disable
Read
Write
Standby
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 8.5–9.5 V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
““High Voltage Sector Protection” on page 37.”
2. WP#/ACC must be high when writing to upper two and lower two sectors.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE# pins to VIL. In PL129J, CE1# and CE2# are the power control and
select the lower (CE1#) or upper (CE2#) halves of the device. CE# is the power
control. OE# is the output control and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
See Table 24 for timing specifications and Figure 11 for the timing diagram. ICC1
in the DC Characteristics table represents the active current specification for
reading array data.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
19
A d v a n c e
I n f o r m a t i o n
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable addresses to valid
output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC–tOE time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. Address bits Amax–A3 select an 8 word page,
and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location.
The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to tPACC. When CE1# and CE#2 are deasserted (=VIH), the
reassertion of CE1# or CE#2 for subsequent access has access time of tACC or
tCE. Here again, CE1#/CE#2 selects the device and OE# is the output control and
should be used to gate data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping Amax–A3 constant and changing
A2–A0 to select the specific word within that page.
Table 2.
Page Select
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, and
erase-suspend program), the device is capable of reading data from one bank of
memory while a program or erase operation is in progress in another bank of
memory (simultaneous operation). The bank can be selected by bank addresses
(A21–A19) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
20
Bank
CE1#
CE2#
PL129J: A21–A20
Bank 1A
0
1
00
Bank 1B
0
1
01, 10, 11
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Bank 2A
1
0
00, 01, 10
Bank 2B
1
0
11
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE1# or CE#2 to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming.
Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word, instead of four. “Word Program Command Sequence” on page
46 has details on programming data to the device using both standard and Unlock
Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 4 indicates the set of address space that each sector occupies. A “bank address” is the set of address bits required to uniquely select a bank. Similarly, a
“sector address” refers to the address bits required to uniquely select a sector.
“Command Definitions” on page 45 has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
ICC2 in the DC Characteristics table represents the active current specification for
the write mode. See the timing specification tables and timing diagrams in “Reset” for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
function is primarily intended to allow faster manufacturing throughput at the
factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on
WP#/ACC for operations other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin should be raised to VCC when not in
use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15–DQ0. Standard
read cycle timings apply in this mode. See “Secured Silicon Sector Addresses” on
page 29 and “Autoselect Command Sequence” on page 46 for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
21
A d v a n c e
I n f o r m a t i o n
The device enters the CMOS standby mode when the CE1# or CE#2 and RESET#
pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage
range than VIH.) If CE1# or CE#2 and RESET# are held at VIH, but not within VIO
± 0.3 V, the device is in standby mode, but the standby current is greater. The
device requires standard access time (tCE) for read access when the device is in
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
ICC3 in “DC Characteristics” represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Note that during automatic sleep mode, OE# must be at VIH before
the device reduces current to the stated sleep mode specification. ICC5 in “DC
Characteristics” represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires
a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of tREADY (not during Embedded Algorithms).
The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 13
for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
(except for RY/BY#) are placed in the highest Impedance state
22
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
Table 3.
Bank 1A
Bank
I n f o r m a t i o n
S29PL129J Sector Architecture (Sheet 1 of 7)
Sector
CE1#
CE2#
Sector Address (A21A12)
Sector Size
(Kwords)
Address Range (x16)
SA1-0
0
1
0000000000
4
000000h–000FFFh
SA1-1
0
1
0000000001
4
001000h–001FFFh
SA1-2
0
1
0000000010
4
002000h–002FFFh
SA1-3
0
1
0000000011
4
003000h–003FFFh
SA1-4
0
1
0000000100
4
004000h–004FFFh
SA1-5
0
1
0000000101
4
005000h–005FFFh
SA1-6
0
1
0000000110
4
006000h–006FFFh
SA1-7
0
1
0000000111
4
007000h–007FFFh
SA1-8
0
1
0000001XXX
32
008000h–00FFFFh
SA1-9
0
1
0000010XXX
32
010000h–017FFFh
SA1-10
0
1
0000011XXX
32
018000h–01FFFFh
SA1-11
0
1
0000100XXX
32
020000h–027FFFh
SA1-12
0
1
0000101XXX
32
028000h–02FFFFh
SA1-13
0
1
0000110XXX
32
030000h–037FFFh
SA1-14
0
1
0000111XXX
32
038000h–03FFFFh
SA1-15
0
1
0001000XXX
32
040000h–047FFFh
SA1-16
0
1
0001001XXX
32
048000h–04FFFFh
SA1-17
0
1
0001010XXX
32
050000h–057FFFh
SA1-18
0
1
0001011XXX
32
058000h–05FFFFh
SA1-19
0
1
0001100XXX
32
060000h–067FFFh
SA1-20
0
1
0001101XXX
32
068000h–06FFFFh
SA1-21
0
1
0001110XXX
32
070000h–077FFFh
SA1-22
0
1
0001111XXX
32
078000h–07FFFFh
SA1-23
0
1
0010000XXX
32
080000h–087FFFh
SA1-24
0
1
0010001XXX
32
088000h–08FFFFh
SA1-25
0
1
0010010XXX
32
090000h–097FFFh
SA1-26
0
1
0010011XXX
32
098000h–09FFFFh
SA1-27
0
1
0010100XXX
32
0A0000h–0A7FFFh
SA1-28
0
1
0010101XXX
32
0A8000h–0AFFFFh
SA1-29
0
1
0010110XXX
32
0B0000h–0B7FFFh
SA1-30
0
1
0010111XXX
32
0B8000h–0BFFFFh
SA1-31
0
1
0011000XXX
32
0C0000h–0C7FFFh
SA1-32
0
1
0011001XXX
32
0C8000h–0CFFFFh
SA1-33
0
1
0011010XXX
32
0D0000h–0D7FFFh
SA1-34
0
1
0011011XXX
32
0D8000h–0DFFFFh
SA1-35
0
1
0011100XXX
32
0E0000h–0E7FFFh
SA1-36
0
1
0011101XXX
32
0E8000h–0EFFFFh
SA1-37
0
1
0011110XXX
32
0F0000h–0F7FFFh
SA1-38
0
1
0011111XXX
32
0F8000h–0FFFFFh
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
23
A d v a n c e
Table 3.
Bank 1B
Bank
24
I n f o r m a t i o n
S29PL129J Sector Architecture (Sheet 2 of 7)
Sector
CE1#
CE2#
Sector Address (A21A12)
Sector Size
(Kwords)
Address Range (x16)
SA1-39
0
1
0100000XXX
32
100000h–107FFFh
SA1-40
0
1
0100001XXX
32
108000h–10FFFFh
SA1-41
0
1
0100010XXX
32
110000h–117FFFh
SA1-42
0
1
0100011XXX
32
118000h–11FFFFh
SA1-43
0
1
0100100XXX
32
120000h–127FFFh
SA1-44
0
1
0100101XXX
32
128000h–12FFFFh
SA1-45
0
1
0100110XXX
32
130000h–137FFFh
SA1-46
0
1
0100111XXX
32
138000h–13FFFFh
SA1-47
0
1
0101000XXX
32
140000h–147FFFh
SA1-48
0
1
0101001XXX
32
148000h–14FFFFh
SA1-49
0
1
0101010XXX
32
150000h–157FFFh
SA1-50
0
1
0101011XXX
32
158000h–15FFFFh
SA1-51
0
1
0101100XXX
32
160000h–167FFFh
SA1-52
0
1
0101101XXX
32
168000h–16FFFFh
SA1-53
0
1
0101110XXX
32
170000h–177FFFh
SA1-54
0
1
0101111XXX
32
178000h–17FFFFh
SA1-55
0
1
0110000XXX
32
180000h–187FFFh
SA1-56
0
1
0110001XXX
32
188000h–18FFFFh
SA1-57
0
1
0110010XXX
32
190000h–197FFFh
SA1-58
0
1
0110011XXX
32
198000h–19FFFFh
SA1-59
0
1
0110100XXX
32
1A0000h–1A7FFFh
SA1-60
0
1
0110101XXX
32
1A8000h–1AFFFFh
SA1-61
0
1
0110110XXX
32
1B0000h–1B7FFFh
SA1-62
0
1
0110111XXX
32
1B8000h–1BFFFFh
SA1-63
0
1
0111000XXX
32
1C0000h–1C7FFFh
SA1-64
0
1
0111001XXX
32
1C8000h–1CFFFFh
SA1-65
0
1
0111010XXX
32
1D0000h–1D7FFFh
SA1-66
0
1
0111011XXX
32
1D8000h–1DFFFFh
SA1-67
0
1
0111100XXX
32
1E0000h–1E7FFFh
SA1-68
0
1
0111101XXX
32
1E8000h–1EFFFFh
SA1-69
0
1
0111110XXX
32
1F0000h–1F7FFFh
SA1-70
0
1
0111111XXX
32
1F8000h–1FFFFFh
SA1-71
0
1
1000000XXX
32
200000h–207FFFh
SA1-72
0
1
1000001XXX
32
208000h–20FFFFh
SA1-73
0
1
1000010XXX
32
210000h–217FFFh
SA1-74
0
1
1000011XXX
32
218000h–21FFFFh
SA1-75
0
1
1000100XXX
32
220000h–227FFFh
SA1-76
0
1
1000101XXX
32
228000h–22FFFFh
SA1-77
0
1
1000110XXX
32
230000h–237FFFh
SA1-78
0
1
1000111XXX
32
238000h–23FFFFh
SA1-79
0
1
1001000XXX
32
240000h–247FFFh
SA1-80
0
1
1001001XXX
32
248000h–24FFFFh
SA1-81
0
1
1001010XXX
32
250000h–257FFFh
SA1-82
0
1
1001011XXX
32
258000h–25FFFFh
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
Table 3.
Bank 1B
Bank
I n f o r m a t i o n
S29PL129J Sector Architecture (Sheet 3 of 7)
Sector
CE1#
CE2#
Sector Address (A21A12)
Sector Size
(Kwords)
Address Range (x16)
SA1-83
0
1
1001100XXX
32
260000h–267FFFh
SA1-84
0
1
1001101XXX
32
268000h–26FFFFh
SA1-85
0
1
1001110XXX
32
270000h–277FFFh
SA1-86
0
1
1001111XXX
32
278000h–27FFFFh
SA1-87
0
1
1010000XXX
32
280000h–287FFFh
SA1-88
0
1
1010001XXX
32
288000h–28FFFFh
SA1-89
0
1
1010010XXX
32
290000h–297FFFh
SA1-90
0
1
1010011XXX
32
298000h–29FFFFh
SA1-91
0
1
1010100XXX
32
2A0000h–2A7FFFh
SA1-92
0
1
1010101XXX
32
2A8000h–2AFFFFh
SA1-93
0
1
1010110XXX
32
2B0000h–2B7FFFh
SA1-94
0
1
1010111XXX
32
2B8000h–2BFFFFh
SA1-95
0
1
1011000XXX
32
2C0000h–2C7FFFh
SA1-96
0
1
1011001XXX
32
2C8000h–2CFFFFh
SA1-97
0
1
1011010XXX
32
2D0000h–2D7FFFh
SA1-98
0
1
1011011XXX
32
2D8000h–2DFFFFh
SA1-99
0
1
1011100XXX
32
2E0000h–2E7FFFh
SA1-100
0
1
1011101XXX
32
2E8000h–2EFFFFh
SA1-101
0
1
1011110XXX
32
2F0000h–2F7FFFh
SA1-102
0
1
1011111XXX
32
2F8000h–2FFFFFh
SA1-103
0
1
1100000XXX
32
300000h–307FFFh
SA1-104
0
1
1100001XXX
32
308000h–30FFFFh
SA1-105
0
1
1100010XXX
32
310000h–317FFFh
SA1-106
0
1
1100011XXX
32
318000h–31FFFFh
SA1-107
0
1
1100100XXX
32
320000h–327FFFh
SA1-108
0
1
1100101XXX
32
328000h–32FFFFh
SA1-109
0
1
1100110XXX
32
330000h–337FFFh
SA1-110
0
1
1100111XXX
32
338000h–33FFFFh
SA1-111
0
1
1101000XXX
32
340000h–347FFFh
SA1-112
0
1
1101001XXX
32
348000h–34FFFFh
SA1-113
0
1
1101010XXX
32
350000h–357FFFh
SA1-114
0
1
1101011XXX
32
358000h–35FFFFh
SA1-115
0
1
1101100XXX
32
360000h–367FFFh
SA1-116
0
1
1101101XXX
32
368000h–36FFFFh
SA1-117
0
1
1101110XXX
32
370000h–377FFFh
SA1-118
0
1
1101111XXX
32
378000h–37FFFFh
SA1-119
0
1
1110000XXX
32
380000h–387FFFh
SA1-120
0
1
1110001XXX
32
388000h–38FFFFh
SA1-121
0
1
1110010XXX
32
390000h–397FFFh
SA1-122
0
1
1110011XXX
32
398000h–39FFFFh
SA1-123
0
1
1110100XXX
32
3A0000h–3A7FFFh
SA1-124
0
1
1110101XXX
32
3A8000h–3AFFFFh
SA1-125
0
1
1110110XXX
32
3B0000h–3B7FFFh
SA1-126
0
1
1110111XXX
32
3B8000h–3BFFFFh
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
25
A d v a n c e
Table 3.
Bank 2A
Bank 1B
Bank
26
I n f o r m a t i o n
S29PL129J Sector Architecture (Sheet 4 of 7)
Sector
CE1#
CE2#
Sector Address (A21A12)
Sector Size
(Kwords)
Address Range (x16)
SA1-127
0
1
1111000XXX
32
3C0000h–3C7FFFh
SA1-128
0
1
1111001XXX
32
3C8000h–3CFFFFh
SA1-129
0
1
1111010XXX
32
3D0000h–3D7FFFh
SA1-130
0
1
1111011XXX
32
3D8000h–3DFFFFh
SA1-131
0
1
1111100XXX
32
3E0000h–3E7FFFh
SA1-132
0
1
1111101XXX
32
3E8000h–3EFFFFh
SA1-133
0
1
1111110XXX
32
3F0000h–3F7FFFh
SA1-134
0
1
1111111XXX
32
3F8000h–3FFFFFh
SA2-0
1
0
0000000XXX
32
000000h–007FFFh
SA2-1
1
0
0000001XXX
32
008000h–00FFFFh
SA2-2
1
0
0000010XXX
32
010000h–017FFFh
SA2-3
1
0
0000011XXX
32
018000h–01FFFFh
SA2-4
1
0
0000100XXX
32
020000h–027FFFh
SA2-5
1
0
0000101XXX
32
028000h–02FFFFh
SA2-6
1
0
0000110XXX
32
030000h–037FFFh
SA2-7
1
0
0000111XXX
32
038000h–03FFFFh
SA2-8
1
0
0001000XXX
32
040000h–047FFFh
SA2-9
1
0
0001001XXX
32
048000h–04FFFFh
SA2-10
1
0
0001010XXX
32
050000h–057FFFh
SA2-11
1
0
0001011XXX
32
058000h–05FFFFh
SA2-12
1
0
0001100XXX
32
060000h–067FFFh
SA2-13
1
0
0001101XXX
32
068000h–06FFFFh
SA2-14
1
0
0001110XXX
32
070000h–077FFFh
SA2-15
1
0
0001111XXX
32
078000h–07FFFFh
SA2-16
1
0
0010000XXX
32
080000h–087FFFh
SA2-17
1
0
0010001XXX
32
088000h–08FFFFh
SA2-18
1
0
0010010XXX
32
090000h–097FFFh
SA2-19
1
0
0010011XXX
32
098000h–09FFFFh
SA2-20
1
0
0010100XXX
32
0A0000h–0A7FFFh
SA2-21
1
0
0010101XXX
32
0A8000h–0AFFFFh
SA2-22
1
0
0010110XXX
32
0B0000h–0B7FFFh
SA2-23
1
0
0010111XXX
32
0B8000h–0BFFFFh
SA2-24
1
0
0011000XXX
32
0C0000h–0C7FFFh
SA2-25
1
0
0011001XXX
32
0C8000h–0CFFFFh
SA2-26
1
0
0011010XXX
32
0D0000h–0D7FFFh
SA2-27
1
0
0011011XXX
32
0D8000h–0DFFFFh
SA2-28
1
0
0011100XXX
32
0E0000h–0E7FFFh
SA2-29
1
0
0011101XXX
32
0E8000h–0EFFFFh
SA2-30
1
0
0011110XXX
32
0F0000h–0F7FFFh
SA2-31
1
0
0011111XXX
32
0F8000h–0FFFFFh
SA2-32
1
0
0100000XXX
32
100000h–107FFFh
SA2-33
1
0
0100001XXX
32
108000h–10FFFFh
SA2-34
1
0
0100010XXX
32
110000h–117FFFh
SA2-35
1
0
0100011XXX
32
118000h–11FFFFh
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
Table 3.
Bank 2A
Bank 2A
Bank
I n f o r m a t i o n
S29PL129J Sector Architecture (Sheet 5 of 7)
Sector
CE1#
CE2#
Sector Address (A21A12)
Sector Size
(Kwords)
Address Range (x16)
SA2-36
1
0
0100100XXX
32
120000h–127FFFh
SA2-37
1
0
0100101XXX
32
128000h–12FFFFh
SA2-38
1
0
0100110XXX
32
130000h–137FFFh
SA2-39
1
0
0100111XXX
32
138000h–13FFFFh
SA2-40
1
0
0101000XXX
32
140000h–147FFFh
SA2-41
1
0
0101001XXX
32
148000h–14FFFFh
SA2-42
1
0
0101010XXX
32
150000h–157FFFh
SA2-43
1
0
0101011XXX
32
158000h–15FFFFh
SA2-44
1
0
0101100XXX
32
160000h–167FFFh
SA2-45
1
0
0101101XXX
32
168000h–16FFFFh
SA2-46
1
0
0101110XXX
32
170000h–177FFFh
SA2-47
1
0
0101111XXX
32
178000h–17FFFFh
SA2-48
1
0
0110000XXX
32
180000h–187FFFh
SA2-49
1
0
0110001XXX
32
188000h–18FFFFh
SA2-50
1
0
0110010XXX
32
190000h–197FFFh
SA2-51
1
0
0110011XXX
32
198000h–19FFFFh
SA2-52
1
0
0110100XXX
32
1A0000h–1A7FFFh
SA2-53
1
0
0110101XXX
32
1A8000h–1AFFFFh
SA2-54
1
0
0110110XXX
32
1B0000h–1B7FFFh
SA2-55
1
0
0110111XXX
32
1B8000h–1BFFFFh
SA2-56
1
0
0111000XXX
32
1C0000h–1C7FFFh
SA2-57
1
0
0111001XXX
32
1C8000h–1CFFFFh
SA2-58
1
0
0111010XXX
32
1D0000h–1D7FFFh
SA2-59
1
0
0111011XXX
32
1D8000h–1DFFFFh
SA2-60
1
0
0111100XXX
32
1E0000h–1E7FFFh
SA2-61
1
0
0111101XXX
32
1E8000h–1EFFFFh
SA2-62
1
0
0111110XXX
32
1F0000h–1F7FFFh
SA2-63
1
0
0111111XXX
32
1F8000h–1FFFFFh
SA2-64
1
0
1000000XXX
32
200000h–207FFFh
SA2-65
1
0
1000001XXX
32
208000h–20FFFFh
SA2-66
1
0
1000010XXX
32
210000h–217FFFh
SA2-67
1
0
1000011XXX
32
218000h–21FFFFh
SA2-68
1
0
1000100XXX
32
220000h–227FFFh
SA2-69
1
0
1000101XXX
32
228000h–22FFFFh
SA2-70
1
0
1000110XXX
32
230000h–237FFFh
SA2-71
1
0
1000111XXX
32
238000h–23FFFFh
SA2-72
1
0
1001000XXX
32
240000h–247FFFh
SA2-73
1
0
1001001XXX
32
248000h–24FFFFh
SA2-74
1
0
1001010XXX
32
250000h–257FFFh
SA2-75
1
0
1001011XXX
32
258000h–25FFFFh
SA2-76
1
0
1001100XXX
32
260000h–267FFFh
SA2-77
1
0
1001101XXX
32
268000h–26FFFFh
SA2-78
1
0
1001110XXX
32
270000h–277FFFh
SA2-79
1
0
1001111XXX
32
278000h–27FFFFh
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
27
A d v a n c e
I n f o r m a t i o n
Table 3. S29PL129J Sector Architecture (Sheet 6 of 7)
Bank 2B
Bank 2A
Bank
28
Sector
CE1#
CE2#
Sector Address (A21A12)
Sector Size
(Kwords)
Address Range (x16)
SA2-80
1
0
1010000XXX
32
280000h–287FFFh
SA2-81
1
0
1010001XXX
32
288000h–28FFFFh
SA2-82
1
0
1010010XXX
32
290000h–297FFFh
SA2-83
1
0
1010011XXX
32
298000h–29FFFFh
SA2-84
1
0
1010100XXX
32
2A0000h–2A7FFFh
SA2-85
1
0
1010101XXX
32
2A8000h–2AFFFFh
SA2-86
1
0
1010110XXX
32
2B0000h–2B7FFFh
SA2-87
1
0
1010111XXX
32
2B8000h–2BFFFFh
SA2-88
1
0
1011000XXX
32
2C0000h–2C7FFFh
SA2-89
1
0
1011001XXX
32
2C8000h–2CFFFFh
SA2-90
1
0
1011010XXX
32
2D0000h–2D7FFFh
SA2-91
1
0
1011011XXX
32
2D8000h–2DFFFFh
SA2-92
1
0
1011100XXX
32
2E0000h–2E7FFFh
SA2-93
1
0
1011101XXX
32
2E8000h–2EFFFFh
SA2-94
1
0
1011110XXX
32
2F0000h–2F7FFFh
SA2-95
1
0
1011111XXX
32
2F8000h–2FFFFFh
SA2-96
1
0
1100000XXX
32
300000h–307FFFh
SA2-97
1
0
1100001XXX
32
308000h–30FFFFh
SA2-98
1
0
1100010XXX
32
310000h–317FFFh
SA2-99
1
0
1100011XXX
32
318000h–31FFFFh
SA2-100
1
0
1100100XXX
32
320000h–327FFFh
SA2-101
1
0
1100101XXX
32
328000h–32FFFFh
SA2-102
1
0
1100110XXX
32
330000h–337FFFh
SA2-103
1
0
1100111XXX
32
338000h–33FFFFh
SA2-104
1
0
1101000XXX
32
340000h–347FFFh
SA2-105
1
0
1101001XXX
32
348000h–34FFFFh
SA2-106
1
0
1101010XXX
32
350000h–357FFFh
SA2-107
1
0
1101011XXX
32
358000h–35FFFFh
SA2-108
1
0
1101100XXX
32
360000h–367FFFh
SA2-109
1
0
1101101XXX
32
368000h–36FFFFh
SA2-110
1
0
1101110XXX
32
370000h–377FFFh
SA2-111
1
0
1101111XXX
32
378000h–37FFFFh
SA2-112
1
0
1110000XXX
32
380000h–387FFFh
SA2-113
1
0
1110001XXX
32
388000h–38FFFFh
SA2-114
1
0
1110010XXX
32
390000h–397FFFh
SA2-115
1
0
1110011XXX
32
398000h–39FFFFh
SA2-116
1
0
1110100XXX
32
3A0000h–3A7FFFh
SA2-117
1
0
1110101XXX
32
3A8000h–3AFFFFh
SA2-118
1
0
1110110XXX
32
3B0000h–3B7FFFh
SA2-119
1
0
1110111XXX
32
3B8000h–3BFFFFh
SA2-120
1
0
1111000XXX
32
3C0000h–3C7FFFh
SA2-121
1
0
1111001XXX
32
3C8000h–3CFFFFh
SA2-122
1
0
1111010XXX
32
3D0000h–3D7FFFh
SA2-123
1
0
1111011XXX
32
3D8000h–3DFFFFh
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
Table 3.
Bank 2B
Bank
I n f o r m a t i o n
S29PL129J Sector Architecture (Sheet 7 of 7)
Sector
CE1#
CE2#
Sector Address (A21A12)
Sector Size
(Kwords)
Address Range (x16)
SA2-124
1
0
1111100XXX
32
3E0000h–3E7FFFh
SA2-125
1
0
1111101XXX
32
3E8000h–3EFFFFh
SA2-126
1
0
1111110XXX
32
3F0000h–3F7FFFh
SA2-127
1
0
1111111000
4
3F8000h–3F8FFFh
SA2-128
1
0
1111111001
4
3F9000h–3F9FFFh
SA2-129
1
0
1111111010
4
3FA000h–3FAFFFh
SA2-130
1
0
1111111011
4
3FB000h–3FBFFFh
SA2-131
1
0
1111111100
4
3FC000h–3FCFFFh
SA2-132
1
0
1111111101
4
3FD000h–3FDFFFh
SA2-133
1
0
1111111110
4
3FE000h–3FEFFFh
SA2-134
1
0
1111111111
4
3FF000h–3FFFFFh
Table 4.
Secured Silicon Sector Addresses
Sector Size
Address Range
Factory-Locked Area
64 words
000000h-00003Fh
Customer-Lockable Area
64 words
000040h-00007Fh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector
protection verification, through identifier codes output on DQ7–DQ0. This mode
is primarily intended for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 5. In addition, when
verifying sector protection, the sector address must appear on the appropriate
highest order address bits. Table 5 shows the remaining address bits that are
don’t care. When all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed in-system through the command
register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in
Table 12. Note: If a Bank Address (BA) (on address bits A21–A19) is asserted
during the third write cycle of the autoselect command, the host system can read
autoselect data that bank and then immediately read array data from the other
bank, without exiting the autoselect mode.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does
not require VID. See “Autoselect Command Sequence” on page 46 for more
information.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
29
A d v a n c e
I n f o r m a t i o n
Table 5. Autoselect Codes for PL129J
Description
Manufacturer
ID: Spansion
products
Device ID
Read
Cycle 1
Read
Cycle 2
Read
Cycle 3
Sector
Protection
Verification
Secured
Silicon
Indicator Bit
(DQ7, DQ6)
CE1# CE2#
L
WE#
L
H
X
A10
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
OE#
A21
to
A12
L
L
L
L
H
H
H
X
SA
X
X
A9 A8
VI
D
VI
D
X
VI
X
VI
D
D
X
X
X
X
A7
A6
A5
to
A4
L
L
X
L
L
X
L
L
L
L
L
X
A3 A2
A1
A0
DQ15
to DQ0
L
L
L
L
0001h
L
L
L
H
227Eh
H
H
H
L
2221h
H
H
H
H
2200h
L
L
H
L
0001h (protected),
0000h (unprotected)
H
DQ7=1 (factory
locked),
DQ6=1 (factory and
customer locked)
L
L
H
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences
30
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
Table 6.
I n f o r m a t i o n
PL129J Boot Sector/Sector Block Addresses for Protection/Unprotection
CE1# Control
CE2# Control
Sector Group
A21-12
Sector/Sector Block
Size
Sector Group
A21-12
Sector/Sector Block
Size
SA1-0
0000000000
4 Kwords
SA2-0–SA2-3
00000XXXXX
128 (4x32) Kwords
SA1-1
0000000001
4 Kwords
SA2-4–SA2-7
00001XXXXX
128 (4x32) Kwords
SA1-2
0000000010
4 Kwords
SA2-8–SA2-11
00010XXXXX
128 (4x32) Kwords
SA1-3
0000000011
4 Kwords
SA2-12–SA2-15
00011XXXXX
128 (4x32) Kwords
SA1-4
0000000100
4 Kwords
SA2-16–SA2-19
00100XXXXX
128 (4x32) Kwords
SA1-5
0000000101
4 Kwords
SA2-20–SA2-23
00101XXXXX
128 (4x32) Kwords
SA1-6
0000000110
4 Kwords
SA2-24–SA2-27
00110XXXXX
128 (4x32) Kwords
SA1-7
0000000111
4 Kwords
SA2-28–SA2-31
00111XXXXX
128 (4x32) Kwords
SA1-8
0000001XXX
32 Kwords
SA2-32–SA2-35
01000XXXXX
128 (4x32) Kwords
SA1-9
0000010XXX
32 Kwords
SA2-36–SA2-39
01001XXXXX
128 (4x32) Kwords
SA1-10
0000011XXX
32 Kwords
SA2-40–SA2-43
01010XXXXX
128 (4x32) Kwords
SA1-11 - SA1-14
00001XXXXX
128 (4x32) Kwords
SA2-44–SA2-47
01011XXXXX
128 (4x32) Kwords
SA1-15 - SA1-18
00010XXXXX
128 (4x32) Kwords
SA2-48–SA2-51
01100XXXXX
128 (4x32) Kwords
SA1-19 - SA1-22
00011XXXXX
128 (4x32) Kwords
SA2-52–SA2-55
01101XXXXX
128 (4x32) Kwords
SA1-23 - SA1-26
00100XXXXX
128 (4x32) Kwords
SA2-56–SA2-59
01110XXXXX
128 (4x32) Kwords
SA1-27 - SA1-30
00101XXXXX
128 (4x32) Kwords
SA2-60–SA2-63
01111XXXXX
128 (4x32) Kwords
SA1-31 - SA1-34
00110XXXXX
128 (4x32) Kwords
SA2-64–SA2-67
10000XXXXX
128 (4x32) Kwords
SA1-35 - SA1-38
00111XXXXX
128 (4x32) Kwords
SA2-68–SA2-71
10001XXXXX
128 (4x32) Kwords
SA1-39 - SA1-42
01000XXXXX
128 (4x32) Kwords
SA2-72–SA2-75
10010XXXXX
128 (4x32) Kwords
SA1-43 - SA1-46
01001XXXXX
128 (4x32) Kwords
SA2-76–SA2-79
10011XXXXX
128 (4x32) Kwords
SA1-47 - SA1-50
01010XXXXX
128 (4x32) Kwords
SA2-80–SA2-83
10100XXXXX
128 (4x32) Kwords
SA1-51 - SA1-54
01011XXXXX
128 (4x32) Kwords
SA2-84–SA2-87
10101XXXXX
128 (4x32) Kwords
SA1-55 - SA1-58
01100XXXXX
128 (4x32) Kwords
SA2-88–SA2-91
10110XXXXX
128 (4x32) Kwords
SA1-59 - SA1-62
01101XXXXX
128 (4x32) Kwords
SA2-92–SA2-95
10111XXXXX
128 (4x32) Kwords
SA1-63 - SA1-66
01110XXXXX
128 (4x32) Kwords
SA2-96–SA2-99
11000XXXXX
128 (4x32) Kwords
SA1-67 - SA1-70
01111XXXXX
128 (4x32) Kwords
SA2-100–SA2-103
11001XXXXX
128 (4x32) Kwords
SA1-71 - SA1-74
10000XXXXX
128 (4x32) Kwords
SA2-104–SA2-107
11010XXXXX
128 (4x32) Kwords
SA1-75 - SA1-78
10001XXXXX
128 (4x32) Kwords
SA2-108–SA2-111
11011XXXXX
128 (4x32) Kwords
SA1-79 - SA1-82
10010XXXXX
128 (4x32) Kwords
SA2-112–SA2-115
11100XXXXX
128 (4x32) Kwords
SA1-83 - SA1-86
10011XXXXX
128 (4x32) Kwords
SA2-116–SA2-119
11101XXXXX
128 (4x32) Kwords
SA1-87 - SA1-90
10100XXXXX
128 (4x32) Kwords
SA2-120–SA2-123
11110XXXXX
128 (4x32) Kwords
SA1-91 - SA1-94
10101XXXXX
128 (4x32) Kwords
SA2-124
1111100XXX
32 Kwords
SA1-95 - SA1-98
10110XXXXX
128 (4x32) Kwords
SA2-125
1111101XXX
32 Kwords
SA1-99 - SA1-102
10111XXXXX
128 (4x32) Kwords
SA2-126
1111110XXX
32 Kwords
SA1-103 - SA1-106
11000XXXXX
128 (4x32) Kwords
SA2-127
1111111000
4 Kwords
SA1-107 - SA1-110
11001XXXXX
128 (4x32) Kwords
SA2-128
1111111001
4 Kwords
SA1-111 - SA1-114
11010XXXXX
128 (4x32) Kwords
SA2-129
1111111010
4 Kwords
SA1-115 - SA1-118
11011XXXXX
128 (4x32) Kwords
SA2-130
1111111011
4 Kwords
SA1-119 - SA1-122
11100XXXXX
128 (4x32) Kwords
SA2-131
1111111100
4 Kwords
SA1-123 - SA1-126
11101XXXXX
128 (4x32) Kwords
SA2-132
1111111101
4 Kwords
SA1-127 - SA1-130
11110XXXXX
128 (4x32) Kwords
SA2-133
1111111110
4 Kwords
SA1-131 - SA1-134
11111XXXXX
128 (4x32) Kwords
SA2-134
1111111111
4 Kwords
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
31
A d v a n c e
I n f o r m a t i o n
Selecting a Sector Protection Mode
The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See “Secured Silicon Sector Addresses” on page 29 for details.
Table 7. Sector Protection Schemes
DYB
PPB
PPB Lock
Sector State
0
0
0
Unprotected—PPB and DYB are changeable
0
0
1
Unprotected—PPB not changeable, DYB is changeable
0
1
0
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
Protected—PPB and DYB are changeable
Protected—PPB not changeable, DYB is changeable
Sector Protection
The PL129J features several levels of sector protection, which can disable both
the program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before
changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in sectors SA1133, SA1-134, SA2-0 and SA2-1.
The WP# Hardware Protection feature is always available, independent of the
software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most
desirable. There are two one-time programmable non-volatile bits that define
which sector protection method is used. If the Persistent Sector Protection
method is desired, programming the Persistent Sector Protection Mode Locking
Bit permanently sets the device to the Persistent Sector Protection mode. If the
Password Sector Protection method is desired, programming the Password Mode
Locking Bit permanently sets the device to the Password Sector Protection mode.
It is not possible to switch between the two protection modes once a locking bit
has been set. One of the two modes must be selected when the device is first
32
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
programmed. This prevents a program or virus from later setting the Password
Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode.
The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to
shipping the device. Contact your local sales office for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the 12 V controlled protection
method in previous flash devices. This new method provides three different sector protection states:
„ Persistently Locked—The sector is protected and cannot be changed.
„ Dynamically Locked—The sector is protected and can be changed by a simple
command.
„ Unlocked—The sector is unprotected and can be changed by a simple command.
To achieve these states, three types of “bits” are used:
„ Persistent Protection Bit
„ Persistent Protection Bit Lock
„ Persistent Sector Protection Mode Locking Bit
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four
sectors (see the sector address tables for specific sector protection groupings).
All 4 Kword boot-block sectors have individual sector Persistent Protection Bits
(PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB
Write Command.
The device erases all PPBs in parallel. If any PPB requires erasure, the device
must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash
device does not have a built-in means of preventing sector PPBs over-erasure.
Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to
“1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable.
There is only one PPB Lock bit per device. The PPB Lock is cleared after powerup or hardware reset. There is no command sequence to unlock the PPB Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware
reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through
the DYB Write Command.
When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and
PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are
changeable.
When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
33
A d v a n c e
I n f o r m a t i o n
the PPB and the DYB related to that sector. For the sectors that have the PPBs
cleared, the DYBs control whether or not the sector is protected or unprotected.
By issuing the DYB Write command sequences, the DYBs are set or cleared, thus
placing each sector in the protected or unprotected state. These are the so-called
Dynamic Locked or Unlocked states. These states are called dynamic states because it is very easy to switch back and forth between the protected and
unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when
changes are needed. The DYBs maybe set or cleared as often as needed.
The PPBs allow for a more static, and difficult to change, level of protection. The
PPBs retain their state across power cycles because the PPBs are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through
a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles.
The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB
Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear
the PPB Lock is to go through a power cycle. System boot code can determine if
any changes to the PPB are needed; for example, to allow new system code to
be downloaded. If no changes are needed then the boot code can set the PPB
Lock to disable any further changes to the PPBs during system operation.
The WP#/ACC write protect pin adds a final level of hardware protection to sectors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible
to change the contents of these sectors. These sectors generally hold system
boot code. The WP#/ACC pin can prevent any changes to the boot code that could
override the choices made while setting up sector protection during system
initialization.
For customers who are concerned about malicious viruses there is another level
of security - the persistently locked state. To persistently protect a given sector
or sector group, the PPBs associated with that sector need to be set to “1”. Once
all PPBs are programmed to the desired settings, the PPB Lock should be set to
“1”. Setting the PPB Lock automatically disables all program and erase commands
to the Non-Volatile PPBs. In effect, the PPB Lock “freezes” the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle.
It is possible to have sectors that have been persistently locked, and sectors that
are left in the dynamic state. The sectors in the dynamic state are all unprotected.
If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors
switch the DYBs to signify protected and unprotected, respectively. If there is a
need to change the status of the persistently locked sectors, a few more steps
are required. First, the PPB Lock bit must be disabled by either putting the device
through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again lock the PPBs, and
the device operates normally again.
The best protection is achieved by executing the PPB lock bit set command early
in the boot code, and protect the boot code by holding WP#/ACC = VIL.
Table 17 contains all possible combinations of the DYB, PPB, and PPB lock relating
to the status of the sector.
34
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
In summary, if the PPB is set, and the PPB lock is set, the sector is protected and
the protection can not be removed until the next power cycle clears the PPB lock.
If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB
then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores
the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read
mode without having modified the contents of the protected sector. An erase
command to a protected sector enables status polling for approximately 50 µs
after which the device returns to read mode without having erased the protected
sector.
The programming of the DYB, PPB, and PPB lock for a given sector can be verified
by writing a DYB/PPB/PPB lock verify command to the device. There is an alternative means of reading the protection status. Take RESET# to VIL and hold WE#
at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of
the PPBs). Scanning the addresses (A18–A11) while (A6, A1, A0) = (0, 1, 0) produces a logical ‘1” code at device output DQ0 for a protected sector or a “0” for
an unprotected sector. In this mode, the other addresses are don’t cares. Address
location with A1 = VIL are reserved for autoselect manufacturer and device
codes.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking
bit exists to guarantee that the device remain in software sector protection. Once
set, the Persistent Sector Protection locking bit prevents programming of the
password protection mode locking bit. This guarantees that a hacker could not
place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences
between the Persistent Sector Protection and the Password Sector Protection
Mode:
When the device is first powered on, or comes out of a reset cycle, the PPB Lock
bit set to the locked state, rather than cleared to the unlocked state.
The only means to clear the PPB Lock bit is by writing a unique 64-bit Password
to the device.
The Password Sector Protection method is otherwise identical to the Persistent
Sector Protection method.
A 64-bit password is the only additional tool utilized in this method.
Once the Password Mode Locking Bit is set, the password is permanently set with
no means to read, program, or erase it. The password is used to clear the PPB
Lock bit. The Password Unlock command must be written to the flash, along with
a password. The flash device internally compares the given password with the
pre-programmed password. If they match, the PPB Lock bit is cleared, and the
PPBs can be altered. If they do not match, the flash device does nothing. There
is a built-in 2 µs delay for each “password check.” This delay is intended to thwart
any efforts to run a program that tries all possible combinations in order to crack
the password.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
35
A d v a n c e
I n f o r m a t i o n
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first
program the password. The password may be correlated to the unique Electronic
Serial Number (ESN) of the particular flash device. Each ESN is different for every
flash device; therefore each password should be different for every flash device.
While programming in the password region, the customer may perform Password
Verify operations.
Once the desired password is programmed in, the customer must then set the
Password Mode Locking Bit. This operation achieves two objectives:
Permanently sets the device to operate using the Password Protection Mode. It is
not possible to reverse this function.
Disables all further commands to the password region. All program, and read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead
to unrecoverable errors. The user must be sure that the Password Protection
method is desired when setting the Password Mode Locking Bit. More importantly,
the user must be sure that the password is correct when the Password Mode
Locking Bit is set. Due to the fact that read operations are disabled, there is no
means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there is not any way to clear the PPB Lock bit.
The Password Mode Locking Bit, once set, prevents reading the 64-bit password
on the DQ bus and further password programming. The Password Mode Locking
Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing
that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through
the use of the Password Program and Verify commands (see “Password Verify
Command”). The password function works in conjunction with the Password
Mode Locking Bit, which when set, prevents the Password Verify command from
reading the contents of the password on the pins of the device.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the upper
two and lower two sectors(PL127J: 0, 1, 268, and 269, PL064J: 0, 1, 140, and
141, PL032J: 0, 1, 76, and 77, PL129J: SA1-133, SA1-134,SA2-0 and SA2-1)
without using VID. This function is provided by the WP# pin and overrides the previously discussed method, “High Voltage Sector Protection” on page 37.
If the system asserts VIL on the WP#/ACC pin, the device disables program and
erase functions in the two outermost 4 Kword sectors on both ends of the flash
array independent of whether it was previously protected or unprotected.
If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two
and lower two sectors to whether they were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on
whether they were last protected or unprotected using the method described in
“High Voltage Sector Protection” on page 37.
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent
behavior of the device may result.
36
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of
the Password Mode Locking Bit after power-up reset. If the Password Mode Lock
Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the
ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue
the Password Unlock command. Successful execution of the Password Unlock
command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock
Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit
is not set.
If the Password Mode Locking Bit is not set, including Persistent Protection Mode,
the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is
set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password
Unlock command is ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming
equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector
unprotect, all unprotected sectors must first be protected prior to the first sector
write cycle.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
37
A d v a n c e
I n f o r m a t i o n
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 4 μs
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 4 μs
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A7-A0 =
00000010
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A7-A0 =
01000010
Wait 100 µs
Increment
PLSCNT
No
Verify Sector
Protect: Write 40h
to sector address
with A7-A0 =
00000010
Reset
PLSCNT = 1
Read from
sector address
with A7-A0 =
00000010
Wait 1.2 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A7-A0 =
00000010
Increment
PLSCNT
No
No
PLSCNT
= 25?
Yes
Yes
Remove VID
from RESET#
No
Yes
Protect another
sector?
No
Write reset
command
Remove VID
from RESET#
Sector Protect
complete
Write reset
command
Device failed
Read from
sector address
with A7-A0 =
00000010
Data = 01h?
Sector Protect
complete
Sector Protect
Algorithm
PLSCNT
= 1000?
Yes
Remove VID
from RESET#
Write reset
command
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Remove VID
from RESET#
Sector Unprotect
complete
Write reset
command
Device failed
Sector Unprotect
complete
Sector Unprotect
Algorithm
Figure 1. In-System Sector Protection/Sector Unprotection Algorithms
38
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from
the RESET# pin, all the previously protected sectors are protected again.
Figure 2 shows the algorithm, and Figure 21 shows the timing diagrams, for this
feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors are unprotected (If WP#/ACC = VIL, upper two and lower
two sectors remain protected).
2. All previously protected sectors are protected once again
Figure 2. Temporary Sector Unprotect Operation
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables
permanent part identification through an Electronic Serial Number (ESN) The
128-word Secured Silicon sector is divided into 64 factory-lockable words that
can be programmed and locked by the customer. The Secured Silicon sector is
located at addresses 000000h-00007Fh in both Persistent Protection mode and
Password Protection mode. Indicator bits DQ6 and DQ7 are used to indicate the
factory-locked and customer locked status of the part.
The system accesses the Secured Silicon Sector through a command sequence
(see “Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence” on page 46). After the system has written the Enter Secured Silicon
Sector command sequence, it may read the Secured Silicon Sector by using the
addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence,
or until power is removed from the device. On power-up, or following a hardware
reset, the device reverts to sending commands to the normal address space. Note
that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
39
A d v a n c e
I n f o r m a t i o n
Factory-Locked Area (64 words)
The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is
locked when the part is shipped, whether or not the area was programmed at the
factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is permanently set to a “1”. Optional Spansion programming services can program the
factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only FASL can program and protect the factory-locked
area, this method ensures the security of the ESN once the product is shipped to
the field. Contact your local sales office for details on using Spansion’s programming services. Note that the ACC function and unlock bypass modes are not
available when the Secured Silicon sector is enabled.
Customer-Lockable Area (64 words)
The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is
shipped unprotected, which allows the customer to program and optionally lock
the area as appropriate for the application. The Secured Silicon Sector Customerlocked Indicator Bit (DQ6) is shipped as “0” and can be permanently locked to “1”
by issuing the Secured Silicon Protection Bit Program Command. The Secured Silicon Sector can be read any number of times, but can be programmed and locked
only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Sector.
The Customer-lockable Secured Silicon Sector area can be protected using one
of the following procedures:
„ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in
Figure 1, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the
Secured Silicon Sector.
„ To verify the protect/unprotect status of the Secured Silicon Sector, follow the
algorithm shown in Figure 3.
Once the Secured Silicon Sector is locked and verified, the system must write the
Exit Secured Silicon Sector Region command sequence to return to reading and
writing the remainder of the array.
The Secured Silicon Sector lock must be used with caution since, once locked,
there is no procedure available for unlocking the Secured Silicon Sector area and
none of the bits in the Secured Silicon Sector memory space can be modified in
any way.
Secured Silicon Sector Protection Bits
The Secured Silicon Sector Protection Bits prevent programming of the Secured
Silicon Sector memory area. Once set, the Secured Silicon Sector memory area
contents are non-modifiable.
40
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
START
RESET# =
VIH or VID
Wait 1 μs
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove VIH or VID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
Figure 3. Secured Silicon Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level signals during VCC
power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE1#, CE2# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE1# = CE2# = VIH
or WE# = VIH. To initiate a write cycle, CE1# / CE2# and WE# must be a logical
zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# (CE1#, CE2# in PL129J) = VIL and OE# = VIH during power up,
the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to the read mode on power-up.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
41
A d v a n c e
I n f o r m a t i o n
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Table 8, Table 9,
Table 10, and Table 11. To terminate reading CFI data, the system must write the
reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 8, Table 9, Table 10, and Table 11. The
system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication
100. Contact your local sales office for copies of these documents.
Table 8. CFI Query Identification String
42
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Table 9. System Interface String
Addresses
Data
Description
1Bh
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0003h
Typical timeout per single byte/word write 2N µs
20h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
0009h
Typical timeout per individual block erase 2N ms
22h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
0004h
Max. timeout for byte/word write 2N times typical
24h
0000h
Max. timeout for buffer write 2N times typical
25h
0004h
Max. timeout per individual block erase 2N times typical
26h
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10. Device Geometry Definition
Addresses
Data
Description
27h
0018h (PL129J)
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Device Size = 2 byte
N
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
00FDh (PL129J)
32h
33h
34h
0000h
0000h
0001h
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
Table 11. Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Addresses
Data
40h
41h
42h
0050h
0052h
0049h
October 28, 2005 S71PL129Jxx_00_A8
Description
Query-unique ASCII string “PRI”
S71PL129JC0/S71PL129JB0/S71PL129JA0
43
A d v a n c e
Table 11.
I n f o r m a t i o n
Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Addresses
Data
Description
43h
0031h
Major version number, ASCII (reflects modifications to the silicon)
44h
0033h
Minor version number, ASCII (reflects modifications to the CFI table)
45h
TBD
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
44
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0007h (PLxxxJ)
Sector Protect/Unprotect scheme
07 = Advanced Sector Protection
4Ah
00E7h (PL129J)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors excluding Bank 1
4Bh
0000h
4Ch
0002h (PLxxxJ)
4Dh
0085h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh
0095h
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh
0001h
Top/Bottom Boot Sector Flag
00h = Uniform device, 01h = Both top and bottom boot with write protect,
02h = Bottom Boot Device, 03h = Top Boot Device,
04h = Both Top and Bottom
50h
0001h
Program Suspend
0 = Not supported, 1 = Supported
57h
0004h
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
58h
0027h (PL129J)
Bank 1 Region Information
X = Number of Sectors in Bank 1
59h
0060h (PL129J)
Bank 2 Region Information
X = Number of Sectors in Bank 2
5Ah
0060h (PL129J)
Bank 3 Region Information
X = Number of Sectors in Bank 3
5Bh
0027h (PL129J)
Bank 4 Region Information
X = Number of Sectors in Bank 4
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 12 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE# (CE1# / CE2# in
PL129J), whichever happens later. All data is latched on the rising edge of WE#
or CE# (CE1# / CE2# in PL129J), whichever happens first. See AC Characteristics
for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. The system can read
array data using the standard read timing, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing
a programming operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” on page 50 for more information.
The system must issue the reset command to return a bank to the read (or erasesuspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See “Reset Command,” for more
information.
See “Requirements for Reading Array Data” on page 19 in “Device Bus Operations” for more information. The AC Characteristics table provides the read
parameters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the bank to which
the system was writing to the read mode. If the program command sequence is
written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to return to the read mode. If a bank entered the autoselect mode while
in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
45
A d v a n c e
I n f o r m a t i o n
If DQ5 goes high during a program or erase operation, writing the reset command
returns the banks to the read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected.
The autoselect command sequence may be written to an address within a bank
that is either in the read or erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing in the
other bank.
The autoselect command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may
read any number of autoselect codes without reinitiating the command sequence.
Table 12 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and
sector address (SA).
The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command
Sequence
The Secured Silicon Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the
Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon
Sector command sequence. The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle Exit Secured Silicon Sector
command sequence. The Exit Secured Silicon Sector command sequence returns
the device to normal operation. The Secured Silicon Sector is not accessible when
the device is executing an Embedded Program or embedded Erase algorithm.
Table 12 shows the address and data requirements for both command sequences.
Also see, “Secured Silicon Sector Flash Memory Region” on page 39 for further information. Note: The ACC function and unlock bypass modes are not available
when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 12 shows the address and
data requirements for the program command sequence. Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable when a [program/
erase] operation is in progress.
When the Embedded Program algorithm is complete, that bank then returns to
the read mode and addresses are no longer latched. The system can determine
the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write
Operation Status” on page 56 for information on these status bits.
46
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the program
operation. The program command sequence should be reinitiated once that bank
has returned to the read mode, to ensure data integrity. Note that the Secured
Silicon Sector, autoselect and CFI functions are unavailable when the Secured Silicon Sector is enabled.
Programming is allowed in any sequence and across sector boundaries. A bit
cannot be programmed from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read shows that the data is
still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program data to a bank faster
than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by
a third write cycle containing the unlock bypass command, 20h. That bank then
enters the unlock bypass mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two unlock cycles required in
the standard program command sequence, resulting in faster total programming
time. Table 12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. (Table 13)
The device offers accelerated program operations through the WP#/ACC pin.
When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock
Bypass program command sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
be at VHH any operation other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
Figure 4 illustrates the algorithm for the program operation. See the Erase/Program Operations table in AC Characteristics for parameters, and Figure 14 for
timing diagrams.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
47
A d v a n c e
I n f o r m a t i o n
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See Table 12 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 12 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” on page 56 for information on these status bits.
Any commands written during the chip erase operation are ignored. Note that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a
[program/erase] operation is in progress. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program
Operations tables in AC Characteristics for parameters, and Figure 16 for timing
diagrams.
48
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 12 shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory
for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs.
During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 µs, otherwise erasure
may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input during the time-out period, the
normal operation cannot be guaranteed. The system must rewrite the command sequence and any additional addresses and commands. Note that Secured
Silicon Sector, autoselect, and CFI functions are unavailable when a [program/
erase] operation is in progress.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See “DQ3: Sector Erase Timer” on page 61). The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. See “Write Operation Status” on
page 56 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program
Operations tables in AC Characteristics for parameters, and Figure 16 for timing
diagrams.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
49
A d v a n c e
I n f o r m a t i o n
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 12 for erase command sequence.
2. See “DQ3: Sector Erase Timer” on page 61 for information on the sector erase
timer.
Figure 5. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase
operation and then read data from, or program data to, any sector not selected
for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 µs time-out
period during the sector erase command sequence. The Erase Suspend command
is ignored if written during the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during the sector erase operation,
the device requires a maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out period and suspends
the erase operation. Addresses are “don’t-cares” when writing the Erase suspend
command.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for
erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See
“Write Operation Status” on page 56 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the
erase-suspend-read mode. The system can determine the status of the program
50
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
operation using the DQ7 or DQ6 status bits, just as in the standard Word Program
operation. See “Write Operation Status” on page 56 for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored in the memory array. When
the device exits the autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See “Secured Silicon Sector Addresses” on page 29 and “Autoselect Command Sequence” on page 46 for details.
To resume the sector erase operation, the system must write the Erase Resume
command (address bits are don’t care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the
Resume command are ignored. Another Erase Suspend command can be written
after the chip has resumed erasing.
Password Program Command
The Password Program Command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. Four Password Program commands are required to program the password.
The system must enter the unlock cycle, password program command (38h) and
the program address/data for each portion of the password when programming.
There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order
required for programming the password. Also, when the password is undergoing
programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete,
the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit
must be set in order to prevent verification. The Password Program Command is
only capable of programming “0”s. Programming a “1” after a cell is programmed
as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell
remaining as a “0”. The password is all ones when shipped from the factory. All
64-bit password combinations are valid as a password.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is
verifiable only when the Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the user attempts to verify the
Password, the device will always drive all F’s onto the DQ data bus.
The Password Verify command is permitted if the Secured Silicon sector is enabled. Also, the device will not operate in Simultaneous Operation when the
Password Verify command is executed. Only the password is returned regardless
of the bank address. The lower two address bits (A1-A0) are valid during the
Password Verify. Writing the Read/Reset command returns the device back to
normal operation.
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the
Password Protection Mode Locking Bit, which prevents further verifies or updates
to the Password. Once programmed, the Password Protection Mode Locking Bit
cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
51
A d v a n c e
I n f o r m a t i o n
command can be executed to improve the program margin. Once the Password
Protection Mode Locking Bit is programmed, the Persistent Sector Protection
Locking Bit program circuitry is disabled, thereby forcing the device to remain in
the Password Protection mode. Exiting the Mode Locking Bit Program command
is accomplished by writing the Read/Reset command.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs
the Persistent Sector Protection Mode Locking Bit, which prevents the Password
Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent
Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode
Locking Bit, the device is forced to remain in the Persistent Sector Protection
mode of operation, once this bit is set. Exiting the Persistent Protection Mode
Locking Bit Program command is accomplished by writing the Read/Reset
command.
Secured Silicon Sector Protection Bit Program Command
The Secured Silicon Sector Protection Bit Program Command programs the Secured Silicon Sector Protection Bit, which prevents the Secured Silicon sector
memory from being cleared. If the Secured Silicon Sector Protection Bit is verified
as programmed without margin, the Secured Silicon Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the VCClevel Secured Silicon Sector Protection Bit Program Command is accomplished by
writing the Read/Reset command.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either
at reset or if the Password Unlock command was successfully executed. There is
no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared
unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the
DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected
as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command
is accomplished by writing the Read/Reset command (only in the Persistent Protection Mode).
DYB Write Command
The DYB Write command is used to set or clear a DYB for a given sector. The high
order address bits (Amax–A12) are issued at the same time as the code 01h or
00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write
cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or
PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the
DYB Write command is accomplished by writing the Read/Reset command.
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs
can be unlocked for modification, thereby allowing the PPBs to become accessible
for modification. The exact password must be entered in order for the unlocking
function to occur. This command cannot be issued any faster than 2 µs at a time
to prevent a hacker from running through all 64-bit combinations in an attempt
52
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored.
Once the Password Unlock command is entered, the RY/BY# indicates that the
device is busy. Approximately 1 µs is required for each portion of the unlock. Once
the first portion of the password unlock completes (RY/BY# is not low or DQ6
does not toggle when read), the next part of the password is written. The system
must thus monitor RY/BY# or the status bits to confirm when to write the next
portion of the password. Seven cycles are required to successfully clear the PPB
Lock Bit.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is
individually programmed (but is bulk erased with the other PPBs). The specific
sector address (A22–A12) are written at the same time as the program command
60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for
the sector, the PPB Program command will not execute and the command will
time-out without programming the PPB.
After programming a PPB, two additional cycles are needed to determine whether
the PPB has been programmed with margin. If the PPB has been programmed
without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is
limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed.
The PPB Program command does not follow the Embedded Program algorithm.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means
for individually erasing a specific PPB. Unlike the PPB program, no specific sector
address is required. However, when the PPB erase command is written all Sector
PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command
will not execute and the command will time-out without erasing the PPBs. After
erasing the PPBs, two additional cycles are needed to determine whether the PPB
has been erased with margin. If the PPBs has been erased without margin, the
erase command should be reissued to improve the program margin.
It is the responsibility of the user to preprogram all PPBs prior to issuing the All
PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure
may occur making it difficult to program the PPB at a later time. Also note that
the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the
PPBs beyond 100 cycles is not guaranteed.
DYB Write Command
The DYB Write command is used for setting the DYB, which is a volatile bit that
is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is
protected regardless of the value of the DYB. If the PPB is cleared, setting the
DYB to a 1 protects the sector from programs or erases. Since this is a volatile
bit, removing power or resetting the device will clear the DYBs. The bank address
is latched when the command is written.
PPB Lock Bit Set Command
The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit
that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector
is protected regardless of the value of the DYB. If the PPB is cleared, setting the
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
53
A d v a n c e
I n f o r m a t i o n
DYB to a 1 protects the sector from programs or erases. Since this is a volatile
bit, removing power or resetting the device will clear the DYBs. The bank address
is latched when the command is written.
Command
The programming of either the PPB or DYB for a given sector or sector group can
be verified by writing a Sector Protection Status command to the device.
Note that there is no single command to independently verify the programming
of a DYB for a given sector group.
Command Definitions Tables
Table 12. Memory Array Command Definitions
Cycles
Bus Cycles (Notes 1–4)
Addr
Read (Note 5)
1
RA
RD
Reset (Note 6)
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
(BA)
555
90
(BA)
X00
01
Device ID (Note 10)
6
555
AA
2AA
55
(BA)
555
90
(BA)
X01
227E
Secured Silicon Sector
Factory Protect (Note
8)
4
555
AA
2AA
55
(BA)
555
90
X03
(Note
8)
Sector Group Protect
Verify (Note 9)
4
555
AAA
2AA
55
(BA)
555
90
(SA)
X02
XX00/
XX01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (Note 11)
1
BA
B0
Program/Erase Resume (Note 12)
1
BA
30
CFI Query (Note 13)
1
55
98
Accelerated Program (Note 15)
2
XX
A0
PA
PD
Unlock Bypass Entry (Note 15)
3
555
AA
2AA
55
555
20
Unlock Bypass Program (Note 15)
2
XX
A0
PA
PD
Unlock Bypass Erase (Note 15)
2
XX
80
XX
10
Unlock Bypass CFI (Notes 13, 15)
1
XX
98
Unlock Bypass Reset (Note 15)
2
XXX
90
XXX
00
Command (Notes)
Autoselect
(Note 7)
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
(BA)
X0E
(Note
10)
(BA)
X0F
(Note
10)
Legend:
BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by Amax:A19.
PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE1#/CE2# pulse, whichever happens
later.
PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE1#/CE2# pulse,
whichever happens first.
RA = Read Address (Amax:A0).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing.
WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#.
X = Don’t care
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
54
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend)
when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information).
7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID
or device ID information. See “Autoselect Command Sequence” on page 46 for more information.
8. The data is DQ6=1 for factory and customer locked and DQ7=1 for factory locked.
9. The data is 00h for an unprotected sector group and 01h for a protected sector group.
10. Device ID must be read across cycles 4, 5, and 6. PL129J (X0Eh = 2221h, X0Fh = 2200h).
11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode.
Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address.
12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address.
13. Command is valid when device is ready to read array data or when device is in autoselect mode.
14. WP#/ACC must be at VID during the entire operation of command.
15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required
to return to the reading array.
Command (Notes)
Cycles
Table 13. Sector Protection Command Definitions
Bus Cycles (Notes 1-4)
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset
1
XXX
F0
Secured Silicon Sector Entry
3
555
AA
2AA
55
555
88
Secured Silicon Sector Exit
4
555
AA
2AA
55
555
90
XX
00
Secured Silicon Protection Bit Program
(Notes 5, 6)
6
555
AA
2AA
55
555
60
OW
68
OW
48
Secured Silicon Protection Bit Status
5
555
AA
2AA
55
555
60
OW
48
OW
RD
(0)
Password Program (Notes 5, 7, 8)
4
555
AA
2AA
55
555
38
XX
PD
[0-3] [0-3]
Password Verify (Notes 6, 8, 9)
4
555
AA
2AA
55
555
C8
PWA PWD
[0-3] [0-3]
Password Unlock (Notes 7, 10, 11)
7
555
AA
2AA
55
555
28
PWA
[0]
PWD
[0]
PWA
[1]
PPB Program (Notes 5, 6, 12)
6
555
AA
2AA
55
555
60
(SA)
WP
68
PPB Status
4
555
AA
2AA
55
555
90
(SA)
WP
RD
(0)
All PPB Erase (Notes 5, 6, 13, 14)
6
555
AA
2AA
55
555
60
WP
60
PPB Lock Bit Set
3
555
AA
2AA
55
555
78
PPB Lock Bit Status (Note 15)
4
555
AA
2AA
55
555
58
SA
RD
(1)
DYB Write (Note 7)
4
555
AA
2AA
55
555
48
SA
X1
DYB Erase (Note 7)
4
555
AA
2AA
55
555
48
SA
X0
DYB Status (Note 6)
4
555
AA
2AA
55
555
58
SA
RD
(0)
PPMLB Program (Notes 5, 6, 12)
6
555
AA
2AA
55
555
60
PL
PPMLB Status (Note 5)
5
555
AA
2AA
55
555
60
SPMLB Program (Notes 5, 6, 12)
6
555
AA
2AA
55
555
SPMLB Status (Note 5)
5
555
AA
2AA
55
555
OW
RD
(0)
PWD
[1]
PWA
[2]
PWD
[2]
(SA)
WP
48
(SA)
WP
RD
(0)
(SA)
40
(SA)
WP
RD
(0)
68
PL
48
PL
RD
(0)
PL
48
PL
RD
(0)
60
SL
68
SL
48
SL
RD
(0)
60
SL
48
SL
RD
(0)
PWA
[3]
PWD
[3]
Legend:
DYB = Dynamic Protection Bit
OW = Address (A7:A0) is (00011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
55
A d v a n c e
I n f o r m a t i o n
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)
WP = PPB Address (A7:A0) is (00000010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than
A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 =
0 in cycle 6, program command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of password.
9. Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at addresses 0-3.
11. A 2 µs timeout is required between any two portions of password.
12. A 100 µs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase
command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB
overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 and the following subsections describe
the function of these bits. DQ7 and DQ6 each offer a method for determining whether
a program or erase operation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine whether an Embedded Program
or Erase operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement
of the datum programmed to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address
to read valid status information on DQ7. If a program address falls within a protected
sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns
to the read mode.
56
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide
an address within any of the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 400 µs, then the
bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ15–DQ0 on the following read cycles. Just prior to the
completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ0 while Output Enable (OE#) is asserted low. That is,
the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed the program or erase operation
and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid
data on DQ15–DQ0 appears on successive read cycles.
Table 14 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling
algorithm. Figure 18 in AC Characteristics shows the Data# Polling timing
diagram.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
57
A d v a n c e
I n f o r m a t i o n
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is
any sector address within the sector being erased. During chip erase, a valid address is
any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously
with DQ5.
Figure 6. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an
Embedded Algorithm is in progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be tied together in parallel with
a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This
includes programming in the Erase Suspend mode.) If the output is high (Ready),
the device is in the read mode, the standby mode, or one of the banks is in the
erase-suspend-read mode.
Table 14 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
58
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 400 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see “DQ7: Data# Polling” on page 56).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to
reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is complete.
Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit
algorithm. Figure 19 in “Read Operation Timings” shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical
form. See also “DQ2: Toggle Bit II”.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
59
A d v a n c e
I n f o r m a t i o n
START
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ7–DQ0)
Address = VA
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle
bit may stop toggling as DQ5 changes to “1.” See “DQ6: Toggle Bit I” and “DQ2: Toggle Bit II” for more information.
Figure 7. Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE1# / CE2# to
control the read cycles.) But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device
is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode
information. See Table 14 to compare outputs for DQ2 and DQ6.
Figure 7 shows the toggle bit algorithm in flowchart form, and the “DQ2: Toggle
Bit II” explains the algorithm. See also “DQ6: Toggle Bit I.” Figure 19 shows the
toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6
in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
60
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see “DQ5: Exceeded Timing Limits”). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling,
the device did not completed the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the
program or erase cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a
location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return
to the read mode (or to the erase-suspend-read mode if a bank was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors are selected for erasure,
the entire time-out also applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also
“Sector Erase Command Sequence” on page 49.
After the sector erase command is written, the system should read the status of
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase
algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device accepts additional
sector erase commands. To ensure the command has been accepted, the system
software should check the status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted.
Table 14 shows the status of DQ3 relative to the other status bits.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
61
A d v a n c e
I n f o r m a t i o n
Table 14. Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Status
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase-SuspendRead
Erase-Suspend-Program
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits.“DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
62
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Absolute Maximum Ratings
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . –0.5 V to +13.0 V
WP#/ACC (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V
All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,
input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum
DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or
I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V.
During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on
pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods
up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the
short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
+0.8 V
–0.5 V
–2.0 V
2.0 V
20 ns
20 ns
Maximum Negative Overshoot Waveform
20 ns
Maximum Positive Overshoot Waveform
Figure 8. Maximum Overshoot Waveforms
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
63
A d v a n c e
I n f o r m a t i o n
Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Supply Voltages
VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7–3.6 V
VIO or 2.7–3.6 V
Notes:
For all AC and DC specifications, VIO = VCC; contact your local sales office for other
VIO options.
64
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
DC Characteristics
Table 15. CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
±1.0
µA
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9, OE#, RESET# Input Load Current
VCC = VCC max; VID= 12.5 V
35
µA
ILR
Reset Leakage Current
VCC = VCC max; VID= 12.5 V
35
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, OE# = VIH
VCC = VCC max
±1.0
µA
ICC1
VCC Active Read Current (Notes 1, 2)
OE# = VIH, VCC = VCC max
(Note 1)
ICC2
VCC Active Write Current (Notes 2, 3)
ICC3
ICC4
5 MHz
20
30
10 MHz
45
55
OE# = VIH, WE# = VIL
15
25
mA
VCC Standby Current (Note 2)
CE#, RESET#, WP#/ACC
= VIO ± 0.3 V
0.2
5
µA
VCC Reset Current (Note 2)
RESET# = VSS ± 0.3 V
0.2
5
µA
ICC5
Automatic Sleep Mode (Notes 2, 4)
VIH = VIO ± 0.3 V;
VIL = VSS ± 0.3 V
0.2
5
µA
ICC6
VCC Active Read-While-Program Current
(Notes 1, 2)
OE# = VIH,
ICC7
VCC Active Read-While-Erase Current
(Notes 1, 2)
OE# = VIH,
ICC8
VCC Active Program-While-EraseSuspended Current (Notes 2, 5)
ICC9
mA
5 MHz
21
45
10 MHz
46
70
5 MHz
21
45
10 MHz
46
70
OE# = VIH
17
25
mA
VCC Active Page Read Current (Note 2)
OE# = VIH, 8 word Page Read
10
15
mA
mA
mA
VIL
Input Low Voltage
VIO = 2.7–3.6 V
–0.5
0.8
V
VIH
Input High Voltage
VIO = 2.7–3.6 V
2.0
VCC+0.3
V
VHH
Voltage for ACC Program Acceleration
VCC = 3.0 V ± 10%
8.5
9.5
V
VID
Voltage for Autoselect and Temporary
Sector Unprotect
VCC = 3.0 V ± 10%
11.5
12.5
V
0.4
V
VOL
Output Low Voltage
IOL = 2.0 mA, VCC = VCC min, VIO = 2.7–3.6
V
IOH = –2.0 mA, VCC = VCC min, VIO = 2.7–3.6
V
VOH
Output High Voltage
VLKO
Low VCC Lock-Out Voltage (Note 5)
2.4
2.3
V
2.5
V
Notes:
1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep
mode current is 1 mA.
5. Not 100% tested.
6. In S29PL129J there are two CE# (CE1#, CE2#).
7. Valid CE1#/CE2# conditions: (CE1# = VIL, CE2# = VIH,) or (CE1# = VIH, CE2# = VIL) or (CE1# = VIH, CE2# = VIH)
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
65
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Test Conditions
3.6 V
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
VIO = 3.0 V
Note: Diodes are IN3064 or equivalent
Figure 9.
Test Setups
Table 16. Test Specifications
Test Condition
All Speeds
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL (including jig capacitance)
30
pF
Input Rise and Fall Times
VIO = 3.0 V
5
ns
Input Pulse Levels
VIO = 3.0 V
0.0–3.0
V
Input timing measurement reference levels
VIO/2
V
Output timing measurement reference levels
VIO/2
V
Switching Waveforms
Table 17. Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
66
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
VIO
I n f o r m a t i o n
VIO/2
In
VIO/2
Measurement Level
Output
0.0 V
Figure 10. Input Waveforms and Measurement Levels
VCC RampRate
All DC characteristics are specified for a VCC ramp rate > 1V/100 µs and VCC
>=VCCQ - 100 mV. If the VCC ramp rate is < 1V/100 µs, a hardware reset
required.+
Read Operations
Table 18. Read-Only Operations
Parameter
Speed Options
JEDEC
Std.
Description
Test Setup
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
55
60
65
70
Unit
Min
55
60
65
70
ns
CE#, OE# = VIL
Max
55
60
65
70
ns
OE# = VIL
Max
55
60
65
70
ns
Max
20
25
25
30
ns
20
25
tPACC Page Access Time
tGLQV
tOE
Output Enable to Output Delay
Max
30
ns
tEHQZ
tDF
Chip Enable to Output High Z (Note 3)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z
(Notes 1, 3)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 3)
Min
5
ns
Output Enable Hold
Time (Note 1)
Read
Min
0
ns
tOEH
Toggle and
Data# Polling
Min
10
ns
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 16 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE#
high to the data bus driven to VCC /2 is taken as tDF.
4. S29PL129J has two CE# (CE1#, CE2#).
5. Valid CE1# / CE2# conditions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) or (CE1# = VIH, CE2# = VIH)
6. Valid CE1# / CE2# transitions: (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL) to (CE1# = CE2# = VIH)
7. Valid CE1# / CE2# transitions: (CE1# = CE2# = VIH) to (CE1# = VIL,CE2# = VIH) or (CE1# = VIH,CE2# = VIL)
8. For 70pF Output Load Capacitance, 2 ns is added to the above tACC,tCE,tPACC,tOE values for all speed grades
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
67
A d v a n c e
I n f o r m a t i o n
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Valid Data
Data
RESET#
RY/BY#
0V
Notes:
1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 11. Read Operation Timings
Same Page
Amax-A3
A2-A0
Aa
tACC
Data
Ab
tPACC
Qa
Ad
Ac
tPACC
Qb
tPACC
Qc
Qd
CE#
OE#
Notes:
1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 12. Page Read Operation Timings
68
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Reset
Table 19.
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
µs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Notes:
1. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
2. S29PL129J - There are two CE# (CE1#, CE2#). In the below waveform CE# = CE1# or CE2#
Figure 13. Reset Timings
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
69
A d v a n c e
I n f o r m a t i o n
Erase/Program Operations
Table 20. Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit
polling
Min
15
ns
tAH
Address Hold Time
Min
tAHT
Address Hold Time From CE1#, CE#2 or OE# high
during toggle bit polling
Min
tDVWH
tDS
Data Setup Time
Min
tWHDX
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
10
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE1# or CE#2 Setup Time
Min
0
ns
tWHEH
tCH
CE1# or CE#2 Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
ns
tWHDL
tWPH
Write Pulse Width High
Min
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tWLAX
55
60
65
70
Unit
55
60
65
70
ns
30
35
0
25
ns
30
20
ns
25
ns
ns
tWHWH1
tWHWH1
Programming Operation (Note 4)
Typ
6
µs
tWHWH1
tWHWH1
Accelerated Programming Operation (Note 4)
Typ
4
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 4)
Typ
0.5
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time from RY/BY#
Min
0
ns
Max
90
ns
Min
35
ns
tBUSY
Program/Erase Valid to RY/BY# Delay
Notes:
1. Not 100% tested.
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#).
4. See Table 25, “Erase And Programming Performance,” on page 79 for more information.
70
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 14.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH
VIL or VIH
tVHH
tVHH
Figure 15.
October 28, 2005 S71PL129Jxx_00_A8
Accelerated Program Timing Diagram
S71PL129JC0/S71PL129JB0/S71PL129JA0
71
A d v a n c e
I n f o r m a t i o n
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
30h
Status
DOUT
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” on
page 56
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 16. Chip/Sector Erase Operation Timings
72
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
Addresses
I n f o r m a t i o n
tWC
tWC
tRC
Valid PA
Valid RA
tWC
tAH
tAS
Valid PA
Valid PA
tAS
tCPH
tACC
tAH
tCE
CE#
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Data
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# Controlled Write Cycles
Figure 17. Back-to-back Read/Write Cycle Timings
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ6–DQ0
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle
Figure 18. Data# Polling Timings (During Embedded Algorithms)
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
73
A d v a n c e
I n f o r m a t i o n
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
DQ6/DQ2
tOE
Valid Data
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
Notes:
1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or
CE# to toggle DQ2 and DQ6.
Figure 20.
74
DQ2 vs. DQ6
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Protect/Unprotect
Table 21. Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tVHH
VHH Rise and Fall Time (See Note)
Min
250
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
Min
4
µs
Note: Not 100% tested.
VID
VID
RESET#
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
tRRB
RY/BY#
Figure 21. Temporary Sector Unprotect Timing Diagram
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
75
A d v a n c e
I n f o r m a t i o n
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Group Protect/Unprotect
Data
60h
60h
Valid*
Verify
40h
Status
1 µs
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
CE#
WE#
OE#
Notes:
1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
2. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
3. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Figure 22.
76
Sector/Sector Block Protect and Unprotect Timing Diagram
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Controlled Erase Operations
Table 22.
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
Description
55
60
65
70
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
55
60
65
70
ns
tAVWL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
30
35
ns
tDVEH
tDS
Data Setup Time
Min
25
30
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE1# or CE#2 Pulse Width
Min
35
40
ns
tEHEL
tCPH
CE1# or CE#2 Pulse Width High
Min
20
25
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
6
µs
tWHWH1
tWHWH1
Accelerated Programming Operation (Note 2)
Typ
4
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
0
ns
Notes:
1. Not 100% tested.
2. See the Table 25, “Erase And Programming Performance,” on page 79 for more information.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
77
A d v a n c e
555 for program
2AA for erase
I n f o r m a t i o n
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device
4. S29PL129J - During CE1# transitions, CE2# = VIH; During CE2# transitions, CE1# = VIH
5. S29PL129J - There are two CE# (CE1#, CE2#). In the above waveform CE# = CE1# or CE2#
Table 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings
Table 24. CE1#/CE2# Timing
Parameter
JEDEC
Std
tCCR
78
Description
CE1#/CE2# Recover Time
Min
S71PL129JC0/S71PL129JB0/S71PL129JA0
All Speed Options
Unit
30
ns
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
CE1#
tCCR
tCCR
CE2#
Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control
Table 25.
Parameter
Erase And Programming Performance
Typ (Note 1)
Max (Note 2)
Unit
Comments
0.5
2
sec
135
216
sec
Excludes 00h programming
prior to erasure (Note 4)
Word Program Time
6
100
µs
Accelerated Word Program Time
4
60
µs
50.4
200
sec
Sector Erase Time
Chip Erase Time
Chip Program Time
(Note 3)
PL129J
PL129J
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6.3
7
pF
COUT
Output Capacitance
VOUT = 0
7.0
8
pF
CIN2
Control Pin Capacitance
VIN = 0
5.5
8
pF
CIN3
WP#/ACC Pin Capacitance
VIN = 0
11
12
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
79
pSRAM Type 6
2M Word by 16-bit CMOS Pseudo Static RAM (32M)
4M Word by 16-bit CMOS Pseudo Static RAM (64M )
ADVANCE
INFORMATION
Features
„ Single power supply voltage of 2.6 to 3.3 V
„ Direct TTL compatibility for all inputs and
outputs
„ Deep power-down mode: Memory cell data
invalid
„ Page operation mode:
„ Logic compatible with SRAM R/W pin
„ Standby current
— Standby = 70 µA (32M)
— Standby = 100 µA (64M)
— Deep power-down Standby = 5 µA
„ Access Times
— Page read operation by 8 words
32M
64M
Access Time
70 ns
CE1# Access Time
70 ns
OE# Access Time
25 ns
Page Access Time
30 ns
Pin Description
Pin Name
Description
A0 to A21
Address Inputs
A0 to A2
Page Address Inputs
I/O1 to I/O16
Data Inputs/Outputs
CE1#
Chip Enable Input
CE2
Chip select Input
WE#
Write Enable Input
OE#
Output Enable Input
LB#,UB#
Data Byte Control Inputs
VDD
Power Supply
GND
Ground
NC
Not Connection
Publication Number S71PL129Jxx_00
Revision A
Amendment 8
Issue Date October 28, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
Functional Description
Mode
CE1#
CE2
OE#
WE#
LB#
UB#
Address
I/O1-8
I/O9-16
Power
Read (Word)
L
H
L
H
L
L
X
DOUT
DOUT
IDDO
Read (Lower Byte)
L
H
L
H
L
H
X
DOUT
High-Z
IDDO
Read (Upper Byte)
L
H
L
H
H
L
X
High-Z
DOUT
IDDO
Write (Word)
L
H
X
L
L
L
X
DIN
DIN
IDDO
Write (Lower Byte)
L
H
X
L
L
H
X
DIN
Invalid
IDDO
Write (Upper Byte)
L
H
X
L
H
L
X
Invalid
DIN
IDDO
Outputs Disabled
L
H
H
H
X
X
X
High-Z
High-Z
IDDO
Standby
H
H
X
X
X
X
X
High-Z
High-Z
IDDO
Deep Power-down Standby
H
L
X
X
X
X
X
High-Z
High-Z
IDDSD
Legend:L = Low-level Input (VIL), H = High-level Input (VIH), X = VIL or VIH, High-Z = High Impedance.
Absolute Maximum Ratings
Symbol
Rating
Value
Unit
VDD
Power Supply Voltage
-1.0 to 3.6
V
VIN
Input Voltage
-1.0 to 3.6
V
VOUT
Output Voltage
-1.0 to 3.6
V
Topr
Operating Temperature
-40 to 85
°C
Tstrg
Storage Temperature
-55 to 150
°C
PD
Power Dissipation
0.6
W
IOUT
Short Circuit Output Current
50
mA
Note: ESD Immunity: Spansion Flash memory Multi-Chip Products (MCPs) may contain component devices that are
developed by Spansion and component devices that are developed by a third party (third-party components). Spansion
components are tested and guaranteed to the ESD immunity levels listed in the corresponding Spansion Flash memory
Qualification Database. Third-party components are neither tested nor guaranteed by Spansion for ESD immunity. However, ESD test results for third-party components may be available from the component manufacturer. Component manufacturer contact information is listed in the Spansion MCP Qualification Report, when available. The Spansion Flash
memory Qualification Database and Spansion MCP Qualification Report are available from Spansion sales offices.
DC Recommended Operating Conditions (Ta = -40°C to 85°C)
Symbol
Parameter
Min
Typ
Max
VDD
Power Supply Voltage
2.6
2.75
3.3
VIH
Input High Voltage
2.0
—
VDD + 0.3 (Note)
VIL
Input Low Voltage
-0.3 (Note)
—
0.4
Unit
V
Note: VIH (Max) VDD = 1.0 V with 10 ns pulse width. VIL (Min) -1.0 V with 10 ns pulse width.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
81
A d v a n c e
I n f o r m a t i o n
DC Characteristics (Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 3 to 4)
Symbol
Parameter
Test Condition
Min
Typ.
Max
Unit
IIL
Input Leakage
Current
VIN = 0 V to VDD
-1.0
—
+1.0
µA
ILO
Output Leakage
Current
Output disable, VOUT = 0 V to VDD
-1.0
—
+1.0
µA
VOH
Output High Voltage
IOH = - 0.5 mA
2.0
¾
V
V
VOL
Output Low Voltage
IOL = 1.0 mA
—
—
0.4
V
IDDO1
Operating Current
CE1#= VIL, CE2 = VIH, IOUT = 0
mA, tRC = min.
ET5UZ8A-43DS
—
—
40
ET5VB5A-43DS
—
—
50
IDDO2
Page Access
Operating Current
CE1#= VIL, CE2 = VIH, IOUT = 0 mA
Page add. cycling, tRC = min.
—
—
25
mA
IDDS
Standby Current
(MOS)
CE1# = VDD - 0.2 V,
CE2 = VDD - 0.2 V
ET5UZ8A-43DS
—
—
70
mA
ET5VB5A-43DS
—
—
100
µA
IDDSD
Deep Power-down
Standby Current
CE2 = 0.2 V
—
—
5
µA
mA
Capacitance (Ta = 25°C, f = 1 MHz)
Symbol
Parameter
Test Condition
Max
Unit
CIN
Input Capacitance
VIN = GND
10
pF
COUT
Output Capacitance
VOUT = GND
10
pF
Note: This parameter is sampled periodically and is not 100% tested.
AC Characteristics and Operating Conditions
(Ta = -40°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11)
Symbol
82
Parameter
Min
Max
Unit
tRC
Read Cycle Time
70
10000
ns
tACC
Address Access Time
—
70
ns
tCO
Chip Enable (CE1#) Access Time
—
70
ns
tOE
Output Enable Access Time
—
25
ns
tBA
Data Byte Control Access Time
—
25
ns
tCOE
Chip Enable Low to Output Active
10
—
ns
tOEE
Output Enable Low to Output Active
0
—
ns
tBE
Data Byte Control Low to Output Active
0
—
ns
tOD
Chip Enable High to Output High-Z
—
20
ns
tODO
Output Enable High to Output High-Z
—
20
ns
tBD
Data Byte Control High to Output High-Z
—
20
ns
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
Symbol
I n f o r m a t i o n
Parameter
Min
Max
Unit
tOH
Output Data Hold Time
10
—
ns
tPM
Page Mode Time
70
10000
ns
tPC
Page Mode Cycle Time
30
—
ns
tAA
Page Mode Address Access Time
—
30
ns
tAOH
Page Mode Output Data Hold Time
10
—
ns
tWC
Write Cycle Time
70
10000
ns
tWP
Write Pulse Width
50
—
ns
tCW
Chip Enable to End of Write
70
—
ns
tBW
Data Byte Control to End of Write
60
—
ns
tAW
Address Valid to End of Write
60
—
ns
tAS
Address Set-up Time
0
—
ns
tWR
Write Recovery Time
0
—
ns
tCEH
Chip Enable High Pulse Width
10
—
ns
tWEH
Write Enable High Pulse Width
6
—
ns
20
ns
tODW
WE# Low to Output High-Z
—
tOEW
WE# High to Output Active
0
ns
tDS
Data Set-up Time
30
—
ns
tDH
Data Hold Time
0
—
ns
tCS
CE2 Set-up Time
0
—
ns
tCH
CE2 Hold Time
300
—
µs
tDPD
CE2 Pulse Width
10
—
ms
tCHC
CE2 Hold from CE1#
0
—
ns
tCHP
CE2 Hold from Power On
30
—
µs
AC Test Conditions
Parameter
Condition
Output load
30 pF + 1 TTL Gate
Input pulse level
VDD - 0.2 V, 0.2 V
Timing measurements
VDD x 0.5
Reference level
VDD x 0.5
tR, tF
October 28, 2005 S71PL129Jxx_00_A8
5 ns
S71PL129JC0/S71PL129JB0/S71PL129JA0
83
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
Read Timings
tRC
Address
A0 to A20(32M)
A0 to A21(64M)
tACC
tOH
tCO
CE1#
Fix-H
CE2
tOE
tOD
OE#
tODO
WE#
tBA
UB#, LB#
tBE
DOUT
I/O1 to I/O16
tBD
tOEE
Hi-Z
VALID DATA OUT
tCOE
Hi-Z
INDETERMINATE
Figure 24.
84
Read Cycle
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
tPM
Address
A0 to A2
tRC
tPC
tPC
tPC
Address
A3 to A20(32M)
A3 to A21(64M)
CE1#
Fix-H
CE2
OE#
WE#
UB#, LB#
tOE
tBA
DOUT
I/O1 to I/O16
tOD
tBD
tAOH
tOEE
tAOH
tAOH
tOH
tBE
DOUT
Hi-Z
tCOE
tCO
DOUT
DOUT
tAA
tAA
tACC
DOUT
Hi-Z
tAA
tODO
* Maximum 8 words
Figure 25. Page Read Cycle (8 Words Access)
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
85
A d v a n c e
I n f o r m a t i o n
Write Timings
tWC
Address
A0 to A20(32M)
A0 to A21(64M)
tAW
tWEH
tAS
tWP
tWR
WE#
tCW
tWR
tBW
tWR
CE1#
tCH
CE2
UB#, LB#
tODW
DOUT
(See Note 10)
I/O1 to I/O16
DIN
tOEW
Hi-Z
tDS
(See Note 9)
(See Note 11)
tDH
VALID DATA IN
(See Note 9)
I/O1 to I/O16
Figure 26.
86
Write Cycle #1 (WE# Controlled) (See Note 8)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
tWC
Address
A0 to A20(32M)
A0 to A21(64M)
tAW
tAS
tWP
tWR
WE#
tCEH
tCW
tWR
CE1#
tCH
CE2
tBW
tWR
UB#, LB#
tBE
DOUT
tODW
Hi-Z
Hi-Z
I/O1 to I/O16
tCOE
tDS
DIN
(See Note 9)
tDH
VALID DATA IN
I/O1 to I/O16
Figure 27. Write Cycle #2 (CE# Controlled) (See Note 8)
Deep Power-down Timing
CE1#
tDPD
CE2
tCS
tCH
Figure 28. Deep Power Down Timing
Power-on Timing
VDD
CE1#
VDD min
tCHC
CE2
tCH
tCHP
Figure 29.
October 28, 2005 S71PL129Jxx_00_A8
Power-on Timing
S71PL129JC0/S71PL129JB0/S71PL129JA0
87
A d v a n c e
I n f o r m a t i o n
Provisions of Address Skew
Read
In case multiple invalid address cycles shorter than tRC min. sustain over 10 µs
in an active status, at least one valid address cycle over tRC min. is required during 10µs.
over 10μs
CE1#
WE#
Address
tRCmin
Figure 30.
Read
Write
In case multiple invalid address cycles shorter than tWC min. sustain over 10 µs
in an active status, at least one valid address cycle over tWC min. is required during 10 µs.
CE1#
tWPmin
WE#
Address
tWCmin
Figure 31. Write
Notes:
1. Stresses greater than listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltages are reference to GND.
3. IDDO depends on the cycle time.
4. IDDO depends on output loading. Specified values are defined with the output open condition.
5. AC measurements are assumed tR, tF = 5 ns.
6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage
reference levels.
7. Data cannot be retained at deep power-down stand-by mode.
8. If OE# is high during the write cycle, the outputs will remain at high impedance.
9. During the output state of I/O signals, input signals of reverse polarity must not be applied.
10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.
11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
88
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
pSRAM Type 1
4Mbit (256K Word x 16-bit)
8Mbit (512K Word x 16-bit)
16Mbit (1M Word x 16-bit)
32Mbit (2M Word x 16-bit)
64Mbit (4M Word x 16-bit)
ADVANCE
INFORMATION
Functional Description
Mode
CE#
CE2/ZZ#
OE#
WE#
UB#
LB#
Addresses
I/O 1-8
I/O 9-16
Power
Read (word)
L
H
L
H
L
L
X
Dout
Dout
IACTIVE
Read (lower byte)
L
H
L
H
H
L
X
Dout
High-Z
IACTIVE
Read (upper byte)
L
H
L
H
L
H
X
High-Z
Dout
IACTIVE
Write (word)
L
H
X
L
L
L
X
Din
Din
IACTIVE
Write (lower byte)
L
H
X
L
H
L
X
Din
Invalid
IACTIVE
Write (upper byte)
L
H
X
L
L
H
X
Invalid
Din
IACTIVE
Outputs disabled
L
H
H
H
X
X
X
High-Z
High-Z
IACTIVE
Standby
H
H
X
X
X
X
X
High-Z
High-Z
ISTANDBY
Deep power down
H
L
X
X
X
X
X
High-Z
High-Z
IDEEP SLEEP
Absolute Maximum Ratings
Item
Symbol
Ratings
Units
Vin, Vout
-0.2 to VCC +0.3
V
Voltage on VCC relative to VSS
VCC
-0.2 to 3.6
V
Power dissipation
PD
1
W
TSTG
-55 to 150
°C
TA
-25 to 85
°C
Voltage on any pin relative to VSS
Storage temperature
Operating temperature
Publication Number S71PL129Jxx_00
Revision A
Amendment 8
Issue Date October 28, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
DC Characteristics
(4Mb pSRAM Asynchronous)
Asynchronous
Performance Grade
-70
Density
Symbol
Parameter
Conditions
4Mb pSRAM
Min
Max
Units
2.7
3.3
V
VCC
Power Supply
VIH
Input High Level
0.8 Vccq
VCC + 0.3
V
VIL
Input Low Level
-0.3
0.4
V
IIL
Input Leakage
Current
Vin = 0 to VCC
0.5
µA
ILO
Output Leakage
Current
OE = VIH or
Chip Disabled
0.5
µA
VOH
Output High
Voltage
IOH = -1.0 mA
IOH = -0.2 mA
V
0.8 Vccq
IOH = -0.5 mA
IOL = 2.0 mA
VOL
Output Low
Voltage
IOL = 0.2 mA
0.2
V
VCC = 3.3 V
25
mA
VCC = 3.0 V
70
IOL = 0.5 mA
IACTIVE
ISTANDBY
Standby Current
VCC = 3.3 V
µA
SLEEP
Deep Power
Down Current
x
µA
IPAR 1/4
1/4 Array PAR
Current
x
µA
IPAR 1/2
1/2 Array PAR
Current
x
µA
IDEEP
90
Operating
Current
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
DC Characteristics
(8Mb pSRAM Asynchronous)
Asynchronous
Version
B
Performance Grade
Density
Symbol
Parameter
Conditions
C
-55
-70
-70
8Mb pSRAM
8Mb pSRAM
8Mb pSRAM
Min
Max
Units
Min
Max
Units
Min
Max
Units
VCC
Power Supply
2.7
3.3
V
2.7
3.6
V
2.7
3.3
V
VIH
Input High Level
2.2
VCC + 0.3
V
2.2
VCC + 0.3
V
0.8
VCC+0.3
V
VIL
Input Low Level
-0.3
0.6
V
-0.3
0.6
V
-0.3
0.4
V
IIL
Input Leakage
Current
Vin = 0 to VCC
0.5
µA
0.5
µA
0.5
µA
ILO
Output Leakage
Current
OE = VIH or
Chip Disabled
0.5
µA
0.5
µA
0.5
µA
IOH = -1.0 mA VCC-0.4
VOH
VCC-0.4
Output High Voltage IOH = -0.2 mA
V
V
0.8 VCCQ
V
IOH = -0.5 mA
IOL = 2.0 mA
VOL
Output Low Voltage
0.4
IOL = 0.2 mA
0.4
V
V
0.2
V
mA
25
mA
IOL = 0.5 mA
IACTIVE
Operating Current
ISTANDBY Standby Current
VCC = 3.3 V
25
VCC = 3.0 V
60
VCC = 3.3 V
mA
µA
23
60
µA
70
µA
Deep Power Down
Current
x
µA
x
µA
x
µA
IPAR 1/4
1/4 Array PAR
Current
x
µA
x
µA
x
µA
IPAR 1/2
1/2 Array PAR
Current
x
µA
x
µA
x
µA
IDEEP
SLEEP
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
91
A d v a n c e
I n f o r m a t i o n
DC Characteristics
(16Mb pSRAM Asynchronous)
Asynchronous
Performance Grade
Density
Symbol
Parameter
Conditions
-55
-70
16Mb pSRAM
16Mb pSRAM
Minimum
Maximum
Units
Minimum
Maximum
Units
VCC
Power Supply
2.7
3.6
V
2.7
3.6
V
VIH
Input High Level
2.2
VCC + 0.3
V
2.2
VCC + 0.3
V
VIL
Input Low Level
-0.3
0.6
V
-0.3
0.6
V
IIL
Input Leakage Current
Vin = 0 to VCC
0.5
µA
0.5
µA
ILO
Output Leakage Current
OE = VIH or Chip Disabled
0.5
µA
0.5
µA
VOH
Output High Voltage
IOH = -1.0 mA
VCC-0.4
VCC-0.4
IOH = -0.2 mA
V
V
IOH = -0.5 mA
IOL = 2.0 mA
VOL
Output Low Voltage
0.4
IOL = 0.2 mA
0.4
V
V
IOL = 0.5 mA
IACTIVE
ISTANDBY
Standby Current
VCC = 3.3 V
25
VCC = 3.0 V
100
VCC = 3.3 V
mA
µA
25
100
mA
µA
Deep Power Down Current
x
µA
x
µA
IPAR 1/4
1/4 Array PAR Current
x
µA
x
µA
IPAR 1/2
1/2 Array PAR Current
x
µA
x
µA
IDEEP SLEEP
92
Operating Current
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
DC Characteristics
(16Mb pSRAM Page Mode)
Page Mode
Performance Grade
Density
Symbol
Parameter
Conditions
-60
-65
-70
16Mb pSRAM
16Mb pSRAM
16Mb pSRAM
Min
Max
Units
Min
Max
Units
Min
Max
Units
2.7
3.3
V
2.7
3.3
V
2.7
3.3
V
VCC
Power Supply
VIH
Input High
Level
0.8 Vccq
VCC + 0.2
V
0.8 Vccq
VCC + 0.2
V
0.8 Vccq
VCC + 0.2
V
VIL
Input Low
Level
-0.2
0.2 Vccq
V
-0.2
0.2 Vccq
V
-0.2
0.2 Vccq
V
IIL
Input Leakage
Current
Vin = 0 to VCC
1
µA
1
µA
1
µA
ILO
Output
Leakage
Current
OE = VIH or
Chip Disabled
1
µA
1
µA
1
µA
VOH
Output High
Voltage
IOH = -1.0 mA
IOH = -0.2 mA
V
IOH = -0.5 mA 0.8 Vccq
V
0.8 Vccq
V
0.8 Vccq
IOL = 2.0 mA
VOL
IACTIVE
ISTANDBY
Output Low
Voltage
Operating
Current
Standby
Current
IOL = 0.2 mA
V
IOL = 0.5 mA
0.2 Vccq
VCC = 3.3 V
25
VCC = 3.0 V
VCC = 3.3 V
100
V
0.2 Vccq
mA
µA
25
100
V
0.2 Vccq
mA
µA
25
100
mA
µA
SLEEP
Deep Power
Down Current
10
µA
10
µA
10
µA
IPAR 1/4
1/4 Array PAR
Current
65
µA
65
µA
65
µA
IPAR 1/2
1/2 Array PAR
Current
80
µA
80
µA
80
µA
IDEEP
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
93
A d v a n c e
I n f o r m a t i o n
DC Characteristics
(32Mb pSRAM Page Mode)
Page Mode
Version
C
Performance Grade
Density
Symbol
Parameter
Conditions
E
-65
-60
-65
-70
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
Min
Max
Units
Min
Max
Units
Min
Max
Units
Min
Max
Units
VCC
Power
Supply
2.7
3.6
V
2.7
3.3
V
2.7
3.3
V
2.7
3.3
V
VIH
Input High
Level
1.4
VCC +
0.2
V
0.8 Vccq
VCC
+ 0.2
V
0.8 Vccq
VCC
+ 0.2
V
0.8
Vccq
VCC
+
0.2
V
VIL
Input Low
Level
-0.2
0.4
V
-0.2
0.2
Vccq
V
-0.2
0.2
Vccq
V
-0.2
0.2
Vccq
V
IIL
Input
Leakage
Current
Vin = 0 to VCC
0.5
µA
1
µA
1
µA
1
µA
ILO
Output
Leakage
Current
OE = VIH or
Chip Disabled
0.5
µA
1
µA
1
µA
1
µA
IOH = -1.0 mA
VOH
Output High
Voltage
IOH = -0.2 mA
0.8
Vccq
V
IOH = -0.5 mA
V
0.8 Vccq
V
V
0.8
Vccq
0.8 Vccq
IOL = 2.0 mA
VOL
Output Low
Voltage
IOL = 0.2 mA
0.2
V
IOL = 0.5 mA
IACTIVE
ISTANDBY
Operating
Current
Standby
Current
VCC = 3.3 V
25
VCC = 3.0 V
VCC = 3.3 V
V
0.2
Vccq
100
mA
µA
25
120
V
0.2
Vccq
mA
µA
25
120
V
0.2
Vccq
mA
µA
25
120
mA
µA
SLEEP
Deep Power
Down
Current
10
µA
10
µA
10
µA
10
µA
IPAR 1/4
1/4 Array
PAR Current
65
µA
75
µA
75
µA
75
µA
IPAR 1/2
1/2 Array
PAR Current
80
µA
90
µA
90
µA
90
µA
IDEEP
94
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
DC Characteristics
(64Mb pSRAM Page Mode)
Page Mode
Performance Grade
-70
Density
Symbol
Parameter
Conditions
64Mb pSRAM
Min
Max
Units
2.7
3.3
V
VCC
Power Supply
VIH
Input High Level
0.8 Vccq
VCC + 0.2
V
VIL
Input Low Level
-0.2
0.2 Vccq
V
IIL
Input Leakage
Current
Vin = 0 to VCC
1
µA
ILO
Output Leakage
Current
OE = VIH or
Chip Disabled
1
µA
VOH
Output High
Voltage
IOH = -1.0 mA
IOH = -0.2 mA
IOH = -0.5 mA
V
0.8 Vccq
IOL = 2.0 mA
VOL
IACTIVE
ISTANDBY
Output Low
Voltage
IOL = 0.2 mA
Operating
Current
V
IOL = 0.5 mA
0.2 Vccq
VCC = 3.3 V
25
mA
VCC = 3.0 V
Standby Current
VCC = 3.3 V
120
µA
SLEEP
Deep Power
Down Current
10
µA
IPAR 1/4
1/4 Array PAR
Current
65
µA
IPAR 1/2
1/2 Array PAR
Current
80
µA
IDEEP
Timing Test Conditions
Item
Input Pulse Level
0.1 VCC to 0.9 VCC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
Operating Temperature
October 28, 2005 S71PL129Jxx_00_A8
0.5 VCC
-25°C to +85°C
S71PL129JC0/S71PL129JB0/S71PL129JA0
95
A d v a n c e
I n f o r m a t i o n
Output Load Circuit
VCC
14.5K
I/O
30 pF
14.5K
Output Load
Figure 32.
Output Load Circuit
Power Up Sequence
After applying power, maintain a stable power supply for a minimum of 200 µs
after CE# > VIH.
96
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
(4Mb pSRAM Page Mode)
Asynchronous
Performance Grade
-70
Density
Read
3 Volt
October 28, 2005 S71PL129Jxx_00_A8
Symbol
Parameter
4Mb pSRAM
Min
Max
70
Units
trc
Read cycle time
ns
taa
Address Access
Time
70
ns
tco
Chip select to
output
70
ns
toe
Output enable to
valid output
20
ns
tba
UB#, LB# Access
time
70
ns
tlz
Chip select to
Low-z output
10
ns
tblz
UB#, LB# Enable
to Low-Z output
10
ns
tolz
Output enable to
Low-Z output
5
ns
thz
Chip enable to
High-Z output
0
20
ns
tbhz
UB#, LB#
disable to High-Z
output
0
20
ns
tohz
Output disable to
High-Z output
0
20
ns
toh
Output hold from
Address Change
10
S71PL129JC0/S71PL129JB0/S71PL129JA0
ns
97
A d v a n c e
I n f o r m a t i o n
Asynchronous
Performance Grade
-70
Density
Other
Write
3 Volt
98
4Mb pSRAM
Symbol
Parameter
Min
Max
twc
Write cycle time
70
ns
tcw
Chipselect to end
of write
70
ns
tas
Address set up
Time
0
ns
taw
Address valid to
end of write
70
ns
tbw
UB#, LB# valid
to end of write
70
ns
twp
Write pulse width
55
ns
twr
Write recovery
time
0
ns
twhz
Write to output
High-Z
tdw
Data to write
time overlap
tdh
20
Units
ns
25
ns
Data hold from
write time
0
ns
tow
End write to
output Low-Z
5
tow
Write high pulse
width
7.5
tpc
Page read cycle
x
tpa
Page address
access time
ns
x
twpc
Page write cycle
x
tcp
Chip select high
pulse width
x
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
(8Mb pSRAM Asynchronous)
Asynchronous
Version
B
Performance Grade
Density
Read
3 Volt
Symbol
Parameter
Min
C
-55
-70
-70
8Mb pSRAM
8Mb pSRAM
8Mb pSRAM
Max
Min
ns
70
Max
Units
Min
ns
70
Max
Units
trc
Read cycle time
taa
Address Access
Time
55
ns
70
ns
70
ns
tco
Chip select to
output
55
ns
70
ns
70
ns
toe
Output enable to
valid output
30
ns
35
ns
20
ns
tba
UB#, LB# Access
time
55
ns
70
ns
70
ns
tlz
Chip select to
Low-z output
5
ns
5
ns
10
ns
tblz
UB#, LB# Enable
to Low-Z output
5
ns
5
ns
10
ns
tolz
Output enable to
Low-Z output
5
ns
5
ns
5
ns
thz
Chip enable to
High-Z output
0
20
ns
0
25
ns
0
20
ns
tbhz
UB#, LB#
disable to High-Z
output
0
20
ns
0
25
ns
0
20
ns
tohz
Output disable to
High-Z output
0
20
ns
0
25
ns
0
20
ns
toh
Output hold from
Address Change
10
ns
10
ns
10
October 28, 2005 S71PL129Jxx_00_A8
55
Units
S71PL129JC0/S71PL129JB0/S71PL129JA0
ns
ns
99
A d v a n c e
I n f o r m a t i o n
Asynchronous
Version
B
Performance Grade
Density
Other
Write
3 Volt
100
Symbol
Parameter
Min
C
-55
-70
-70
8Mb pSRAM
8Mb pSRAM
8Mb pSRAM
Max
Units
Min
Max
Units
Min
Max
Units
twc
Write cycle time
55
ns
70
ns
70
ns
tcw
Chip select to
end of write
45
ns
55
ns
70
ns
tas
Address set up
Time
0
ns
0
ns
0
ns
taw
Address valid to
end of write
45
ns
55
ns
70
ns
tbw
UB#, LB# valid
to end of write
45
ns
55
ns
70
ns
twp
Write pulse width
45
ns
55
ns
55
ns
twr
Write recovery
time
0
ns
0
ns
0
ns
twhz
Write to output
High-Z
tdw
Data to write
time overlap
tdh
25
ns
25
20
ns
40
ns
40
ns
25
ns
Data hold from
write time
0
ns
0
ns
0
ns
tow
End write to
output Low-Z
5
tow
Write high pulse
width
x
tpc
Page read cycle
x
tpa
Page address
access time
5
x
ns
x
5
x
x
x
ns
x
x
ns
x
x
x
twpc
Page write cycle
x
x
x
tcp
Chip select high
pulse width
x
x
x
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
(16Mb pSRAM Asynchronous)
Asynchronous
Performance Grade
Density
Read
3 Volt
October 28, 2005 S71PL129Jxx_00_A8
Symbol
Parameter
Min
-55
-70
16Mb pSRAM
16Mb pSRAM
Max
55
Units
Min
ns
70
Max
Units
trc
Read cycle time
taa
Address Access
Time
55
ns
70
ns
tco
Chip select to
output
55
ns
70
ns
toe
Output enable to
valid output
30
ns
35
ns
tba
UB#, LB# Access
time
55
ns
70
ns
tlz
Chip select to
Low-z output
5
ns
5
ns
tblz
UB#, LB# Enable
to Low-Z output
5
ns
5
ns
tolz
Output enable to
Low-Z output
5
ns
5
ns
thz
Chip enable to
High-Z output
0
25
ns
0
25
ns
tbhz
UB#, LB#
disable to High-Z
output
0
25
ns
0
25
ns
tohz
Output disable to
High-Z output
0
25
ns
0
25
ns
toh
Output hold from
Address Change
10
ns
10
S71PL129JC0/S71PL129JB0/S71PL129JA0
ns
ns
101
A d v a n c e
I n f o r m a t i o n
Asynchronous
Performance Grade
-55
Density
Other
Write
3 Volt
102
Symbol
Parameter
-70
16Mb pSRAM
Min
Max
16Mb pSRAM
Units
Min
Max
Units
twc
Write cycle time
55
ns
70
ns
tcw
Chipselect to end
of write
50
ns
55
ns
tas
Address set up
Time
0
ns
0
ns
taw
Address valid to
end of write
50
ns
55
ns
tbw
UB#, LB# valid
to end of write
50
ns
55
ns
twp
Write pulse width
50
ns
55
ns
twr
Write recovery
time
0
ns
0
ns
twhz
Write to output
High-Z
tdw
Data to write
time overlap
tdh
25
ns
25
ns
25
ns
25
ns
Data hold from
write time
0
ns
0
ns
tow
End write to
output Low-Z
5
tow
Write high pulse
width
x
tpc
Page read cycle
x
tpa
Page address
access time
5
x
ns
x
x
ns
x
x
x
twpc
Page write cycle
x
x
tcp
Chip select high
pulse width
x
x
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
(16Mb pSRAM Page Mode)
Page Mode
Performance Grade
Density
Read
3 Volt
Symbol
Parameter
-60
-65
-70
16Mb pSRAM
16Mb pSRAM
16Mb pSRAM
Min
Max
Units
Min
Max
Units
Min
Max
Units
60
20k
ns
65
20k
ns
70
20k
ns
trc
Read cycle time
taa
Address Access
Time
60
ns
65
ns
70
ns
tco
Chip select to
output
60
ns
65
ns
70
ns
toe
Output enable to
valid output
25
ns
25
ns
25
ns
tba
UB#, LB# Access
time
60
ns
65
ns
70
ns
tlz
Chip select to
Low-z output
10
ns
10
ns
10
ns
tblz
UB#, LB# Enable
to Low-Z output
10
ns
10
ns
10
ns
tolz
Output enable to
Low-Z output
5
ns
5
ns
5
ns
thz
Chip enable to
High-Z output
0
5
ns
0
5
ns
0
5
ns
tbhz
UB#, LB#
disable to High-Z
output
0
5
ns
0
5
ns
0
5
ns
tohz
Output disable to
High-Z output
0
5
ns
0
5
ns
0
5
ns
toh
Output hold from
Address Change
5
ns
5
ns
5
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
ns
103
A d v a n c e
I n f o r m a t i o n
Page Mode
Performance Grade
-60
Density
Other
Write
3 Volt
104
-65
16Mb pSRAM
-70
16Mb pSRAM
16Mb pSRAM
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
twc
Write cycle time
60
20k
ns
65
20k
ns
70
20k
ns
tcw
Chipselect to end
of write
50
ns
60
ns
60
ns
tas
Address set up
Time
0
ns
0
ns
0
ns
taw
Address valid to
end of write
50
ns
60
ns
60
ns
tbw
UB#, LB# valid
to end of write
50
ns
60
ns
60
ns
twp
Write pulse width
50
ns
50
ns
50
ns
twr
Write recovery
time
0
ns
0
ns
0
ns
twhz
Write to output
High-Z
tdw
Data to write
time overlap
tdh
5
ns
5
ns
5
ns
20
ns
20
ns
20
ns
Data hold from
write time
0
ns
0
ns
0
ns
tow
End write to
output Low-Z
5
tow
Write high pulse
width
7.5
tpc
Page read cycle
25
tpa
Page address
access time
twpc
Page write cycle
25
tcp
Chip select high
pulse width
10
5
ns
7.5
20k
ns
25
25
ns
20k
ns
25
ns
10
5
ns
7.5
20k
ns
25
25
ns
20k
ns
25
ns
10
S71PL129JC0/S71PL129JB0/S71PL129JA0
ns
20k
ns
25
ns
20k
ns
ns
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
(32Mb pSRAM Page Mode)
Page Mode
Version
C
Performance Grade
Density
Read
3 Volt
Symbol
Parameter
E
-65
-60
-65
-70
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
Min
Max
Units
Min
Max
Units
Min
Max
Units
Min
Max
Units
65
20k
ns
60
20k
ns
65
20k
ns
70
20k
ns
trc
Read cycle time
taa
Address Access
Time
65
ns
60
ns
65
ns
70
ns
tco
Chip select to
output
65
ns
60
ns
65
ns
70
ns
toe
Output enable to
valid output
20
ns
25
ns
25
ns
25
ns
tba
UB#, LB# Access
time
65
ns
60
ns
65
ns
70
ns
tlz
Chip select to
Low-z output
10
ns
10
ns
10
ns
10
ns
tblz
UB#, LB# Enable
to Low-Z output
10
ns
10
ns
10
ns
10
ns
tolz
Output enable to
Low-Z output
5
ns
5
ns
5
ns
5
ns
thz
Chip enable to
High-Z output
0
20
ns
0
5
ns
0
5
ns
0
5
ns
tbhz
UB#, LB#
disable to High-Z
output
0
20
ns
0
5
ns
0
5
ns
0
5
ns
tohz
Output disable to
High-Z output
0
20
ns
0
5
ns
0
5
ns
0
5
ns
toh
Output hold from
Address Change
5
ns
5
ns
5
ns
5
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
ns
105
A d v a n c e
I n f o r m a t i o n
Page Mode
Version
C
Performance Grade
Density
Other
Write
3 Volt
106
E
-65
-60
-65
-70
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
32Mb pSRAM
Symbol
Parameter
Min
Max
Units
Min
Max
Units
Min
Max
Units
Min
Max
Units
twc
Write cycle time
65
20k
ns
60
20k
ns
65
20k
ns
70
20k
ns
tcw
Chipselect to end
of write
55
ns
50
ns
60
ns
60
ns
tas
Address set up
Time
0
ns
0
ns
0
ns
0
ns
taw
Address valid to
end of write
55
ns
50
ns
60
ns
60
ns
tbw
UB#, LB# valid
to end of write
55
ns
50
ns
60
ns
60
ns
twp
Write pulse width
55
ns
50
ns
50
ns
50
ns
twr
Write recovery
time
ns
0
ns
0
ns
0
ns
twhz
Write to output
High-Z
tdw
Data to write
time overlap
tdh
20k
0
5
ns
5
ns
5
ns
5
ns
25
ns
20
ns
20
ns
20
ns
Data hold from
write time
0
ns
0
ns
0
ns
0
ns
tow
End write to
output Low-Z
5
tow
Write high pulse
width
7.5
tpc
Page read cycle
25
tpa
Page address
access time
twpc
Page write cycle
25
tcp
Chip select high
pulse width
10
5
ns
7.5
20k
ns
25
25
ns
20k
ns
25
ns
10
5
ns
7.5
20k
ns
25
25
ns
20k
ns
25
ns
10
S71PL129JC0/S71PL129JB0/S71PL129JA0
5
ns
7.5
20k
ns
25
25
ns
20k
ns
25
ns
10
ns
20k
ns
25
ns
20k
ns
ns
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
(64Mb pSRAM Page Mode)
Page Mode
Performance Grade
-70
Density
Read
3 Volt
October 28, 2005 S71PL129Jxx_00_A8
Symbol
Parameter
64Mb pSRAM
Min
Max
Units
70
20k
ns
trc
Read cycle time
taa
Address Access
Time
70
ns
tco
Chip select to
output
70
ns
toe
Output enable to
valid output
25
ns
tba
UB#, LB# Access
time
70
ns
tlz
Chip select to
Low-z output
10
ns
tblz
UB#, LB# Enable
to Low-Z output
10
ns
tolz
Output enable to
Low-Z output
5
ns
thz
Chip enable to
High-Z output
0
5
ns
tbhz
UB#, LB#
disable to High-Z
output
0
5
ns
tohz
Output disable to
High-Z output
0
5
ns
toh
Output hold from
Address Change
5
S71PL129JC0/S71PL129JB0/S71PL129JA0
ns
107
A d v a n c e
I n f o r m a t i o n
Page Mode
Performance Grade
-70
Density
Other
Write
3 Volt
64Mb pSRAM
Symbol
Parameter
Min
Max
Units
twc
Write cycle time
70
20k
ns
tcw
Chipselect to end
of write
60
ns
tas
Address set up
Time
0
ns
taw
Address valid to
end of write
60
ns
tbw
UB#, LB# valid
to end of write
60
ns
twp
Write pulse width
50
twr
Write recovery
time
twhz
Write to output
High-Z
tdw
Data to write
time overlap
tdh
20k
0
ns
ns
5
ns
20
ns
Data hold from
write time
0
ns
tow
End write to
output Low-Z
5
tow
Write high pulse
width
7.5
tpc
Page read cycle
20
tpa
Page address
access time
twpc
Page write cycle
20
tcp
Chip select high
pulse width
10
ns
20k
ns
20
ns
20k
ns
ns
Timing Diagrams
Read Cycle
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Figure 33.
108
Data Valid
Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
tRC
Address
tAA
CE#
tCO
tLZ
tHZ
tOE
OE#
tOLZ
tOHZ
tLB, tUB
LB#, UB#
tBLZ
High-Z
Data Valid
Data Out
Figure 34.
October 28, 2005 S71PL129Jxx_00_A8
tBHZ
Timing Waveform of Read Cycle (WE# = ZZ# = VIH)
S71PL129JC0/S71PL129JB0/S71PL129JA0
109
A d v a n c e
I n f o r m a t i o n
tPGMAX
Page Address (A4 - A20)
tRC
tPC
Word Address (A0 - A3)
tAA
tPA
CE#
tHZ
tCO
tOE
tOHZ
OE#
tOLZ
LB#, UB#
tBHZ
tLB, tUB
High-Z
tBLZ,
Data Out
Figure 35.
110
Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = VIH)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Write Cycle
tWC
Addr es s
tWR
tAW
CE#
tCW
tBW
LB#, UB#
tAS
tWP
WE#
tDW
High-Z
tDH
Data Valid
Dat a In
tWHZ
tOW
High-Z
Da ta Out
Figure 36. Timing Waveform of Write Cycle (WE# Control, ZZ# = VIH)
tWC
Ad dres s
tAW
tWR
CE#
tCW
tAS
tBW
LB#, UB#
tWP
WE#
tDW
tDH
Data Valid
Dat a In
tWHZ
High-Z
Da ta O ut
Figure 37. Timing Waveform of Write Cycle (CE# Control, ZZ# = VIH)
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
111
A d v a n c e
I n f o r m a t i o n
tPGMAX
Page A ddr es s
(A4 - A 20)
tWC
tPWC
Wor d A ddr es s
(A0 - A3 )
tAS
tCW
CE#
tWP
WE#
tLBW, tUBW
LB#, UB#
tDW
tDH
tPDW
tPDH
tPDW
tPDH
High-Z
Dat a Out
Figure 38.
Timing Waveform of Page Mode Write Cycle (ZZ# = VIH)
Power Savings Modes (For 16M Page Mode, 32M and 64M Only)
There are several power savings modes.
„ Partial Array Self Refresh
„ Temperature Compensated Refresh (64M)
„ Deep Sleep Mode
„ Reduced Memory Size (32M, 16M)
The operation of the power saving modes ins controlled by the settings of bits
contained in the Mode Register. This definition of the Mode Register is shown in
Figure 39 and the various bits are used to enable and disable the various low
power modes as well as enabling Page Mode operation. The Mode Register is set
by using the timings defined in Figure xxx.
Partial Array Self Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a
16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is
determined by the respective bit settings in the Mode Register. The register settings for the PASR operation are defined in Table xxx. In this PASR mode, when
ZZ# is active low, only the portion of the array that is set in the register is re-
112
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
freshed. The data in the remainder of the array will be lost. The PASR operation
mode is only available during standby time (ZZ# low) and once ZZ# is returned
high, the device resumes full array refresh. All future PASR cycles will use the
contents of the Mode Register that has been previously set. To change the address space of the PASR mode, the Mode Register must be reset using the
previously defined procedures. For PASR to be activated, the register bit, A4 must
be set to a one (1) value, “PASR Enabled”. If this is the case, PASR will be activated 10 µs after ZZ# is brought low. If the A4 register bit is set equal to zero
(0), PASR will not be activated.
Temperature Compensated Refresh (for 64Mb)
In this mode of operation, the internal refresh rate can be optimized for the operation temperature used and this can then lower standby current. The DRAM
array in the PSRAM must be refreshed internally on a regular basis. At higher
temperatures, the DRAM cell must be refreshed more often than at lower temperatures. By setting the temperature of operation in the Mode Register, this
refresh rate can be optimized to yield the lowest standby current at the given operating temperature. There are four different temperature settings that can be
programmed in to the PSRAM. These are defined in Figure 39.
Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity
of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 register bit set to a zero (0), “Deep Sleep Enabled”. If this is the case, Deep Sleep
will be entered 10 µs after ZZ# is brought low. The device will remain in this mode
as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep
Sleep will not be activated.
Reduced Memory Size (for 32M and 16M)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb
device. The mode and array size are determined by the settings in the VA register.
The VA register is set according to the following timings and the bit settings in
the table “Address Patterns for RMS”. The RMS mode is enabled at the time of ZZ
transitioning high and the mode remains active until the register is updated. To
return to the full 32Mb address space, the VA register must be reset using the
previously defined procedures. While operating in the RMS mode, the unselected
portion of the array may not be used.
Other Mode Register Settings (for 64M)
The Page Mode operation can also be enabled and disabled using the Mode Register. Register bit A7 controls the operation of Page Mode and setting this bit to a
one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode
operation is disabled.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
113
A d v a n c e
I n f o r m a t i o n
64 Mb
A21 - A8
A7
32 Mb / 16 Mb
A6
Reserved
Must set to all 0
A5
A4
A3
0 = 15oC
0
1 = 45oC
0
0 = 70oC
1
1 = 85oC (default)
A1
A0
Array Mode
for ZZ#
Temp
Compensated
Refresh
1
A2
0 = PAR (default)
1 = RMS
1
1
1
1
0
0
0
0
PAR Section
1
1
0
0
1
1
0
0
1 = Top 1/4 array
0 = Top 1/2 array
1 = Top 3/4 array
0 = No PAR
1 = Bottom 1/4 array
0 = Bottom 1/2 array
1 = Bottom 3/4 array
0 = Full array (default)
Page Mode
0 = Page Mode Disabled (default)
1 = Page Mode Enabled
Deep Sleep Enable/Disable
0 = Deep Sleep Enabled
1 = Deep Sleep Disabled (default)
Figure 39. Mode Register
tWC
Address
tAS
tAW
tWR
CE#
tWP
WE#
tCDZZ
tZZWE
ZZ#
Figure 40.
114
Mode Register Update Timings (UB#, LB#, OE# are Don’t Care)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
tZZMIN
ZZ#
tR
tCDZZ
CE#
Figure 41. Deep Sleep Mode - Entry/Exit Timings (for 64M)
tWC
A4
tAS
tAW
CE#
tWR
tWP
WE#
LB#, UB#
tZZWE
tBW
tR
tZZMIN
ZZ#
Figure 42.
Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M)
Mode Register Update and Deep Sleep Timings
Item
Symbol
Min
Chip deselect to ZZ# low
tCDZZ
5
ZZ# low to WE# low
tZZWE
10
Write register cycle time
tWC
70/85
ns
1
Chip enable to end of write
tCW
70/85
ns
1
Address valid to end of write
tAW
70/85
ns
1
Write recovery time
tWR
0
ns
Address setup time
tAS
0
ns
Write pulse width
tWR
40
ns
tZZMIN
10
µs
tR
200
µs
Deep Sleep Pulse Width
Deep Sleep Recovery
Max
Unit
Note
ns
500
ns
Notes:
1. Minimum cycle time for writing register is equal to speed grade of product.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
115
A d v a n c e
I n f o r m a t i o n
Address Patterns for PASR (A4=1) (64M)
A2
A1
A0
Active Section
Address Space
Size
Density
1
1
1
Top quarter of die
300000h-3FFFFFh
1Mb x 16
16Mb
1
1
0
Top half of die
200000h-3FFFFFh
2Mb x 16
32Mb
1
0
1
Reserved
1
0
0
No PASR
None
0
0
0
1
1
Bottom quarter of die
000000h-0FFFFFh
1Mb x 16
16Mb
0
1
0
Bottom half of die
000000h-1FFFFFh
2Mb x 16
32Mb
0
0
1
Reserved
0
0
0
Full array
000000h-3FFFFFh
4Mb x 16
64Mb
116
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Deep ICC Characteristics (for 64Mb)
Item
Symbol
PASR Mode Standby Current
IPASR
Test
Array Partition
VIN = VCC or 0V, Chip Disabled, tA = 85°C
Item
Symbol
Temperature Compensated Refresh Current
Max Temperature
ITCR
Typ
Max
None
10
1/4 Array
60
1/2 Array
80
Full Array
120
Typ
Max
15°C
50
45°C
60
70°C
80
85°C
120
Item
Symbol
Test
Deep Sleep Current
IZZ
VIN = VCC or 0V, Chip in ZZ# mode, tA = 25°C
Unit
µA
Unit
µA
Typ
Max
Unit
10
µA
Address Patterns for PAR (A3= 0, A4=1) (32M)
A2
A1
A0
Active Section
0
1
1
One-quarter of die
0
1
0
x
0
1
1
Address Space
Size
Density
000000h - 07FFFFh
512Kb x 16
8Mb
One-half of die
000000h - 0FFFFFh
1Mb x 16
16Mb
0
Full die
000000h - 1FFFFFh
2Mb x 16
32Mb
1
1
One-quarter of die
180000h - 1FFFFFh
512Kb x 16
8Mb
1
0
One-half of die
100000h - 1FFFFFh
1Mb x 16
16Mb
Size
Density
Address Patterns for RMS (A3 = 1, A4 = 1) (32M)
A2
A1
A0
Active Section
0
1
1
One-quarter of die
000000h - 07FFFFh
512Kb x 16
8Mb
0
1
0
One-half of die
000000h - 0FFFFFh
1Mb x 16
16Mb
1
1
1
One-quarter of die
180000h - 1FFFFFh
512Kb x 16
8Mb
1
1
0
One-half of die
100000h - 1FFFFFh
1Mb x 16
16Mb
October 28, 2005 S71PL129Jxx_00_A8
Address Space
S71PL129JC0/S71PL129JB0/S71PL129JA0
117
A d v a n c e
I n f o r m a t i o n
Low Power ICC Characteristics (32M)
Item
Symbol
Test
VIN = VCC or 0V,
PAR Mode Standby Current IPAR
Chip Disabled, tA= 85 C
o
VIN = VCC or 0V,
RMS Mode Standby Current IRMSSB
Deep Sleep Current
Array Partition
Chip Disabled, tA= 85 C
o
Typ
Max
Unit
1/4 Array
75
µA
1/2 Array
90
µA
8Mb Device
75
µA
16Mb Device
90
µA
10
µA
VIN = VCC or 0V,
IZZ
Chip in ZZ mode, tA= 85oC
Address Patterns for PAR (A3= 0, A4=1) (16M)
A2
A1
A0
Active Section
0
1
1
One-quarter of die
0
1
0
x
0
1
1
Address Space
Size
Density
00000h - 0FFFFh
256Kb x 16
4Mb
One-half of die
00000h - 7FFFFh
512Kb x 16
8Mb
0
Full die
00000h - FFFFFh
1Mb x 16
16Mb
1
1
One-quarter of die
C0000h - FFFFh
256Kb x 16
4Mb
1
0
One-half of die
80000h - 1FFFFFh
512Kb x 16
8Mb
Size
Density
Address Patterns for RMS (A3 = 1, A4 = 1) (16M)
A2
A1
A0
Active Section
Address Space
0
1
1
One-quarter of die
00000h - 0FFFFh
256Kb x 16
4Mb
0
1
0
One-half of die
00000h - 7FFFFh
512Kb x 16
8Mb
1
1
1
One-quarter of die
C0000h - FFFFFh
256Kb x 16
4Mb
1
1
0
One-half of die
80000h - FFFFFh
512Kb x 16
8Mb
Low Power ICC Characteristics (16M)
Item
Symbol
Array Partition
VIN = VCC or 0V,
PAR Mode Standby Current
IPAR
RMS Mode Standby Current
IRMSSB
Deep Sleep Current
IZZ
118
Test
Chip Disabled, tA= 85 C
o
VIN = VCC or 0V,
Chip Disabled, tA= 85 C
o
VIN = VCC or 0V,
Chip in ZZ# mode, tA= 85oC
S71PL129JC0/S71PL129JB0/S71PL129JA0
Typ
Max
1/4 Array
65
1/2 Array
80
4Mb Device
65
8Mb Device
80
10
Unit
µA
µA
µA
S71PL129Jxx_00_A8 October 28, 2005
Type 2 pSRAM
16Mbit (1M Word x 16-bit)
32Mbit (2M Word x 16-bit)
64Mbit (4M Word x 16-bit)
128Mbit (8M Word x 16-bit)
ADVANCE
INFORMATION
Features
„ Process Technology: CMOS
„ Organization: x16 bit
„ Power Supply Voltage: 2.7~3.1V
„ Three State Outputs
„ Compatible with Low Power SRAM
Product Information
Density
VCC Range
Standby
(ISB1, Max.)
Operating
(ICC2, Max.)
Mode
16Mb
2.7-3.1V
80 µA
30 mA
Dual CS
16Mb
2.7-3.1V
80 µA
35 mA
Dual CS and Page Mode
32Mb
2.7-3.1V
100 µA
35 mA
Dual CS
32Mb
2.7-3.1V
100 µA
40 mA
Dual CS and Page Mode
64Mb
2.7-3.1V
TBD
TBD
Dual CS
64Mb
2.7-3.1V
120 µA
45 µA
Dual CS and Page Mode
128Mb
2.7-3.1V
TBD
TBD
Dual CS and Page Mode
Publication Number S71PL129Jxx_00
Revision A
Amendment 8
Issue Date October 28, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
Pin Description
Pin Name
CS1#, CS2
Description
I/O
Chip Select
I
OE#
Output Enable
I
WE#
Write Enable
I
Lower/Upper Byte Enable
I
Address Inputs
I
LB#, UB#
A0-A19 (16M)
A0-A20 (32M)
A0-A21 (64M)
A0-A22 (128M)
I/O0-I/O15
Data Inputs/Outputs
I/O
VCC/VCCQ
Power Supply
—
VSS/VSSQ
Ground
—
Not Connection
—
Do Not Use
—
NC
DNU
Power Up Sequence
120
1.
Apply power.
2.
Maintain stable power (VCC min.=2.7V) for a minimum 200 µs with
CS1#=high or CS2=low.
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
Power Up
Min. 200 s
VCC(Min)
VCC
CS1#
CS2
Power Up Mode
Figure 43.
Normal Operation
Power Up 1 (CS1# Controlled)
Notes:
1. After VCC reaches VCC(Min.), wait 200 µs with CS1# high. Then the device gets into the normal operation.
Min. 200μs
~
~
VCC(Min)
~
~ ~
~
VCC
CS1#
~
~
CS2
Power Up Mode
Figure 44.
Normal Operation
Power Up 2 (CS2 Controlled)
Notes:
1. After VCC reaches VCC(Min.), wait 200 µs with CS2 low. Then the device gets into the normal operation.
Functional Description
Mode
CS1#
CS2
OE#
WE#
LB#
UB#
I/O1-8
I/O9-16
Power
Deselected
H
X
X
X
X
X
High-Z
High-Z
Standby
Deselected
X
L
X
X
X
X
High-Z
High-Z
Standby
Deselected
X
X
X
X
H
H
High-Z
High-Z
Standby
Output Disabled
L
H
H
H
L
X
High-Z
High-Z
Active
Outputs Disabled
L
H
H
H
X
L
High-Z
High-Z
Active
Lower Byte Read
L
H
L
H
L
H
DOUT
High-Z
Active
Upper Byte Read
L
H
L
H
H
L
High-Z
DOUT
Active
Word Read
L
H
L
H
L
L
DOUT
DOUT
Active
Lower Byte Write
L
H
X
L
L
H
DIN
High-Z
Active
Upper Byte Write
L
H
X
L
H
L
High-Z
DIN
Active
Word Write
L
H
X
L
L
L
DIN
DIN
Active
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
121
A d v a n c e
I n f o r m a t i o n
Legend:X = Don’t care (must be low or high state).
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VIN , VOUT
-0.2 to VCC+0.3V
V
Voltage on VCC supply relative to VSS
VCC
-0.2 to 3.6V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
°C
Voltage on any pin relative to VSS
Notes:
1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating
conditions longer than one second may affect reliability.
DC Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
VCC
Power Supply Voltage
2.7
2.9
3.1
VSS
Ground
0
0
0
VIH
Input High Voltage
VIL
2.2 (16Mb, 32Mb, 128Mb)
0.8 x VCC (64Mb
Input Low Voltage
-0.2 (Note 3)
Unit
VCC + 0.3 (16Mb, 32Mb, 128Mb)
—
VCC + 0.2 (64Mb)
V
(Note 2)
—
0.6
Notes:
1. TA=-40 to 85°C, unless otherwise specified.
2. Overshoot: VCC+1.0V in case of pulse width ≤ 20ns.
3. Undershoot: -1.0V in case of pulse width ≤ 20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance
(Ta = 25°C, f = 1 MHz)
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
VIN = 0V
—
8
pF
CIO
Input/Output Capacitance
VOUT = 0V
—
10
pF
Note: This parameter is sampled periodically and is not 100% tested.
122
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
DC and Operating Characteristics
Common
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN=VSS to VCC
-1
—
1
µA
Output Leakage Current
ILO
CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL or
LB#=UB#=VIH, VIO=VSS to VCC
-1
—
1
µA
Output Low Voltage
VOL
IOL=2.1mA
—
—
0.4
V
Output High Voltage
VOH
IOH=-1.0mA
2.4
—
—
V
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
123
A d v a n c e
I n f o r m a t i o n
16M pSRAM
Item
Symbol
—
—
7
mA
Async
Cycle time=Min, IIO=0mA, 100% duty,
CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL,
VIN=VIH or VIL
—
—
30
mA
Page
Cycle time=tRC+3tPC, IIO=0mA, 100% duty,
CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL,
VIN-VIH or VIL
35
mA
80
µA
ICC2
Standby Current (CMOS)
Min Typ Max Unit
Cycle time=1µs, 100% duty, IIO=0mA,
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
ICC1
Average Operating
Current
Test Conditions
ISB1 (Note 1)
Other inputs=0-VCC
1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1#
controlled) or
—
—
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
32M pSRAM
Item
Symbol
—
—
7
mA
Async
Cycle time=Min, IIO=0mA, 100% duty,
CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL,
VIN=VIH or VIL
—
—
35
mA
Page
Cycle time=tRC+3tPC, IIO=0mA, 100% duty,
CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL,
VIN-VIH or VIL
40
mA
100
µA
ICC2
Standby Current (CMOS)
Min Typ Max Unit
Cycle time=1µs, 100% duty, IIO=0mA,
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
ICC1
Average Operating
Current
Test Conditions
ISB1 (Note 1)
Other inputs=0-VCC
1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1#
controlled) or
—
—
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
124
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
64M pSRAM
Item
Symbol
Test Conditions
Cycle time=1µs, 100% duty, IIO=0mA,
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
—
—
TBD
mA
Async
Cycle time=Min, IIO=0mA, 100% duty,
CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL,
VIN=VIH or VIL
—
—
TBD
mA
Page
Cycle time=tRC+3tPC, IIO=0mA, 100% duty,
CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL,
VIN-VIH or VIL
45
mA
120
µA
ICC1
Average Operating
Current
ICC2
Standby Current (CMOS)
Min Typ Max Unit
ISB1 (Note 1)
Other inputs=0-VCC
1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1#
controlled) or
—
—
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from
the time when standby mode is set up.
128M pSRAM
Item
Average Operating
Current
Symbol
Test Conditions
Min Typ Max Unit
ICC1
Cycle time=1µs, 100% duty, IIO=0mA, CS1#≤0.2V,
LB#≤0.2V and/or UB#≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or
VIN≥VCC-0.2V
—
—
TBD
mA
ICC2
Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL,
CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL
—
—
TBD
mA
—
—
TBD
µA
Other inputs=0-VCC
Standby Current (CMOS) ISB1 (Note 1) 1. CS1# ≥ VCC - 0.2, CS2 ≥ VCC - 0.2V (CS1# controlled) or
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
Notes:
Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measured after 60ms
from the time when standby mode is set up.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
125
A d v a n c e
I n f o r m a t i o n
AC Operating Conditions
Test Conditions (Test Load and Test Input/Output Reference)
„ Input pulse level: 0.4 V to 2.2 V (16Mb, 32Mb, 128Mb); 0.3 V to 2.2 V
(64Mb)
„ Input rising and falling time: 5ns (16Mb, 32Mb); 3ns (64Mb, 128Mb)
„ Input and output reference voltage: 1.5V (16Mb, 32Mb); 0.5 x VCC (64Mb,
128Mb)
„ Output load (See Figure 45): 50pF (16Mb, 32Mb); 30pF (64Mb, 128Mb)
Dout
CL
Figure 45.
Output Load
Note: Including scope and jig capacitance.
126
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
(Ta = -40°C to 85°C, VCC = 2.7 to 3.1 V)
Speed Bins
70ns
Write
Read
Symbol
Parameter
Min
Max
Unit
tRC
Read Cycle Time
70
—
ns
tAA
Address Access Time
—
70
ns
tCO
Chip Select to Output
—
70
ns
tOE
Output Enable to Valid Output
—
35
ns
tBA
UB#, LB# Access Time
—
70
ns
tLZ
Chip Select to Low-Z Output
10
—
ns
tBLZ
UB#, LB# Enable to Low-Z Output
10
—
ns
tOLZ
Output Enable to Low-Z Output
5
—
ns
tHZ
Chip Disable to High-Z Output
0
25
ns
tBHZ
UB#, LB# Disable to High-Z Output
0
25
ns
tOHZ
Output Disable to High-Z Output
0
25
ns
tOH
Output Hold from Address Change
5
(3 for 64Mb)
—
ns
tPC
Page Cycle Time
25
—
ns
tPA
Page Access Time
—
20
ns
tWC
Write Cycle Time
70
—
ns
tCW
Chip Select to End of Write
60
—
ns
tAS
Address Set-up Time
0
—
ns
tAW
Address Valid to End of Write
60
—
ns
tBW
UB#, LB# Valid to End of Write
60
—
ns
tWP
Write Pulse Width
55 (Note 1)
—
ns
tWR
Write Recovery Time
0
—
ns
tWHZ
Write to Output High-Z
0
25
ns
tDW
Data to Write Time Overlap
30
—
ns
tDH
Data Hold from Write Time
0
—
ns
tOW
End Write to Output Low-Z
5
—
ns
Notes:
1. tWP (min)=70ns for continuous write operation over 50 times.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
127
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
Read Timings
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
Figure 46. Timing Waveform of Read Cycle(1)
Notes:
1. Address Controlled, CS1#=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL.
tRC
Address
tOH
tAA
tCO
CS1#
CS2
tHZ
tBA
UB#, LB#
tBHZ
tOE
OE#
tOLZ
tBLZ
Data out
tOHZ
tLZ
High-Z
Data Valid
Figure 47.
Timing Waveform of Read Cycle(2)
Notes:
1. WE#=VIH.
128
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Address1)
Valid
Address
A1~A0
Valid
Address
Valid
Address
tAA
Valid
Address
Valid
Address
tPC
CS1#
CS2
tCO
OE#
tPA
tOE
High Z
DQ15~DQ0
tOHZ
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Figure 48. Timing Waveform of Page Cycle (Page Mode Only)
Notes:
1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21, 128Mb: A2 ~ A22.
tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels.
At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
tOE(max) is met only when OE# becomes enabled after tAA(max).
If invalid address signals shorter than min. tRC are continuously repeated for over 4µs, the device needs a normal read
timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4µs.
Write Timings
tWC
Address
tCW
tWR
CS1#
CS2
tAW
tBW
UB#, LB#
tWP
WE#
tAS
Data in
tDW
High-Z
tOW
Data Undefined
Figure 49.
October 28, 2005 S71PL129Jxx_00_A8
High-Z
Data Valid
tWHZ
Data out
tDH
Write Cycle #1 (WE# Controlled)
S71PL129JC0/S71PL129JB0/S71PL129JA0
129
A d v a n c e
I n f o r m a t i o n
tWC
Address
tAS
tWR
tCW
CS1#
tAW
CS2
tBW
UB#, LB#
tWP
WE#
tDW
tDH
Data Valid
Data in
High-Z
Data out
Figure 50.
Write Cycle #2 (CS1# Controlled)
tWC
Address
tAS
tWR
tCW
CS1#
tAW
CS2
tBW
UB#, LB#
tWP(1)
WE#
tDW
Data Valid
Data in
Data out
tDH
High-Z
Figure 51. Timing Waveform of Write Cycle(3) (CS2 Controlled)
130
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
tWC
Address
tWR
tCW
CS1#
tAW
CS2
tBW
UB#, LB#
tAS
tWP
WE#
tDW
tDH
Data Valid
Data in
High-Z
Data out
Figure 52.
Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
Notes:
1. A write occurs during the overlap (tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low
with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A
write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is measured from the beginning of
write to the end of write.
2. tCW is measured from the CS1# going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1# or WE# going
high.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
131
pSRAM Type 7
16Mb(1M word x 16-bit)
32Mb(2M word x 16-bit)
64Mb(4M word x 16-bit)
CMOS 1M/2M/4M-Word x 16-bit pSRAM
ADVANCE
INFORMATION
Features
„ Low Voltage Operating Condition
„ Asynchronous SRAM Interface
„ Fast Access Time
„ Wide Operating Temperature
— VDD = +2.7 V to +3.1 V
— TA = -30°C to +85°C
— tCE = tAA = 60 ns max (16M)
„ Byte Control by LB and UB
„ Various Power Down modes
— tCE = tAA = 65 ns max (32M/64M)
„ 8 words Page Access Capability
— Sleep (16M)
— tPAA = 20 ns max (32M/64M)
— Sleep, 4M-bit Partial, or 8M-bit Partial (32M)
— Sleep, 8M-bit Partial, or 16M-bit Partial (64M)
Pin Description
Pin Name
Description
A21 to A0
Address Input: A19 to A0 for 16M, A20 to A0 for 32M, A21 to A0 for 64M
CE1#
Chip Enable (Low Active)
CE2
Chip Enable (High Active)
WE#
Write Enable (Low Active)
OE#
Output Enable (Low Active)
UB#
Upper Byte Control (Low Active)
LB#
Lower Byte Control (Low Active)
DQ16-9
Upper Byte Data Input/Output
DQ8-1
Lower Byte Data Input/Output
VDD
Power Supply
VSS
Ground
Publication Number S71PL129Jxx_00
Revision A
Amendment 8
Issue Date October 28, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
A d v a n c e
I n f o r m a t i o n
Functional Description
Mode
CE2#
CE1#
H
H
Standby (Deselect)
Output Disable (Note 1)
WE#
OE#
LB#
UB#
X
X
X
H
H
X
Output Disable (No Read)
Read (Upper Byte)
H
Read (Lower Byte)
Read (Word)
H
L
L
No Write
Write (Upper Byte)
L
Write (Lower Byte)
H
Write (Word)
Power Down
L
X
X
X
A21-0
DQ8-1
DQ16-9
X
X
High-Z
High-Z
X
Note 3
High-Z
High-Z
H
H
Valid
High-Z
High-Z
H
L
Valid
High-Z
Output Valid
L
H
Valid
Output Valid
High-Z
L
L
Valid
Output Valid
Output Valid
H
H
Valid
Invalid
Invalid
H
L
Valid
Invalid
Input Valid
L
H
Valid
Input Valid
Invalid
L
L
Valid
Input Valid
Input Valid
X
X
X
High-Z
High-Z
Legend:L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.
Notes:
1.
Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of 1ms limitation.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for
details.
3. Can be either VIL or VIH but must be valid before Read or Write.
Power Down (for 32M, 64M Only)
Power Down
The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the device in powerdown mode and maintains the low-power idle state as long as CE2 is kept Low. CE2 High resumes
the device from power-down mode. These devices have three power-down modes. These can be
programmed by series of read/write operation. Each mode has following features.
32M
64M
Mode
Retention Data
Retention Address
Mode
Retention Data
Retention Address
Sleep (default)
No
N/A
Sleep (default)
No
N/A
4M Partial
4M bit
00000h to 3FFFFh
8M Partial
8M bit
00000h to 7FFFFh
8M Partial
8M bit
00000h to 7FFFFh
16M Partial
16M bit
00000h to FFFFFh
The default state is Sleep and it is the lowest power consumption but all data is lost once CE2 is
brought to Low for Power Down. It is not required to program to Sleep mode after power-up.
Power Down Program Sequence
The program requires 6 read/write operations with a unique address. Between each read/write
operation requires that device be in standby mode. The following table shows the detail sequence.
October 28, 2005 S71PL129Jxx_00_A8
Cycle #
Operation
Address
Data
1st
Read
3FFFFFh (MSB)
Read Data (RDa)
2nd
Write
3FFFFFh
RDa
S71PL129JC0/S71PL129JB0/S71PL129JA0
133
A d v a n c e
I n f o r m a t i o n
Cycle #
Operation
Address
Data
3rd
Write
3FFFFFh
RDa
4th
Write
3FFFFFh
Don’t Care (X)
5th
Write
3FFFFFh
X
6th
Read
Address Key
Read Data (RDb)
The first cycle reads from the most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle. If the second or
third cycle is written into the different address, the program is cancelled, and the data written by
the second or third cycle is valid as a normal write operation.
The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles is “don’t care.”
If the fourth or fifth cycles are written into different address, the program is also cancelled but
write data might not be written as normal write operation.
The last cycle is to read from specific address key for mode selection.
Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored in memory cell array can be lost. So, it should perform this program prior to
regular read/write operation if Partial mode is used.
Address Key
The address key has following format.
Mode
134
Address
32M
64M
A21
A20
A19
A18 - A0
Binary
Sleep (default)
Sleep (default)
1
1
1
1
3FFFFFh
4M Partial
N/A
1
1
0
1
37FFFFh
8M Partial
8M Partial
1
0
1
1
2FFFFFh
N/A
16M Partial
1
0
0
1
27FFFFh
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Voltage of VDD Supply Relative to VSS
VDD
-0.5 to +3.6
V
VIN, VOUT
-0.5 to +3.6
V
Short Circuit Output Current
IOUT
±50
mA
Storage temperature
TSTG
-55 to +125
°C
Voltage at Any Pin Relative to VSS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
(See Warning Below)
Parameter
Symbol
Min
Max
Unit
VDD
2.7
3.1
V
VSS
0
0
V
High Level Input Voltage (Note 1)
VIH
VDD * 0.8
VDD+0.2
V
High Level Input Voltage (Note 1)
VIL
-0.3
VDD * 0.2
V
Ambient Temperature
TA
-30
85
°C
Supply Voltage
Notes:
1.
Maximum DC voltage on input and I/O pins is VDD+0.2V. During voltage transitions, inputs can positive overshoot to VDD+1.0V for periods
of up to 5 ns.
2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, inputs can negative overshoot VSS to -1.0V for
periods of up to 5ns.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges can
adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representative beforehand.
Package Capacitance
Test conditions: TA = 25°C, f = 1.0 MHz
Symbol
Description
Test Setup
Typ
Max
Unit
CIN1
Address Input Capacitance
VIN = 0V
—
5
pF
CIN2
Control Input Capacitance
VIN = 0V
—
5
pF
CIO
Data Input/Output Capacitance
VIO = 0V
—
8
pF
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
135
A d v a n c e
I n f o r m a t i o n
DC Characteristics
(Under Recommended Conditions Unless Otherwise Noted)
Parameter
Symbol
16M
Test Conditions
32M
64M
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Input Leakage
Current
ILI
VIN = VSS to VDD
-1.0
+1.0
-1.0
+1.0
-1.0
+1.0
μA
Output Leakage
Current
ILO
VOUT = VSS to VDD, Output Disable
-1.0
+1.0
-1.0
+1.0
-1.0
+1.0
μA
Output High
Voltage Level
VOH
VDD = VDD(min), IOH = –0.5mA
2.2
—
2.4
—
2.4
—
V
Output Low
Voltage Level
VOL
IOL = 1mA
—
0.4
—
0.4
—
0.4
V
10
—
10
—
10
μA
IDDPS
VDD Power
Down Current
IDDP4
IDDP8
SLEEP
VDD = VDD max.,
VIN = VIH or VIL,
CE2 ≤ 0.2 V
IDDP16
IDDS
VDD = VDD max.,
VIN = VIH or VIL
CE1 = CE2 = VIH
IDDS1
VDD = VDD max.,
VIN ≤ 0.2V or VIN ≥ VDD – 0.2V,
CE1 = CE2 ≥ VDD – 0.2V
VDD Standby
Current
VDD
Active Current
VDD Page
Read Current
IDDA1
IDDA2
IDDA3
VDD = VDD max.,
VIN = VIH or VIL,
CE1 = VIL and CE2= VIH,
IOUT=0mA
4M Partial
N/A
—
40
8M Partial
N/A
—
50
16M Partial
N/A
TA< +85°C
TA< +40°C
N/A
N/A
μA
—
80
μA
—
100
μA
1.5
mA
170
μA
90
μA
—
1
—
1.5
—
—
100
—
80
—
tRC / tWC = min.
—
20
—
30
—
40
mA
tRC / tWC = 1μs
—
3
—
3
—
5
mA
—
10
—
10
mA
VDD = VDD max., VIN = VIH or VIL,
CE1 = VIL and CE2= VIH,
IOUT=0mA, tPRC = min.
N/A
Notes:
1.
All voltages are referenced to VSS.
2. DC Characteristics are measured after following POWER-UP timing.
3. IOUT depends on the output load conditions.
136
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise
Noted)
Read Operation
16M
Parameter
32M
64M
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Notes
Read Cycle Time
tRC
70
1000
65
1000
65
1000
ns
1, 2
CE1# Access Time
tCE
—
60
—
65
—
65
ns
3
OE# Access Time
tOE
—
40
—
40
—
40
ns
3
Address Access Time
tAA
—
60
—
65
—
65
ns
3, 5
LB# / UB# Access Time
tBA
—
30
—
30
—
30
ns
3
Page Address Access Time
tPAA
N/A
—
20
—
20
ns
3,6
Page Read Cycle Time
tPRC
N/A
20
1000
20
1000
ns
1, 6, 7
Output Data Hold Time
tOH
5
—
5
—
5
—
ns
3
CE1# Low to Output Low-Z
tCLZ
5
—
5
—
5
—
ns
4
OE# Low to Output Low-Z
tOLZ
0
—
0
—
0
—
ns
4
LB# / UB# Low to Output Low-Z
tBLZ
0
—
0
—
0
—
ns
4
CE1# High to Output High-Z
tCHZ
—
20
—
20
—
20
ns
3
OE# High to Output High-Z
tOHZ
—
20
—
14.5
—
14
ns
3
LB# / UB# High to Output High-Z
tBHZ
—
20
—
20
—
20
ns
3
Address Setup Time to CE1# Low
tASC
−6
—
–6
—
–6
—
ns
Address Setup Time to OE# Low
tASO
10
—
10
—
10
—
ns
tAX
—
10
—
10
—
10
ns
5, 8
Address Hold Time from CE1# High
tCHAH
-6
—
–6
—
–6
—
ns
9
Address Hold Time from OE# High
tOHAH
-6
—
–6
—
–6
—
ns
WE# High to OE# Low Time for Read
tWHOL
10
1000
25
1000
25
1000
ns
tCP
10
—
12
—
12
—
ns
Address Invalid Time
CE1# High Pulse Width
10
Notes:
1.
Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system operation, please
contact local Spansion representative for the relaxation of 1µs limitation.
2. Address should not be changed within minimum tRC.
3. The output load 50 pF with 50 ohm termination to VDD x 0.5 (16M), The output load 50 pF (32M and 64M).
4. The output load 5pF.
5. Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low.
6. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access.
7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 µs. In other
words, Page Read Cycle must be closed within 4 µs.
8. Applicable when at least two of address inputs among applicable are switched from previous state.
9. tRC(min) and tPRC(min) must be satisfied.
10. If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read can become longer by the
amount of subtracting the actual value from the specified minimum value.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
137
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Write Operation
Parameter
Symbol
16M
32M
64M
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Notes
Write Cycle Time
tWC
70
1000
65
1000
65
1000
ns
1,2
Address Setup Time
tAS
0
—
0
—
0
—
ns
3
CE1# Write Pulse Width
tCW
45
—
40
—
40
—
ns
3
WE# Write Pulse Width
tWP
45
—
40
—
40
—
ns
3
LB#/UB# Write Pulse Width
tBW
45
—
40
—
40
—
ns
3
LB#/UB# Byte Mask Setup Time
tBS
-5
—
–5
—
–5
—
ns
4
LB#/UB# Byte Mask Hold Time
tBH
-5
—
–5
—
–5
—
ns
5
Write Recovery Time
tWR
0
—
0
—
0
—
ns
6
CE1# High Pulse Width
tCP
10
—
12
—
12
—
ns
WE# High Pulse Width
tWHP
7.5
1000
7.5
1000
7.5
1000
ns
LB#/UB# High Pulse Width
tBHP
10
1000
12
1000
12
1000
ns
Data Setup Time
tDS
15
—
12
—
12
—
ns
Data Hold Time
tDH
0
—
0
—
0
—
ns
OE# High to CE1# Low Setup Time for Write
tOHCL
-5
—
–5
—
–5
—
ns
8
OE# High to Address Setup Time for Write
tOES
0
—
0
—
0
—
ns
9
LB# and UB# Write Pulse Overlap
tBWO
30
—
30
—
30
—
ns
7
Notes:
1.
Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system operation, please
contact local Spansion representative for the relaxation of 1µs limitation.
2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7. tWPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum VIH level.
8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met.
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data
bus is in High-Z.
138
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
AC Characteristics
Power Down Parameters
Parameter
Symbol
16M
32M
64M
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
CE2 Low Setup Time for Power Down Entry
tCSP
10
—
10
—
10
—
ns
CE2 Low Hold Time after Power Down Entry
tC2LP
80
—
65
—
65
—
ns
CE1# High Hold Time following CE2 High after Power Down Exit
[SLEEP mode only]
tCHH
300
—
300
—
300
—
μs
1
CE1# High Hold Time following CE2 High after Power Down Exit
[not in SLEEP mode]
tCHHP
1
—
1
—
μs
2
CE1# High Setup Time following CE2 High after Power Down Exit
tCHS
0
—
0
—
ns
1
Unit
Note
N/A
0
—
Notes:
1.
Applicable also to power-up.
2. Applicable when 4Mb and 8Mb Partial modes are programmed.
Other Timing Parameters
Parameter
Symbol
16M
32M
64M
Min.
Max.
Min.
Max.
Min.
Max.
CE1# High to OE# Invalid Time for Standby Entry
tCHOX
10
—
10
—
10
—
ns
CE1# High to WE# Invalid Time for Standby Entry
tCHWX
10
—
10
—
10
—
ns
CE2 Low Hold Time after Power-up
tC2LH
50
—
50
—
50
—
μs
CE1# High Hold Time following CE2 High after Power-up
tCHH
300
—
300
—
300
—
μs
tT
1
25
1
25
1
25
ns
Input Transition Time
1
2
Notes:
1.
Some data might be written into any address location if tCHWX(min) is not satisfied.
2. The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, it can violate the AC
specification of some of the timing parameters.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
139
A d v a n c e
I n f o r m a t i o n
AC Characteristics
AC Test Conditions
Symbol
Description
Test Setup
Value
Unit
VIH
Input High Level
VDD * 0.8
V
VIL
Input Low Level
VDD * 0.2
V
Input Timing Measurement Level
VDD * 0.5
V
5
ns
VREF
tT
Input Transition Time
Between VIL and VIH
Note
AC Measurement Output Load Circuits
VDD *0.5 V
50 ohm
VDD
DEVICE
UNDER
TEST
0.1 μF
OUT
50 pF
VSS
Figure 53.
AC Output Load Circuit – 16 Mb
VDD
DEVICE
UNDER
TEST
0.1μF
VSS
50pF
Figure 54.
140
OUT
AC Output Load Circuit – 32 Mb and 64 Mb
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
Read Timings
tRC
ADDRESS VALID
ADDRESS
tASC
tCE
tCHAH
tASC
CE1#
tCP
tOE
tCHZ
OE#
tOHZ
tBA
LB#/UB#
tBHZ
tBLZ
tOLZ
DQ
(Output)
tCLZ
VALID DATA OUTPUT
tOH
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 55.
Read Timing #1 (Basic Timing)
tAx
tRC
ADDRESS
tRC
ADDRESS VALID
ADDRESS VALID
tAA
CE1#
tAA
tOHAH
Low
tASO
tOE
OE#
LB#/UB#
tOLZ
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
tOHZ
VALID DATA OUTPUT
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 56. Read Timing #2 (OE# Address Access
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
141
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
tAX
tRC
ADDRESS
tAx
ADDRESS VALID
tAA
CE1#, OE#
Low
tBA
tBA
LB#
tBA
UB#
tBHZ
tBHZ
tOH
tBLZ
tBLZ
tOH
DQ1-8
(Output)
VALID DATA
OUTPUT
DQ9-16
(Output)
VALID DATA
OUTPUT
tBLZ
tBHZ
tOH
VALID DATA OUTPUT
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 57.
Read Timing #3 (LB#/UB# Byte Access)
tRC
ADDRESS
(A21-A3)
ADDRESS VALID
tRC
ADDRESS
(A2-A0)
ADDRESS VALID
tASC
tPRC
tPRC
ADDRESS
VALID
ADDRESS
VALID
tPAA
tPRC
ADDRESS
VALID
tPAA
tCHAH
tPAA
CE1#
tCHZ
tCE
OE#
LB#/UB#
tCLZ
tOH
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Normal Access)
VALID DATA OUTPUT
(Page Access)
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 58.
142
Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
tRC
ADDRESS
(A21-A3)
tRC
ADDRESS
(A2-A0)
tPRC
tAA
tPRC
tRC
ADDRESS
VALID
ADDRESS
VALID
tAx
ADDRESS VALID
ADDRESS VALID
tRC
CE1#
tAX
ADDRESS
VALID
tPAA
ADDRESS
VALID
tAA
tPAA
Low
tASO
tOE
OE#
tBA
LB#/UB#
tOLZ
tBLZ
DQ
(Output)
tOH
tOH
tOH
tOH
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Notes:
1.
This timing diagram assumes CE2=H and WE#=H.
2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
Figure 59.
Read Timing #5 (Random and Page Address Access for 32M and 64M Only)
Write Timings
tWC
ADDRESS
ADDRESS VALID
tAS
tCW
tWR
CE1#
tAS
tCP
tAS
tWP
tWR
WE#
tAS
tWHP
tAS
tBW
tWR
LB#, UB#
tAS
tBHP
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Note: This timing diagram assumes CE2=H.
Figure 60.
October 28, 2005 S71PL129Jxx_00_A8
Write Timing #1 (Basic Timing)
S71PL129JC0/S71PL129JB0/S71PL129JA0
143
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
tWC
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
tOHAH
CE1#
Low
tAS
tWP
tWR
tAS
tWP
tWR
WE#
tWHP
LB#, UB#
tOES
OE#
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
VALID DATA INPUT
VALID DATA INPUT
Note:This timing diagram assumes CE2=H.
Figure 61. Write Timing #2 (WE# Control)
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
tWC
Low
tAS
tWP
tAS
tWP
tWHP
WE#
tBH
tWR
tBS
LB#
tBS
tWR
tBH
UB#
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 62.
144
Write Timing #3-1(WE#/LB#/UB# Byte Write Control)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Timing Diagrams
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
tWC
Low
tWR
WE#
tWR
tWHP
tAS
tBW
tBS
tBH
LB#
tAS
tBH
tBS
tBW
UB#
tDS
DQ1-8
(Input)
tDH
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 63. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
tWC
Low
WE#
tAS
tBW
tWR
LB#
tAS
tBW
tWR
tBHP
tBWO
DQ1-8
(Input)
tDS
tDH
tDS
VALID
DATA INPUT
tAS
tBW
VALID
DATA INPUT
tWR
UB#
tAS
tBHP
tDS
DQ9-16
(Input)
tDH
tDH
VALID
DATA INPUT
tWR
tBWO
tBW
tDS
tDH
VALID
DATA INPUT
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 64. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
145
A d v a n c e
I n f o r m a t i o n
Read/Write Timings
tWC
ADDRESS
tRC
WRITE ADDRESS
tCHAH
tAS
tCW
READ ADDRESS
tWR
tASC
tCE
tCHAH
CE1#
tCP
tCP
WE#
UB#, LB#
tOHCL
OE#
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
Notes:
1.
This timing diagram assumes CE2=H.
2. Write address is valid from either CE1# or WE# of last falling edge.
Figure 65.
Read/Write Timing #1-1 (CE1# Control)
tWC
ADDRESS
tRC
WRITE ADDRESS
tCHAH
tAS
READ ADDRESS
tWR
tASC
tCE
tCHAH
CE1#
tCP
tCP
tWP
WE#
UB#, LB#
tOHCL
tOE
OE#
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Notes:
1.
This timing diagram assumes CE2=H.
2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
Figure 66.
146
Read / Write Timing #1-2 (CE1#/WE#/OE# Control)
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Read/Write Timings
tWC
ADDRESS
tRC
WRITE ADDRESS
READ ADDRESS
tOHAH
CE1#
tOHAH
tAA
Low
tAS
WE#
tWR
tWP
tOES
UB#, LB#
tASO
OE#
tOE
tWHOL
tOHZ
tDS
tOH
tDH
tOHZ
tOH
tOLZ
DQ
READ DATA OUTPUT
READ DATA OUTPUT
WRITE DATA INPUT
Notes:
1.
This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 67. Read / Write Timing #2 (OE#, WE# Control)
tWC
ADDRESS
tRC
WRITE ADDRESS
READ ADDRESS
tAA
CE1#
Low
tOHAH
tOHAH
WE#
tOES
tAS
tBW
tWR
tBA
UB#, LB#
tBHZ
tASO
OE#
tWHOL
tOH
tDS
tDH
tBHZ
tOH
tBLZ
DQ
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Notes:
1.
This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 68. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
147
A d v a n c e
I n f o r m a t i o n
Read/Write Timings
CE1#
tCHS
tC2LH
tCHH
CE2
VDD
VDD min
0V
Notes:
1.
2.
The tC2LH specifies after VDD reaches specified minimum level.
For 32M only: The minimum and maximum VDD transition time from 0 V to specified VDD minimum are 30 µs and 50 ms respectively.
Figure 69. Power-up Timing #1
CE1#
tCHH
CE2
VDD
VDD min
0V
Notes:
1.
2.
The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1# and CE2.
For 32M only: The minimum and maximum VDD transition time from 0 V to specified VDD minimum are 30 µs and 50 ms respectively. If
transition time of VDD (from 0 V to VDD min.) is longer than 50 ms, POWER-UP Timing #1 must be applied.
Figure 70.
Power-up Timing #2
CE1#
tCHS
CE2
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and
Power-Down program was not performed prior to this reset.
Figure 71.
148
Power Down Entry and Exit Timing
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Read/Write Timings
CE1#
tCHOX
tCHWX
OE#
WE#
Active (Read)
Standby
Active (Write)
Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
tRC (min) period for Standby mode from CE1# Low to High transition.
Figure 72. Standby Entry Timing after Read or Write
ADDRESS
tRC
tWC
tWC
MSB*1
MSB*1
MSB*1
tCP
tCP
tWC
tWC
MSB*1
tCP
tRC
MSB*1
tCP
Key*2
tCP
tCP*3
CE1#
OE#
WE#
LB#, UB#
DQ*3
RDa
Cycle #1
RDa
Cycle #2
RDa
Cycle #3
X
Cycle #4
X
Cycle #5
RDb
Cycle #6
Notes:
1.
The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in page 134. If not, the operation and data are not guaranteed.
3. After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
Figure 73.
October 28, 2005 S71PL129Jxx_00_A8
Power Down Program Timing (for 32M/64M Only)
S71PL129JC0/S71PL129JB0/S71PL129JA0
149
A d v a n c e
I n f o r m a t i o n
Revision Summary
Revision A0 (June 9, 2004)
Initial release.
Revision A1 (July 19, 2004)
Global Change
Change all instances of FASL to Spansion
Added Colophon text.
Product Selector Guide
Replaced “S71PL129JA0-9Z” with “S71PL129JA0-9P”.
Ordering Information
In Model Number section replaced pSRAM part number with “See valid combinations table”.
Revision A2 (July 21, 2004)
Connection Diagrams
Changed Row D of pinout for accuracy.
Added the following note: “May be shared depending on density:A21 is shared for the 64M pSRAM
configuration;A20 is shred for the 32M pSRAM configuration; A19 is shared for the 16M pSRAM
configuration.
Revision A3 (October 18, 2004)
Core Flash Module
Replaced core flash module from S29PL127J_064J_032J_MCP_00_A1_E to
S29PL129J_MCP_00_A0
Revision A4 (November 30, 2004)
Product Selector Guide
Added a new model number.
Valid Combinations Table
Whole table updated with new OPNs.
Revision A5 (December 23, 2004)
Connection Diagram
Updated pin L5.
Valid Combinations Table
Added a note to the bottom of the table.
Revision A6 (June 15, 2005)
Updated pSRAM Type 2 section.
Revision A7 (July 29, 2005)
Updated pSRAM Type 7 section
150
S71PL129JC0/S71PL129JB0/S71PL129JA0
S71PL129Jxx_00_A8 October 28, 2005
A d v a n c e
I n f o r m a t i o n
Revision A8 (October 28, 2005)
Product Selector Guide
Updated to include two new part numbers
Valid Combinations table
Updated entire table
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
October 28, 2005 S71PL129Jxx_00_A8
S71PL129JC0/S71PL129JB0/S71PL129JA0
151