SPANSION S71WS128JB0BFWAY3

S71WS-J Based MCPs
Stacked Multi-Chip Product (MCP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with CosmoRAM
Data Sheet
PRELIMINARY
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Publication Number S71WS-J_04
Revision A
Amendment 2
Issue Date August 19, 2005
P r e l i m i n a r y
Notice On Data Sheet Designations
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
S71WS-J Based MCPs
Stacked Multi-Chip Product (MCP)
128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory
with CosmoRAM
Data Sheet
PRELIMINARY
Distinctive Characteristics
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General Description
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Flash Memory Density
0E
S65$0
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256Mb
128Mb
6:6-&
6:6-&
64Mb
0E
6:6-%
6:6-%
0E
6:6-$
6:6-$
Publication Number S71WS-J_04
Revision A
Amendment 2
Issue Date August 19, 2005
P r e l i m i n a r y
Product Selector Guide
Device-Model#
6:6-$<
6:6-%<
Flash Density
0E
6:6-$$<
6:6-%$<
pSRAM Density
Flash Speed
(MHz)
pSRAM
Speed
(MHz/ns)
0E
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&RVPR5$0
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S71WS-J Based MCPs
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
S71WS-J Based MCPs
Notice On Data Sheet Designations . . . . . . . . . . . ii
Advance Information .......................................................................................ii
Preliminary ..........................................................................................................ii
Combination .......................................................................................................ii
Full Production (No Designation on Document) ...................................ii
MCP Features ........................................................................................................ 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 2
MCP Block Diagram .............................................................................................6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Lookahead Connection Diagram . . . . . . . . . . . . 10
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 12
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 14
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ........................................................................................... 14
FTA084—84-ball Fine-Pitch Ball Grid Array
(FBGA) 8 x 11.6 mm Package ............................................................................15
TLC080—80-ball Fine-Pitch Ball Grid Array
(FBGA) 7 x 9 mm Package ............................................................................... 16
TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package .........17
Persistent Protection Bit Lock ....................................................................... 38
Standby Mode ...................................................................................................... 39
Automatic Sleep Mode ..................................................................................... 39
RESET#: Hardware Reset Input ................................................................ 39
Output Disable Mode ...................................................................................40
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$OJRULWKPV 7DEOH6HFXUHG6LOLFRQ6HFWRU$GGUHVVHV Secured Silicon Sector Protection Bit ...................................................... 43
Hardware Data Protection ......................................................................... 43
Write Protect (WP#) .......................................................................................44
Low VCC Write Inhibit .................................................................................44
Write Pulse “Glitch” Protection ...............................................................44
Logical Inhibit ...................................................................................................44
Power-Up Write Inhibit ...............................................................................44
Common Flash Memory Interface (CFI) . . . . . . . 45
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S29WS128/064J
General Description . . . . . . . . . . . . . . . . . . . . . . . .20
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 22
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .24
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 25
7DEOH'HYLFH%XV2SHUDWLRQV VersatileIO™ (VIO) Control .............................................................................25
Requirements for Asynchronous Read Operation (Non-Burst) ..........25
Requirements for Synchronous (Burst) Read Operation ...................... 26
8-, 16-, and 32-Word Linear Burst with Wrap Around ......................27
7DEOH%XUVW$GGUHVV*URXSV Configuration Register ......................................................................................27
Handshaking ..........................................................................................................27
Simultaneous Read/Write Operations with Zero Latency ................... 28
Writing Commands/Command Sequences ................................................ 28
Accelerated Program Operation .................................................................. 28
Autoselect Mode ................................................................................................ 29
7DEOH$XWRVHOHFW&RGHV+LJK9ROWDJH0HWKRG Sector/Sector Block Protection and Unprotection ................................. 30
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3URWHFWLRQ8QSURWHFWLRQ Sector Protection ...........................................................................................34
Persistent Sector Protection ...........................................................................34
Persistent Protection Bit (PPB) ..................................................................35
Persistent Protection Bit Lock (PPB Lock) .............................................35
Dynamic Protection Bit (DYB) ...................................................................35
7DEOH6HFWRU3URWHFWLRQ6FKHPHV Persistent Sector Protection Mode Locking Bit ........................................37
Password Protection Mode .............................................................................37
Password and Password Mode Locking Bit ................................................37
64-bit Password ...................................................................................................38
August 19, 2005 S71WS-J_04_A2
Reading Array Data ........................................................................................... 62
Set Configuration Register Command Sequence ..................................... 62
)LJXUH6\QFKURQRXV$V\QFKURQRXV6WDWH'LDJUDP Read Mode Setting ......................................................................................... 63
Programmable Wait State Configuration ............................................... 63
7DEOH3URJUDPPDEOH:DLW6WDWH6HWWLQJV Standard wait-state Handshaking Option ...............................................64
7DEOH:DLW6WDWHVIRU6WDQGDUGZDLWVWDWH+DQGVKDNLQJ Read Mode Configuration ...........................................................................64
7DEOH5HDG0RGH6HWWLQJV Burst Active Clock Edge Configuration .................................................. 65
RDY Configuration ........................................................................................ 65
7DEOH&RQILJXUDWLRQ5HJLVWHU Reset Command .................................................................................................66
Autoselect Command Sequence .................................................................... 67
Enter/Exit Secured Silicon Sector Command Sequence ......................... 67
Program Command Sequence ........................................................................68
Unlock Bypass Command Sequence ........................................................68
)LJXUH3URJUDP2SHUDWLRQ Chip Erase Command Sequence ...................................................................69
Sector Erase Command Sequence ................................................................70
Erase Suspend/Erase Resume Commands ................................................... 71
)LJXUH(UDVH2SHUDWLRQ Password Program Command ....................................................................... 72
Password Verify Command ............................................................................. 73
Password Protection Mode Locking Bit Program Command .............. 73
Persistent Sector Protection Mode Locking Bit
Program Command ........................................................................................... 73
Secured Silicon Sector Protection Bit Program Command .................. 73
PPB Lock Bit Set Command ............................................................................ 74
DPB Write/Erase/Status Command ............................................................. 74
Password Unlock Command .......................................................................... 74
PPB Program Command .................................................................................. 75
All PPB Erase Command .................................................................................. 75
PPB Status Command ....................................................................................... 75
PPB Lock Bit Status Command ...................................................................... 75
Command Definitions ....................................................................................... 76
7DEOH&RPPDQG'HILQLWLRQV S71WS-J Based MCPs
3
P r e l i m i n a r y
Write Operation Status . . . . . . . . . . . . . . . . . . . . .79
DQ7: Data# Polling ............................................................................................79
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%DQN )LJXUH([DPSOHRI:DLW6WDWHV,QVHUWLRQ )LJXUH%DFNWR%DFN5HDG:ULWH&\FOH7LPLQJV DQ6: Toggle Bit I ................................................................................................ 81
CosmoRAM
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DQ2: Toggle Bit II .............................................................................................. 82
7DEOH'4DQG'4,QGLFDWLRQV Reading Toggle Bits DQ6/DQ2 ......................................................................83
DQ5: Exceeded Timing Limits ....................................................................... 84
DQ3: Sector Erase Timer ................................................................................ 84
7DEOH:ULWH2SHUDWLRQ6WDWXV Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . 114
Functional Description . . . . . . . . . . . . . . . . . . . . . 115
Asynchronous Operation (Page Mode) .......................................................115
Functional Description . . . . . . . . . . . . . . . . . . . . . 116
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 85
Synchronous Operation (Burst Mode) ........................................................116
)LJXUH0D[LPXP1HJDWLYH2YHUVKRRW:DYHIRUP )LJXUH0D[LPXP3RVLWLYH2YHUVKRRW:DYHIRUP State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 86
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .87
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
)LJXUH7HVW6HWXS 7DEOH7HVW6SHFLILFDWLRQV Key to Switching Waveforms . . . . . . . . . . . . . . . 88
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 89
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AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 89
VCC Power-up ..................................................................................................... 89
)LJXUH9&&3RZHUXS'LDJUDP CLK Characterization ....................................................................................... 90
)LJXUH&/.&KDUDFWHUL]DWLRQ AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 91
Synchronous/Burst Read @ VIO = 1.8 V ...................................................... 91
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)LJXUH/LQHDU%XUVWZLWK5'<6HW2QH&\FOH%HIRUH'DWD Asynchronous Mode Read @ VIO = 1.8 V ..................................................95
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Erase/Program Operations @ VIO = 1.8 V ................................................. 98
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)LJXUH'4YV'4 Temporary Sector Unprotect ....................................................................... 107
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Initial/Standby State ............................................................................................117
)LJXUH,QLWLDO6WDQGE\6WDWH'LDJUDP Asynchronous Operation State .....................................................................117
)LJXUH$V\QFKURQRXV2SHUDWLRQ6WDWH'LDJUDP Synchronous Operation State ........................................................................118
)LJXUH6\QFKURQRXV2SHUDWLRQ'LDJUDP Functional Description . . . . . . . . . . . . . . . . . . . . . 118
Power-up ...............................................................................................................118
Configuration Register ......................................................................................118
CR Set Sequence ................................................................................................118
Power Down ........................................................................................................121
Burst Read/Write Operation ..........................................................................121
)LJXUH%XUVW5HDG2SHUDWLRQ )LJXUH%XUVW:ULWH2SHUDWLRQ CLK Input Function ..........................................................................................122
ADV# Input Function .......................................................................................123
WAIT# Output Function ................................................................................123
)LJXUH5HDG/DWHQF\'LDJUDP Address Latch by ADV# .................................................................................125
Burst Length ........................................................................................................125
Single Write .........................................................................................................125
Write Control ....................................................................................................126
)LJXUH:ULWH&RQWUROV Burst Read Suspend ..........................................................................................126
)LJXUH%XUVW5HDG6XVSHQG'LDJUDP Burst Write Suspend ........................................................................................127
)LJXUH%XUVW:ULWH6XVSHQG'LDJUDP Burst Read Termination ..................................................................................127
)LJXUH%XUVW5HDG7HUPLQDWLRQ'LDJUDP Burst Write Termination ................................................................................128
)LJXUH%XUVW:ULWH7HUPLQDWLRQ'LDJUDP Absolute Maximum Ratings . . . . . . . . . . . . . . . . 129
Recommended Operating Conditions (See
Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 129
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 130
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 131
Read Operation ..................................................................................................131
Write Operation ............................................................................................... 133
Synchronous Operation - Clock Input (Burst Mode) ............................134
Synchronous Operation - Address Latch (Burst Mode) .......................134
Synchronous Read Operation (Burst Mode) ............................................ 135
Synchronous Write Operation (Burst Mode) ..........................................136
Power Down Parameters ............................................................................... 137
Other Timing Parameters ............................................................................... 137
AC Test Conditions ......................................................................................... 137
AC Measurement Output Load Circuit .....................................................138
)LJXUH2XWSXW/RDG&LUFXLW S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139
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%\WH:ULWH&RQWURO )LJXUH$V\QFKURQRXV:ULWH7LPLQJ:(/%8%
%\WH:ULWH&RQWURO )LJXUH$V\QFKURQRXV:ULWH7LPLQJ:(/%8%
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&(&RQWURO )LJXUH$V\QFKURQRXV5HDG:ULWH7LPLQJ
&(:(2(&RQWURO
)LJXUH$V\QFKURQRXV5HDG:ULWH7LPLQJ
2(:(&RQWURO )LJXUH$V\QFKURQRXV5HDG:ULWH7LPLQJ
2(:(/%8%&RQWURO )LJXUH&ORFN,QSXW7LPLQJ )LJXUH$GGUHVV/DWFK7LPLQJ6\QFKURQRXV0RGH
)LJXUH06\QFKURQRXV5HDG7LPLQJ2(&RQWURO
)LJXUH06\QFKURQRXV5HDG7LPLQJ&(&RQWURO )LJXUH06\QFKURQRXV5HDG7LPLQJ$'9&RQWURO
)LJXUH6\QFKURQRXV5HDG:$,72XWSXW7LPLQJ
&RQWLQXRXV5HDG )LJXUH06\QFKURQRXV5HDG7LPLQJ2(&RQWURO
)LJXUH06\QFKURQRXV5HDG7LPLQJ&(&RQWURO )LJXUH06\QFKURQRXV5HDG7LPLQJ$'9&RQWURO
)LJXUH6\QFKURQRXV:ULWH7LPLQJ:(/HYHO&RQWURO
)LJXUH6\QFKURQRXV:ULWH7LPLQJ:(6LQJOH
&ORFN3XOVH&RQWURO )LJXUH6\QFKURQRXV:ULWH7LPLQJ$'9&RQWURO )LJXUH6\QFKURQRXV:ULWH7LPLQJ:(/HYHO&RQWURO
6LQJOH:ULWH )LJXUH06\QFKURQRXV5HDGWR:ULWH7LPLQJ&(
&RQWURO )LJXUH06\QFKURQRXV5HDGWR:ULWH7LPLQJ$'9
&RQWURO )LJXUH06\QFKURQRXV5HDGWR:ULWH7LPLQJ&(
&RQWURO )LJXUH06\QFKURQRXV5HDGWR:ULWH7LPLQJ$'9
&RQWURO )LJXUH6\QFKURQRXV:ULWHWR5HDG7LPLQJ
&(&RQWURO )LJXUH6\QFKURQRXV:ULWHWR5HDG7LPLQJ
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2SHUDWLRQ )LJXUH&RQILJXUDWLRQ5HJLVWHU6HW7LPLQJ6\QFKURQRXV
2SHUDWLRQ COSMORAM Type 1 – 1.8 V, 16 Mb
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
General Description . . . . . . . . . . . . . . . . . . . . . . . 169
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Function Truth Table . . . . . . . . . . . . . . . . . . . . . . 171
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 171
Recommended Operating Conditions . . . . . . . . 171
Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 172
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 172
Read Operation .................................................................................................172
Write Operation .............................................................................................. 173
Power Down Parameters ...............................................................................174
Other Timing Parameters ...............................................................................174
AC Test Conditions .........................................................................................174
AC Measurement Output Load Circuit .....................................................174
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 175
)LJXUH5HDG7LPLQJ%DVLF7LPLQJ )LJXUH5HDG7LPLQJ2(DQG$GGUHVV$FFHVV )LJXUH5HDG7LPLQJ/%8%%\WH$FFHVV )LJXUH:ULWH7LPLQJ%DVLF7LPLQJ )LJXUH:ULWH7LPLQJ:(&RQWURO )LJXUH:ULWH7LPLQJ±:(/%8%%\WH:ULWH
&RQWURO )LJXUH:ULWH7LPLQJ±:(/%8%%\WH:ULWH
&RQWURO )LJXUH:ULWH7LPLQJ±:(/%8%%\WH:ULWH
&RQWURO )LJXUH:ULWH7LPLQJ±:(/%8%%\WH:ULWH
&RQWURO )LJXUH5HDG:ULWH7LPLQJ±&(&RQWURO )LJXUH5HDG:ULWH7LPLQJ±&(:(2(
&RQWURO )LJXUH5HDG:ULWH7LPLQJ2(:(&RQWURO )LJXUH5HDG:ULWH7LPLQJ2(:(/%8%&RQWURO )LJXUH3RZHU8S7LPLQJ )LJXUH3RZHU'RZQ(QWU\DQG([LW7LPLQJ )LJXUH6WDQGE\(QWU\7LPLQJDIWHU5HDGRU:ULWH Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 183
Revision Summary
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
5
P r e l i m i n a r y
MCP Block Diagram
F-VCC
Flash-only Address
Shared Address
A22
CLK
F-WP#
F-ACC
(Note 3) F1-CE#
OE#
WE#
F-RST#
AVD#
VCC
VID
16
DQ15 to DQ0
CLK
WP#
ACC
Flash 1
CE#
Flash 2
OE#
(Note 4)
WE#
RESET#
RDY
AVD#
(Note 3) F2-CE#
R-VCC
R-UB#
R-LB#
(Note 1) R-CE2
RDY
VSS
A22
R-CE1#
DQ15 to DQ0
VCC
VCCQ
CLK (Note 5) WAIT#
CE# I/O15 to I/O0
WE#
OE#
pSRAM
UB#
VSSQ
LB#
16
AVD# (Note 5)
(Note 2) R-CRE
1RWHV
6
5&5(LVRQO\SUHVHQWLQ&HOOXODU5$0FRPSDWLEOHS65$0
5&(LVRQO\SUHVHQWLQ&RVPR5$0FRPSDWLEOHS65$0
)RU)ODVK S65$0)&( &()RU)ODVKS65$0&( )&(DQG)&(LVWKHFKLSHQDEOHSLQIRUWKHVHFRQG)ODVK
2QO\QHHGHGIRU6:6-&DQG6:6-
&/.DQG$9'QRWDSSOLFDEOHIRU0ES65$0
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Connection Diagrams
(CosmoRAM Type-based)
EDOO)LQH3LWFK%DOO*ULG$UUD\
&RVPR5$0EDVHG3LQRXW7RS9LHZ%DOOV
)DFLQJ'RZQ
A1
A10
NC
NC
Legend
B2
B3
B4
B5
B6
B7
B8
B9
AVD#
RFU
CLK
F2-CE#
RFU
RFU
RFU
RFU
C2
C3
C4
C5
C6
C7
C8
C9
WP#
A7
LB#s
ACC
WE#
A8
A11
RFU
D2
D3
D4
D5
D6
D7
D9
D10
A3
A6
UB#s
RESET#
CE2s
A19
A12
A15
E2
E3
E4
E5
E6
E7
E8
E9
A2
A5
A18
RDY
A20
A9
A13
A21
F2
F3
F4
F5
F6
F7
F8
F9
A1
A4
A17
RFU
A23
A10
A14
A22
G2
G3
G4
G5
G6
G7
G8
G9
A0
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
H2
H3
H4
H5
H6
H7
H8
H9
CE1#f
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
J2
J3
J4
J5
J6
J7
J8
J9
CE1#s
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
K2
K3
K4
K5
K6
K7
K8
K9
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
L2
L3
L4
L5
L6
L7
L8
L9
RFU
RFU
RFU
VCCf
RFU
RFU
RFU
RFU
Shared
1st Flash only
2nd Flash only
1st RAM only
Reserved for
Future Use
M1
M10
NC
NC
1RWHV
,Q0&3¶VEDVHGRQDVLQJOH6:6[[[-6:6[[[-EDOO%LV5)8,Q0&3¶VEDVHGRQWZR6:6[[[-6:6-EDOO%LV&(IRU
)&(
$GGUHVVHVDUHVKDUHGEWZHHQ)ODVKDQG5$0GHSHQGLQJRQWKHGHQVLW\RIWKHS65$0
MCP
Flash-only Addresses
Shared Addresses
6:6-$
$$
$$
6:6-%
$
$$
6:6-$
$$
$$
6:6-%
$$
$$
6:6-&
$
$$
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
7
P r e l i m i n a r y
MCP
Flash-only Addresses
Shared Addresses
$
$$
6:6-&
6SHFLDO+DQGOLQJ,QVWUXFWLRQV)RU)%*$3DFNDJH
6SHFLDOKDQGOLQJLVUHTXLUHGIRU)ODVK0HPRU\SURGXFWVLQ)%*$SDFNDJHV
)ODVKPHPRU\GHYLFHVLQ)%*$SDFNDJHVPD\EHGDPDJHGLIH[SRVHGWRXOWUDVRQLFFOHDQLQJPHWK
RGV7KHSDFNDJHDQGRUGDWDLQWHJULW\PD\EHFRPSURPLVHGLIWKHSDFNDJHERG\LVH[SRVHGWR
WHPSHUDWXUHVDERYH°&IRUSURORQJHGSHULRGVRIWLPH
(CosmoRAM Type-based)
EDOO)LQH3LWFK%DOO*ULG$UUD\
&RVPR5$0EDVHG3LQRXW7RS9LHZ%DOOV
Legend
A1
A2
A3
A4
A5
A6
A7
A8
AVD#
RFU
CLK
F2-CE#
RFU
RFU
RFU
RFU
B1
B2
B3
B4
B5
B6
B7
B8
WP#
A7
LB#s
ACC
WE#
A8
A11
RFU
C1
C2
C3
C4
C5
C6
C7
C8
A3
A6
UB#s
RESET#
CE2s
A19
A12
A15
D1
D2
D3
D4
D5
D6
D7
D8
A2
A5
A18
RDY
A20
A9
A13
A21
E1
E2
E3
E4
E5
E6
E7
E8
A1
A4
A17
RFU
A23
A10
A14
A22
F1
F2
F3
F4
F5
F6
F7
F8
A0
VSS
DQ1
RFU
RFU
DQ6
RFU
A16
G1
G2
G3
G4
G5
G6
G7
G8
CE1#f
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
H1
H2
H3
H4
H5
H6
H7
H8
CE1#s
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
J1
J2
J3
J4
J5
J6
J7
J8
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
K1
K2
K3
K4
K5
K6
K7
K8
RFU
RFU
RFU
VCCf
RFU
RFU
RFU
RFU
Shared
1st Flash only
2nd Flash only
1st RAM only
Reserved for
Future Use
1RWHV
,Q0&3¶VEDVHGRQDVLQJOH6:6[[[-6:6[[[-EDOO%LV5)8,Q0&3¶VEDVHGRQWZR6:6[[[-6:6-EDOO%LV&(IRU
)&(
$GGUHVVHVDUHVKDUHGEWZHHQ)ODVKDQG5$0GHSHQGLQJRQWKHGHQVLW\RIWKHS65$0
7KHEDOOSLQRXWLVDSSOLFDEOHRQO\WRWKRVH0&3VZLWK)ODVKGHQVLW\RI0ERU0E)RUDOOWKHRWKHU0&3VLQFOXGHGLQWKLVGDWDVKHHW
SOHDVHXVHWKHEDOOSLQRXWIRUGHVLJQ
MCP
8
Flash-only Addresses
Shared Addresses
6:6-$
$$
$$
6:6-%
$
$$
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
MCP
Flash-only Addresses
Shared Addresses
6:6-$
$$
$$
6:6-%
$$
$$
6:6-&
$
$$
6:6-&
$
$$
6SHFLDO+DQGOLQJ,QVWUXFWLRQV)RU)%*$3DFNDJH
6SHFLDOKDQGOLQJLVUHTXLUHGIRU)ODVK0HPRU\SURGXFWVLQ)%*$SDFNDJHV
)ODVKPHPRU\GHYLFHVLQ)%*$SDFNDJHVPD\EHGDPDJHGLIH[SRVHGWRXOWUDVRQLFFOHDQLQJPHWK
RGV7KHSDFNDJHDQGRUGDWDLQWHJULW\PD\EHFRPSURPLVHGLIWKHSDFNDJHERG\LVH[SRVHGWR
WHPSHUDWXUHVDERYH°&IRUSURORQJHGSHULRGVRIWLPH
9
S71WS-J_04A2 August 19, 2005
P r e l i m i n a r y
Lookahead Connection Diagram
Legend:
A1
A2
A9
A10
DNU
DNU
DNU
DNU
B1
B2
B9
B10
DNU
DNU
DNU
DNU
C2
C3
C4
C5
C6
C7
C8
C9
AVD#
VSS
CLK
F2-CE#
F-VCC
F-CLK
R-OE#
F2-OE#
D2
D3
D4
D5
D6
D7
D8
D9
F-WP#
A7
WE#
A8
A11
F3-CE#
R-LB# WP#/ACC
E2
E3
E4
E5
E6
E7
E8
E9
A3
A6
R-UB#
F-RST#
R1-CE2
A19
A12
A15
F5
F6
F7
F8
F9
RDY
A20
A9
A13
A21
F2
F3
F4
A2
A5
A18
G2
G3
G4
G5
G6
G7
G8
G9
A1
A4
A17
R2-CE1
A23
A10
A14
A22
H2
H3
H4
H5
H6
H7
H8
H9
A0
VSS
DQ1
R2-VCC
R2-CE2
DQ6
A24
A16
J2
J3
J4
J5
J6
J7
J8
J2
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
Shared
or DNU
(Do Not Use)
MirrorBit Data-storage Only
Flash/Data Shared Only
1st Flash Only
Flash Only
1st RAM Only
2nd RAM Only
K2
K3
K4
K5
K5
K6
K7
K8
K9
R1-CE1#
DQ0
DQ10
F-VCC
R1-VCC
DQ12
DQ7
VSS
L2
L2
L3
L4
L5
L6
L7
L8
L9
DQ8
DQ2
DQ11
A25
DQ5
DQ14
WP#/ACC
R-VCC
M2
M3
M4
M5
M6
M7
M8
M9
A27
A26
VSS
F-VCC
F4-CE#
R-VCCQ
F-VCCQ
R-CLK
xRAM Shared Only
N1
N2
N9
N10
F-DQS0
DNU
DNU
F-DQS-1
P1
P2
P9
P10
DNU
DNU
DNU
DNU
1RWHV
)DQG)GHQRWH;,3&RGH)ODVKZKLOH)DQG)GHQRWH'DWD&RPSDQLRQ)ODVK
,QDGGLWLRQWREHLQJGHILQHGDV)&(%DOO&FDQDOVREHDVVLJQHGDV)&(IRUFRGHIODVKWKDWKDVWZRFKLSHQDEOHVLJQDOV
)RU0&3VUHTXLULQJ99FFDQG99LRXVHWKH9/RRNDKHDG3LQRXWLQRUGHUWRDFFRPPRGDWHH[WUD$9'056DQG&/.SLQVIRUWKH
S65$0LIQHHGHG
5HIHUWR$SSOLFDWLRQ1RWHRQSLQRXWVXEVHWVWRPDWFKWKHSDFNDJHVL]HRIIHULQJV
%DOO%LVVKDUHGEHWZHHQ)ODVK5'<DQG5$0:$,7VLJQDOV
August 19, 2005 S71WS-J_04A2
10
P r e l i m i n a r y
Input/Output Descriptions
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August 19, 2005 S71WS-J_04_A2
$GGUHVVLQSXWV
'DWDLQSXWRXWSXW
2XWSXW(QDEOHLQSXW$V\QFKURQRXVUHODWLYHWR&/.
IRUWKH%XUVWPRGH
:ULWH(QDEOHLQSXW
*URXQG
1R&RQQHFWQRWFRQQHFWHGLQWHUQDOO\
5HDG\RXWSXW,QGLFDWHVWKHVWDWXVRIWKH%XUVWUHDG
VKDUHGZLWK:$,7SLQRI5$0
&ORFNLQSXW,QEXUVWPRGHDIWHUWKHLQLWLDOZRUGLV
RXWSXWVXEVHTXHQWDFWLYHHGJHVRI&/.LQFUHPHQW
WKHLQWHUQDODGGUHVVFRXQWHU6KRXOGEHDW9,/RU9,+
ZKLOHLQDV\QFKURQRXVPRGH
$GGUHVV9DOLGLQSXW,QGLFDWHVWRGHYLFHWKDWWKH
YDOLGDGGUHVVLVSUHVHQWRQWKHDGGUHVVLQSXWV
/RZ IRUDV\QFKURQRXVPRGHLQGLFDWHVYDOLG
DGGUHVVIRUEXUVWPRGHFDXVHVVWDUWLQJDGGUHVVWR
EHODWFKHG
+LJK GHYLFHLJQRUHVDGGUHVVLQSXWV
+DUGZDUHUHVHWLQSXW/RZ GHYLFHUHVHWVDQG
UHWXUQVWRUHDGLQJDUUD\GDWD
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SURJUDPDQGHUDVHIXQFWLRQVLQWKHIRXURXWHUPRVW
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$FFHOHUDWHGLQSXW$W9++DFFHOHUDWHV
SURJUDPPLQJDXWRPDWLFDOO\SODFHVGHYLFHLQXQORFN
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6:6-
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&KLSHQDEOHLQSXWIRUS65$0
S71WS-J Based MCPs
11
P r e l i m i n a r y
Ordering Information
7KHRUGHUQXPEHULVIRUPHGE\DYDOLGFRPELQDWLRQVRIWKHIROORZLQJ
S71WS
256
J
C0
BA
W
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S71WS064JA0 Valid Combinations (WS064J Flash + 16Mb pSRAM)
Base Ordering
Part Number
Package Marking
Temperature
Range
6:6-$%$:<
:6-$%$:<
ƒ&WRƒ&
6:6-$%):<
:6-$%):<
ƒ&WRƒ&
1RWHV
7\SHLVVWDQGDUG6SHFLI\RWKHURSWLRQVDVUHTXLUHG
%*$SDFNDJHPDUNLQJRPLWVOHDGLQJ³6´DQGSDFNLQJW\SH
GHVLJQDWRUIURPRUGHULQJSDUWQXPEHU
12
Burst Speed
0+]
Material Set
Supplier
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Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations
and to check on newly released combinations.
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
S71WS064JB0 Valid Combinations (WS064J Flash + 32Mb pSRAM)
Base Ordering
Part Number
Package Marking
Temperature
Range
6:6-%%$:<
:6-%%$:<
ƒ&WRƒ&
6:6-%%):<
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S71WS-J Based MCPs
13
P r e l i m i n a r y
Physical Dimensions
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
D1
A
D
eD
0.15 C
(2X)
10
9
SE 7
8
7
6
E
E1
5
4
eE
3
2
1
M L K J
INDEX MARK
PIN A1
CORNER
B
10
TOP VIEW
H G F
E D C
B A
PIN A1
CORNER
7
SD
0.15 C
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
0.08 C
SIDE VIEW
6
b
84X
0.15
0.08
M C A B
M C
NOTES:
PACKAGE
TLA 084
JEDEC
N/A
DxE
11.60 mm x 8.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.17
---
---
A2
0.81
---
0.97
NOTE
PROFILE
E
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
84
0.40
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
14
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY SIZE
0.35
2.
BALL HEIGHT
11.60 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BODY THICKNESS
D
Øb
1.
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
S71WS-J Based MCPs
3372-2 \ 16-038.22a
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
D1
A
D
eD
0.15 C
10
(2X)
9
SE 7
8
7
6
E
E1
5
4
eE
3
2
1
M L K J
INDEX MARK
PIN A1
CORNER
B
10
TOP VIEW
H G F
E D C
B A
PIN A1
CORNER
7
SD
0.15 C
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
84X
0.08 C
SIDE VIEW
6
b
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
FTA 084
JEDEC
N/A
DxE
11.60 mm x 8.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.40
A1
0.17
---
---
A2
1.02
---
1.17
NOTE
PROFILE
E
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
eE
84
0.40
0.80 BSC.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY SIZE
0.35
2.
BODY THICKNESS
11.60 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BALL HEIGHT
D
φb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10,E1,E10
F1,F10,G1,G10,H1,H10
J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3388 \ 16-038.21a
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
15
P r e l i m i n a r y
TLC080—80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package
D1
A
D
eD
0.15 C
(2X)
8
7
SE 7
6
5
E
E1
4
3
eE
2
1
K
INDEX MARK
PIN A1
CORNER
B
10
TOP VIEW
J
H
G
F
E
D
C
B
A
7
SD
0.15 C
PIN A1
CORNER
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
0.08 C
SIDE VIEW
6
b
80X
0.15
0.08
M C A B
M C
NOTES:
PACKAGE
TLC 080
JEDEC
N/A
DxE
9.00 mm x 7.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.17
---
---
A2
0.81
---
0.97
NOTE
PROFILE
BODY SIZE
E
7.00 BSC.
BODY SIZE
D1
7.20 BSC.
MATRIX FOOTPRINT
E1
5.60 BSC.
MATRIX FOOTPRINT
MD
10
MATRIX SIZE D DIRECTION
ME
8
MATRIX SIZE E DIRECTION
80
0.35
0.40
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
9.00 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BALL HEIGHT
D
φb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3430 \ 16-038.22 \ 10.15.04
16
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
TSC080 - Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm Package
D1
A
D
eD
0.15 C
(2X)
8
7
SE 7
6
5
E
E1
4
3
eE
2
1
INDEX MARK
PIN A1
CORNER
K
B
9
TOP VIEW
J
H
G
F
E
D
C
B
A
7
SD
0.15 C
PIN A1
CORNER
(2X)
BOTTOM VIEW
A
0.20 C
A2
A1
C
0.08 C
SIDE VIEW
6
b
80X
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
TSC 080
JEDEC
N/A
DxE
9.00 mm x 7.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.17
---
---
A2
0.81
---
0.97
NOTE
PROFILE
BODY SIZE
7.00 BSC.
BODY SIZE
D1
7.20 BSC.
MATRIX FOOTPRINT
E1
5.60 BSC.
MATRIX FOOTPRINT
MD
10
MATRIX SIZE D DIRECTION
ME
8
MATRIX SIZE E DIRECTION
n
80
eE
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
9.00 BSC.
0.40
2.
BALL HEIGHT
E
0.35
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BODY THICKNESS
D
Øb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3496 \ 16-038.22 \ 5.20.05
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
17
S29WS128/064J
Flash Family for Multi-Chip Products (MCP)
128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
PRELIMINARY
Distinctive Characteristics
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Revision A
Amendment 2
Issue Date August 19, 2005
P r e l i m i n a r y
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S71WS-J Based MCPs
19
P r e l i m i n a r y
General Description
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20
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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7KHVHFWRUHUDVHDUFKLWHFWXUHDOORZVPHPRU\VHFWRUVWREHHUDVHGDQGUHSURJUDPPHG
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
21
P r e l i m i n a r y
Product Selector Guide
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22
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Block Diagram of Simultaneous Operation Circuit
Bank A Address
Bank A
Latches and
Control Logic
VSSIO
Y-Decoder
VCC
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OE#
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Bank B Address
DQ15–DQ0
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DQ15–DQ0
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Bank C Address
Y-Decoder
X-Decoder
DQ15–DQ0
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Bank D
Latches and
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Bank D Address
Y-Decoder
X-Decoder
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
23
P r e l i m i n a r y
Input/Output Descriptions
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Device Bus Operations
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
25
P r e l i m i n a r y
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Requirements for Synchronous (Burst) Read Operation
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26
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
DQG:RUG/LQHDU%XUVWZLWK:UDS$URXQG
7KHUHPDLQLQJWKUHHEXUVWUHDGPRGHVDUHRIWKHOLQHDUZUDSDURXQGGHVLJQLQ
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WKHVHPRGHVWKHEXUVWDGGUHVVHVUHDGDUHGHWHUPLQHGE\WKHJURXSZLWKLQZKLFK
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Table 2. Burst Address Groups
0RGH
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S71WS-J Based MCPs
27
P r e l i m i n a r y
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28
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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S71WS-J Based MCPs
29
P r e l i m i n a r y
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
August 19, 2005 S71WS-J_04_A2
6HFWRU
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31
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Table 5.
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
August 19, 2005 S71WS-J_04_A2
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P r e l i m i n a r y
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7KH3HUVLVWHQW6HFWRU3URWHFWLRQPHWKRGUHSODFHVWKHROG9FRQWUROOHGSURWHF
WLRQPHWKRGZKLOHDWWKHVDPHWLPHHQKDQFLQJIOH[LELOLW\E\SURYLGLQJWKUHH
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34
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
3HUVLVWHQW3URWHFWLRQ%LW33%
$VLQJOH3HUVLVWHQWQRQYRODWLOH3URWHFWLRQ%LWLVDVVLJQHGWRDPD[LPXPRIIRXU
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SURWHFWLRQZKHQFKDQJHVDUHQHHGHG7KH'3%VPD\EHVHWRUFOHDUHGDVRIWHQ
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PLQHLIDQ\FKDQJHVWRWKH33%DUHQHHGHGHJWRDOORZQHZV\VWHPFRGHWREH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
35
P r e l i m i n a r y
GRZQORDGHG,IQRFKDQJHVDUHQHHGHGWKHQWKHERRWFRGHFDQVHWWKH33%/RFN
WRGLVDEOHDQ\IXUWKHUFKDQJHVWRWKH33%VGXULQJV\VWHPRSHUDWLRQ
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WHPERRWFRGH6RWKH:3SLQFDQSUHYHQWDQ\FKDQJHVWRWKHERRWFRGHWKDW
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SURWHFWHG,IWKHUHLVDQHHGWRSURWHFWVRPHRIWKHPDVLPSOH'3%:ULWH
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'3%
33%
33%/RFN
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8QSURWHFWHG²33%DQG'3%DUHFKDQJHDEOH
3URWHFWHG²33%DQG'3%DUHFKDQJHDEOH
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8QSURWHFWHG²33%QRWFKDQJHDEOH'3%LV
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36
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
,IWKHXVHUDWWHPSWVWRSURJUDPRUHUDVHDSURWHFWHGVHFWRUWKHGHYLFHLJQRUHV
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UHDGPRGHZLWKRXWKDYLQJPRGLILHGWKHFRQWHQWVRIWKHSURWHFWHGVHFWRU$Q
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—VDIWHUZKLFKWKHGHYLFHUHWXUQVWRUHDGPRGHZLWKRXWKDYLQJHUDVHGWKH
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7KHSURJUDPPLQJRIWKH'3%33%DQG33%ORFNIRUDJLYHQVHFWRUFDQEHYHUL
ILHGE\ZULWLQJD'3%33%33%ORFNYHULI\FRPPDQGWRWKHGHYLFH
Persistent Sector Protection Mode Locking Bit
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ELWH[LVWVWRJXDUDQWHHWKDWWKHGHYLFHUHPDLQLQVRIWZDUHVHFWRUSURWHFWLRQ
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Password Protection Mode
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„ 7KHRQO\PHDQVWRFOHDUWKH33%/RFNELWLVE\ZULWLQJDXQLTXHELW3DVV
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7KHUHLVDEXLOWLQ—VGHOD\IRUHDFK³SDVVZRUGFKHFN´7KLVGHOD\LVLQWHQGHGWR
WKZDUWDQ\HIIRUWVWRUXQDSURJUDPWKDWWULHVDOOSRVVLEOHFRPELQDWLRQVLQRUGHU
WRFUDFNWKHSDVVZRUG
Password and Password Mode Locking Bit
,QRUGHUWRVHOHFWWKH3DVVZRUGVHFWRUSURWHFWLRQVFKHPHWKHFXVWRPHUPXVWILUVW
SURJUDPWKHSDVVZRUG)$6/UHFRPPHQGVWKDWWKHSDVVZRUGEHVRPHKRZFRUUH
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
37
P r e l i m i n a r y
,W SHUPDQHQWO\ VHWV WKH GHYLFH WR RSHUDWH XVLQJ WKH 3DVVZRUG 3URWHFWLRQ
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DIWHUVHWWLQJWKH3DVVZRUG0RGH/RFNLQJ%LWWKHUHZLOOEHQRZD\WRFOHDUWKH
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WKURXJKWKHXVHRIWKH3DVVZRUG3URJUDPDQG9HULI\FRPPDQGVVHH³3DVVZRUG
3URJUDP&RPPDQG´VHFWLRQRQSDJHDQG³3DVVZRUG9HULI\&RPPDQG´VHF
WLRQRQSDJH7KHSDVVZRUGIXQFWLRQZRUNVLQFRQMXQFWLRQZLWKWKH3DVVZRUG
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UHDGLQJWKHFRQWHQWVRIWKHSDVVZRUGRQWKHSLQVRIWKHGHYLFH
Persistent Protection Bit Lock
7KH3HUVLVWHQW3URWHFWLRQ%LW33%/RFNLVDYRODWLOHELWWKDWUHIOHFWVWKHVWDWHRI
WKH3DVVZRUG0RGH/RFNLQJ%LWDIWHUSRZHUXSUHVHW,IWKH3DVVZRUG0RGH/RFN
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PHDQVIRUFOHDULQJWKH33%/RFN%LWLVE\LVVXLQJDKDUGZDUHRUSRZHUXSUHVHW
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38
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Standby Mode
:KHQWKHV\VWHPLVQRWUHDGLQJRUZULWLQJWRWKHGHYLFHLWFDQSODFHWKHGHYLFH
LQWKHVWDQGE\PRGH,QWKLVPRGHFXUUHQWFRQVXPSWLRQLVJUHDWO\UHGXFHGDQG
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,&&LQWKH³'&&KDUDFWHULVWLFV´VHFWLRQRQSDJHUHSUHVHQWVWKHVWDQGE\FXU
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Automatic Sleep Mode
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PHGLDWHO\WHUPLQDWHVDQ\RSHUDWLRQLQSURJUHVVWULVWDWHVDOORXWSXWVUHVHWVWKH
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DUUD\GDWD7KHRSHUDWLRQWKDWZDVLQWHUUXSWHGVKRXOGEHUHLQLWLDWHGRQFHWKHGH
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&XUUHQWLVUHGXFHGIRUWKHGXUDWLRQRIWKH5(6(7SXOVH:KHQ5(6(7LVKHOG
DW966“9WKHGHYLFHGUDZV&026VWDQGE\FXUUHQW,&&,I5(6(7LVKHOG
DW9,/EXWQRWZLWKLQ966“9WKHVWDQGE\FXUUHQWZLOOEHJUHDWHU
5(6(7PD\EHWLHGWRWKHV\VWHPUHVHWFLUFXLWU\$V\VWHPUHVHWZRXOGWKXVDOVR
UHVHWWKH)ODVKPHPRU\HQDEOLQJWKHV\VWHPWRUHDGWKHERRWXSILUPZDUHIURP
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GDWDDJDLQ,I5(6(7LVDVVHUWHGZKHQDSURJUDPRUHUDVHRSHUDWLRQLVQRWH[
HFXWLQJWKHUHVHWRSHUDWLRQLVFRPSOHWHGZLWKLQDWLPHRIW5($'<QRWGXULQJ
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9,+
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
39
P r e l i m i n a r y
2XWSXW'LVDEOH0RGH
:KHQWKH2(LQSXWLVDW9,+RXWSXWIURPWKHGHYLFHLVGLVDEOHG7KHRXWSXWVDUH
SODFHGLQWKHKLJKLPSHGDQFHVWDWH
67$57
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3URJUDP2SHUDWLRQV
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8QSURWHFW&RPSOHWHG
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$OOSURWHFWHGVHFWRUVXQSURWHFWHG,I:3 9,/RXWHUPRVWERRWVHFWRUVZLOOUHPDLQSURWHFWHG
$OOSUHYLRXVO\SURWHFWHGVHFWRUVDUHSURWHFWHGRQFHDJDLQ
Figure 1. Temporary Sector Unprotect Operation
40
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 μs
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 μs
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A7:A0 =
01000010
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A7:A0 =
00000010
Increment
PLSCNT
Temporary Sector
Unprotect Mode
Reset
PLSCNT = 1
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Wait 1.5 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
Yes
No
Yes
Protect another
sector?
Device failed
PLSCNT
= 1000?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Figure 2.
August 19, 2005 S71WS-J_04_A2
In-System Sector Protection/Sector Unprotection Algorithms
S71WS-J Based MCPs
41
P r e l i m i n a r y
Secured Silicon Sector Flash Memory Region
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SHUPDQHQWSDUWLGHQWLILFDWLRQWKURXJKDQ(OHFWURQLF6HULDO1XPEHU(617KH
6HFXUHG6LOLFRQ6HFWRULVZRUGVLQOHQJWKDQGORFDWHGDWDGGUHVVHV
KK7KH)DFWRU\,QGLFDWRU%LW'4LVXVHGWRLQGLFDWHZKHWKHU
RUQRWWKH)DFWRU\6HFXUHG6LOLFRQ6HFWRULVORFNHGZKHQVKLSSHGIURPWKHIDF
WRU\7KH&XVWRPHU,QGLFDWRU%LW'4LVXVHGWRLQGLFDWHZKHWKHURUQRWWKH
&XVWRPHU6HFXUHG6LOLFRQ6HFWRULVORFNHGZKHQVKLSSHGIURPWKHIDFWRU\7KHVH
ELWVDUHSHUPDQHQWO\VHWDWWKHIDFWRU\DQGFDQQRWEHFKDQJHGLQRUGHUWRSUH
YHQWFORQLQJRIDIDFWRU\ORFNHGSDUW7KLVHQVXUHVWKHVHFXULW\RIWKH(61DQG
FXVWRPHUFRGHRQFHWKHSURGXFWLVVKLSSHGWRWKHILHOG
)$6/ŒRIIHUVWKHGHYLFHZLWKDZRUG)DFWRU\6HFXUHG6LOLFRQ6HFWRUWKDWLV
ORFNHGZKHQWKHSDUWLVVKLSSHGDQGDZRUGV&XVWRPHU6HFXUHG6LOLFRQ6HF
WRUWKDWLVHLWKHUORFNHGRULVORFNDEOH7KH)DFWRU\6HFXUHG6LOLFRQ6HFWRULV
DOZD\VSURWHFWHGZKHQVKLSSHGIURPWKHIDFWRU\DQGKDVWKH)DFWRU\,QGLFDWRU
%LW'4SHUPDQHQWO\VHWWRD³´7KH&XVWRPHU6HFXUHG6LOLFRQ6HFWRULV
VKLSSHGXQSURWHFWHGZLWKWKH&XVWRPHU,QGLFDWRU%LW'4VHWWR³´DOORZLQJ
FXVWRPHUVWRXWLOL]HWKDWVHFWRULQDQ\PDQQHUWKH\FKRRVH2QFHWKH&XVWRPHU
6HFXUHG6LOLFRQ6HFWRUDUHDLVSURWHFWHGWKH&XVWRPHU,QGLFDWRU%LWZLOOEHSHU
PDQHQWO\VHWWR³´
7KHV\VWHPDFFHVVHVWKH6HFXUHG6LOLFRQ6HFWRUWKURXJKDFRPPDQGVHTXHQFH
VHH³(QWHU([LW6HFXUHG6LOLFRQ6HFWRU&RPPDQG6HTXHQFH´$IWHUWKHV\VWHP
KDVZULWWHQWKH(QWHU6HFXUHG6LOLFRQ6HFWRUFRPPDQGVHTXHQFHLWPD\UHDG
WKH6HFXUHG6LOLFRQ6HFWRUE\XVLQJWKHDGGUHVVHVQRUPDOO\RFFXSLHGE\WKH
PHPRU\DUUD\7KLVPRGHRIRSHUDWLRQFRQWLQXHVXQWLOWKHV\VWHPLVVXHVWKH([LW
6HFXUHG6LOLFRQ6HFWRUFRPPDQGVHTXHQFHRUXQWLOSRZHULVUHPRYHGIURPWKH
GHYLFH:KLOH6HFXUHG6LOLFRQ6HFWRUDFFHVVLVHQDEOHG0HPRU\$UUD\UHDGDF
FHVVSURJUDPRSHUDWLRQVDQGHUDVHRSHUDWLRQVWRDOOVHFWRUVRWKHUWKDQ6$DUH
DOVRDYDLODEOH2QSRZHUXSRUIROORZLQJDKDUGZDUHUHVHWWKHGHYLFHUHYHUWVWR
VHQGLQJFRPPDQGVWRWKHQRUPDODGGUHVVVSDFH
)DFWRU\/RFNHG)DFWRU6HFXUHG6LOLFRQ6HFWRU3URJUDPPHGDQG
3URWHFWHG$WWKH)DFWRU\
,QDIDFWRU\VHFWRUORFNHGGHYLFHWKH)DFWRU\6HFXUHG6LOLFRQ6HFWRULVSURWHFWHG
ZKHQWKHGHYLFHLVVKLSSHGIURPWKHIDFWRU\ZKHWKHURUQRWWKHDUHDZDVSUR
JUDPPHGDWWKHIDFWRU\7KH)DFWRU\6HFXUHG6LOLFRQ6HFWRUFDQQRWEHPRGLILHG
LQDQ\ZD\2SWLRQDO6SDQVLRQŒSURJUDPPLQJVHUYLFHFDQSUHSURJUDPDUDQGRP
(61DFXVWRPHUGHILQHGFRGHRUDQ\FRPELQDWLRQRIWKHWZR7KH)DFWRU\6H
FXUHG6LOLFRQ6HFWRULVORFDWHGDWDGGUHVVHVK±)K
7KHGHYLFHLVDYDLODEOHSUHSURJUDPPHGZLWKRQHRIWKHIROORZLQJ
„ $UDQGRPVHFXUH(61RQO\ZLWKLQWKH)DFWRU6HFXUHG6LOLFRQ6HFWRU
„ &XVWRPHU FRGH ZLWKLQ WKH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU WKURXJK WKH
6SDQVLRQSURJUDPPLQJVHUYLFH
„ %RWKDUDQGRPVHFXUH(61DQGFXVWRPHUFRGHWKURXJKWKH6SDQVLRQSUR
JUDPPLQJVHUYLFH
Table 7.
42
Secured Silicon Sector Addresses
6HFWRU
6HFWRU6L]H
$GGUHVV5DQJH
&XVWRPHU
ZRUGV
K)K
)DFWRU\
ZRUGV
K)K
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
&XVWRPHUVPD\RSWWRKDYHWKHLUFRGHSURJUDPPHGE\)$6/WKURXJKWKH6SDQ
VLRQSURJUDPPLQJVHUYLFH)$6/SURJUDPVWKHFXVWRPHU¶VFRGHZLWKRUZLWKRXW
WKHUDQGRP(617KHGHYLFHVDUHWKHQVKLSSHGIURP)$6/¶VIDFWRU\ZLWKWKH)DF
WRU\6HFXUHG6LOLFRQ6HFWRUDQG&XVWRPHU6HFXUHG6LOLFRQ6HFWRUSHUPDQHQWO\
ORFNHG&RQWDFWWKHORFDOVDOHVRIILFHIRUGHWDLOVRQXVLQJ6SDQVLRQSURJUDPPLQJ
VHUYLFHV
&XVWRPHU6HFXUHG6LOLFRQ6HFWRU
7KHFXVWRPHUORFNDEOHDUHDLVVKLSSHGXQSURWHFWHGZKLFKDOORZVWKHFXVWRPHU
WRSURJUDPDQGRSWLRQDOO\ORFNWKHDUHDDVDSSURSULDWHIRUWKHDSSOLFDWLRQVHFX
ULW\IHDWXUHLVQRWUHTXLUHGWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUFDQEHWUHDWHG
DVDQDGGLWLRQDO)ODVKPHPRU\VSDFH7KH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUFDQ
EHUHDGDQ\QXPEHURIWLPHVEXWFDQEHSURJUDPPHGDQGORFNHGRQO\RQFH
1RWHWKDWWKHDFFHOHUDWHGSURJUDPPLQJ$&&DQGXQORFNE\SDVVIXQFWLRQVDUH
QRWDYDLODEOHZKHQSURJUDPPLQJWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUEXWUHDG
LQJLQ%DQNV$%DQG&LVDYDLODEOH7KH&XVWRPHU6HFXUHG6LOLFRQ6HFWRULV
ORFDWHGDWDGGUHVVHVK±)K
7KH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUDUHDFDQEHSURWHFWHGXVLQJRQHRIWKH
IROORZLQJSURFHGXUHV
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TXHQFHDQGWKHQIROORZWKHLQV\VWHPVHFWRUSURWHFWDOJRULWKPDVVKRZQLQ
)LJXUH³,Q6\VWHP6HFWRU3URWHFWLRQ6HFWRU8QSURWHFWLRQ$OJRULWKPV´RQ
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WHPSURWHFWLRQRIWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRU5HJLRQZLWKRXWUDLVLQJ
DQ\GHYLFHSLQWRDKLJKYROWDJH1RWHWKDWWKLVPHWKRGLVRQO\DSSOLFDEOHWR
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„ :ULWHWKH6HFXUHG6LOLFRQ6HFWRU3URWHFWLRQ%LW/RFNFRPPDQGVHTXHQFH
2QFHWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRULVORFNHGDQGYHULILHGWKHV\VWHP
PXVWZULWHWKH([LW6HFXUHG6LOLFRQ6HFWRU5HJLRQFRPPDQGVHTXHQFHWRUHWXUQ
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ORFNHGWKHUHLVQRSURFHGXUHDYDLODEOHIRUXQORFNLQJWKH&XVWRPHU6HFXUHG6LOL
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6HFXUHG6LOLFRQ6HFWRU3URWHFWLRQ%LW
7KH&XVWRPHU6HFXUHG6LOLFRQ6HFWRU3URWHFWLRQ%LWSUHYHQWVSURJUDPPLQJRI
WKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUPHPRU\DUHD2QFHVHWWKH&XVWRPHU6H
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+DUGZDUH'DWD3URWHFWLRQ
7KHFRPPDQGVHTXHQFHUHTXLUHPHQWRIXQORFNF\FOHVIRUSURJUDPPLQJRUHUDVLQJ
SURYLGHVGDWDSURWHFWLRQDJDLQVWLQDGYHUWHQWZULWHVUHIHUWR7DEOH³&RPPDQG
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7KHGHYLFHRIIHUVWZRW\SHVRIGDWDSURWHFWLRQDWWKHVHFWRUOHYHO
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
43
P r e l i m i n a r y
7KHIROORZLQJKDUGZDUHGDWDSURWHFWLRQPHDVXUHVSUHYHQWDFFLGHQWDOHUDVXUHRU
SURJUDPPLQJZKLFKPLJKWRWKHUZLVHEHFDXVHGE\VSXULRXVV\VWHPOHYHOVLJQDOV
GXULQJ9&&SRZHUXSDQGSRZHUGRZQWUDQVLWLRQVRUIURPV\VWHPQRLVH
Write Protect (WP#)
7KH:ULWH3URWHFWIHDWXUHSURYLGHVDKDUGZDUHPHWKRGRISURWHFWLQJWKHIRXU
RXWHUPRVWVHFWRUV7KLVIXQFWLRQLVSURYLGHGE\WKH:3SLQDQGRYHUULGHVWKH
SUHYLRXVO\GLVFXVVHG6HFWRU3URWHFWLRQ8QSURWHFWLRQPHWKRG
,IWKHV\VWHPDVVHUWV9,/RQWKH:3SLQWKHGHYLFHGLVDEOHVSURJUDPDQGHUDVH
IXQFWLRQVLQWKHIRXU³RXWHUPRVW´.ZRUGERRWVHFWRUV7KHIRXURXWHUPRVW
.ZRUGERRWVHFWRUVDUHWKHIRXUVHFWRUVFRQWDLQLQJWKHORZHVWDGGUHVVHV6$
6$RUWKHIRXUVHFWRUVFRQWDLQLQJWKHKLJKHVWDGGUHVVHV:6-6$
6$:6-6$6$RUERWKWKHORZHUIRXU6$6$DQGXSSHU
IRXUVHFWRUV:6-6$6$:6-6$6$LQDGXDOERRW
FRQILJXUHGGHYLFH
,IWKHV\VWHPDVVHUWV9,+RQWKH:3SLQWKHGHYLFHUHYHUWVWRZKHWKHUWKH
XSSHUDQGRUORZHUIRXUVHFWRUVZHUHODVWVHWWREHSURWHFWHGRUXQSURWHFWHG
7KDWLVVHFWRUSURWHFWLRQRUXQSURWHFWLRQIRUWKHVHVHFWRUVGHSHQGVRQZKHWKHU
WKH\ZHUHODVWSURWHFWHGRUXQSURWHFWHGXVLQJWKHPHWKRGGHVFULEHGLQ³33%3UR
JUDP&RPPDQG´VHFWLRQRQSDJH
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KDYLRURIWKHGHYLFHPD\UHVXOW
/RZ9&&:ULWH,QKLELW
:KHQ9&&LVOHVVWKDQ9/.2WKHGHYLFHGRHVQRWDFFHSWDQ\ZULWHF\FOHV7KLVSUR
WHFWVGDWDGXULQJ9&&SRZHUXSDQGSRZHUGRZQ7KHFRPPDQGUHJLVWHUDQGDOO
LQWHUQDOSURJUDPHUDVHFLUFXLWVDUHGLVDEOHGDQGWKHGHYLFHUHVHWVWRUHDGLQJ
DUUD\GDWD6XEVHTXHQWZULWHVDUHLJQRUHGXQWLO9&&LVJUHDWHUWKDQ9/.27KHV\V
WHPPXVWSURYLGHWKHSURSHUVLJQDOVWRWKHFRQWUROLQSXWVWRSUHYHQWXQLQWHQWLRQDO
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:ULWHF\FOHVDUHLQKLELWHGE\KROGLQJDQ\RQHRI2( 9,/&( 9,+RU:( 9,+7RLQLWLDWHDZULWHF\FOH&(DQG:(PXVWEHDORJLFDO]HURZKLOH2(LVD
ORJLFDORQH
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QRWDFFHSWFRPPDQGVRQWKHULVLQJHGJHRI:(7KHLQWHUQDOVWDWHPDFKLQHLV
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44
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Common Flash Memory Interface (CFI)
7KH&RPPRQ)ODVK,QWHUIDFH&),VSHFLILFDWLRQRXWOLQHVGHYLFHDQGKRVWV\VWHP
VRIWZDUHLQWHUURJDWLRQKDQGVKDNHZKLFKDOORZVVSHFLILFYHQGRUVSHFLILHGVRIW
ZDUHDOJRULWKPVWREHXVHGIRUHQWLUHIDPLOLHVRIGHYLFHV6RIWZDUHVXSSRUWFDQ
WKHQEHGHYLFHLQGHSHQGHQW-('(&,'LQGHSHQGHQWDQGIRUZDUGDQGEDFN
ZDUGFRPSDWLEOH IRU WKH VSHFLILHG IODVK GHYLFH IDPLOLHV )ODVK YHQGRUV FDQ
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7KLVGHYLFHHQWHUVWKH&),4XHU\PRGHZKHQWKHV\VWHPZULWHVWKH&),4XHU\
FRPPDQGKWRDGGUHVVKDQ\WLPHWKHGHYLFHLVUHDG\WRUHDGDUUD\GDWD
7KHV\VWHPFDQUHDG&),LQIRUPDWLRQDWWKHDGGUHVVHVJLYHQLQ7DEOHV7R
WHUPLQDWHUHDGLQJ&),GDWDWKHV\VWHPPXVWZULWHWKHUHVHWFRPPDQG
7KHV\VWHPFDQDOVRZULWHWKH&),TXHU\FRPPDQGZKHQWKHGHYLFHLVLQWKHDX
WRVHOHFWPRGH7KHGHYLFHHQWHUVWKH&),TXHU\PRGHDQGWKHV\VWHPFDQUHDG
&),GDWDDWWKHDGGUHVVHVJLYHQLQ7DEOHV7KHV\VWHPPXVWZULWHWKHUHVHW
FRPPDQGWRUHWXUQWKHGHYLFHWRWKHDXWRVHOHFWPRGH
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DYDLODEOHYLDWKH)$6/VLWHDWWKHIROORZLQJ85/
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WDWLYHIRUFRSLHVRIWKHVHGRFXPHQWV
Table 8. CFI Query Identification String
$GGUHVVHV
'DWD
K
K
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K
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4XHU\8QLTXH$6&,,VWULQJ³45<´
K
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K
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S71WS-J Based MCPs
45
P r e l i m i n a r y
Table 9. System Interface String
$GGUHVVHV
'DWD
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9&&0LQZULWHHUDVH
'±'YROW'±'PLOOLYROW
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K
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7\SLFDOWLPHRXWIRU0LQVL]HEXIIHUZULWH1—VK QRWVXSSRUWHG
K
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7\SLFDOWLPHRXWSHULQGLYLGXDOEORFNHUDVH1PV
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7\SLFDOWLPHRXWIRUIXOOFKLSHUDVH1PVK QRWVXSSRUWHG
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0D[WLPHRXWIRUE\WHZRUGZULWH1WLPHVW\SLFDO
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0D[WLPHRXWIRUEXIIHUZULWH1WLPHVW\SLFDO
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0D[WLPHRXWSHULQGLYLGXDOEORFNHUDVH1WLPHVW\SLFDO
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Table 10. Device Geometry Definition
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 11.
Primary Vendor-Specific Extended Query
$GGUHVVHV
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S71WS-J Based MCPs
47
P r e l i m i n a r y
Table 12.
%DQN
%DQN'
48
WS128J Sector Address Table
6HFWRU
6HFWRU6L]H
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 12.
%DQN
%DQN&
August 19, 2005 S71WS-J_04_A2
WS128J Sector Address Table
6HFWRU
6HFWRU6L]H
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S71WS-J Based MCPs
49
P r e l i m i n a r y
Table 12.
%DQN
%DQN&
50
6HFWRU
WS128J Sector Address Table
6HFWRU6L]H
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 12.
%DQN
%DQN&
August 19, 2005 S71WS-J_04_A2
WS128J Sector Address Table
6HFWRU
6HFWRU6L]H
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6$
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S71WS-J Based MCPs
51
P r e l i m i n a r y
Table 12.
%DQN
%DQN%
52
WS128J Sector Address Table
6HFWRU
6HFWRU6L]H
[$GGUHVV5DQJH
6$
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6$
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 12.
%DQN
%DQN%
August 19, 2005 S71WS-J_04_A2
6HFWRU
WS128J Sector Address Table
6HFWRU6L]H
[$GGUHVV5DQJH
6$
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K)))K
6$
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6$
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S71WS-J Based MCPs
53
P r e l i m i n a r y
Table 12.
%DQN
%DQN%
54
6HFWRU
WS128J Sector Address Table
6HFWRU6L]H
[$GGUHVV5DQJH
6$
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6$
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6$
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 12.
%DQN
%DQN$
August 19, 2005 S71WS-J_04_A2
WS128J Sector Address Table
6HFWRU
6HFWRU6L]H
[$GGUHVV5DQJH
6$
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K)))K
6$
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K))))K
6$
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6$
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S71WS-J Based MCPs
55
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
%DQN'
56
6HFWRU
6HFWRU6L]H
[$GGUHVV5DQJH
6$
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K)))K
6$
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K)))K
6$
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K)))K
6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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6$
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K))))K
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
%DQN&
August 19, 2005 S71WS-J_04_A2
6HFWRU
6HFWRU6L]H
[$GGUHVV5DQJH
6$
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K)))K
6$
.ZRUGV
K))))K
6$
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K)))K
6$
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K))))K
6$
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$K$)))K
6$
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$K$))))K
6$
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6$
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6$
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6$
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6$
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'K')))K
6$
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'K'))))K
6$
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(K()))K
6$
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(K())))K
6$
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)K))))K
6$
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)K)))))K
6$
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K)))K
6$
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K))))K
6$
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K)))K
6$
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K))))K
6$
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K)))K
6$
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K))))K
6$
.ZRUGV
K)))K
6$
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K))))K
S71WS-J Based MCPs
57
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
%DQN&
58
6HFWRU
6HFWRU6L]H
[$GGUHVV5DQJH
6$
.ZRUGV
K)))K
6$
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K))))K
6$
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K)))K
6$
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K))))K
6$
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K)))K
6$
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K))))K
6$
.ZRUGV
K)))K
6$
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K))))K
6$
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K)))K
6$
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6$
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6$
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K))))K
6$
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$K$)))K
6$
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$K$))))K
6$
.ZRUGV
%K%)))K
6$
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%K%))))K
6$
.ZRUGV
&K&)))K
6$
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&K&))))K
6$
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'K')))K
6$
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'K'))))K
6$
.ZRUGV
(K()))K
6$
.ZRUGV
(K())))K
6$
.ZRUGV
)K))))K
6$
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)K)))))K
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
%DQN%
August 19, 2005 S71WS-J_04_A2
6HFWRU
6HFWRU6L]H
[$GGUHVV5DQJH
6$
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K)))K
6$
.ZRUGV
K))))K
6$
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K)))K
6$
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K))))K
6$
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K)))K
6$
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6$
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K)))K
6$
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K))))K
6$
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6$
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6$
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6$
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K))))K
6$
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K)))K
6$
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K))))K
6$
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K)))K
6$
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K))))K
6$
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K)))K
6$
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K))))K
6$
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K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
$K$)))K
6$
.ZRUGV
$K$))))K
6$
.ZRUGV
%K%)))K
6$
.ZRUGV
%K%))))K
S71WS-J Based MCPs
59
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
%DQN%
60
6HFWRU
6HFWRU6L]H
[$GGUHVV5DQJH
6$
.ZRUGV
&K&)))K
6$
.ZRUGV
&K&))))K
6$
.ZRUGV
'K')))K
6$
.ZRUGV
'K'))))K
6$
.ZRUGV
(K()))K
6$
.ZRUGV
(K())))K
6$
.ZRUGV
)K))))K
6$
.ZRUGV
)K)))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 13. WS064J Sector Address Table
%DQN
%DQN$
August 19, 2005 S71WS-J_04_A2
6HFWRU
6HFWRU6L]H
[$GGUHVV5DQJH
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
K)))K
6$
.ZRUGV
K))))K
6$
.ZRUGV
$K$)))K
6$
.ZRUGV
$K$))))K
6$
.ZRUGV
%K%)))K
6$
.ZRUGV
%K%))))K
6$
.ZRUGV
&K&)))K
6$
.ZRUGV
&K&))))K
6$
.ZRUGV
'K')))K
6$
.ZRUGV
'K'))))K
6$
.ZRUGV
(K()))K
6$
.ZRUGV
(K())))K
6$
.ZRUGV
)K))))K
6$
.ZRUGV
)K))))K
6$
.ZRUGV
)K))))K
6$
.ZRUGV
)$K)$)))K
6$
.ZRUGV
)%K)%)))K
6$
.ZRUGV
)&K)&)))K
6$
.ZRUGV
)'K)')))K
6$
.ZRUGV
)(K)()))K
6$
.ZRUGV
))K)))))K
S71WS-J Based MCPs
61
P r e l i m i n a r y
Command Definitions
:ULWLQJVSHFLILFDGGUHVVDQGGDWDFRPPDQGVRUVHTXHQFHVLQWRWKHFRPPDQG
UHJLVWHULQLWLDWHVGHYLFHRSHUDWLRQV7DEOH³&RPPDQG'HILQLWLRQV´RQSDJH
GHILQHVWKHYDOLGUHJLVWHUFRPPDQGVHTXHQFHV:ULWLQJLQFRUUHFWDGGUHVVDQG
GDWDYDOXHVRUZULWLQJWKHPLQWKHLPSURSHUVHTXHQFHPD\SODFHWKHGHYLFHLQDQ
XQNQRZQVWDWH7KHV\VWHPPXVWZULWHWKHUHVHWFRPPDQGWRUHWXUQWKHGHYLFH
WRUHDGLQJDUUD\GDWD5HIHUWRWKH$&&KDUDFWHULVWLFVVHFWLRQIRUWLPLQJGLDJUDPV
Reading Array Data
7KHGHYLFHLVDXWRPDWLFDOO\VHWWRUHDGLQJDUUD\GDWDDIWHUGHYLFHSRZHUXS1R
FRPPDQGVDUHUHTXLUHGWRUHWULHYHGDWDLQDV\QFKURQRXVPRGH(DFKEDQNLV
UHDG\WRUHDGDUUD\GDWDDIWHUFRPSOHWLQJDQ(PEHGGHG3URJUDPRU(PEHGGHG
(UDVHDOJRULWKP
$IWHUWKHGHYLFHDFFHSWVDQ(UDVH6XVSHQGFRPPDQGWKHFRUUHVSRQGLQJEDQN
HQWHUVWKHHUDVHVXVSHQGUHDGPRGHDIWHUZKLFKWKHV\VWHPFDQUHDGGDWDIURP
DQ\QRQHUDVHVXVSHQGHGVHFWRUZLWKLQWKHVDPHEDQN$IWHUFRPSOHWLQJDSUR
JUDPPLQJRSHUDWLRQLQWKH(UDVH6XVSHQGPRGHWKHV\VWHPPD\RQFHDJDLQ
UHDGDUUD\GDWDIURPDQ\QRQHUDVHVXVSHQGHGVHFWRUZLWKLQWKHVDPHEDQN6HH
WKH³(UDVH6XVSHQG(UDVH5HVXPH&RPPDQGV´VHFWLRQRQSDJHIRUPRUH
LQIRUPDWLRQ
7KHV\VWHPPXVWLVVXHWKHUHVHWFRPPDQGWRUHWXUQDEDQNWRWKHUHDGRUHUDVH
VXVSHQGUHDGPRGHLI'4JRHVKLJKGXULQJDQDFWLYHSURJUDPRUHUDVHRSHUD
WLRQRULIWKHEDQNLVLQWKHDXWRVHOHFWPRGH6HHWKH³5HVHW&RPPDQG´VHFWLRQ
RQSDJHIRUPRUHLQIRUPDWLRQ
6HHDOVR³5HTXLUHPHQWVIRU$V\QFKURQRXV5HDG2SHUDWLRQ1RQ%XUVW´VHFWLRQ
RQSDJHDQG³5HTXLUHPHQWVIRU6\QFKURQRXV%XUVW5HDG2SHUDWLRQ´VHFWLRQ
RQSDJHIRUPRUHLQIRUPDWLRQ7KH$V\QFKURQRXV5HDGDQG6\QFKURQRXV
%XUVW5HDGWDEOHVSURYLGHWKHUHDGSDUDPHWHUVDQG)LJXUH³&/.6\QFKURQRXV
%XUVW0RGH5HDGULVLQJDFWLYH&/.´RQSDJH)LJXUH³6\QFKURQRXV%XUVW
0RGH5HDG´RQSDJHDQG)LJXUH³$V\QFKURQRXV0RGH5HDGZLWK/DWFKHG
$GGUHVVHV´RQSDJHVKRZWKHWLPLQJV
Set Configuration Register Command Sequence
7KHGHYLFHXVHVDFRQILJXUDWLRQUHJLVWHUWRVHWWKHYDULRXVEXUVWSDUDPHWHUV
QXPEHURIZDLWVWDWHVEXUVWUHDGPRGHDFWLYHFORFNHGJH5'<FRQILJXUDWLRQ
DQGV\QFKURQRXVPRGHDFWLYH7KHFRQILJXUDWLRQUHJLVWHUPXVWEHVHWEHIRUHWKH
GHYLFHZLOOHQWHUEXUVWPRGH
7KHFRQILJXUDWLRQUHJLVWHULVORDGHGZLWKDWKUHHF\FOHFRPPDQGVHTXHQFH7KH
ILUVWWZRF\FOHV DUHVWDQGDUGXQORFNVHTXHQFHV2QWKHWKLUG F\FOHWKH GDWD
VKRXOGEH&KDGGUHVVELWV$±$VKRXOGEHKDQGDGGUHVVELWV$±$
VHWWKHFRGHWREHODWFKHG7KHGHYLFHZLOOSRZHUXSRUDIWHUDKDUGZDUHUHVHW
ZLWKWKHGHIDXOWVHWWLQJZKLFKLVLQDV\QFKURQRXVPRGH7KHUHJLVWHUPXVWEHVHW
EHIRUHWKHGHYLFHFDQHQWHUV\QFKURQRXVPRGH7KHFRQILJXUDWLRQUHJLVWHUFDQ
QRWEHFKDQJHGGXULQJGHYLFHRSHUDWLRQVSURJUDPHUDVHRUVHFWRUORFN
62
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(D15 = 1)
Synchronous Read
Mode Only
Figure 3. Synchronous/Asynchronous State Diagram
5HDG0RGH6HWWLQJ
2QSRZHUXSRUKDUGZDUHUHVHWWKHGHYLFHLVVHWWREHLQDV\QFKURQRXVUHDG
PRGH7KLVVHWWLQJDOORZVWKHV\VWHPWRHQDEOHRUGLVDEOHEXUVWPRGHGXULQJV\V
WHPRSHUDWLRQV$GGUHVV$GHWHUPLQHVWKLVVHWWLQJ³¶IRUDV\QFKURQRXVPRGH
³´IRUV\QFKURQRXVPRGH
3URJUDPPDEOH:DLW6WDWH&RQILJXUDWLRQ
7KHSURJUDPPDEOHZDLWVWDWHIHDWXUHLQIRUPVWKHGHYLFHRIWKHQXPEHURIFORFN
F\FOHVWKDWPXVWHODSVHDIWHU$9'LVGULYHQDFWLYHEHIRUHGDWDZLOOEHDYDLODEOH
7KLVYDOXHLVGHWHUPLQHGE\WKHLQSXWIUHTXHQF\RIWKHGHYLFH$GGUHVVELWV$±
$GHWHUPLQHWKHVHWWLQJVHH7DEOH³3URJUDPPDEOH:DLW6WDWH6HWWLQJV´RQ
SDJH
7KHZDLWVWDWHFRPPDQGVHTXHQFHLQVWUXFWVWKHGHYLFHWRVHWDSDUWLFXODUQXPEHU
RIFORFNF\FOHVIRUWKHLQLWLDODFFHVVLQEXUVWPRGH7KHQXPEHURIZDLWVWDWHVWKDW
VKRXOGEHSURJUDPPHGLQWRWKHGHYLFHLVGLUHFWO\UHODWHGWRWKHFORFNIUHTXHQF\
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
63
P r e l i m i n a r y
Table 14.
Programmable Wait State Settings
$
$
$
7RWDO,QLWLDO$FFHVV&\FOHV
GHIDXOW
5HVHUYHG
5HVHUYHG
1RWHV
8SRQSRZHUXSRUKDUGZDUHUHVHWWKHGHIDXOWVHWWLQJLVVHYHQZDLWVWDWHV
5'<ZLOOGHIDXOWWREHLQJDFWLYHZLWKGDWDZKHQWKH:DLW6WDWH6HWWLQJLVVHWWRDWRWDOLQLWLDODFFHVVF\FOHRI
,WLVUHFRPPHQGHGWKDWWKHZDLWVWDWHFRPPDQGVHTXHQFHEHZULWWHQHYHQLIWKH
GHIDXOWZDLWVWDWHYDOXHLVGHVLUHGWRHQVXUHWKHGHYLFHLVVHWDVH[SHFWHG$
KDUGZDUHUHVHWZLOOVHWWKHZDLWVWDWHWRWKHGHIDXOWVHWWLQJ
6WDQGDUGZDLWVWDWH+DQGVKDNLQJ2SWLRQ
7KHKRVWV\VWHPPXVWVHWWKHDSSURSULDWHQXPEHURIZDLWVWDWHVLQWKHIODVKGH
YLFHGHSHQGLQJXSRQWKHFORFNIUHTXHQF\7KHKRVWV\VWHPVKRXOGVHWDGGUHVVELWV
$±$WRIRUDFORFNIUHTXHQF\RI0+]
7DEOHGHVFULEHVWKHW\SLFDOQXPEHURIFORFNF\FOHVZDLWVWDWHVIRUYDULRXV
FRQGLWLRQV
Table 15. Wait States for Standard wait-state Handshaking
7\SLFDO1RRI&ORFN&\FOHVDIWHU$9'/RZ
%XUVW0RGH
&RQGLWLRQV
0+]
:RUGRU:RUGRU&RQWLQXRXV
9,2 9
:RUG
9,2 9
,QWKHDQGZRUGEXUVWUHDGPRGHVWKHDGGUHVVSRLQWHUGRHVQRWFURVVZRUGERXQGDULHVDGGUHVVHV
ZKLFKDUHPXOWLSOHVRI)K
7KHKRVWV\VWHPPXVWVHWWKHDSSURSULDWHQXPEHURIZDLWVWDWHVLQWKHIODVKGH
YLFHGHSHQGLQJXSRQWKHFORFNIUHTXHQF\7KHDXWRVHOHFWIXQFWLRQDOORZVWKHKRVW
V\VWHPWRGHWHUPLQHZKHWKHUWKHIODVKGHYLFHLVHQDEOHGIRUKDQGVKDNLQJ6HH
WKH³$XWRVHOHFW&RPPDQG6HTXHQFH´VHFWLRQRQSDJHIRUPRUHLQIRUPDWLRQ
5HDG0RGH&RQILJXUDWLRQ
7KHGHYLFHVXSSRUWVIRXUGLIIHUHQWUHDGPRGHVFRQWLQXRXVPRGHDQGDQG
ZRUGOLQHDUZUDSDURXQGPRGHV$FRQWLQXRXVVHTXHQFHEHJLQVDWWKHVWDUWLQJ
DGGUHVVDQGDGYDQFHVWKHDGGUHVVSRLQWHUXQWLOWKHEXUVWRSHUDWLRQLVFRPSOHWH
,IWKHKLJKHVWDGGUHVVLQWKHGHYLFHLVUHDFKHGGXULQJWKHFRQWLQXRXVEXUVWUHDG
PRGHWKHDGGUHVVSRLQWHUZUDSVDURXQGWRWKHORZHVWDGGUHVV
64
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
)RUH[DPSOHDQHLJKWZRUGOLQHDUUHDGZLWKZUDSDURXQGEHJLQVRQWKHVWDUWLQJ
DGGUHVVZULWWHQWRWKHGHYLFHDQGWKHQDGYDQFHVWRWKHQH[WZRUGERXQGDU\
7KHDGGUHVVSRLQWHUWKHQUHWXUQVWRWKHVWZRUGDIWHUWKHSUHYLRXVHLJKWZRUG
ERXQGDU\ZUDSSLQJWKURXJKWKHVWDUWLQJORFDWLRQ7KHVL[WHHQDQGWKLUW\WZROLQ
HDUZUDSDURXQGPRGHVRSHUDWHLQDIDVKLRQVLPLODUWRWKHHLJKWZRUGPRGH
7DEOHVKRZVWKHDGGUHVVELWVDQGVHWWLQJVIRUWKHIRXUUHDGPRGHV
Table 16.
Read Mode Settings
$GGUHVV%LWV
%XUVW0RGHV
$
$
&RQWLQXRXV
ZRUGOLQHDUZUDSDURXQG
ZRUGOLQHDUZUDSDURXQG
ZRUGOLQHDUZUDSDURXQG
1RWH8SRQSRZHUXSRUKDUGZDUHUHVHWWKHGHIDXOWVHWWLQJLVFRQWLQXRXV
%XUVW$FWLYH&ORFN(GJH&RQILJXUDWLRQ
%\GHIDXOWWKHGHYLFHZLOOGHOLYHUGDWDRQWKHULVLQJHGJHRIWKHFORFNDIWHUWKH
LQLWLDOV\QFKURQRXVDFFHVVWLPH6XEVHTXHQWRXWSXWVZLOODOVREHRQWKHIROORZLQJ
ULVLQJHGJHVEDUULQJDQ\GHOD\V7KHGHYLFHFDQEHVHWVRWKDWWKHIDOOLQJFORFN
HGJHLVDFWLYHIRUDOOV\QFKURQRXVDFFHVVHV$GGUHVVELW$GHWHUPLQHVWKLVVHW
WLQJ³´IRUULVLQJDFWLYH³´IRUIDOOLQJDFWLYH
5'<&RQILJXUDWLRQ
%\GHIDXOWWKHGHYLFHLVVHWVRWKDWWKH5'<SLQZLOORXWSXW92+ZKHQHYHUWKHUH
LVYDOLGGDWDRQWKHRXWSXWV7KHGHYLFHFDQEHVHWVRWKDW5'<JRHVDFWLYHRQH
GDWDF\FOHEHIRUHDFWLYHGDWD$GGUHVVELW$GHWHUPLQHVWKLVVHWWLQJ³´IRU
5'<DFWLYHZLWKGDWD³´IRU5'<DFWLYHRQHFORFNF\FOHEHIRUHYDOLGGDWD,Q
DV\QFKURQRXVPRGH5'<LVDQRSHQGUDLQRXWSXW
Configuration Register
7DEOHVKRZVWKHDGGUHVVELWVWKDWGHWHUPLQHWKHFRQILJXUDWLRQUHJLVWHUVHWWLQJV
IRUYDULRXVGHYLFHIXQFWLRQV
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
65
P r e l i m i n a r y
Table 17.
Configuration Register
$GGUHVV%LW
)XQFWLRQ
$
6HW'HYLFH
5HDG0RGH
$
5'<
5'<DFWLYHRQHFORFNF\FOHEHIRUHGDWD
5'<DFWLYHZLWKGDWDGHIDXOW
$
&ORFN
%XUVWVWDUWVDQGGDWDLVRXWSXWRQWKHIDOOLQJHGJHRI&/.
%XUVWVWDUWVDQGGDWDLVRXWSXWRQWKHULVLQJHGJHRI&/.GHIDXOW
$
$
$
$
$
6HWWLQJV%LQDU\
6\QFKURQRXV5HDG%XUVW0RGH(QDEOHG
$V\QFKURQRXV0RGHGHIDXOW
6\QFKURQRXV0RGH
5HDG0RGH
3URJUDPPDEOH :DLW6WDWH
&RQWLQXRXVGHIDXOW
ZRUGOLQHDUZLWKZUDSDURXQG
ZRUGOLQHDUZLWKZUDSDURXQG
ZRUGOLQHDUZLWKZUDSDURXQG
'DWDLVYDOLGRQWKHQGDFWLYH&/.HGJHDIWHU$9'WUDQVLWLRQWR9,+
'DWDLVYDOLGRQWKHUGDFWLYH&/.HGJHDIWHU$9'WUDQVLWLRQWR9,+
'DWDLVYDOLGRQWKHWKDFWLYH&/.HGJHDIWHU$9'WUDQVLWLRQWR9,+
'DWDLVYDOLGRQWKHWKDFWLYH&/.HGJHDIWHU$9'WUDQVLWLRQWR9,+
'DWDLVYDOLGRQWKHWKDFWLYH&/.HGJHDIWHU$9'WUDQVLWLRQWR9,+
'DWDLVYDOLGRQWKHWKDFWLYH&/.HGJHDIWHU$9'WUDQVLWLRQWR9,+GHIDXOW
5HVHUYHG
5HVHUYHG
1RWH'HYLFHZLOOEHLQWKHGHIDXOWVWDWHXSRQSRZHUXSRUKDUGZDUHUHVHW
Reset Command
:ULWLQJWKHUHVHWFRPPDQGUHVHWVWKHEDQNVWRWKHUHDGRUHUDVHVXVSHQGUHDG
PRGH$GGUHVVELWVDUHGRQ¶WFDUHVIRUWKLVFRPPDQG
7KHUHVHWFRPPDQGPD\EHZULWWHQEHWZHHQWKHVHTXHQFHF\FOHVLQDQHUDVH
FRPPDQGVHTXHQFHEHIRUHHUDVLQJEHJLQV7KLVUHVHWVWKHEDQNWRZKLFKWKHV\V
WHPZDVZULWLQJWRWKHUHDGPRGH2QFHHUDVXUHEHJLQVKRZHYHUWKHGHYLFH
LJQRUHVUHVHWFRPPDQGVXQWLOWKHRSHUDWLRQLVFRPSOHWH
7KHUHVHWFRPPDQGPD\EHZULWWHQEHWZHHQWKHVHTXHQFHF\FOHVLQDSURJUDP
FRPPDQGVHTXHQFHEHIRUHSURJUDPPLQJEHJLQVSULRUWRWKHWKLUGF\FOH7KLVUH
VHWVWKHEDQNWRZKLFKWKHV\VWHPZDVZULWLQJWRWKHUHDGPRGH,IWKHSURJUDP
FRPPDQGVHTXHQFHLVZULWWHQWRDEDQNWKDWLVLQWKH(UDVH6XVSHQGPRGHZULW
LQJWKHUHVHWFRPPDQGUHWXUQVWKDWEDQNWRWKHHUDVHVXVSHQGUHDGPRGH2QFH
SURJUDPPLQJEHJLQVKRZHYHUWKHGHYLFHLJQRUHVUHVHWFRPPDQGVXQWLOWKHRS
HUDWLRQLVFRPSOHWH
7KHUHVHWFRPPDQGPD\EHZULWWHQEHWZHHQWKHVHTXHQFHF\FOHVLQDQDXWRVHOHFW
FRPPDQGVHTXHQFH2QFHLQWKHDXWRVHOHFWPRGHWKHUHVHWFRPPDQGPXVWEH
ZULWWHQWRUHWXUQWRWKHUHDGPRGH,IDEDQNHQWHUHGWKHDXWRVHOHFWPRGHZKLOH
LQWKH(UDVH6XVSHQGPRGHZULWLQJWKHUHVHWFRPPDQGUHWXUQVWKDWEDQNWRWKH
HUDVHVXVSHQGUHDGPRGH
,I'4JRHVKLJKGXULQJDSURJUDPRUHUDVHRSHUDWLRQZULWLQJWKHUHVHWFRPPDQG
UHWXUQVWKHEDQNVWRWKHUHDGPRGHRUHUDVHVXVSHQGUHDGPRGHLIWKDWEDQN
ZDVLQ(UDVH6XVSHQG
66
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Autoselect Command Sequence
7KHDXWRVHOHFWFRPPDQGVHTXHQFHDOORZVWKHKRVWV\VWHPWRDFFHVVWKHPDQX
IDFWXUHUDQGGHYLFHFRGHVDQGGHWHUPLQHZKHWKHURUQRWDVHFWRULVSURWHFWHG
7DEOH³&RPPDQG'HILQLWLRQV´RQSDJHVKRZVWKHDGGUHVVDQGGDWDUH
TXLUHPHQWV7KHDXWRVHOHFWFRPPDQGVHTXHQFHPD\EHZULWWHQWRDQDGGUHVV
ZLWKLQDEDQNWKDWLVHLWKHULQWKHUHDGRUHUDVHVXVSHQGUHDGPRGH7KHDXWRVH
OHFWFRPPDQGPD\QRWEHZULWWHQZKLOHWKHGHYLFHLVDFWLYHO\SURJUDPPLQJRU
HUDVLQJLQWKHRWKHUEDQN
7KHDXWRVHOHFWFRPPDQGVHTXHQFHLVLQLWLDWHGE\ILUVWZULWLQJWZRXQORFNF\FOHV
7KLVLVIROORZHGE\DWKLUGZULWHF\FOHWKDWFRQWDLQVWKHEDQNDGGUHVVDQGWKHDX
WRVHOHFWFRPPDQG7KHEDQNWKHQHQWHUVWKHDXWRVHOHFWPRGH1RVXEVHTXHQW
GDWDZLOOEHPDGHDYDLODEOHLIWKHDXWRVHOHFWGDWDLVUHDGLQV\QFKURQRXVPRGH
7KHV\VWHPPD\UHDGDWDQ\DGGUHVVZLWKLQWKHVDPHEDQNDQ\QXPEHURIWLPHV
ZLWKRXWLQLWLDWLQJDQRWKHUDXWRVHOHFW FRPPDQGVHTXHQFH5HDGFRPPDQGVWR
RWKHUEDQNVZLOOUHWXUQGDWDIURPWKHDUUD\7KHIROORZLQJWDEOHGHVFULEHVWKHDG
GUHVVUHTXLUHPHQWVIRUWKHYDULRXVDXWRVHOHFWIXQFWLRQVDQGWKHUHVXOWLQJGDWD
%$UHSUHVHQWVWKHEDQNDGGUHVVDQG6$UHSUHVHQWVWKHVHFWRUDGGUHVV7KHGH
YLFH,'LVUHDGLQWKUHHF\FOHV
'HVFULSWLRQ
$GGUHVV
5HDG'DWD
0DQXIDFWXUHU,'
%$K
K
'HYLFH,':RUG
%$K
(K
'HYLFH,':RUG
%$(K
'HYLFH,':RUG
%$)K
6HFWRU3URWHFWLRQ
9HULILFDWLRQ
6$K
K:6-
(K:6-
K:6-
K:6-
ORFNHG
XQORFNHG
'4'4 '4)DFWRU\/RFN%LW
/RFNHG 1RW/RFNHG
'4&XVWRPHU/RFN%LW
/RFNHG 1RW/RFNHG
'4+DQGVKDNH%LW
,QGLFDWRU%LWV
%$K
5HVHUYHG
6WDQGDUG+DQGVKDNH
'4'4%RRW&RGH
'XDO%RRW6HFWRU
7RS%RRW6HFWRU
%RWWRP%RRW6HFWRU
'4'4 7KHV\VWHPPXVWZULWHWKHUHVHWFRPPDQGWRUHWXUQWRWKHUHDGPRGHRUHUDVH
VXVSHQGUHDGPRGHLIWKHEDQNZDVSUHYLRXVO\LQ(UDVH6XVSHQG
Enter/Exit Secured Silicon Sector Command Sequence
7KH6HFXUHG6LOLFRQ6HFWRUUHJLRQSURYLGHVDVHFXUHGGDWDDUHDFRQWDLQLQJD
UDQGRPHLJKWZRUGHOHFWURQLFVHULDOQXPEHU(617KHV\VWHPFDQDFFHVVWKH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
67
P r e l i m i n a r y
6HFXUHG6LOLFRQ6HFWRUUHJLRQE\LVVXLQJWKHWKUHHF\FOH(QWHU6HFXUHG6LOLFRQ
6HFWRUFRPPDQGVHTXHQFH7KHGHYLFHFRQWLQXHVWRDFFHVVWKH6HFXUHG6LOLFRQ
6HFWRUUHJLRQXQWLOWKHV\VWHPLVVXHVWKHIRXUF\FOH([LW6HFXUHG6LOLFRQ6HFWRU
FRPPDQGVHTXHQFH7KH([LW6HFXUHG6LOLFRQ6HFWRUFRPPDQGVHTXHQFHUH
WXUQVWKHGHYLFHWRQRUPDORSHUDWLRQ7KH6HFXUHG6LOLFRQ6HFWRULVQRW
DFFHVVLEOHZKHQWKHGHYLFHLVH[HFXWLQJDQ(PEHGGHG3URJUDPRUHPEHGGHG
(UDVHDOJRULWKP7DEOH³&RPPDQG'HILQLWLRQV´RQSDJHVKRZVWKHDG
GUHVVDQGGDWDUHTXLUHPHQWVIRUERWKFRPPDQGVHTXHQFHV
7KHIROORZLQJFRPPDQGVDUHQRWDOORZHGZKHQWKH6HFXUHG6LOLFRQLVDFFHVVLEOH
² &),
² 8QORFN%\SDVV(QWU\
² 8QORFN%\SDVV3URJUDP
² 8QORFN%\SDVV5HVHW
² (UDVH6XVSHQG5HVXPH
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Program Command Sequence
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68
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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Chip Erase Command Sequence
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S71WS-J Based MCPs
69
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70
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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S71WS-J Based MCPs
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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S71WS-J Based MCPs
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
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S71WS-J Based MCPs
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6XVSHQGPRGH'DWD3ROOLQJSURGXFHVD³´RQ'47KHV\VWHPPXVWSURYLGH
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
79
P r e l i m i n a r y
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
1RWHV
9$ 9DOLGDGGUHVVIRUSURJUDPPLQJ'XULQJDVHFWRUHUDVHRSHUDWLRQDYDOLGDGGUHVVLVDQ\VHFWRUDGGUHVVZLWKLQ
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'4VKRXOGEHUHFKHFNHGHYHQLI'4 ³´EHFDXVH'4PD\FKDQJHVLPXOWDQHRXVO\ZLWK'4
Figure 6. Data# Polling Algorithm
80
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RDY: Ready
7KH5'<LVDGHGLFDWHGRXWSXWWKDWZKHQWKHGHYLFHLVFRQILJXUHGLQWKH6\QFKUR
QRXVPRGHLQGLFDWHVZKHQDWORJLFORZWKHV\VWHPVKRXOGZDLWFORFNF\FOH
EHIRUHH[SHFWLQJWKHQH[WZRUGRIGDWD7KH5'<SLQLVRQO\FRQWUROOHGE\&(
8VLQJWKH5'<&RQILJXUDWLRQ&RPPDQG6HTXHQFH5'<FDQEHVHWVRWKDWDORJLF
ORZLQGLFDWHVWKHV\VWHPVKRXOGZDLWFORFNF\FOHVEHIRUHH[SHFWLQJYDOLGGDWD
7KHIROORZLQJFRQGLWLRQVFDXVHWKH5'<RXWSXWWREHORZGXULQJWKHLQLWLDODFFHVV
LQEXUVWPRGHDQGDIWHUWKHERXQGDU\WKDWRFFXUVHYHU\ZRUGVEHJLQQLQJ
ZLWKWKHWKDGGUHVV)K
:KHQWKHGHYLFHLVFRQILJXUHGLQ$V\QFKURQRXV0RGHWKH5'<LVDQRSHQGUDLQ
RXWSXWSLQZKLFKLQGLFDWHVZKHWKHUDQ(PEHGGHG$OJRULWKPLVLQSURJUHVVRU
FRPSOHWHG7KH5'<VWDWXVLVYDOLGDIWHUWKHULVLQJHGJHRIWKHILQDO:(SXOVHLQ
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,IWKHRXWSXWLVORZ%XV\WKHGHYLFHLVDFWLYHO\HUDVLQJRUSURJUDPPLQJ7KLV
LQFOXGHVSURJUDPPLQJLQWKH(UDVH6XVSHQGPRGH,IWKHRXWSXWLVLQKLJKLP
SHGDQFH5HDG\WKHGHYLFHLVLQWKHUHDGPRGHWKHVWDQGE\PRGHRULQWKH
HUDVHVXVSHQGUHDGPRGH7DEOH³:ULWH2SHUDWLRQ6WDWXV´RQSDJHVKRZV
WKHRXWSXWVIRU5'<
DQ6: Toggle Bit I
7RJJOH%LW,RQ'4LQGLFDWHVZKHWKHUDQ(PEHGGHG3URJUDPRU(UDVHDOJRULWKP
LVLQSURJUHVVRUFRPSOHWHRUZKHWKHUWKHGHYLFHKDVHQWHUHGWKH(UDVH6XVSHQG
PRGH7RJJOH%LW,PD\EHUHDGDWDQ\DGGUHVVLQWKHVDPHEDQNDQGLVYDOLG
DIWHUWKHULVLQJHGJHRIWKHILQDO:(SXOVHLQWKHFRPPDQGVHTXHQFHSULRUWR
WKHSURJUDPRUHUDVHRSHUDWLRQDQGGXULQJWKHVHFWRUHUDVHWLPHRXW
'XULQJDQ(PEHGGHG3URJUDPRU(UDVHDOJRULWKPRSHUDWLRQVXFFHVVLYHUHDGF\
FOHVWRDQ\DGGUHVVFDXVH'4WRWRJJOH:KHQWKHRSHUDWLRQLVFRPSOHWH'4
VWRSVWRJJOLQJ
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DUHSURWHFWHG'4WRJJOHVIRUDSSUR[LPDWHO\—VWKHQUHWXUQVWRUHDGLQJ
DUUD\GDWD,IQRWDOOVHOHFWHGVHFWRUVDUHSURWHFWHGWKH(PEHGGHG(UDVHDOJR
ULWKPHUDVHVWKHXQSURWHFWHGVHFWRUVDQGLJQRUHVWKHVHOHFWHGVHFWRUVWKDWDUH
SURWHFWHG
7KHV\VWHPFDQXVH'4DQG'4WRJHWKHUWRGHWHUPLQHZKHWKHUDVHFWRULVDF
WLYHO\HUDVLQJRULVHUDVHVXVSHQGHG:KHQWKHGHYLFHLVDFWLYHO\HUDVLQJWKDWLV
WKH(PEHGGHG(UDVHDOJRULWKPLVLQSURJUHVV'4WRJJOHV:KHQWKHGHYLFHHQ
WHUVWKH(UDVH6XVSHQGPRGH'4VWRSVWRJJOLQJ+RZHYHUWKHV\VWHPPXVW
DOVRXVH'4WRGHWHUPLQHZKLFKVHFWRUVDUHHUDVLQJRUHUDVHVXVSHQGHG$OWHU
QDWLYHO\WKHV\VWHPFDQXVH'4VHHWKHVXEVHFWLRQRQ'4'DWD3ROOLQJ
,IDSURJUDPDGGUHVVIDOOVZLWKLQDSURWHFWHGVHFWRU'4WRJJOHVIRUDSSUR[L
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UHDGLQJDUUD\GDWD
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
81
P r e l i m i n a r y
7RJJOH%LW,RQ'4UHTXLUHVHLWKHU2(RU&(WREHGHDVVHUWHHGDQGUHDVVHUWHG
WRVKRZWKHFKDQJHLQVWDWH
START
Read Byte
(DQ0-DQ7)
Address = VA
Read Byte
(DQ0-DQ7)
Address = VA
DQ6 = Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
DQ6 = Toggle?
No
Yes
FAIL
PASS
1RWH7KHV\VWHPVKRXOGUHFKHFNWKHWRJJOHELWHYHQLI'4 ³´EHFDXVHWKHWRJJOHELWPD\VWRSWRJJOLQJDV'4FKDQJHVWR
³´6HHWKHVXEVHFWLRQVRQ'4DQG'4IRUPRUHLQIRUPDWLRQ
Figure 7. Toggle Bit Algorithm
DQ2: Toggle Bit II
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VHFWRULVDFWLYHO\HUDVLQJWKDWLVWKH(PEHGGHG(UDVHDOJRULWKPLVLQSURJUHVV
RUZKHWKHUWKDWVHFWRULVHUDVHVXVSHQGHG7RJJOH%LW,,LVYDOLGDIWHUWKHULVLQJ
HGJHRIWKHILQDO:(SXOVHLQWKHFRPPDQGVHTXHQFH
82
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
'4WRJJOHVZKHQWKHV\VWHPUHDGVDWDGGUHVVHVZLWKLQWKRVHVHFWRUVWKDWKDYH
EHHQVHOHFWHGIRUHUDVXUH%XW'4FDQQRWGLVWLQJXLVKZKHWKHUWKHVHFWRULVDF
WLYHO\HUDVLQJRULVHUDVHVXVSHQGHG'4E\FRPSDULVRQLQGLFDWHVZKHWKHUWKH
GHYLFHLVDFWLYHO\HUDVLQJRULVLQ(UDVH6XVSHQGEXWFDQQRWGLVWLQJXLVKZKLFK
VHFWRUVDUHVHOHFWHGIRUHUDVXUH7KXVERWKVWDWXVELWVDUHUHTXLUHGIRUVHFWRUDQG
PRGHLQIRUPDWLRQ5HIHUWR7DEOH³'4DQG'4,QGLFDWLRQV´RQSDJHWR
FRPSDUHRXWSXWVIRU'4DQG'4
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SDJH ³'4 7RJJOH %LW ,´ RQ SDJH )LJXUH ³7RJJOH %LW 7LPLQJV
'XULQJ(PEHGGHG$OJRULWKP´RQSDJHDQG7DEOH³'4DQG'4,QGL
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Table 19. DQ6 and DQ2 Indications
,IGHYLFHLV
DQGWKHV\VWHPUHDGV
WKHQ'4
DQG'4
SURJUDPPLQJ
DWDQ\DGGUHVV
WRJJOHV
GRHVQRWWRJJOH
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DWDQDGGUHVVZLWKLQVHFWRUVQRW
VHOHFWHGIRUHUDVXUH
WRJJOHV
GRHVQRWWRJJOH
DWDQDGGUHVVZLWKLQDVHFWRU
VHOHFWHGIRUHUDVXUH
GRHVQRWWRJJOH
WRJJOHV
DWDQDGGUHVVZLWKLQVHFWRUVQRW
VHOHFWHGIRUHUDVXUH
UHWXUQVDUUD\GDWD
UHWXUQVDUUD\GDWD7KHV\VWHPFDQUHDG
IURPDQ\VHFWRUQRWVHOHFWHGIRUHUDVXUH
DWDQ\DGGUHVV
WRJJOHV
LVQRWDSSOLFDEOH
DFWLYHO\HUDVLQJ
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SURJUDPPLQJLQ
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Reading Toggle Bits DQ6/DQ2
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:KHQHYHUWKHV\VWHPLQLWLDOO\EHJLQVUHDGLQJWRJJOHELWVWDWXVLWPXVWUHDG'4±
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VHH WKH VHFWLRQ RQ '4 ,I LW LV WKH V\VWHP VKRXOG WKHQ GHWHUPLQH DJDLQ
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MXVWDV'4ZHQWKLJK,IWKHWRJJOHELWLVQRORQJHUWRJJOLQJWKHGHYLFHKDVVXF
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GHYLFHGLGQRWFRPSOHWHGWKHRSHUDWLRQVXFFHVVIXOO\DQGWKHV\VWHPPXVWZULWH
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7KHUHPDLQLQJVFHQDULRLVWKDWWKHV\VWHPLQLWLDOO\GHWHUPLQHVWKDWWKHWRJJOHELW
LVWRJJOLQJDQG'4KDVQRWJRQHKLJK7KHV\VWHPPD\FRQWLQXHWRPRQLWRUWKH
WRJJOHELWDQG'4WKURXJKVXFFHVVLYHUHDGF\FOHVGHWHUPLQLQJWKHVWDWXVDVGH
VFULEHGLQWKHSUHYLRXVSDUDJUDSK$OWHUQDWLYHO\LWPD\FKRRVHWRSHUIRUPRWKHU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
83
P r e l i m i n a r y
V\VWHPWDVNV,QWKLVFDVHWKHV\VWHPPXVWVWDUWDWWKHEHJLQQLQJRIWKHDOJR
ULWKPZKHQLWUHWXUQVWRGHWHUPLQHWKHVWDWXVRIWKHRSHUDWLRQ)LJXUH³7RJJOH
%LW$OJRULWKP´RQSDJH
DQ5: Exceeded Timing Limits
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QDOSXOVHFRXQWOLPLW8QGHUWKHVHFRQGLWLRQV'4SURGXFHVD³´LQGLFDWLQJWKDW
WKHSURJUDPRUHUDVHF\FOHZDVQRWVXFFHVVIXOO\FRPSOHWHG
7KHGHYLFHPD\RXWSXWD³´RQ'4LIWKHV\VWHPWULHVWRSURJUDPD³´WRD
ORFDWLRQWKDWZDVSUHYLRXVO\SURJUDPPHGWR³´2QO\DQHUDVHRSHUDWLRQFDQ
FKDQJHD³´EDFNWRD³´8QGHUWKLVFRQGLWLRQWKHGHYLFHKDOWVWKHRSHUDWLRQ
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WRWKHUHDGPRGHRUWRWKHHUDVHVXVSHQGUHDGPRGHLIDEDQNZDVSUHYLRXVO\
LQWKHHUDVHVXVSHQGSURJUDPPRGH
DQ3: Sector Erase Timer
$IWHUZULWLQJDVHFWRUHUDVHFRPPDQGVHTXHQFHWKHV\VWHPPD\UHDG'4WRGH
WHUPLQHZKHWKHURUQRWHUDVXUHKDVEHJXQ7KHVHFWRUHUDVHWLPHUGRHVQRW
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'4'DWD3ROOLQJRU'47RJJOH%LW,WRHQVXUHWKDWWKHGHYLFHKDVDFFHSWHG
WKHFRPPDQGVHTXHQFHDQGWKHQUHDG'4,I'4LV³´WKH(PEHGGHG(UDVH
DOJRULWKPKDVEHJXQDOOIXUWKHUFRPPDQGVH[FHSW(UDVH6XVSHQGDUHLJQRUHG
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WLRQDOVHFWRUHUDVHFRPPDQGV7RHQVXUHWKHFRPPDQGKDVEHHQDFFHSWHGWKH
V\VWHPVRIWZDUHVKRXOGFKHFNWKHVWDWXVRI'4SULRUWRDQGIROORZLQJHDFKVXE
VHTXHQWVHFWRUHUDVHFRPPDQG,I'4LVKLJKRQWKHVHFRQGVWDWXVFKHFNWKH
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84
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Table 20. Write Operation Status
6WDWXV
6WDQGDUG
0RGH
(UDVH
6XVSHQG
0RGH
(PEHGGHG3URJUDP$OJRULWKP
(PEHGGHG(UDVH$OJRULWKP
(UDVH6XVSHQG
5HDG1RWH
'4
1RWH
'4
'4
1RWH
'4
'4
7RJJOH
7RJJOH
1RWRJJOH
'4
1RWH
5'<
1RWH
1$
1RWRJJOH
1RWH
7RJJOH
1$
7RJJOH
+LJK
,PSHGDQFH
(UDVH
6XVSHQGHG6HFWRU
1RQ(UDVH
6XVSHQGHG6HFWRU
'DWD
'DWD
'DWD
'DWD
'DWD
+LJK
,PSHGDQFH
'4
7RJJOH
1$
1$
(UDVH6XVSHQG3URJUDP
1RWH
1RWHV
'4VZLWFKHVWRµ¶ZKHQDQ(PEHGGHG3URJUDPRU(PEHGGHG(UDVHRSHUDWLRQKDVH[FHHGHGWKHPD[LPXPWLPLQJ
OLPLWV5HIHUWRWKHVHFWLRQRQ'4IRUPRUHLQIRUPDWLRQ
'4DQG'4UHTXLUHDYDOLGDGGUHVVZKHQUHDGLQJVWDWXVLQIRUPDWLRQ5HIHUWRWKHDSSURSULDWHVXEVHFWLRQIRU
IXUWKHUGHWDLOV
:KHQUHDGLQJZULWHRSHUDWLRQVWDWXVELWVWKHV\VWHPPXVWDOZD\VSURYLGHWKHEDQNDGGUHVVZKHUHWKH(PEHGGHG
$OJRULWKPLVLQSURJUHVV7KHGHYLFHRXWSXWVDUUD\GDWDLIWKHV\VWHPDGGUHVVHVDQRQEXV\EDQN
7KHV\VWHPPD\UHDGHLWKHUDV\QFKURQRXVO\RUV\QFKURQRXVO\EXUVWZKLOHLQHUDVHVXVSHQG
7KH5'<SLQDFWVDGHGLFDWHGRXWSXWWRLQGLFDWHWKHVWDWXVRIDQHPEHGGHGHUDVHRUSURJUDPRSHUDWLRQLVLQSURJUHVV
7KLVLVDYDLODEOHLQWKH$V\QFKURQRXVPRGHRQO\
:KHQWKHGHYLFHLVVHWWR$V\QFKURQRXVPRGHWKHVHVWDWXVIODJVVKRXOGEHUHDGE\&(WRJJOH
Absolute Maximum Ratings
6WRUDJH7HPSHUDWXUH3ODVWLF3DFNDJHV ±ƒ&WRƒ&
$PELHQW7HPSHUDWXUHZLWK3RZHU$SSOLHG ±ƒ&WRƒ&
9ROWDJHZLWK5HVSHFWWR*URXQG
$OO,QSXWVDQG,2VH[FHSWDVQRWHGEHORZ1RWH ±9WR9,29
9&&1RWH ±9WR9
9,2 ±9WR9
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WKDQRQHVHFRQG
6WUHVVHVDERYHWKRVHOLVWHGXQGHU³$EVROXWH0D[LPXP5DWLQJV´PD\FDXVHSHUPDQHQWGDPDJHWRWKHGHYLFH7KLVLV
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
85
P r e l i m i n a r y
QV
QV
9
±9
±9
QV
Figure 8.
Maximum Negative Overshoot Waveform
QV
9&&
9
9&&
9
9
QV
QV
Figure 9. Maximum Positive Overshoot Waveform
Operating Ranges
&RPPHUFLDO&'HYLFHV
$PELHQW7HPSHUDWXUH7$ƒ&WRƒ&
,QGXVWULDO,'HYLFHV
$PELHQW7HPSHUDWXUH7$ ±ƒ&WRƒ&
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9&&6XSSO\9ROWDJHV 9WR9
9,26XSSO\9ROWDJHV 9WR9
9&&! 9,2P9
Operating ranges define those limits between which the functionality of the device is guaranteed.
86
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
DC Characteristics
CMOS Compatible
3DUDPHWHU
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P r e l i m i n a r y
Switching Waveforms
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P r e l i m i n a r y
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P r e l i m i n a r y
AC Characteristics
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6
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Figure 17. 8-word Linear Burst with Wrap Around
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
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P r e l i m i n a r y
AC Characteristics
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P r e l i m i n a r y
AC Characteristics
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August 19, 2005 S71WS-J_04_A2
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Figure 23. Asynchronous Program Operation Timings: WE# Latched Addresses
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Program Command Sequence (last two cycles)
Read Status Data
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7KH&RQILJXUDWLRQ5HJLVWHUPXVWEHVHWWRWKH6\QFKURQRXV5HDG0RGH
Figure 24. Synchronous Program Operation Timings: WE# Latched Addresses
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
101
P r e l i m i n a r y
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data
tAVCH
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
VA
PA
555h
Data
A0h
VA
In
Progress
PD
Complete
tDS
tDH
tCAS
CE#
OE#
tCH
tCSW
tWP
WE#
tWHWH1
tWPH
tWC
tVCS
VCC
1RWHV
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(LWKHU&(RU$9'LVUHTXLUHGWRJRIURPORZWRKLJKLQEHWZHHQSURJUDPPLQJFRPPDQGVHTXHQFHV
7KH6\QFKURQRXVSURJUDPPLQJRSHUDWLRQLVGHSHQGHQWRIWKH6HW'HYLFH5HDG0RGHELWLQWKH&RQILJXUDWLRQ5HJLVWHU
7KH&RQILJXUDWLRQ5HJLVWHUPXVWEHVHWWRWKH6\QFKURQRXV5HDG0RGH
Figure 25.
102
Synchronous Program Operation Timings: CLK Latched Addresses
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Erase Command Sequence (last two cycles)
VIH
Read Status Data
CLK
VIL
tAVDP
AVD#
tAH
tAS
Addresses
VA
SA
2AAh
555h for
chip erase
Data
55h
VA
10h for
chip erase
In
Progress
30h
Complete
tDS
tDH
CE#
tCH
OE#
tWP
WE#
tCS
tVCS
tWHWH2
tWPH
tWC
VCC
Figure 26. Chip/Sector Erase Command Sequence
1RWHV
6$LVWKHVHFWRUDGGUHVVIRU6HFWRU(UDVH
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
103
P r e l i m i n a r y
AC Characteristics
CE#
AVD#
WE#
Addresses
PA
Don't Care
Data
OE#
ACC
1 μs
A0h
Don't Care
PD
Don't Care
tVIDS
VID
tVID
VIL or VIH
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Figure 27.
104
Accelerated Unlock Bypass Programming Timing
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
AVD#
tCEZ
tCE
CE#
tCH
tOEZ
tOE
OE#
tOEH
WE#
tACC
Addresses
VA
VA
Status Data
Data
Status Data
1RWHV
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FRPSOHWHDQG'DWD3ROOLQJZLOORXWSXWWUXHGDWD
:KLOHLQ$V\QFKURQRXVPRGH5'<ZLOOEHORZZKLOHWKHGHYLFHLVLQHPEHGGHGHUDVHRUSURJUDPPLQJPRGH
Figure 28.
Data# Polling Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tCH
tOEZ
tOE
OE#
tOEH
WE#
tACC
Addresses
VA
Data
VA
Status Data
Status Data
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9$ 9DOLG$GGUHVV7ZRUHDGF\FOHVDUHUHTXLUHGWRGHWHUPLQHVWDWXV:KHQWKH(PEHGGHG$OJRULWKPRSHUDWLRQLV
FRPSOHWHWKHWRJJOHELWVZLOOVWRSWRJJOLQJ
:KLOHLQ$V\QFKURQRXVPRGH5'<ZLOOEHORZZKLOHWKHGHYLFHLVLQHPEHGGHGHUDVHRUSURJUDPPLQJPRGH
Figure 29.
August 19, 2005 S71WS-J_04_A2
Toggle Bit Timings (During Embedded Algorithm)
S71WS-J Based MCPs
105
P r e l i m i n a r y
AC Characteristics
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC
Data
tIACC
Status Data
Status Data
RDY
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DFWLYHRQHFORFNF\FOHEHIRUHGDWD
Figure 30.
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Synchronous Data Polling Timings/Toggle Bit Timings
(UDVH
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6XVSHQG3URJUDP
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WRWRJJOH'4DQG'4
Figure 31.
106
DQ2 vs. DQ6
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Temporary Sector Unprotect
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VID
VID
RESET#
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RDY
Figure 32.
August 19, 2005 S71WS-J_04_A2
Temporary Sector Unprotect Timing Diagram
S71WS-J Based MCPs
107
P r e l i m i n a r y
AC Characteristics
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
1 µs
Valid*
Verify
60h
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 1.5 ms
CE#
WE#
OE#
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108
Sector/Sector Block Protect and Unprotect Timing Diagram
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60
C61
C62
3C
3D
3E
C63
C63
C63
C64
C65
C66
C67
3F
3F
3F
40
41
42
43
CLK
Address (hex)
AVD#
(stays high)
tRACC
tRACC
RDY
(Note 1)
latency
tRACC
tRACC
RDY
(Note 2)
Data
latency
D60
D61
D62
D63
D64
D65
D66
D67
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Figure 34.
August 19, 2005 S71WS-J_04_A2
Latency with Boundary Crossing
S71WS-J Based MCPs
109
P r e l i m i n a r y
AC Characteristics
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60
C61
C62
3C
3D
3E
C63
C63
C63
C64
3F
3F
3F
40
CLK
Address (hex)
AVD#
(stays high)
tRACC
RDY
(Note 1)
latency
tRACC
tRACC
RDY
Data
OE#,
CE#
tRACC
(Note 2)
latency
D60
D61
D62
D63
Invalid
Read Status
(stays low)
1RWHV
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Figure 35. Latency with Boundary Crossing into Program/Erase Bank
110
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
total number of clock cycles
following addresses being latched
OE#
1
2
3
0
1
4
5
6
7
3
4
5
CLK
2
number of clock cycles
programmed
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A14, A13, A12 = “111” ⇒ Reserved
A14, A13, A12 = “110” ⇒ Reserved
A14, A13, A12 = “101” ⇒ 5 programmed, 7 total
A14, A13, A12 = “100” ⇒ 4 programmed, 6 total
A14, A13, A12 = “011” ⇒ 3 programmed, 5 total
A14, A13, A12 = “010” ⇒ 2 programmed, 4 total
A14, A13, A12 = “001” ⇒ 1 programmed, 3 total
A14, A13, A12 = “000” ⇒ 0 programmed, 2 total
1RWH)LJXUHDVVXPHVDGGUHVV'LVQRWDWDQDGGUHVVERXQGDU\DFWLYHFORFNHGJHLVULVLQJDQGZDLWVWDWHLVVHWWR³´
Figure 36.
August 19, 2005 S71WS-J_04_A2
Example of Wait States Insertion
S71WS-J Based MCPs
111
P r e l i m i n a r y
AC Characteristics
Read status (at least two cycles) in same bank
and/or array data from other bank
Last Cycle in
Program or
Sector Erase
Command Sequence
tWC
tRC
Begin another
write or program
command sequence
tRC
tWC
CE#
OE#
tOE
tOEH
tGHWL
WE#
tWPH
tWP
tDS
tOEZ
tACC
tOEH
tDH
Data
RD
RD
PD/30h
AAh
tSR/W
Addresses
PA/SA
RA
RA
555h
tAS
AVD#
tAH
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Figure 37. Back-to-Back Read/Write Cycle Timings
112
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Erase and Programming Performance
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
113
CosmoRAM
32Mbit (2M word x 16-bit)
64Mbit (4M word x 16-bit)
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Pin Description (32M)
Pin Name
$WR$
Description
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Publication Number S71WS-J_04
Revision A
Amendment 2
Issue Date August 19, 2005
P r e l i m i n a r y
Functional Description
Asynchronous Operation (Page Mode)
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
115
P r e l i m i n a r y
Functional Description
Synchronous Operation (Burst Mode)
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
State Diagrams
Initial/Standby State
Asynchronous Operation
(Page Mode)
Power Up
Synchronous Operation
(Burst Mode)
Power
Down
@M=1
CE2=L
CE2=H
Common State
CR Set
Pause Time
@M=0
Power
Down
CE2=L
Standby
Standby
CE2=H
@RP=0
CE2=H
@RP=1
(64M Only)
Initial Standby State Diagram
Figure 38.
Asynchronous Operation State
CE2=CE1# = H
Standby
CE1# = L
CE1# = L &
WE# = L
CE1# = H
Output
Disable
CE1# = H
CE1# = H
WE# = H
OE# = L
WE# = L
Byte Control
CE1# = L &
OE# = L
OE# = H
Write
Read
Address Change
or Byte Control
Byte Control @OE# = L
Figure 39.
August 19, 2005 S71WS-J_04_A2
Asynchronous Operation State Diagram
S71WS-J Based MCPs
117
P r e l i m i n a r y
Synchronous Operation State
CE2 = CE1# = H
Standby
CE1# = H
CE1# = H
CE1# = H
CE1# = H
Read
Suspend
Write
Suspend
WE# = H
WE# = L
CE1# = L
ADV# Low Pulse
& WE# = L
CE1# = L
ADV# Low Pulse
& OE# = L
Write
ADV# Low Pulse
OE# = H
OE# = L
Read
ADV# Low Pulse
ADV# Low Pulse
(@BL = 8 or 16, and after burst
operation is completed)
Figure 40.
Synchronous Operation Diagram
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Functional Description
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Configuration Register
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DPRQJRSWLRQDOIHDWXUHV(DFKVHOHFWLRQRIIHDWXUHVLVVHWWKURXJK&56HWVH
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GHYLFHLVFRQILJXUHGIRUDV\QFKURQRXVRSHUDWLRQZLWKVOHHSSRZHUGRZQIHDWXUH
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CR Set Sequence
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HDFKUHDGZULWHRSHUDWLRQUHTXLUHVWKHGHYLFHWREHLQVWDQGE\PRGH7KHIROORZ
LQJWDEOHVKRZVWKHGHWDLOVHTXHQFH
118
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Address
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Cycle #
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Address
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UG
:ULWH
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WHQLQWRWKHGLIIHUHQWDGGUHVVWKH&56HWLVFDQFHOOHGDQGWKHGDWDZULWWHQE\WKH
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S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Power Down
7KH3RZHU'RZQLVORZSRZHULGOHVWDWHFRQWUROOHGE\&(&(/RZGULYHVWKH
GHYLFHLQSRZHUGRZQPRGHDQGPDLQWDLQVORZSRZHULGOHVWDWHDVORQJDV&(LV
NHSW/RZ&(+LJKUHVXPHVWKHGHYLFHIURPSRZHUGRZQPRGH7KHVHGHYLFHV
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RSHUDWLRQV(DFKPRGHKDVIROORZLQJIHDWXUHV
32M
64M
Mode
Data Retention Size
Retention Address
Mode
Data Retention Size
Retention Address
6OHHSGHIDXOW
1R
1$
6OHHSGHIDXOW
1R
1$
03DUWLDO
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7KLVLVHIIHFWLYHRQO\ZKHQ36LVVHWRQ6OHHSPRGH:KHQ3DUWLDOPRGHLVVH
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Burst Read/Write Operation
6\QFKURQRXVEXUVWUHDGZULWHRSHUDWLRQSURYLGHVIDVWHUPHPRU\DFFHVVWKDWV\Q
FKURQL]HGWRPLFURFRQWUROOHURUV\VWHPEXVIUHTXHQF\&RQILJXUDWLRQ5HJLVWHU6HW
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WRSHUIRUPV\QFKURQRXVEXUVWUHDGZULWHRSHUDWLRQLWLVUHTXLUHGWRFRQWUROQHZ
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
121
P r e l i m i n a r y
CLK
ADDRESS
Valid
ADV#
CE1#
OE#
High
WE#
DQ
RL
High-Z
Q1
QBL
Q2
BL
WAIT#
High-Z
Figure 41. Burst Read Operation
CLK
ADDRESS
Valid
ADV#
CE1#
High
OE#
WE#
DQ
High-Z
RL-1
D1
D2
DBL
BL
WAIT#
High-Z
Figure 42.
Burst Write Operation
CLK Input Function
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IUHTXHQF\GXULQJV\QFKURQRXVEXUVWUHDGZULWHRSHUDWLRQ7KH&/.LQSXWLQFUH
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S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
ADV# Input Function
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LVDSSOLFDEOHWRV\QFKURQRXVRSHUDWLRQDVZHOODVDV\QFKURQRXVRSHUDWLRQ$'9
LQSXWLVDFWLYHGXULQJ&( /DQG&( +GLVDEOHV$'9LQSXW$OODGGUHVVHV
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WURO$'9WR+LJK
WAIT# Output Function
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DWLQJLQV\QFKURQRXVEXUVWPRGH
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GDWDRXWDWQH[WFORFNF\FOHLVLQYDOLGDQG:$,7RXWSXWEHFRPHV+LJKRQHFORFN
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IRUHQWLUHZULWHF\FOHVLQFOXGLQJ:(ZULWHVXVSHQG7KHDFWXDOZULWHGDWDODWFK
LQJVWDUWVRQWKHDSSURSULDWHFORFNHGJHZLWKUHVSHFWWR9DOLG&ORFN(GJH5HDG
/DWHQF\DQG%XUVW/HQJWK'XULQJ:(ZULWHVXVSHQG:$,7RXWSXWGRHVQ¶WLQ
GLFDWHGDWDEXVVWDWXVEXWFDUULHVWKHVDPHOHYHOIURPSUHYLRXVFORFNF\FOHNHSW
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SHQGHG:$,7RXWSXWEHFRPHKLJKLPSHGDQFHDIWHUVSHFLILHGWLPHGXUDWLRQ
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7KHEXUVWZULWHRSHUDWLRQRI0DQGWKHERWKEXUVWUHDGZULWHRSHUDWLRQRI0
DUHDOZD\VVWDUWHGDIWHUIL[HGODWHQF\ZLWKUHVSHFWWR5HDG/DWHQF\VHWLQ&5
:KHQWKHGHYLFHLVRSHUDWLQJLQDV\QFKURQRXVPRGH:$,7RXWSXWLVDOZD\VLQ
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
123
P r e l i m i n a r y
Latency
5HDG/DWHQF\5/LVWKHQXPEHURIFORFNF\FOHVEHWZHHQWKH DGGUHVVEHLQJ
ODWFKHGDQGILUVWUHDGGDWDEHFRPLQJDYDLODEOHGXULQJV\QFKURQRXVEXUVWUHDGRS
HUDWLRQ,WLVVHWWKURXJK&56HWVHTXHQFHDIWHUSRZHUXS2QFHVSHFLILF5/LVVHW
WKURXJK&56HWVHTXHQFHZULWHODWHQF\WKDWLVWKHQXPEHURIFORFNF\FOHVEH
WZHHQDGGUHVVEHLQJODWFKHGDQGILUVWZULWHGDWDEHLQJODWFKHGLVDXWRPDWLFDOO\
VHWWR5/7KHEXUVWRSHUDWLRQLVDOZD\VVWDUWHGDIWHUIL[HGODWHQF\ZLWKUHVSHFW
WR5HDG/DWHQF\VHWLQ&55/ LVDYDLODEOHRQO\IRU0
CLK
0
ADDRESS
1
2
3
4
5
6
Q1
Q2
Q3
Q4
Q5
D2
D3
D4
D5
D5
Q1
Q2
Q3
Q4
D2
D3
D4
D5
Q1
Q2
Q3
D2
D3
D4
Q1
Q2
D2
D3
Valid
ADV#
CE1#
OE# or WE#
RL=3
DQ [Out]
WAIT#
High-Z
DQ [In]
WAIT#
D1
High-Z
RL=4
DQ [Out]
WAIT#
High-Z
DQ [In]
WAIT#
D1
High-Z
RL=5
DQ [Out]
WAIT#
High-Z
DQ [In]
WAIT#
D1
High-Z
RL=6
DQ [Out]
WAIT#
High-Z
DQ [In]
WAIT#
D1
High-Z
Figure 43. Read Latency Diagram
124
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Address Latch by ADV#
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VSHFLILHGVHWXSWLPHDJDLQVWHLWKHUWKHQHJDWLYHHGJHRI$'9RUQHJDWLYHHGJH
RI&(ZKLFKHYHUFRPHVODWH$QGWKHGHWHUPLQHGYDOLGDGGUHVVPXVWQRWEH
FKDQJHGGXULQJ$'9 /SHULRG
Burst Length
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7KHEXUVWW\SHLVVHTXHQWLDOWKDWLVLQFUHPHQWDOGHFRGLQJVFKHPHZLWKLQDERXQG
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FRXQWHUDVVLJQWRWKHSUHYLRXVDGGUHVVXQWLOUHDFKLQJWKHHQGRIERXQGDU\DG
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Read Address Sequence
Start Address
(A6-A0)
BL = 8
BL = 16
Continuous
K
()
K
)
K
)
K
)
&K
&)%
&)%
&'()
'K
'()&
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1RWH5HDGDGGUHVVLQ+H[DGHFLPDO
Single Write
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EHFRQILJXUHGHLWKHUWR³%XUVW5HDG6LQJOH:ULWH´RUWR³%XUVW5HDG%XUVW
:ULWH´WKURXJK&5VHWVHTXHQFH2QFHWKHGHYLFHLVFRQILJXUHGWR³%XUVW5HDG
6LQJOH:ULWH´PRGHWKHEXUVWOHQJWKIRUV\QFKURQRXVZULWHRSHUDWLRQLVDOZD\V
IL[HGUHJDUGOHVVRI%/YDOXHVVHWLQ&5ZKLOHEXUVWOHQJWKIRUUHDGLVLQDFFRU
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
125
P r e l i m i n a r y
Write Control
7KHGHYLFHKDVWZRW\SHVRI:(VLJQDOFRQWUROPHWKRG³:(/HYHO&RQWURO´DQG
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XUHGWKURXJK&5VHWVHTXHQFH
CLK
0
ADDRESS
1
3
2
4
5
6
D1
D2
D3
D4
D1
D2
D3
D4
Valid
ADV#
RL=5
CE1#
WE# Level Control
WE#
tWLD
DQ [In]
WAIT#
tWLTH
High-Z
WE# Single Clock Pulse Control
tWSCK
WE#
tCKWH
DQ [In]
WAIT#
tCLTH
tWLTH
High-Z
Figure 44. Write Controls
Burst Read Suspend
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126
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
CLK
tCKOH tOSCK
tCKOH tOSCK
OE#
tAC
tOHZ
Q1
DQ
tAC
Q2
Q2
tCKQX
tCKTV
tAC
tOLZ
tAC
Q3
tCKQX
Q4
tCKQX
WAIT#
Figure 45. Burst Read Suspend Diagram
Burst Write Suspend
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RSHUDWLRQ:(EURXJKWWR+LJKVXVSHQGVEXUVWZULWHRSHUDWLRQ2QFH:(LV
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,QRUGHUWRJXDUDQWHHWRODWFKWKHODVWGDWDLQSXWEHIRUHVXVSHQVLRQDQGILUVWGDWD
LQSXWDIWHUUHVXPSWLRQWKHVSHFLILHGPLQLPXPYDOXHRI:( /KROGWLPHDQG
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IXQFWLRQLVDYDLODEOHZKHQWKHGHYLFHLVRSHUDWLQJLQ:(OHYHOFRQWUROOHGEXUVW
ZULWHRQO\
CLK
tCKWH tWSCK
tCKWH tWSCK
WE#
tDSCK
DQ
tDSCK
D1
D2
tDHCK
WAIT#
tDSCK
D2
tDHCK
tDSCK
D3
D4
tDHCK
High
Figure 46.
Burst Write Suspend Diagram
Burst Read Termination
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
127
P r e l i m i n a r y
&( +,WLVLQKLELWHGWRWHUPLQDWHEXUVWUHDGEHIRUHILUVWGDWDRXWLVFRPSOHWHG
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KROGWLPHIURPFORFNHGJHPXVWEHVDWLVILHG$IWHUWHUPLQDWLRQWKHVSHFLILHGPLQ
LPXPUHFRYHU\WLPHLVUHTXLUHGWRVWDUWQHZDFFHVV
CLK
ADDRESS
Valid
ADV#
tTRB
tCKCLH
tCHZ
tCKOH
tOHZ
CE1#
OE#
WAIT#
tCHTZ
tAC
High-Z
tCKQX
Q1
DQ
Q2
Figure 47.
Burst Read Termination Diagram
Burst Write Termination
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&( +,WLVLQKLELWHGWRWHUPLQDWHEXUVWZULWHEHIRUHILUVWGDWDLQLVFRPSOHWHG
,QRUGHUWRJXDUDQWHHODVWZULWHGDWDEHLQJODWFKHGWKHVSHFLILHGPLQLPXPYDOXHV
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VSHFLILHGPLQLPXPUHFRYHU\WLPHLVUHTXLUHGWRVWDUWQHZDFFHVV
CLK
ADDRESS
Valid
ADV#
tTRB
tCKCLH
tCHCK
CE1#
tCKWH
WE#
WAIT#
DQ
tCHTZ
tDSCK
tDSCK
D1
tDHCK
D2
tDHCK
Figure 48.
128
High-Z
Burst Write Termination Diagram
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Absolute Maximum Ratings
Item
Symbol
Value
Unit
9''
WR
9
9,19287
WR
9
6KRUW&LUFXLW2XWSXW&XUUHQW
,287
“
P$
6WRUDJHWHPSHUDWXUH
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9ROWDJHRI9''6XSSO\5HODWLYHWR966
9ROWDJHDW$Q\3LQ5HODWLYHWR966
:$51,1*6HPLFRQGXFWRUGHYLFHVFDQEHSHUPDQHQWO\GDPDJHGE\DSSOLFDWLRQRIVWUHVVYROWDJHFXUUHQWWHPSHUDWXUH
HWFLQH[FHVVRIDEVROXWHPD[LPXPUDWLQJV'RQRWH[FHHGWKHVHUDWLQJV
Recommended Operating Conditions (See Warning Below)
32M
Parameter
64M
Symbol
Min
Max
Min
Max
Unit
9''
9
966
9
+LJK/HYHO,QSXW9ROWDJH1RWH
9,+
9''[
9''
9''[
9''
9
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9''[
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$OZD\VXVHVHPLFRQGXFWRUGHYLFHVZLWKLQWKHUHFRPPHQGHGRSHUDWLQJFRQGLWLRQV2SHUDWLRQRXWVLGHWKHVHUDQJHVPD\
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Package Pin Capacitance
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Symbol
Description
Test Setup
Typ
Max
Unit
&,1
$GGUHVV,QSXW&DSDFLWDQFH
9,1 9
²
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&,1
&RQWURO,QSXW&DSDFLWDQFH
9,1 9
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&,2
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9,2 9
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
129
P r e l i m i n a r y
DC Characteristics
(Under Recommended Conditions Unless Otherwise Noted)
0
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6\PERO
0
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130
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
32M
Parameter
64M
Symbol
Min.
Max.
Min.
Max.
Unit
Notes
5HDG&\FOH7LPH
W5&
QV
&($FFHVV7LPH
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²
²
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2($FFHVV7LPH
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²
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²
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²
²
QV
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W%/=
²
²
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²
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²
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W%+=
²
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²
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²
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
131
P r e l i m i n a r y
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$SSOLFDEOHWR$WR$ZKHQ&(LVNHSWDW/RZ
$SSOLFDEOHRQO\WR$$DQG$ZKHQ&(LVNHSWDW/RZIRUWKHSDJHDGGUHVVDFFHVV
,QFDVH3DJH5HDG&\FOHLVFRQWLQXHGZLWKNHHSLQJ&(VWD\V/RZ&(PXVWEHEURXJKWWR+LJKZLWKLQ—V,QRWKHU
ZRUGV3DJH5HDG&\FOHPXVWEHFORVHGZLWKLQ—V
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HTXDORUJUHDWHUWKDQW5&IRUHDFKDFFHVV
$SSOLFDEOHWRDGGUHVVDFFHVVZKHQDWOHDVWWZRRIDGGUHVVLQSXWVDUHVZLWFKHGIURPSUHYLRXVVWDWH
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DPRXQWRIVXEWUDFWLQJDFWXDOYDOXHIURPVSHFLILHGPLQLPXPYDOXH
132
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Write Operation
32M
Parameter
64M
Symbol
Min.
Max.
Min.
Max.
Unit
Notes
:ULWH&\FOH7LPH
W:&
QV
$GGUHVV6HWXS7LPH
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²
²
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²
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²
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W$69
²
²
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²
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²
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²
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W:+3
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²
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²
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²
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1RWHV
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0LQLPXPYDOXHPXVWEHHTXDORUJUHDWHUWKDQWKHVXPRIZULWHSXOVHW&:W:3RUW%:DQGZULWHUHFRYHU\WLPHW:5
:ULWHSXOVHLVGHILQHGIURP+LJKWR/RZWUDQVLWLRQRI&(:(RU/%8%ZKLFKHYHURFFXUVODVW
W93/LVVSHFLILHGIURPWKHQHJDWLYHHGJHRIHLWKHU&(RU$'9ZKLFKHYHUFRPHVODWH7KHVXPRIW93/DQGW93+PXVWEH
HTXDORUJUHDWHUWKDQW:&IRUHDFKDFFHVV
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&(LVEURXJKWWR/RZ2QFHUHDGF\FOHLVLQLWLDWHGQHZZULWHSXOVHVKRXOGEHLQSXWDIWHUPLQLPXPW5&LVPHW
,I2(LV/RZDIWHUQHZDGGUHVVLQSXWUHDGF\FOHLVLQLWLDWHG,QRWKHUZRUG2(PXVWEHEURXJKWWR+LJKDWWKHVDPHWLPH
RUEHIRUHQHZDGGUHVVYDOLG2QFHUHDGF\FOHLVLQLWLDWHGQHZZULWHSXOVHVKRXOGEHLQSXWDIWHUPLQLPXPW5&LVPHWDQGGDWD
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August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
133
P r e l i m i n a r y
Synchronous Operation - Clock Input (Burst Mode)
32M
Parameter
Symbol
Min.
5/ 5/ &ORFN3HULRG
5/ 64M
Max.
1$
W&.
5/ Min.
Max.
Unit
²
QV
²
²
QV
²
²
QV
²
Notes
QV
&ORFN+LJK7LPH
W&.+
²
²
QV
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W&./
²
²
QV
&ORFN5LVH)DOO7LPH
W&.7
²
²
QV
1RWHV
&ORFNSHULRGLVGHILQHGEHWZHHQYDOLGFORFNHGJHV
&ORFNULVHIDOOWLPHLVGHILQHGEHWZHHQ9,+0LQDQG9,/0D[
Synchronous Operation - Address Latch (Burst Mode)
32M
Parameter
64M
Symbol
Min.
Max.
Min.
Max.
Unit
Notes
$GGUHVV6HWXS7LPHWR$'9/RZ
W$69/
²
²
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$GGUHVV6HWXS7LPHWR&(/RZ
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²
²
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$GGUHVV+ROG7LPHIURP$'9+LJK
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²
²
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²
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²
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²
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$'9/RZ+ROG7LPHIURP&/.
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²
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W9+9/
²
²
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$'9/RZ6HWXS7LPHWR&/.
&(/RZ6HWXS7LPHWR&/.
5/ 5/ 5/ 5/ 1RWHV
W$6&/LVDSSOLFDEOHLI&(LVEURXJKWWR/RZDIWHU$'9LVEURXJKWWR/RZ
W$69/LVDSSOLFDEOHLI$'9LVEURXJKWWR/RZDIWHU&(LVEURXJKWWR/RZ
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$SSOLFDEOHWRWKHVWYDOLGFORFNHGJH
134
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Synchronous Read Operation (Burst Mode)
32M
Parameter
64M
Symbol
Min.
Max.
Min.
Max.
Unit
W5&%
²
²
QV
W$&
²
²
QV
²
QV
2XWSXW+ROG7LPHIURP&/.
W&.4;
²
²
QV
&(/RZWR:$,7/RZ
W&/7/
QV
2(/RZWR:$,7/RZ
W2/7/
QV
$'9/RZWR:$,7/RZ
W9/7/
QV
&/.WR:$,79DOLG7LPH
W&.79
²
²
QV
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W&.7;
²
²
QV
&(/RZWR2XWSXW/RZ=
W&/=
²
²
QV
2(/RZWR2XWSXW/RZ=
W2/=
²
²
QV
/%8%/RZWR2XWSXW/RZ=
W%/=
²
²
QV
&(+LJKWR2XWSXW+LJK=
W&+=
²
²
QV
2(+LJKWR2XWSXW+LJK=
W2+=
²
²
QV
/%8%+LJKWR2XWSXW+LJK=
W%+=
²
²
QV
&(+LJKWR:$,7+LJK=
W&+7=
²
²
QV
2(+LJKWR:$,7+LJK=
W2+7=
²
²
QV
2(/RZ6HWXS7LPHWRVW'DWDRXW
W2/4
²
²
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²
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2(6HWXS7LPHWR&/.
W26&.
²
²
QV
2(+ROG7LPHIURP&/.
W&.2+
²
²
QV
%XUVW(QG&(/RZ+ROG7LPHIURP&/.
W&.&/+
²
²
QV
%XUVW(QG8%/%+ROG7LPHIURP&/.
W&.%+
²
²
QV
²
²
QV
²
²
QV
%XUVW5HDG&\FOH7LPH
5/ &/.$FFHVV7LPH
%XUVW7HUPLQDWH5HFRYHU\7LPH
5/ %/ %/ &RQWLQXRXV
W75%
1$
Notes
1RWHV
7KHRXWSXWORDGS)ZLWKRKPWHUPLQDWLRQWR9''9
:$,7GULYHV+LJKDWWKHEHJLQQLQJGHSHQGLQJRQ2(IDOOLQJHGJHWLPLQJ
W&.79LVJXDUDQWHHGDIWHUW2/7/PD[IURP2(IDOOLQJHGJHDQGW26&.PXVWEHVDWLVILHG
7KHRXWSXWORDGLVS)ZLWKRXWDQ\RWKHUORDG
2QFHWKH\DUHGHWHUPLQHGWKH\PXVWQRWEHFKDQJHGXQWLOWKHHQGRIEXUVW
'HILQHGIURPWKH/RZWR+LJKWUDQVLWLRQRI&(WRWKH+LJKWR/RZWUDQVLWLRQRIHLWKHU$'9RU&(ZKLFKHYHURFFXUVODWH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
135
P r e l i m i n a r y
Synchronous Write Operation (Burst Mode)
32M
Parameter
64M
Symbol
Min.
Max.
Min.
Max.
Unit
%XUVW:ULWH&\FOH7LPH
W:&%
²
²
QV
'DWD6HWXS7LPHWR&ORFN
W'6&.
²
²
QV
'DWD+ROG7LPHIURP&/.
W'+&.
²
²
QV
:(/RZ6HWXS7LPHWRVW'DWD,Q
W:/'
²
²
QV
W%6
²
²
QV
:(6HWXS7LPHWR&/.
W:6&.
²
²
QV
:(+ROG7LPHIURP&/.
W&.:+
²
²
QV
&(/RZWR:$,7+LJK
W&/7+
QV
:(/RZWR:$,7+LJK
W:/7+
QV
&(+LJKWR:$,7+LJK=
W&+7=
²
²
QV
:(+LJKWR:$,7+LJK=
W:+7=
²
²
QV
%XUVW(QG&(/RZ+ROG7LPHIURP&/.
W&.&/+
²
²
QV
%XUVW(QG&(+LJK6HWXS7LPHWRQH[W&/.
W&+&.
²
²
QV
%XUVW(QG8%/%+ROG7LPHIURP&/.
W&.%+
²
²
QV
%XUVW:ULWH5HFRYHU\7LPH
W:5%
%/ W75%
²
²
QV
%/ &RQWLQXRXV
W75%
²
²
QV
8%/%6HWXS7LPHIRU:ULWH
%XUVW7HUPLQDWH5HFRYHU\7LPH
Notes
QV
1RWHV
'HILQHGIURPWKHYDOLGLQSXWHGJHWRWKH+LJKWR/RZWUDQVLWLRQRIHLWKHU$'9&(RU:(ZKLFKHYHURFFXUVODVW$QG
RQFHWKH\DUHGHWHUPLQHGWKH\PXVWQRWEHFKDQJHGXQWLOWKHHQGRIEXUVW
7KHRXWSXWORDGS)ZLWKRKPWHUPLQDWLRQWR9''9
'HILQHGIURPWKHYDOLGFORFNHGJHZKHUHODVWGDWDLQEHLQJODWFKHGDWWKHHQGRIEXUVWZULWHWRWKH+LJKWR/RZWUDQVLWLRQRI
HLWKHU$'9RU&(ZKLFKHYHURFFXUVODWHIRUWKHQH[WDFFHVV
'HILQHGIURPWKH/RZWR+LJKWUDQVLWLRQRI&(WRWKH+LJKWR/RZWUDQVLWLRQRIHLWKHU$'9RU&(ZKLFKHYHURFFXUVODWH
IRUWKHQH[WDFFHVV
136
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Power Down Parameters
32M
Parameter
64M
Symbol
Min.
Max.
Min.
Max.
Unit
&(/RZ6HWXS7LPHIRU3RZHU'RZQ(QWU\
W&63
²
²
QV
&(/RZ+ROG7LPHDIWHU3RZHU'RZQ(QWU\
W&/3
²
²
QV
&(/RZ+ROG7LPHIRU5HVHWWR$V\QFKURQRXV0RGH
W&/35
²
—V
1$
Notes
&(+LJK+ROG7LPHIROORZLQJ&(+LJKDIWHU3RZHU
'RZQ([LW>6/((3PRGHRQO\@
W&++
²
²
—V
&(+LJK+ROG7LPHIROORZLQJ&(+LJKDIWHU3RZHU
'RZQ([LW>QRWLQ6/((3PRGH@
W&++3
²
²
—V
&(+LJK6HWXS7LPHIROORZLQJ&(+LJKDIWHU3RZHU
'RZQ([LW
W&+6
²
²
QV
Notes
1RWHV
$SSOLFDEOHZKHQ53 5HVHWWR3DJHPRGH535HVHWWR3DJHPRGHLVDYDLODEOHRQO\IRU0
$SSOLFDEOHDOVRWRSRZHUXS
$SSOLFDEOHZKHQ3DUWLDOPRGHLVVHW
Other Timing Parameters
32M
Parameter
64M
Symbol
Min.
Max.
Min.
Max.
Unit
&(+LJKWR2(,QYDOLG7LPHIRU6WDQGE\(QWU\
W&+2;
²
²
QV
&(+LJKWR:(,QYDOLG7LPHIRU6WDQGE\(QWU\
W&+:;
²
²
QV
&(/RZ+ROG7LPHDIWHU3RZHUXS
W&/+
²
²
—V
&(+LJK+ROG7LPHIROORZLQJ&(+LJKDIWHU3RZHUXS
W&++
²
²
—V
W7
QV
,QSXW7UDQVLWLRQ7LPH
1RWHV
6RPHGDWDPLJKWEHZULWWHQLQWRDQ\DGGUHVVORFDWLRQLIW&+:;PLQLVQRWVDWLVILHG
([FHSWIRUFORFNLQSXWWUDQVLWLRQWLPH
7KH,QSXW7UDQVLWLRQ7LPHW7DW$&WHVWLQJLVQVIRU$V\QFKURQRXVRSHUDWLRQDQGQVIRU6\QFKURQRXVRSHUDWLRQ
UHVSHFWLYHO\,IDFWXDOW7LVORQJHUWKDQQVRUQVVSHFLILHGDV$&WHVWFRQGLWLRQLWPD\YLRODWH$&VSHFLILFDWLRQRIVRPH
WLPLQJSDUDPHWHUV6HHWKH$&7HVW&RQGLWLRQVVHFWLRQ
AC Test Conditions
Symbol
Description
Test Setup
Value
Unit
9,+
,QSXW+LJK/HYHO
9''
9
9,/
,QSXW/RZ/HYHO
9''
9
,QSXW7LPLQJ0HDVXUHPHQW/HYHO
9''
9
QV
QV
95()
W7
,QSXW7UDQVLWLRQ7LPH
August 19, 2005 S71WS-J_04_A2
$V\QF
6\QF
%HWZHHQ9,/DQG9,+
S71WS-J Based MCPs
Note
137
P r e l i m i n a r y
AC Measurement Output Load Circuit
VDD*0.5V
50ohm
VDD
DEVICE
UNDER
TEST
0.1μF
VSS
50pF
Figure 49.
138
OUT
Output Load Circuit
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Timing Diagrams
tRC
ADDRESS VALID
ADDRESS
ADV#
Low
tASC
tCE
tCHAH
tASC
CE1#
tCP
tOE
tCHZ
OE#
tOHZ
tBA
LB# / UB#
tBHZ
tBLZ
tOLZ
DQ
(Output)
VALID DATA OUTPUT
tOH
Figure 50. Asynchronous Read Timing #1-1 (Basic Timing)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG:( +
tRC
ADDRESS VALID
ADDRESS
tAHV
tAV
tVPL
ADV#
tASC
tASC
tCE
CE1#
tCP
tOE
tCHZ
OE#
tOHZ
tBA
LB# / UB#
tBHZ
tBLZ
DQ
(Output)
tOLZ
VALID DATA OUTPUT
Figure 51.
tOH
Asynchronous Read Timing #1-2 (Basic Timing)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG:( +
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
139
P r e l i m i n a r y
tAX
tRC
ADDRESS
tRC
ADDRESS VALID
ADDRESS VALID
tAA
CE1#
tAA
tOHAH
Low
tASO
tOE
OE#
LB# / UB#
tOLZ
tOH
tOHZ
tOH
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Figure 52. Asynchronous Read Timing #2 (OE# & Address Access)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +$'9 /DQG:( +
tAX
tRC
ADDRESS
tAX
ADDRESS VALID
tAA
CE1#, OE#
Low
tBA
tBA
LB#
tBA
UB#
tBHZ
tBHZ
tOH
tBLZ
tBLZ
tOH
DQ1-8
(Output)
VALID DATA
OUTPUT
DQ9-16
(Output)
tBLZ
VALID DATA
OUTPUT
tOH
tBHZ
VALID DATA OUTPUT
Figure 53.
Asynchronous Read Timing #3 (LB# / UB# Byte Access)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +$'9 /DQG:( +
140
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
tRC
ADDRESS
(A21-A3)
ADDRESS VALID
tRC
ADDRESS
(A2-A0)
ADDRESS VALID
tPRC
tPRC
ADDRESS
VALID
ADDRESS
VALID
tPAA
tASC
tPRC
ADDRESS
VALID
tPAA
tPAA
tCHAH
ADV#
CE1#
tCHZ
tCE
OE#
LB# / UB#
tCLZ
tOH
tOH
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
(Page Access)
VALID DATA OUTPUT
(Normal Access)
Figure 54. Asynchronous Read Timing #4 (Page Address Access after CE1# Control Access)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG:( +
tRC
ADDRESS
(A21-A3)
tRC
ADDRESS VALID
tRC
ADDRESS
(A2-A0)
tRC
ADDRESS
VALID
ADDRESS
VALID
tAX
ADDRESS VALID
tPRC
tAA
CE1#
tAX
tPRC
ADDRESS
VALID
tPAA
ADDRESS
VALID
tAA
tPAA
Low
tASO
tOE
OE#
tBA
LB# / UB#
tOLZ
tBLZ
DQ
(Output)
tOH
tOH
VALID DATA OUTPUT
(Normal Access)
Figure 55.
tOH
tOH
VALID DATA OUTPUT
(Page Access)
Asynchronous Read Timing #5 (Random and Page Address
Access)
1RWHV
7KLVWLPLQJGLDJUDPDVVXPHV&( +$'9 /DQG:( +
(LWKHURUERWK/%DQG8%PXVWEH/RZZKHQERWK&(DQG2(DUH/RZ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
141
P r e l i m i n a r y
tWC
ADDRESS
ADV#
ADDRESS VALID
Low
tAS
tCW
tWRC
tAS
CE1#
tAS
tWP
tWR
tAS
WE#
tAS
tBW
tBR
tAS
LB#, UB#
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Figure 56.
Asynchronous Write Timing #1-1 (Basic Timing)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG$'9 /
tWC
ADDRESS
ADDRESS VALID
tVPL
ADV#
tAS
tAHV
tCW
tWRC
tAS
CE1#
tAS
tWP
tWR
tAS
WE#
tAS
tBW
tBR
tAS
LB#, UB#
tOHCL
OE#
tDS
tDH
DQ
(Input)
VALID DATA INPUT
Figure 57. Asynchronous Write Timing #1-2 (Basic Timing)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +
142
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
tWC
tWC
ADDRESS VALID
ADDRESS
ADDRESS VALID
tOHAH
CE1#
Low
tAS
tWP
tWR
tAS
tWP
tWR
WE#
UB#, LB#
tOES
OE#
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
VALID DATA INPUT
VALID DATA INPUT
Figure 58. Asynchronous Write Timing #2 (WE# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG$'9 /
tWC
ADDRESS VALID
ADDRESS
CE1#
tWC
ADDRESS VALID
Low
tAS
tWP
tAS
tWP
WE#
tBH
tBR
tBS
LB#
tBS
tBR
tBH
UB#
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 59. Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +$'9 /DQG2( +
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
143
P r e l i m i n a r y
tWC
ADDRESS VALID
ADDRESS
CE1#
tWC
ADDRESS VALID
Low
tWR
tWR
WE#
tAS
tBW
tBS
tBH
LB#
tBH
tBS
tAS
tBW
UB#
tDS
DQ1-8
(Input)
tDH
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 60. Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +$'9 /DQG2( +
tWC
ADDRESS VALID
ADDRESS VALID
ADDRESS
CE1#
tWC
Low
WE#
tAS
tBW
tBR
tBS
tBH
LB#
tBS
tBH
tAS
tBW
tBR
UB#
tDS
tDH
DQ1-8
(Input)
VALID DATA INPUT
tDS
tDH
DQ9-16
(Input)
VALID DATA INPUT
Figure 61. Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +$'9 /DQG2( +
144
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
tWC
ADDRESS VALID
ADDRESS
CE1#
tWC
ADDRESS VALID
Low
WE#
tAS
tBW
tBR
tAS
tBW
tBR
LB#
tBWO
DQ1-8
(Input)
tDH
tDS
tDS
VALID
DATA INPUT
tAS
tBW
tDH
VALID
DATA INPUT
tBR
tAS
tBR
tBWO
tBW
UB#
tDS
DQ9-16
(Input)
tDH
tDS
VALID
DATA INPUT
tDH
VALID
DATA INPUT
Figure 62. Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +$'9 /DQG2( +
tWC
ADDRESS
tRC
WRITE ADDRESS
tCHAH
tAS
tCW
READ ADDRESS
tWRC
tASC
tCE
tCHAH
CE1#
tCP
tCP
WE#
UB#, LB#
tOHCL
OE#
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
READ DATA OUTPUT
Figure 63.
WRITE DATA INPUT
Asynchronous Read / Write Timing #1-1 (CE1# Control)
1RWHV
7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG$'9 /
:ULWHDGGUHVVLVYDOLGIURPHLWKHU&(RU:(RIODVWIDOOLQJHGJH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
145
P r e l i m i n a r y
tWC
ADDRESS
tRC
WRITE ADDRESS
tCHAH
READ ADDRESS
tAS
tWR
tASC
tCE
tCHAH
CE1#
tCP
tCP
tWP
WE#
UB#, LB#
tOHCL
tOE
OE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
READ DATA OUTPUT
WRITE DATA INPUT
READ DATA OUTPUT
Figure 64. Asynchronous Read / Write Timing #1-2 (CE1# / WE# / OE# Control)
1RWHV
7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG$'9 /
2(FDQEHIL[HG/RZGXULQJZULWHRSHUDWLRQLILWLV&(FRQWUROOHGZULWHDW5HDG:ULWH5HDG6HTXHQFH
tWC
ADDRESS
tRC
WRITE ADDRESS
READ ADDRESS
tOHAH
CE1#
Low
tAS
WE#
tOHAH
tAA
tWR
tWP
tOES
UB#, LB#
tASO
tOE
OE#
tOHZ
tOH
tDS
tDH
tOHZ
tOH
tOLZ
DQ
READ DATA OUTPUT
Figure 65.
WRITE DATA INPUT
READ DATA OUTPUT
Asynchronous Read / Write Timing #2 (OE#, WE# Control)
1RWHV
7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG$'9 /
&(FDQEHWLHGWR/RZIRU:(DQG2(FRQWUROOHGRSHUDWLRQ
146
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
tWC
ADDRESS
tRC
WRITE ADDRESS
READ ADDRESS
tAA
CE1#
Low
tOHAH
tOHAH
WE#
tOES
tAS
tBW
tBR
tBA
UB#, LB#
tBHZ
tASO
OE#
tDS
tOH
tDH
tBHZ
tOH
tBLZ
DQ
READ DATA OUTPUT
Figure 66.
READ DATA OUTPUT
WRITE DATA INPUT
Asynchronous Read / Write Timing #3 (OE,# WE#, LB#, UB# Control)
1RWHV
7KLVWLPLQJGLDJUDPDVVXPHV&( +DQG$'9 /
&(FDQEHWLHGWR/RZIRU:(DQG2(FRQWUROOHGRSHUDWLRQ
tCK
CLK
tCK
tCKH
tCKL
tCKT
tCKT
Figure 67. Clock Input Timing
1RWHV
6WDEOHFORFNLQSXWPXVWEHUHTXLUHGGXULQJ&( /
W&.LVGHILQHGEHWZHHQYDOLGFORFNHGJHV
W&.7LVGHILQHGEHWZHHQ9,+0LQDQG9,/0D[
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
147
P r e l i m i n a r y
Case #1
Case #2
CLK
ADDRESS
Valid
Valid
tASCL
tCKVH
tAHV
tVSCK
tCKVH
tAHV
tASVL
tVSCK
ADV#
tVPL
tVLCL
tVPL
tCLCK
Low
CE1#
Figure 68. Address Latch Timing (Synchronous Mode)
1RWHV
&DVHLVWKHWLPLQJZKHQ&(LVEURXJKWWR/RZDIWHU$'9LVEURXJKWWR/RZ&DVHLVWKHWLPLQJZKHQ$'9LV
EURXJKWWR/RZDIWHU&(LVEURXJKWWR/RZ
W93/LVVSHFLILHGIURPWKHQHJDWLYHHGJHRIHLWKHU&(RU$'9ZKLFKHYHUFRPHVODWH$WOHDVWRQHYDOLGFORFNHGJHPXVWEH
LQSXWGXULQJ$'9 /
W96&.DQGW&/&.DUHDSSOLHGWRWKHVWYDOLGFORFNHGJHGXULQJ$'9 /
148
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tVSCK
tVSCK
tCKVH
tCKVH
ADV#
tVPL
tVHVL
tVPL
tASCL
tASCL
CE1#
tCLCK
tCLCK
tCKOH
tCP
OE#
tOLQ
WE#
High
tCKBH
tBLQ
LB#, UB#
tCKTV
WAIT#
tOHTZ
High-Z
tOLTL
DQ
tCKTV
tCKTX
tAC
tAC
Q1
High-Z
tOLZ
Figure 69.
tCKQX
tAC
tCKTX
tOHZ
QBL
tCKQX
32M Synchronous Read Timing #1 (OE# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
149
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tAHV
tVSCK
tVSCK
tCKVH
tCKVH
ADV#
tVPL
tVHVL
tVPL
tASCL
tASCL
CE1#
tCP
tCLCK
tCKCLH
tCLCK
OE#
WE#
High
tCKBH
LB#, UB#
tCKTV
tCKTV
tCHTZ
tCLTL
WAIT#
tCLTL
DQ
tCKTX
tAC
tAC
Q1
tCLZ
Figure 70.
tCKQX
tAC
tCKTX
tCLZ
tCHZ
QBL
tCKQX
32M Synchronous Read Timing #2 (CE1# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
150
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tVSCK
tAHV
tVSCK
tCKVH
tCKVH
ADV#
tVPL
tVHVL
tVPL
CE1#
Low
OE#
Low
WE#
High
LB#, UB#
tCKTV
tCKTV
WAIT#
tCKTX
DQ
tAC
tAC
Q1
tCKQX
tAC
tCKTX
QBL
tCKQX
Figure 71. 32M Synchronous Read Timing #3 (ADV# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
151
P r e l i m i n a r y
RL=5
CLK
XXX7Fh
ADDRESS
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVPL
tASCL
CE1#
tCLCK
OE#
tOLQ
WE#
High
tBLQ
LB#, UB#
tCKTV
WAIT#
tCKTV
tCKTV
High-Z
tCKTX
tOLTL
DQ
tCKTX
tAC
tAC
tCKTX
tAC
tAC
Q1
High-Z
tOLZ
Q2
tCKQX
tCKQX
tAC
Q3
tCKQX
Figure 72. Synchronous Read - WAIT# Output Timing (Continuous Read)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
152
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tVSCK
tVSCK
tCKVH
tCKVH
ADV#
tVPL
tVHVL
tVPL
tASCL
tASCL
CE1#
tCLCK
tCLCK
tCKOH
tCP
OE#
tOLQ
WE#
High
tCKBH
tBLQ
LB#, UB#
tCKTV
WAIT#
High-Z
tOLTL
DQ
tOHTZ
tCKTX
tAC
tAC
Q1
High-Z
tOLZ
Figure 73.
tCKQX
tOHZ
tAC
QBL
tCKQX
64M Synchronous Read Timing #1 (OE# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
153
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tVSCK
tASVL
tAHV
tVSCK
tCKVH
tCKVH
ADV#
tVPL
tVHVL
tVPL
tASCL
tASCL
CE1#
tCP
tCLCK
tCKCLH
tCLCK
OE#
WE#
High
tCKBH
LB#, UB#
tCKTV
tCHTZ
tCLTL
WAIT#
tCLTL
tCKTX
tAC
tAC
Q1
DQ
tCLZ
Figure 74.
tCKQX
tAC
tCLZ
tCHZ
QBL
tCKQX
64M Synchronous Read Timing #2 (CE1# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
154
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tRCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tVSCK
tAHV
tVSCK
tCKVH
tCKVH
ADV#
tVPL
tVHVL
tVPL
CE1#
Low
OE#
Low
WE#
High
LB#, UB#
tCKTV
tVLTL
tVLTL
WAIT#
tCKTX
DQ
tAC
tAC
Q1
tCKQX
tAC
QBL
tCKQX
Figure 75. 64M Synchronous Read Timing #3 (ADV# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
155
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tAHV
tVSCK
tVSCK
tCKVH
tCKVH
tVHVL
ADV#
tVPL
tWRB
tVPL
tCLCK
tASCL
tASCL
CE1#
tCLCK
OE#
tCP
High
tWLD
tCKWH
WE#
tBS
tCKBH
tBS
LB#, UB#
WAIT#
High-Z
tWLTH
DQ
tDSCK
tDSCK
D1
tDSCK
D2
tDHCK
tWHTZ
DBL
tDHCK
Figure 76. Synchronous Write Timing #1 (WE# Level Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
156
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tAHV
tVSCK
tVSCK
tCKVH
tCKVH
tVHVL
ADV#
tVPL
tWRB
tASCL
tVPL
tCLCK
tASCL
CE1#
tCLCK
tCP
tCKCLH
High
OE#
tWSCK
tCKWH
tWSCK
tCKWH
WE#
tBS
tCKBH
tBS
LB#, UB#
WAIT#
High-Z
tWLTH
tDSCK
tDSCK
D1
DQ
tDSCK
D2
tDHCK
tCHTZ
tWLTH
DBL
tDHCK
Figure 77. Synchronous Write Timing #2 (WE# Single Clock Pulse Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
157
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tAHV
tVSCK
tVSCK
tCKVH
tCKVH
ADV#
tVHVL
tVPL
tVPL
tWRB
CE1#
High
OE#
WE#
tBS
tCKBH
tBS
LB#, UB#
High
WAIT#
tDSCK
DQ
tDSCK
D1
tDSCK
D2
tDHCK
DBL
tDHCK
Figure 78. Synchronous Write Timing #3 (ADV# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
158
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
Valid
tASVL
tAHV
tASVL
tAHV
tVSCK
tVSCK
tCKVH
tCKVH
tVHVL
ADV#
tVPL
tWRB
tVPL
tASCL
tASCL
tCLCK
CE1#
tCLCK
OE#
tCP
High
tWLD
tCKWH
WE#
tBS
tCKBH
tBS
LB#, UB#
WAIT#
High-Z
tWLTH
tDSCK
tWHTZ
tWLTH
D1
DQ
tDHCK
Figure 79. Synchronous Write Timing #4 (WE# Level Control, Single Write)
1RWHV
7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQGVLQJOHZULWHRSHUDWLRQ
:ULWHGDWDLVODWFKHGRQWKHYDOLGFORFNHGJH
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
159
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVHVL
tCKCLH
tVPL
tCLCK
tASCL
tCKCLH
CE1#
tCP
OE#
WE#
tCKBH
tBS
tCKBH
LB#, UB#
tCHTZ
tCKTV
WAIT#
tAC
DQ
QBL-1
tCKQX
tCKTX
tCHZ
tCLTH
tDSCK
QBL
D1
tDHCK
tCKQX
Figure 80.
tDSCK
tDSCK
D2
tDHCK
tDSCK
D3
DBL
tDHCK
tDHCK
32M Synchronous Read to Write Timing #1(CE1# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
160
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVPL
tVHVL
CE1#
tCKOH
OE#
tWLD
tCKWH
WE#
tCKBH
tBS
tCKBH
LB#, UB#
tOHTZ
tCKTV
WAIT#
tOHZ
tAC
DQ
QBL-1
tCKQX
tCKTX
tWLTH
QBL
tDSCK
tDSCK
D1
tDHCK
tCKQX
tDSCK
D2
tDHCK
tDSCK
D3
tDHCK
DBL
tDHCK
Figure 81. 32M Synchronous Read to Write Timing #2(ADV# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
161
P r e l i m i n a r y
RL=5
CLK
tWCB
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVHVL
tCKCLH
tVPL
tCLCK
tASCL
tCKCLH
CE1#
tCP
OE#
WE#
tCKBH
tBS
tCKBH
LB#, UB#
tCHTZ
WAIT#
tCHZ
tAC
DQ
QBL-1
tCKQX
tCLTH
tDSCK
QBL
tDSCK
D1
tDHCK
tCKQX
tDSCK
D2
tDHCK
tDSCK
D3
DBL
tDHCK
tDHCK
Figure 82. 64M Synchronous Read to Write Timing #1(CE1# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
162
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVPL
tVHVL
CE1#
tCKOH
OE#
tWLD
tCKWH
WE#
tCKBH
tBS
tCKBH
LB#, UB#
tOHTZ
WAIT#
tOHZ
tAC
DQ
QBL-1
tCKQX
tWLTH
QBL
tDSCK
tDSCK
D1
tDHCK
tCKQX
tDSCK
D2
tDHCK
tDSCK
D3
tDHCK
DBL
tDHCK
Figure 83. 64M Synchronous Read to Write Timing #2(ADV# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
163
P r e l i m i n a r y
RL=5
CLK
tCKT
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVPL
tASCL
tCKCLH
CE1#
tCP
tCLCK
tWRB
OE#
WE#
tCKBH
LB#, UB#
tCKTV
High-Z
WAIT#
tDSCK
DQ
tDSCK
DBL-1
tDHCK
tCHTZ
tCLTL
tCKTX
tAC
tAC
DBL
tDHCK
Q1
tCLZ
tCKQX
Q2
tCKQX
Figure 84. Synchronous Write to Read Timing #1 (CE1# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
164
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
RL=5
CLK
tCKT
ADDRESS
Valid
tASVL
tAHV
tVSCK
tCKVH
ADV#
tVPL
tWRB
Low
CE1#
OE#
tOLQ
tCKWH
WE#
tCKBH
tBLQ
LB#, UB#
tCKTV
High-Z
WAIT#
tDSCK
DQ
tDSCK
DBL-1
tWHTZ
tOLTL
tCKTX
tAC
DBL
tDHCK
tDHCK
tAC
Q1
tOLZ
tCKQX
Q2
tCKQX
Figure 85. Synchronous Write to Read Timing #2 (ADV# Control)
1RWH7KLVWLPLQJGLDJUDPDVVXPHV&( +WKHYDOLGFORFNHGJHRQULVLQJHGJHDQG%/ RU
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
165
P r e l i m i n a r y
CE1#
tCHS
tC2LH
tCHH
CE2
VDD
VDD min
0V
Figure 86. Power-up Timing #1
1RWH7KHW&/+VSHFLILHVDIWHU9''UHDFKHVVSHFLILHGPLQLPXPOHYHO
CE1#
tCHH
CE2
VDD
VDD min
0V
Figure 87.
Power-up Timing #2
1RWH7KHW&++VSHFLILHVDIWHU9''UHDFKHVVSHFLILHGPLQLPXPOHYHODQGDSSOLFDEOHWRERWK&(DQG&(
CE1#
tCHS
CE2
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Figure 88. Power Down Entry and Exit Timing
1RWH7KLV3RZHU'RZQPRGHFDQEHDOVRXVHGDVDUHVHWWLPLQJLIWKH32:(583WLPLQJDERYHFRXOGQRWEHVDWLVILHG
DQG3RZHU'RZQSURJUDPZDVQRWSHUIRUPHGSULRUWRWKLVUHVHW
166
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
CE1#
tCHOX
tCHWX
OE#
WE#
Active (Read)
Standby
Figure 89.
Active (Write)
Standby
Standby Entry Timing after Read or Write
1RWH%RWKW&+2;DQGW&+:;GHILQHWKHHDUOLHVWHQWU\WLPLQJIRU6WDQGE\PRGH,IHLWKHURIWLPLQJLVQRWVDWLVILHGLWWDNHV
W5&PLQSHULRGIRU6WDQGE\PRGHIURP&(/RZWR+LJKWUDQVLWLRQ
ADDRESS
tRC
tWC
tWC
MSB*1
MSB*1
MSB*1
tCP
tCP
tWC
tWC
MSB*1
tCP
tRC
MSB*1
tCP
Key*2
tCP*3
(tRC)
tCP
CE1#
OE#
WE#
LB#, UB#
RDa
DQ*3
Cycle #1
Figure 90.
RDa
Cycle #2
RDa
Cycle #3
X
Cycle #4
X
Cycle #5
RDb
Cycle #6
Configuration Register Set Timing #1 (Asynchronous Operation)
1RWHV
7KHDOODGGUHVVLQSXWVPXVWEH+LJKIURP&\FOHWR
7KHDGGUHVVNH\PXVWFRQILUPWKHIRUPDWVSHFLILHGLQWKH)XQFWLRQDO'HVFULSWLRQVHFWLRQ,IQRWWKHRSHUDWLRQDQGGDWDDUH
QRWJXDUDQWHHG
$IWHUW&3RUW5&IROORZLQJ&\FOHWKH&RQILJXUDWLRQ5HJLVWHU6HWLVFRPSOHWHGDQGUHWXUQHGWRWKHQRUPDORSHUDWLRQW&3DQG
W5&DUHDSSOLFDEOHWRUHWXUQLQJWRDV\QFKURQRXVPRGHDQGWRV\QFKURQRXVPRGHUHVSHFWLYHO\
%\WHUHDGRUZULWHLVDYDLODEOHLQDGGLWLRQWR:RUGUHDGRUZULWH$WOHDVWRQHE\WHFRQWUROVLJQDO/%RU8%QHHGWREH
/RZ
August 19, 2005 S71WS-J_04_A2
S71WS-J Based MCPs
167
P r e l i m i n a r y
CLK
ADDRESS MSB
MSB
tRCB
MSB
tWCB
MSB
tWCB
MSB
tWCB
Key
tWCB
tRCB
ADV#
tTRB
tTRB
tTRB
tTRB
tTRB
tTRB
CE1#
OE#
WE#
LB#, UB#
WAIT#
RL
DQ
RL-1
RL-1
RDa
RDa
RDa
Cycle#1
Cycle#2
Cycle#3
RL-1
RL-1
X
Cycle#4
RL
X
RDb
Cycle#5
Cycle#6
Figure 91. Configuration Register Set Timing #2 (Synchronous Operation)
1RWHV
7KHDOODGGUHVVLQSXWVPXVWEH+LJKIURP&\FOHWR
7KHDGGUHVVNH\PXVWFRQILUPWKHIRUPDWVSHFLILHGLQWKH)XQFWLRQDO'HVFULSWLRQVHFWLRQ,IQRWWKHRSHUDWLRQDQGGDWDDUH
QRWJXDUDQWHHG
$IWHUW75%IROORZLQJ&\FOHWKH&RQILJXUDWLRQ5HJLVWHU6HWLVFRPSOHWHGDQGUHWXUQHGWRWKHQRUPDORSHUDWLRQ
%\WHUHDGRUZULWHLVDYDLODEOHLQDGGLWLRQWR:RUGUHDGRUZULWH$WOHDVWRQHE\WHFRQWUROVLJQDO/%RU8%QHHGWREH
/RZ
168
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
COSMORAM Type 1 – 1.8 V, 16 Mb
CMOS 1,048,576-Word x 16 Bit pSRAM
PRELIMINARY
Features
„ $V\QFKURQRXV65$0,QWHUIDFH
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General Description
7KH&26025$07\SHLVD&026S65$0ZLWKDV\QFKURQRXV6WDWLF5DQGRP$FFHVV0HPRU\
65$0LQWHUIDFHFRQWDLQLQJVWRUDJHVDFFHVVLEOHLQDELWIRUPDW7KLV&26025$0
7\SHLVVXLWHGIRUPRELOHDSSOLFDWLRQVVXFKDV&HOOXODU+DQGVHWDQG3'$
Publication Number S71WS-J_04
Revision A
Amendment 2
Issue Date August 19, 2005
P r e l i m i n a r y
Pin Description
3LQ1DPH
'HVFULSWLRQ
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Block Diagram
9''
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$±$
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$GGUHVV
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2XWSXW
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2(
170
S71WS-J Based MCPs
S71WS-J_04_A2 August 19, 2005
P r e l i m i n a r y
Function Truth Table
0RGH
&(
&(
+
+
6WDQGE\'HVHOHFW
2XWSXW'LVDEOH1RWH
:(
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+
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2XWSXW
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industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
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