SPANSION S73WS256ND0BFWA73

S73WS256N Based MCPs
Stacked Multi-Chip Product (MCP)
512/256 Megabit (32M/16M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory with
256/128 Megabit (4M/2M x 16-bit x 4 Banks) Mobile SDRAM
on Shared Data Bus
ADVANCE
INFORMATION
Data Sheet
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Publication Number S73WS256N_00
Revision A
Amendment 3
Issue Date December 16, 2005
A d v a n c e
I n f o r m a t i o n
Notice On Data Sheet Designations
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ii
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
S73WS256N based MCPs
Stacked Multi-Chip Product (MCP)
512/256 Megabit (32M/16M x 16-bit) CMOS 1.8 Volt-only,
Simultaneous Read/Write, Burst Mode Flash Memory with 256/
128 Megabit (4M/2M x 16-bit x 4 Banks) Mobile SDRAM on
Shared Data Bus
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
0&3)HDWXUHV
„ 3RZHUVXSSO\YROWDJHRIWR9
+LJK3HUIRUPDQFH
„ )ODVKDFFHVVWLPHQV
„ )ODVKEXUVWIUHTXHQF\0+]0+]0+]
„ 0RELOH6'5$0EXUVWIUHTXHQF\0+]
„ 3DFNDJH
² [PP
„ 2SHUDWLQJ7HPSHUDWXUH
² ±ƒ&WRƒ&ZLUHOHVV
General Description
7KH6:6VHULHVLVDSURGXFWOLQHRIVWDFNHG0XOWL&KLS3URGXFW0&3SDFNDJHVDQGFRQVLVWV
RI
„ 2QHRUWZRLQWKLVFDVHRQHGLHLVXVHGDVFRGHDQGWKHRWKHUDVGDWDIODVK
PHPRU\GLH
„ 2QH0RELOH6'5$0GLH
„ 6KDUHGDGGUHVVGDWDEXVIRU)ODVKDQG0RELOH6'5$0EDOOSLQRXW
7KHSURGXFWVFRYHUHGE\WKLVGRFXPHQWDUHOLVWHGLQWKHWDEOHEHORZ)RUGHWDLOVDERXWWKHLU
VSHFLILFDWLRQVSOHDVHUHIHUWRWKHLQGLYLGXDOFRQVWLWXHQWGDWDVKHHWVIRUIXUWKHUGHWDLOV
Flash Memory Density
0RELOH
6'5$0
'HQVLW\
0E
256Mb
512Mb
6:61'
6:61'(
0E
Publication Number S73WS256N_00
Revision A
6:61((
Amendment 3
Issue Date December 16, 2005
A d v a n c e
1
Product Selector Guide
Device-Model#
6:61'%$:$
6:61'%$:$%
Flash
Density
(Code)
Flash
Density
(Data)
Flash Initial/Burst
Speed (ns/MHz)
0E
²
QV0+]
6:61'(%$:7
6:61'(%$:7%
6:61((%$:7
6:61'%):$
6:61'%):$%
0E 0E
6:61((%):7
6:61((%):7%
QV0+]
0+]
0E
²
QV0+]
0+]
QV0+]
0+]
S73WS256N Based MCPs
Package
VHFWRU
[[
XQSURWHFWHG EDOO
VHFWRU
[[
XQSURWHFWHG EDOO
VHFWRU
[[
XQSURWHFWHG EDOO
0+]
DYB
0E 0E
Supplier
6:61'(%):7
6:61'(%):7%
SDRAM SDRAM burst
Density Speed (MHz)
6:61((%$:7%
2
I n f o r m a t i o n
VHFWRU
[[
XQSURWHFWHG EDOO
S73WS256N_00_A3 December 16, 2005
A d v a n c e
I n f o r m a t i o n
Table of Contents
S73WS256N Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
1
2
3
4
5
6
7
8
9
10
11
12
13
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 2 x 256Mb Flash with 256Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 2 x 256Mb Flash with 128Mb SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 256MbFlash with 128Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4 Lookahead Diagram on Shared Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Logic Symbol for MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 12.0 mm Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 FTF137—137-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 12.0 x 1.4 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.3 Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.4 Synchronous (Burst) Read Mode & Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.4.1 Continuous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.4.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
12.4.3 8-, 16-, 32-Word Linear Burst without Wrap Around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
12.4.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
12.5 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.6 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.6.1 Single Word Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.6.2 Write Buffer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.6.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.6.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.6.5 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.6.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.6.7 Accelerated Program/Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.6.8 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.6.9 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.7 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.8 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.9 Handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.10 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.11 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7.1 WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
3
A d v a n c e
14
15
16
17
18
I n f o r m a t i o n
13.7.2 ACC Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7.3 Low VCC Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.7.4 Write Pulse “Glitch Protection” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.7.5 Power-Up Write Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.3 Hardware RESET# Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15.2 Customer Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
16.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
16.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.6 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.7 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.8.1 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.8.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
16.8.3 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
16.8.4 AC Characteristics—Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
16.8.5 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
16.8.6 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
16.8.7 Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16.8.8 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
17.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Mobile SDRAM Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Temperature Compensated Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Command Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
No Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e
I n f o r m a t i o n
40
41
42
43
44
45
46
47
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Burst Terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Deep Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
47.1 Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
47.2 Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
47.3 Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
47.4 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
47.5 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
47.6 Deep Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
47.7 Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
47.8 Burst Read/Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
47.9 Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
47.9.1 Read with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
47.10 Write with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
48 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
49 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
49.1 Revision A0 (April 1, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
49.2 Revision A1 (April 25, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
49.3 Revision A2 (April 25, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
49.4 Revision A3 (April 25, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Mobile SDRAM Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
AC Operating Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Operating AC Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Simplified Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Mode Register Field Table to Program Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Normal MRS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
EMRS for PASR (Partial Array Self Ref) & DS (Driver Strength) . . . . . . . . . . . . . . . . . . . . 169
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Internal Temperature Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . 170
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
64.1 Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
64.2 Burst Length = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
65.1 Addresses of 64Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.1.1 Bank Addresses (BA0 ~ BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.1.2 Address Inputs (A0 ~ A11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.2 Addresses of 128Mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.2.1 Bank Addresses (BA0 ~ BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
65.2.2 Address Inputs (A0 ~ A11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.4 Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.5 NOP and Device Deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.6 DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
65.7 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
5
A d v a n c e
I n f o r m a t i o n
65.8
65.9
65.10
65.11
65.12
65.13
65.14
65.15
65.16
65.17
66
67
68
69
70
71
Extended Mode Register Set (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Bank Activate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
All Banks Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Basic Feature and Function Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
65.17.1 Auto Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
65.17.2 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
About Burst Type Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
About Burst Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Function Truth Table (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Function Truth Table (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
SDRAM Type 2 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Mobile SDRAM Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
6
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
AC Operating Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Operating AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Simplified Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Mode Register Field Table to Program Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
82.1 Normal MRS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
82.2 EMRS for PASR (Partial Array Self Refresh) and DS (Driver Strength) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
83.1 Internal Temperature Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
85.1 Burst Length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
85.2 Burst Length = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
86.1 Addresses of 256Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
86.1.1. Bank Addresses (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
86.1.2 Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
86.2 Addresses of 512Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.2.1. Bank Addresses (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.2.2 Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.3 Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.4 Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.5 NOP and Device Deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
86.6 DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
86.7 Mode Register Set (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
86.8 Extended Mode Register Set (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
86.9 Bank Activate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
86.10 Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
86.11 Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
86.12 All Banks Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e
87
88
89
90
91
92
93
94
I n f o r m a t i o n
86.13 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
86.14 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
86.15 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
86.16 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Basic Feature and Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
87.1 Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
87.2 DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
87.3 CAS# Interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
87.4 CAS# Interrupt 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
87.5 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
87.6 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Burst Type Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Burst Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Function Truth Table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Function Truth Table 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
SDRAM Type 2 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
MCP Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
7
A d v a n c e
I n f o r m a t i o n
List of Tables
7DEOH
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7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
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7DEOH
7DEOH
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7DEOH
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7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
7DEOH
8
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S73WS256N_00_A3 December 16, 2005
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S73WS256N Based MCPs
9
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10
I n f o r m a t i o n
&ORFN6XVSHQG([LWDQG3RZHU'RZQ([LW $XWR5HIUHVK 6HOI5HIUHVK 3RZHU8S6HTXHQFHIRU0RELOH6'5$0 6LQJOH%LW5HDG:ULWH5HDG&\FOH6DPH3DJH#&$6/DWHQF\ %XUVW/HQJWK 5HDG:ULWH&\FOHDW6DPH%DQN#%XUVW/HQJWK W5'/ &/. 3DJH5HDG:ULWH&\FOHDW6DPH%DQN#%XUVW/HQJWK W5'/ &/.
3DJH5HDG&\FOHDW'LIIHUHQW%DQN#%XUVW/HQJWK 3DJH:ULWH&\FOHDW'LIIHUHQW%DQN#%XUVW/HQJWK W5'/ &/. 5HDG:ULWH&\FOHDW'LIIHUHQW%DQN#%XUVW/HQJWK 5HDG:ULWH&\FOHZLWK$XWR3UHFKDUJH#%XUVW/HQJWK 5HDG:ULWH&\FOHZLWK$XWR3UHFKDUJH#%XUVW/HQJWK &ORFN6XVSHQVLRQ'402SHUDWLRQ&\FOH#&$6/DWHQF\ %XUVW/HQJWK 5HDG,QWHUUXSWHGE\3UHFKDUJH&RPPDQG5HDG%XUVW6WRS&\FOH#)XOO3DJH%XUVW :ULWH,QWHUUXSWHGE\3UHFKDUJH&RPPDQG:ULWH%XUVW6WRS&\FOH#)XOO3DJH%XUVWW5'/ &/. %XUVW5HDG6LQJOHELW:ULWH&\FOH#%XUVW/HQJWK $FWLYH3UHFKDUJH3RZHU'RZQ0RGH#&$6/DWHQF\ %XUVW/HQJWK 6HOI5HIUHVK(QWU\([LW&\FOH
0RGH5HJLVWHU6HW&\FOHDQG$XWR5HIUHVK&\FOH ([WHQGHG0RGH5HJLVWHU6HW&\FOH
'&2XWSXW/RDG&LUFXLW
$&2XWSXW/RDG&LUFXLW
3DUWLDO$UUD\6HOI5HIUHVK$UHDV
&ORFN6XVSHQG'XULQJ:ULWH
&ORFN6XVSHQG'XULQJ5HDG%/ :ULWH0DVN%/ 5HDG0DVN%/ '40ZLWK&/RFN6XVSHQGHG)XOO3DJH5HDG 5HDG,QWHUUXSWHGE\5HDG%/ :ULWH,QWHUUXSWHGE\:ULWH%/ :ULWH,QWHUUXSWHGE\5HDG%/ 5HDG,QWHUUXSWHGE\:ULWHDQG'40 :ULWH,QWHUUXSWHGE\3UHFKDUJHDQG'40 3UHFKDUJH $XWR3UHFKDUJH %XUVW6WRSDQG,QWHUUXSWHGE\3UHFKDUJH 0RGH5HJLVWHU6HW &ORFN6XVSHQG([LWDQG3RZHU'RZQ([LW $XWR5HIUHVK 6HOI5HIUHVK 3RZHU8S6HTXHQFH 6LQJOH%LW5HDG:ULWH5HDG&\FOH6DPH3DJH#&$6/DWHQF\ %XUVW/HQJWK 5HDG:ULWH&\FOHDW6DPH%DQN#%XUVW/HQJWK W5'/ &/. 5HDG:ULWH&\FOHDW6DPH%DQN#%XUVW/HQJWK W5'/ &/. 3DJH5HDG&\FOHDW'LIIHUHQW%DQN#%XUVW/HQJWK 3DJH:ULWH&\FOHDW'LIIHUHQW%DQN#%XUVW/HQJWK W5'/ &/. 5HDG:ULWH&\FOHDW'LIIHUHQW%DQN#%XUVW/HQJWK 5HDG:ULWH&\FOHZLWK$XWR3UHFKDUJH,#%XUVW/HQJWK 5HDG:ULWH&\FOHZLWK$XWR3UHFKDUJH#%XUVW/HQJWK &ORFN6XVSHQVLRQ'402SHUDWLRQ&\FOH#&$6/DWHQF\ %XUVW/HQJWK 5HDG,QWHUUXSWHGE\3UHFKDUJH&RPPDQG5HDG%XUVW6WRS&\FOH#)XOO3DJH%XUVW :ULWH,QWHUUXSWHGE\3UHFKDUJH&RPPDQG:ULWH%XUVW6WRS&\FOH#)XOO3DJH%XUVWW5'/ &/.
%XUVW5HDG6LQJOHELW:ULWH&\FOH#%XUVW/HQJWK $FWLYH3UHFKDUJH3RZHU'RZQ0RGH#&$6/DWHQF\ %XUVW/HQJWK 6HOI5HIUHVK(QWU\([LW&\FOH
([WHQGHG0RGH5HJLVWHU6HW&\FOH
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e
2
I n f o r m a t i o n
MCP Block Diagram
VCCf
A23 - A0
max +1*
VCC
VID
DQ15 to DQ0
16
CLK
WP#
ACC Flash 1
Flash 2
CE#
(Note 2)
OE#
WE#
RDY
RESET#
AVD#
CLK
WP#f1
ACC
(Note 1) CE#f1
OE#
WE#
RESET#
AVD#
RDY
CE#f2
D-VCC
D-VCCQ
A12 - A0
D-CLK
D-CE#
D-WE#
D-BA0
D-BA1
D-CKE
D-RAS#
D-CAS#
D-DM0
D-DM1
DQ15 to DQ0
VSS
D-max + 1*
VCC
VCCQ
CLK
CE# DQ15 to DQ0
WE#
BA0
BA1
CKE
SDRAM
RAS#
CAS#
DM0
DM1
16
VSSQ
D-VSSQ
* Amax = A23
D-Amax = A12
1RWHV
)RUDRQH)ODVKFRQILJXUDWLRQ&(I &(
)RUDWZR)ODVKFRQILJXUDWLRQ&(I &(IRU)ODVKDQG&(I &(IRU)ODVK&(ILVWKH
FKLSHQDEOHSLQIRUWKHVHFRQG)ODVK
)ODVKDQG6'5$0VKDUHFRPPRQ$$DQG'4'4
$SSOLFDEOHRQO\IRUWKH6:61'(DQG6:61((GHYLFHV
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
11
A d v a n c e
3
3.1
I n f o r m a t i o n
Connection Diagrams
2 x 256Mb Flash with 256Mb SDRAM
EDOO)LQH3LWFK%DOO*ULG$UUD\
7RS9LHZ%DOOV)DFLQJ'RZQ
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
DNU
DNU
DNU
DNU
DNU
DNU
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
DNU
RFU
D-CAS#
D-RAS# D-WE#
DNU
DNU
DNU
DNU
DNU
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
DNU
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
DNU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
DNU
WP#
A7
D-DM0
ACC
WE#
A8
A11
F2-CE#
DNU
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
DNU
A3
A6
D-DM1
F-RST#
RFU
A19
A12
A15
DNU
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DNU
A2
A5
A18
RDY
A20
A9
A13
A21
DNU
G1
G2
G3
G4
G6
G7
G8
G9
G10
DNU
A1
A4
A17
A23
A10
A14
A22
DNU
H1
H2
H3
H4
H7
H8
H9
H10
DNU
A0
VSS
DQ1
DQ6
RFU
A16
DNU
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
DNU
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
DNU
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DNU
RFU
DQ0
DQ10
F-VCC
D-VCC
DQ12
DQ7
VSS
DNU
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
DNU
D-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
DNU
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
DNU
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU
DNU
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
RFU
D-BA0
DNU
DNU
DNU
DNU
DNU
DNU
D-BA1
RFU
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
D-VSS
DNU
DNU
DNU
DNU
DNU
DNU
RFU
RFU
Legend
Flash/SDRAM Shared
SDRAM only
Reserved for
Future Use
Data Flash only
Flash/Data Shared
Code Flash Only
Do Not Use
1RWHV
7LHWKH6'5$0966DQG9664WR'966
7LHWKH6'5$09&&DQG9&&4WR'9&&
6SHFLDO+DQGOLQJ,QVWUXFWLRQV)RU)%*$3DFNDJH
6SHFLDOKDQGOLQJLVUHTXLUHGIRU)ODVK0HPRU\SURGXFWVLQ)%*$SDFNDJHV
)ODVKPHPRU\GHYLFHVLQ)%*$SDFNDJHVPD\EHGDPDJHGLIH[SRVHGWRXOWUD
VRQLFFOHDQLQJPHWKRGV7KHSDFNDJHDQGRUGDWDLQWHJULW\PD\EHFRPSURPLVHG
LIWKHSDFNDJHERG\LVH[SRVHGWRWHPSHUDWXUHVDERYH°&IRUSURORQJHGSHUL
RGVRIWLPH
12
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e
3.2
I n f o r m a t i o n
2 x 256Mb Flash with 128Mb SDRAM
EDOO)LQH3LWFK%DOO*ULG$UUD\
7RS9LHZ%DOOV)DFLQJ'RZQ
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
DNU
DNU
DNU
DNU
DNU
DNU
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
DNU
DNU
DNU
DNU
DNU
DNU
RFU
D-CAS#
D-RAS# D-WE#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
DNU
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
DNU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
DNU
WP#
A7
D-DM0
ACC
WE#
A8
A11
F2-CE#
DNU
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
DNU
A3
A6
D-DM1
F-RST#
RFU
A19
A12
A15
DNU
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DNU
A2
A5
A18
RDY
A20
A9
A13
A21
DNU
G1
G2
G3
G4
G6
G7
G8
G9
G10
DNU
A1
A4
A17
A23
A10
A14
A22
DNU
H1
H2
H3
H4
H7
H8
H9
H10
DNU
A0
VSS
DQ1
DQ6
RFU
A16
DNU
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
DNU
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
DNU
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DNU
RFU
DQ0
DQ10
F-VCC
D-VCC
DQ12
DQ7
VSS
DNU
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
DNU
D-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
DNU
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
DNU
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU
DNU
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
RFU
D-BA0
DNU
DNU
DNU
DNU
DNU
DNU
D-BA1
RFU
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
D-VSS
DNU
RFU
RFU
DNU
DNU
DNU
DNU
DNU
Legend
Flash/SDRAM Shared
SDRAM only
Reserved for
Future Use
Data Flash only
Flash/Data Shared
Code Flash Only
Do Not Use
1RWHV
7LHWKH6'5$0966DQG9664WR'966
7LHWKH6'5$09&&DQG9&&4WR'9&&
6SHFLDO+DQGOLQJ,QVWUXFWLRQV)RU)%*$3DFNDJH
6SHFLDOKDQGOLQJLVUHTXLUHGIRU)ODVK0HPRU\SURGXFWVLQ)%*$SDFNDJHV
)ODVKPHPRU\GHYLFHVLQ)%*$SDFNDJHVPD\EHGDPDJHGLIH[SRVHGWRXOWUD
VRQLFFOHDQLQJPHWKRGV7KHSDFNDJHDQGRUGDWDLQWHJULW\PD\EHFRPSURPLVHG
LIWKHSDFNDJHERG\LVH[SRVHGWRWHPSHUDWXUHVDERYH°&IRUSURORQJHGSHUL
RGVRIWLPH
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
13
A d v a n c e
3.3
I n f o r m a t i o n
256MbFlash with 128Mb SDRAM
EDOO)LQH3LWFK%DOO*ULG$UUD\
7RS9LHZ%DOOV)DFLQJ'RZQ
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
DNU
DNU
DNU
DNU
DNU
DNU
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
DNU
DNU
DNU
DNU
DNU
DNU
RFU
D-CAS#
D-RAS# D-WE#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
DNU
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
DNU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
DNU
WP#
A7
D-DM0
ACC
WE#
A8
A11
RFU
DNU
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
DNU
A3
A6
D-DM1
F-RST#
RFU
A19
A12
A15
DNU
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DNU
A2
A5
A18
RDY
A20
A9
A13
A21
DNU
G1
G2
G3
G4
G6
G7
G8
G9
G10
DNU
A1
A4
A17
A23
A10
A14
A22
DNU
H1
H2
H3
H4
H7
H8
H9
H10
DNU
A0
VSS
DQ1
DQ6
RFU
A16
DNU
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
DNU
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
DNU
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DNU
RFU
DQ0
DQ10
F-VCC
D-VCC
DQ12
DQ7
VSS
DNU
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
DNU
D-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
DNU
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
DNU
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU
DNU
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
RFU
D-BA0
DNU
DNU
DNU
DNU
DNU
DNU
D-BA1
RFU
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
D-VSS
DNU
DNU
DNU
DNU
DNU
DNU
RFU
RFU
Legend
Flash/SDRAM Shared
SDRAM only
Reserved for
Future Use
Code Flash Only
Do Not Use
1RWHV
7LHWKH6'5$0966DQG9664WR'966
7LHWKH6'5$09&&DQG9&&4WR'9&&
6SHFLDO+DQGOLQJ,QVWUXFWLRQV)RU)%*$3DFNDJH
6SHFLDOKDQGOLQJLVUHTXLUHGIRU)ODVK0HPRU\SURGXFWVLQ)%*$SDFNDJHV
)ODVKPHPRU\GHYLFHVLQ)%*$SDFNDJHVPD\EHGDPDJHGLIH[SRVHGWRXOWUD
VRQLFFOHDQLQJPHWKRGV7KHSDFNDJHDQGRUGDWDLQWHJULW\PD\EHFRPSURPLVHG
LIWKHSDFNDJHERG\LVH[SRVHGWRWHPSHUDWXUHVDERYH°&IRUSURORQJHGSHUL
RGVRIWLPH
14
S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e
3.4
I n f o r m a t i o n
Lookahead Diagram on Shared Bus
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
DNU
DNU
DNU
DNU
DNU
DNU
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
DNU
D-DQS3
D-CAS#
D-RAS#
D-WE#
DNU
DNU
DNU
DNU
DNU
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
DNU
AVD#
VSS
CLK
F2-CE#
F-VCC
F-CLK#
R-OE#
F2-OE#
DNU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
DNU
WP#
D-A7
D-DM0/
R-LB#
ACC
WE#
A8
A11
F3-CE#
DNU
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
DNU
A3
A6
D-DM1/
R-UB#
F-RST#
R-CE2
A19
A12
A15
DNU
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DNU
A2
A5
A18
A20
A9
A13
A21
DNU
RDY/WAIT#
G1
G2
G3
G4
G6
G7
G8
G9
G10
DNU
A1
A4
A17
A23
A10
A14
A22
DNU
H1
H2
H3
H4
H7
H8
H9
H10
DNU
A0
VSS
DQ1
DQ6
A24
A16
DNU
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
DNU
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
R-CRE
or R-MRS
DNU
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DNU
R-CE1#
DQ0
DQ10
F-VCC
R-VCC
DQ12
DQ7
VSS
DNU
L1
L2
L2
L2
L3
L4
L5
L6
L7
L8
L9
L10
DNU
R-VCC
DQ8
DQ2
DQ11
A25
DQ5
DQ14
WP#
DNU
M1
M2
M3
M4
M5
M6
M7
M8
M9
DNU
A27
A26
VSS
F-VCC
F4-CE#
R-VCCQ
F-VCCQ
DD-CLK#
DNU
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
F-DQS0
D-BA0
DNU
DNU
DNU
DNU
DNU
DNU
D-BA1
F-DQS1
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
D-DQS0
D-VSS
DNU
DNU
DNU
DNU
DNU
DNU
D-DQS2
D-DQS1
Legend:
RFU
(Reserved for
Future Use)
Code Flash Only
MirrorBit Data
Only
Flash/Data
Shared
Flash/xRAM
Shared
pSRAM Only
xRAM Shared
SDRAM Only
M10
1RWHV
,QDGGLWLRQWREHLQJGHILQHGDV)&(%DOO&FDQDOVREHDVVLJQHGDV)&(IRUFRGHIODVKWKDW
KDVWZRFKLSHQDEOHVLJQDOV
)DQG)GHQRWH;,3&RGH)ODVKZKLOH)DQG)GHQRWH'DWD&RPSDQLRQ)ODVK
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
15
A d v a n c e
4
Input/Output Descriptions
$$
$$
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TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 12.0 mm Package
D1
A
D
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10
9
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6
E
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5
4
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10
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7
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0.15 C
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BOTTOM VIEW
0.20 C
A A2
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137X
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6
b
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
TLD 137
JEDEC
N/A
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12.00 mm x 9.00 mm
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SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.17
---
---
A2
0.81
---
0.97
D
NOTE
PROFILE
BODY SIZE
9.00 BSC.
BODY SIZE
10.40 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
14
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
137
0.35
0.40
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
12.00 BSC.
E
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BALL HEIGHT
D1
φb
1.
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6
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7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
G5,H5,H6
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3393\ 16-038.22a
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S73WS256N Based MCPs
S73WS256N_00_A3 December 16, 2005
A d v a n c e
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D1
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7
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0.20 C
A A2
A1
C
0.08 C
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6
b
137X
0.15
0.08
M C A B
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NOTES:
PACKAGE
FTF 137
JEDEC
N/A
DxE
SYMBOL
12.00 mm x 9.00 mm
PACKAGE
MIN
NOM
MAX
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---
---
1.40
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D
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NOTE
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4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BODY THICKNESS
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY SIZE
9.00 BSC.
BODY SIZE
10.40 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
14
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
n
137
BALL COUNT
0.40
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL HEIGHT
E
0.35
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2.
PROFILE
D1
Øb
1.
0.45
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
G5,H5,H6
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WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
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3532 \ 16-038.21 \ 12.13.05
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
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S29WS-N MirrorBitTM Flash Family
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Publication Number S29WS-N_m0
Revision I
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Issue Date December 3, 2005
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P r e l i m i n a r y
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Block Diagram
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Figure 9.1. S29WS-N Block Diagram
24
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
10 Additional Resources
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December 3, 2005 S29WS-N_m0_I0
25
P r e l i m i n a r y
11
Product Overview
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6HFXUHG6LOLFRQ6HFWRULV2QH7LPH3URJUDPPDEOH
Memory Map
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Table 11.1
Bank
Size
Sector
Count
Sector Size
(KB)
0%
0%
0%
0%
0%
Bank
S29WS256N Sector & Memory Address Map
Sector/
Sector Range
Address Range
6$
K±)))K
6$
K±)))K
6$
K±%)))K
6$
&K±))))K
6$WR6$
K±))))KWR)K±)))))K
6$WR6$
K±))))KWR)K±)))))K
6$WR6$
K±))))KWR)K±)))))K
6$WR6$
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6$WR6$
K±))))KWR)K±)))))K
0%
6$WR6$
K±))))KWR)K±)))))K
0%
6$WR6$
K±))))KWR)K±)))))K
0%
6$WR6$
K±))))KWR)K±)))))K
0%
6$WR6$
K±))))KWR)K±)))))K
0%
6$WR6$
K±))))KWR)K±)))))K
0%
6$WR6$
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0%
6$WR6$
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0%
6$WR6$
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0%
6$WR6$
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0%
6$WR6$
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6$WR6$
)K±)))))KWR)(K±)())))K
0%
6$
))K±)))))K
6$
))K±)))))K
6$
))K±))%)))K
6$
))&K±))))))K
Notes
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$OO.%VHFWRUV
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WKDWDUHQRWH[SOLFLWO\OLVWHGVXFKDV6$±6$KDYHVHFWRUVWDUWLQJDQGHQGLQJDGGUHVVHVWKDWIRUPWKHVDPHSDWWHUQDVDOORWKHUVHFWRUV
RIWKDWVL]H)RUH[DPSOHDOO.%VHFWRUVKDYHWKHSDWWHUQ[[K±[[))))K
26
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 11.2. S29WS128N Sector & Memory Address Map
Bank Size
0%
Sector
Count
Sector Size
(KB)
Sector/
Sector Range
Address Range
6$
K±)))K
6$
K±)))K
6$
K±%)))K
Bank
6$
&K±))))K
6$WR6$
K±))))KWRK±))))K
0%
6$WR6$
K±))))KWR)K±)))))K
0%
6$WR6$
K±))))KWRK±))))K
0%
6$WR6$
K±))))KWR)K±)))))K
0%
6$WR6$
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0%
6$WR6$
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0%
6$WR6$
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0%
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0%
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0%
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0%
6$WR6$
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0%
6$WR6$
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0%
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0%
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K±))))KWR(K±())))K
6$
)K±))))K
6$
)K±))))K
6$
)K±)%)))K
6$
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Notes
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ERWWRPRIDGGUHVVDEOHPHPRU\
$OO.%VHFWRUV
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WKDWDUHQRWH[SOLFLWO\OLVWHGVXFKDV6$±6$KDYHVHFWRUVWDUWLQJDQGHQGLQJDGGUHVVHVWKDWIRUPWKHVDPHSDWWHUQDVDOORWKHUVHFWRUV
RIWKDWVL]H)RUH[DPSOHDOO.%VHFWRUVKDYHWKHSDWWHUQ[[K±[[))))K
December 3, 2005 S29WS-N_m0_I0
27
P r e l i m i n a r y
12 Device Operations
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LQJDQGUHVHWIHDWXUHVRIWKH)ODVKGHYLFHV
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LWVHOIGRHVQRWRFFXS\DQ\DGGUHVVDEOHPHPRU\ORFDWLRQUDWKHULWLVFRPSRVHGRIODWFKHVWKDW
VWRUHWKHFRPPDQGVDORQJZLWKWKHDGGUHVVDQGGDWDLQIRUPDWLRQQHHGHGWRH[HFXWHWKHFRP
PDQG7KHFRQWHQWVRIWKHUHJLVWHUVHUYHDVLQSXWWRWKHLQWHUQDOVWDWHPDFKLQHDQGWKHVWDWH
PDFKLQHRXWSXWVGLFWDWHWKHIXQFWLRQRIWKHGHYLFH:ULWLQJLQFRUUHFWDGGUHVVDQGGDWDYDOXHVRU
ZULWLQJWKHPLQDQLPSURSHUVHTXHQFHPD\SODFHWKHGHYLFHLQDQXQNQRZQVWDWHLQZKLFKFDVH
WKHV\VWHPPXVWZULWHWKHUHVHWFRPPDQGWRUHWXUQWKHGHYLFHWRWKHUHDGLQJDUUD\GDWDPRGH
12.1
Device Operation Table
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Table 12.1
Operation
Device Operations
CE#
OE#
WE#
Addresses
DQ15–0
RESET#
CLK
AVD#
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/
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;
;
/HJHQG / /RJLF+ /RJLF; 'RQ¶W&DUH,2 ,QSXW2XWSXW
12.2
Asynchronous Read
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28
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
12.3
Page Read Mode
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JDWHGDWDWRWKHRXWSXWLQSXWVLIWKHGHYLFHLVVHOHFWHG)DVWSDJHPRGHDFFHVVHVDUHREWDLQHG
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UHTXLUHGWRUHWULHYHGDWD(DFKEDQNLVUHDG\WRUHDGDUUD\GDWDDIWHUFRPSOHWLQJDQ(PEHGGHG
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5HDGVIURPWKHPHPRU\DUUD\PD\EHSHUIRUPHGLQFRQMXQFWLRQZLWKWKH(UDVH6XVSHQGDQG3UR
JUDP6XVSHQGIHDWXUHV$IWHUWKHGHYLFHDFFHSWVDQ(UDVH6XVSHQGFRPPDQGWKHFRUUHVSRQGLQJ
EDQNHQWHUVWKHHUDVHVXVSHQGUHDGPRGHDIWHUZKLFKWKHV\VWHPFDQUHDGGDWDIURPDQ\QRQ
HUDVHVXVSHQGHGVHFWRUZLWKLQWKHVDPHEDQN7KHV\VWHPFDQUHDGDUUD\GDWDXVLQJWKHVWDQ
GDUGUHDGWLPLQJH[FHSWWKDWLILWUHDGVDWDQDGGUHVVZLWKLQHUDVHVXVSHQGHGVHFWRUVWKHGHYLFH
RXWSXWVVWDWXVGDWD$IWHUFRPSOHWLQJDSURJUDPPLQJRSHUDWLRQLQWKH(UDVH6XVSHQGPRGHWKH
V\VWHPPD\RQFHDJDLQUHDGDUUD\GDWDZLWKWKHVDPHH[FHSWLRQ$IWHUWKHGHYLFHDFFHSWVD3UR
JUDP6XVSHQGFRPPDQGWKHFRUUHVSRQGLQJEDQNHQWHUVWKHSURJUDPVXVSHQGUHDGPRGHDIWHU
ZKLFKWKHV\VWHPFDQUHDGGDWDIURPDQ\QRQSURJUDPVXVSHQGHGVHFWRUZLWKLQWKHVDPHEDQN
7KHGHDVVHUWLRQDQGUHDVVHUWLRQRI$9'FUHDWHVDQHZW$&&7KHXVHUPXVWNHHS$9'ORZ
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Table 12.2 Word Selection within a Page
12.4
:RUG
$
$
:RUG
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:RUG
:RUG
Synchronous (Burst) Read Mode & Configuration Register
:KHQDVHULHVRIDGMDFHQWDGGUHVVHVQHHGVWREHUHDGIURPWKHGHYLFHLQRUGHUIURPORZHVWWR
KLJKHVWDGGUHVVWKHV\QFKURQRXVRUEXUVWUHDGPRGHFDQEHXVHGWRVLJQLILFDQWO\UHGXFHWKH
RYHUDOOWLPHQHHGHGIRUWKHGHYLFHWRRXWSXWDUUD\GDWD$IWHUDQLQLWLDODFFHVVWLPHUHTXLUHGIRU
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December 3, 2005 S29WS-N_m0_I0
29
P r e l i m i n a r y
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3ULRUWRHQWHULQJWKHEXUVWPRGHWKHV\VWHPVKRXOGILUVWGHWHUPLQHWKHFRQILJXUDWLRQUHJLVWHU
VHWWLQJVDQGUHDGWKHFXUUHQWUHJLVWHUVHWWLQJVLIGHVLUHGYLDWKH5HDG&RQILJXUDWLRQ5HJLVWHU
FRPPDQGVHTXHQFHDQGWKHQZULWHWKHFRQILJXUDWLRQUHJLVWHUFRPPDQGVHTXHQFH6HH6HFWLRQ
&RQILJXUDWLRQ5HJLVWHUDQG7DEOH 0HPRU\$UUD\&RPPDQGVIRUIXUWKHUGHWDLOV
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(CR15 = 1)
Synchronous Read
Mode Only
Figure 12.1. Synchronous/Asynchronous State Diagram
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WKHVWDUWLQJDGGUHVVLVRQHWZRRUWKUHHORFDWLRQVDERYHWKHGLYLVLEOHE\IRXUDGGUHVVLH
ZKHUH$>@LVRU
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RIWKHGHYLFH2QHDGGLWLRQDOZDLWVWDWHPXVWEHLQVHUWHGZKHQFURVVLQJWKLVERXQGDU\LIWKH
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„ FORFNIUHTXHQF\WKHVSHHGDWZKLFKWKHGHYLFHLVH[SHFWHGWREXUVWGDWD+LJKHUVSHHGV
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30
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 12.3 Address Latency (S29WS256N)
:RUG
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Table 12.4 Address Latency (S29WS128N)
:RUG
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ZV
ZV
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ZV
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'
'
'
'
ZV
'
ZV
ZV
ZV
'
'
'
'
'
'
'
'
'
'
'
Table 12.5 Address/Boundary Crossing Latency (S29WS256N @ 80MHz)
:RUG
:DLW6WDWHV
&\FOH
ZV
'
'
'
'
ZV
ZV
'
'
'
ZV
'
'
'
ZV
ZV
ZV
'
'
'
ZV
'
'
ZV
ZV
ZV
ZV
'
'
'
ZV
'
ZV
ZV
ZV
ZV
ZV
'
'
'
Table 12.6 Address/Boundary Crossing Latency (S29WS256N @ 66 MHz)
:RUG
:DLW6WDWHV
&\FOH
ZV
'
'
'
'
ZV
'
'
'
'
ZV
'
'
'
ZV
ZV
'
'
'
'
ZV
'
'
ZV
ZV
ZV
'
'
'
'
ZV
'
ZV
ZV
ZV
ZV
'
'
'
'
Table 12.7 Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
:RUG
:DLW6WDWHV
&\FOH
ZV
'
'
'
'
'
'
'
'
'
ZV
'
'
'
ZV
'
'
'
'
'
ZV
'
'
ZV
ZV
'
'
'
'
'
ZV
'
ZV
ZV
ZV
'
'
'
'
'
Table 12.8 Address/Boundary Crossing Latency (S29WS128N)
:RUG
:DLW6WDWHV
ZV
'
'
'
'
ZV
'
'
'
'
ZV
'
'
'
ZV
ZV
'
'
'
'
ZV
'
'
ZV
ZV
ZV
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'
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ZV
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ZV
ZV
ZV
ZV
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'
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December 3, 2005 S29WS-N_m0_I0
&\FOH
31
P r e l i m i n a r y
Note: Setup Configuration Register parameters
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Command Cycle
CR = Configuration Register Bits CR15-CR0
Load Initial Address
Address = RA
RA = Read Address
Read Initial Data
RD = DQ[15:0]
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
RD = Read Data
5HIHUWRWKH/DWHQF\WDEOHV
Read Next Data
RD = DQ[15:0]
No
Delay X Clocks
Yes
Crossing
Boundary?
No
End of Data?
Yes
Completed
Figure 12.2.
Synchronous Read
&RQWLQXRXV%XUVW5HDG0RGH
,QWKHFRQWLQXRXVEXUVWUHDGPRGHWKHGHYLFHRXWSXWVVHTXHQWLDOEXUVWGDWDIURPWKHVWDUWLQJ
DGGUHVVJLYHQDQGWKHQZUDSDURXQGWRDGGUHVVKZKHQLWUHDFKHVWKHKLJKHVWDGGUHVV
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5(6(7 9,/&RQWLQXRXVEXUVWPRGHFDQDOVREHDERUWHGE\DVVHUWLQJ$9'ORZDQGSURYLGLQJ
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,IWKHDGGUHVVEHLQJUHDGFURVVHVDZRUGOLQHERXQGDU\DVPHQWLRQHGDERYHDQGWKHVXE
VHTXHQWZRUGOLQHLVQRWEHLQJSURJUDPPHGRUHUDVHGDGGLWLRQDOODWHQF\F\FOHVDUHUHTXLUHGDV
UHIOHFWHGE\WKHFRQILJXUDWLRQUHJLVWHUWDEOH7DEOH
,IWKHDGGUHVVFURVVHVDEDQNERXQGDU\ZKLOHWKHVXEVHTXHQWEDQNLVSURJUDPPLQJRUHUDVLQJ
WKHGHYLFHSURYLGHVUHDGVWDWXVLQIRUPDWLRQDQGWKHFORFNLVLJQRUHG8SRQFRPSOHWLRQRIVWDWXV
UHDGRUSURJUDPRUHUDVHRSHUDWLRQWKHKRVWFDQUHVWDUWDEXUVWUHDGRSHUDWLRQXVLQJDQHZDG
GUHVVDQG$9'SXOVH
32
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
:RUG/LQHDU%XUVW5HDGZLWK:UDS$URXQG
,QDOLQHDUEXUVWUHDGRSHUDWLRQDIL[HGQXPEHURIZRUGVRUZRUGVDUHUHDGIURP
FRQVHFXWLYHDGGUHVVHVWKDWDUHGHWHUPLQHGE\WKHJURXSZLWKLQZKLFKWKHVWDUWLQJDGGUHVVIDOOV
7KHJURXSVDUHVL]HGDFFRUGLQJWRWKHQXPEHURIZRUGVUHDGLQDVLQJOHEXUVWVHTXHQFHIRUD
JLYHQPRGHVHH7DEOH
)RUH[DPSOHLIWKHVWDUWLQJDGGUHVVLQWKHZRUGPRGHLV&KWKHDGGUHVVUDQJHWREHUHDG
ZRXOGEH)KDQGWKHEXUVWVHTXHQFHZRXOGEH&'()$%K7KXVWKHGH
YLFHRXWSXWVDOOZRUGVLQWKDWEXUVWDGGUHVVJURXSXQWLODOOZRUGDUHUHDGUHJDUGOHVVRIZKHUH
WKHVWDUWLQJDGGUHVVRFFXUVLQWKHDGGUHVVJURXSDQGWKHQWHUPLQDWHVWKHEXUVWUHDG
,QDVLPLODUIDVKLRQWKHZRUGDQGZRUG/LQHDU:UDSPRGHVEHJLQWKHLUEXUVWVHTXHQFHRQ
WKHVWDUWLQJDGGUHVVSURYLGHGWRWKHGHYLFHWKHQZUDSEDFNWRWKHILUVWDGGUHVVLQWKHVHOHFWHG
DGGUHVVJURXS
1RWHWKDWLQWKLVPRGHWKHDGGUHVVSRLQWHUGRHVQRWFURVVWKHERXQGDU\WKDWRFFXUVHYHU\
ZRUGVWKXVQRDGGLWLRQDOZDLWVWDWHVDUHLQVHUWHGGXHWRERXQGDU\FURVVLQJ
Table 12.9 Burst Address Groups
Mode
Group Size
Group Address Ranges
ZRUG
ZRUGV
K)KK
ZRUG
ZRUGV
)K)K)K
ZRUG
ZRUGV
)K)K)K
:RUG/LQHDU%XUVWZLWKRXW:UDS$URXQG
,IZUDSDURXQGLVQRWHQDEOHGIRUOLQHDUEXUVWUHDGRSHUDWLRQVWKHZRUGZRUGRUZRUG
EXUVWH[HFXWHVXSWRWKHPD[LPXPPHPRU\DGGUHVVRIWKHVHOHFWHGQXPEHURIZRUGV7KHEXUVW
VWRSVDIWHURUDGGUHVVHVDQGGRHVQRWZUDSDURXQGWRWKHILUVWDGGUHVVRIWKHVHOHFWHG
JURXS
)RUH[DPSOHLIWKHVWDUWLQJDGGUHVVLQWKHZRUGPRGHLV&KWKHDGGUHVVUDQJHWREHUHDG
ZRXOGEHKDQGWKHEXUVWVHTXHQFHZRXOGEH&'()KLIZUDSDURXQG
LVQRWHQDEOHG7KHQH[WDGGUHVVWREHUHDGUHTXLUHVDQHZDGGUHVVDQG$9'SXOVH1RWHWKDW
LQWKLVEXUVWUHDGPRGHWKHDGGUHVVSRLQWHUPD\FURVVWKHERXQGDU\WKDWRFFXUVHYHU\
ZRUGVZKLFKZLOOLQFXUWKHDGGLWLRQDOERXQGDU\FURVVLQJZDLWVWDWH
&RQILJXUDWLRQ5HJLVWHU
7KHFRQILJXUDWLRQUHJLVWHUVHWVYDULRXVRSHUDWLRQDOSDUDPHWHUVDVVRFLDWHGZLWKEXUVWPRGH8SRQ
SRZHUXSRUKDUGZDUHUHVHWWKHGHYLFHGHIDXOWVWRWKHDV\QFKURQRXVUHDGPRGHDQGWKHFRQ
ILJXUDWLRQUHJLVWHUVHWWLQJVDUHLQWKHLUGHIDXOWVWDWH 7KHKRVWV\VWHPVKRXOGGHWHUPLQHWKH
SURSHUVHWWLQJVIRUWKHHQWLUHFRQILJXUDWLRQUHJLVWHUDQGWKHQH[HFXWHWKH6HW&RQILJXUDWLRQ5HJ
LVWHUFRPPDQGVHTXHQFHEHIRUHDWWHPSWLQJEXUVWRSHUDWLRQV7KHFRQILJXUDWLRQUHJLVWHULVQRW
UHVHWDIWHUGHDVVHUWLQJ&(7KH&RQILJXUDWLRQ5HJLVWHUFDQDOVREHUHDGXVLQJDFRPPDQGVH
TXHQFHVHH7DEOH7KHIROORZLQJOLVWGHVFULEHVWKHUHJLVWHUVHWWLQJV
December 3, 2005 S29WS-N_m0_I0
33
P r e l i m i n a r y
Table 12.10 Configuration Register
&5%LW
&5
&5
)XQFWLRQ
6HW'HYLFH5HDG
0RGH
6:61DWRU:DLW6WDWHVHWWLQJ
$OORWKHUV
6:61
6:61
6:61
3URJUDPPDEOH
:DLW6WDWH
&5
&5
6\QFKURQRXV5HDG%XUVW0RGH(QDEOHG
$V\QFKURQRXV5HDG0RGHGHIDXOW(QDEOHG
5HVHUYHG
&5
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6HWWLQJV%LQDU\
6:61
0+]
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0+]
6:61
6:61
5'<3RODULW\
'DWDYDOLGRQWKDFWLYH&/.HGJHDIWHUDGGUHVVHV
ODWFKHG
'DWDYDOLGRQWKDFWLYH&/.HGJHDIWHUDGGUHVVHV
ODWFKHG
'DWDYDOLGRQWKDFWLYH&/.HGJHDIWHUDGGUHVVHV
ODWFKHGGHIDXOW
5HVHUYHG
5HVHUYHG
,QVHUWVZDLWVWDWHVEHIRUHLQLWLDOGDWDLVDYDLODEOH6HWWLQJ
JUHDWHUQXPEHURIZDLWVWDWHVEHIRUHLQLWLDOGDWDUHGXFHV
ODWHQF\DIWHULQLWLDOGDWD
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&5
5HVHUYHG
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5HIHUWR6\QFKURQRXV%XUVW5HDGWLPLQJGLDJUDPV
&RQILJXUDWLRQ5HJLVWHULVLQWKHGHIDXOWVWDWHXSRQSRZHUXSRUKDUGZDUHUHVHW
5HDGLQJWKH&RQILJXUDWLRQ7DEOH7KHFRQILJXUDWLRQUHJLVWHUFDQEHUHDGZLWKDIRXUF\FOHFRP
PDQGVHTXHQFH6HH7DEOHIRUVHTXHQFHGHWDLOV$VRIWZDUHUHVHWFRPPDQGLVUHTXLUHGDIWHU
UHDGLQJRUVHWWLQJWKHFRQILJXUDWLRQUHJLVWHUWRVHWWKHGHYLFHLQWRWKHFRUUHFWVWDWH
34
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
12.5
Autoselect
7KH$XWRVHOHFWLVXVHGIRUPDQXIDFWXUHU,''HYLFHLGHQWLILFDWLRQDQGVHFWRUSURWHFWLRQLQIRUPD
WLRQ7KLV PRGHLVSULPDULO\ LQWHQGHGIRU SURJUDPPLQJ HTXLSPHQWWRDXWRPDWLFDOO\ PDWFKD
GHYLFHZLWKLWVFRUUHVSRQGLQJSURJUDPPLQJDOJRULWKP7KH$XWRVHOHFWFRGHVFDQDOVREHDF
FHVVHGLQV\VWHP:KHQYHULI\LQJ VHFWRUSURWHFWLRQWKHVHFWRUDGGUHVVPXVWDSSHDURQWKH
DSSURSULDWHKLJKHVWRUGHUDGGUHVVELWVVHH7DEOH7KHUHPDLQLQJDGGUHVVELWVDUHGRQ
W
FDUH7KHPRVWVLJQLILFDQWIRXUELWVRIWKHDGGUHVVGXULQJWKHWKLUGZULWHF\FOHVHOHFWVWKHEDQN
IURPZKLFKWKH$XWRVHOHFWFRGHVDUHUHDGE\WKHKRVW$OORWKHUEDQNVFDQEHDFFHVVHGQRUPDOO\
IRUGDWDUHDGZLWKRXWH[LWLQJWKH$XWRVHOHFWPRGH
„
7RDFFHVVWKH$XWRVHOHFWFRGHVWKHKRVWV\VWHPPXVWLVVXHWKH$XWRVHOHFWFRPPDQG
„
7KH$XWRVHOHFWFRPPDQGVHTXHQFHPD\EHZULWWHQWRDQDGGUHVVZLWKLQDEDQNWKDWLVHLWKHU
LQWKHUHDGRUHUDVHVXVSHQGUHDGPRGH
„
7KH$XWRVHOHFWFRPPDQGPD\QRWEHZULWWHQZKLOHWKHGHYLFHLVDFWLYHO\SURJUDPPLQJRU
HUDVLQJ$XWRVHOHFWGRHVQRWVXSSRUWVLPXOWDQHRXVRSHUDWLRQVRUEXUVWPRGH
„
7KHV\VWHPPXVWZULWHWKHUHVHWFRPPDQGWRUHWXUQWRWKHUHDGPRGHRUHUDVHVXVSHQG
UHDGPRGHLIWKHEDQNZDVSUHYLRXVO\LQ(UDVH6XVSHQG
6HH7DEOHIRUFRPPDQGVHTXHQFHGHWDLOV
Table 12.11 Autoselect Addresses
Description
Address
Read Data
0DQXIDFWXUHU,'
%$K
K
'HYLFH,':RUG
%$K
(K
'HYLFH,':RUG
%$(K
'HYLFH,':RUG
%$)K
:61
:61
'4'4 5HVHUYHG
'4)DFWRU\/RFN%LW /RFNHG 1RW/RFNHG
'4&XVWRPHU/RFN%LW /RFNHG 1RW/RFNHG
'4+DQGVKDNH%LW 5HVHUYHG 6WDQGDUG+DQGVKDNH
,QGLFDWRU%LWV
6HH1RWH
%$K
'4'4:33URWHFWLRQ%RRW&RGH :33URWHFWVERWK7RS%RRWDQG
%RWWRP%RRW6HFWRUV 5HVHUYHG
'4 5HVHUYHG
'4'<%3RZHUXS6WDWH>/RFN5HJLVWHU'4@ 8QORFNHGXVHURSWLRQ
/RFNHGGHIDXOW
'433%(UDVHDELOLW\>/RFN5HJLVWHU'4@ (UDVHDOORZHG
(UDVHGLVDEOHG
6HFWRU%ORFN/RFN
8QORFN
6$K
K /RFNHGK 8QORFNHG
1RWH)RU:61DQG:6'4DQG'4DUHUHVHUYHG
December 3, 2005 S29WS-N_m0_I0
35
P r e l i m i n a r y
Software Functions and Sample Code
Table 12.12 Autoselect Entry
//')XQFWLRQ OOGB$XWRVHOHFW(QWU\&PG
Cycle
Operation
Byte Address
Word Address
Data
8QORFN&\FOH
:ULWH
%$[$$$K
%$[K
[$$K
8QORFN&\FOH
:ULWH
%$[K
%$[$$K
[K
$XWRVHOHFW&RPPDQG
:ULWH
%$[$$$K
%$[K
[K
Table 12.13 Autoselect Exit
//')XQFWLRQ OOGB$XWRVHOHFW([LW&PG
Cycle
Operation
Byte Address
Word Address
Data
8QORFN&\FOH
:ULWH
EDVH;;;K
EDVH;;;K
[)K
1RWHV
$Q\RIIVHWZLWKLQWKHGHYLFHZRUNV
%$ %DQN$GGUHVV7KHEDQNDGGUHVVLVUHTXLUHG
EDVH EDVHDGGUHVV
7KHIROORZLQJLVD&VRXUFHFRGHH[DPSOHRIXVLQJWKHDXWRVHOHFWIXQFWLRQWRUHDGWKHPDQXIDF
WXUHU,'5HIHUWRWKH6SDQVLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQG
ZZZIXMLWVXFRPIRU JHQHUDOLQIRUPDWLRQRQ 6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQW
JXLGHOLQHV
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/*
Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
36
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
12.6
Program/Erase Operations
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PXVWGULYH$9'DQG&(WR9,/DQG2(WR9,+ZKHQSURYLGLQJDQDGGUHVVWRWKHGHYLFHDQG
GULYH:(DQG&(WR9,/DQG2(WR9,+ZKHQZULWLQJFRPPDQGVRUSURJUDPPLQJGDWD
$GGUHVVHVDUHODWFKHGRQWKHODVWIDOOLQJHGJHRI:(RU&(ZKLOHGDWDLVODWFKHGRQWKHVW
ULVLQJHGJHRI:(RU&(
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KDOWLQJDQ\IXUWKHURSHUDWLRQDQGUHTXLULQJDUHVHWFRPPDQG$VXFFHHGLQJUHDGVKRZV
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„
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VHTXHQFHVKRXOGEHUHLQLWLDWHGRQFHWKHGHYLFHKDVUHWXUQHGWRWKHUHDGPRGHWRHQVXUH
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FRPPDQGZULWHF\FOHVDUHXVHGWRSURJUDPDQLQGLYLGXDO)ODVKDGGUHVV7KHGDWDIRUWKLVSUR
JUDPPLQJRSHUDWLRQFRXOGEHRUELWVZLGH:KLOHWKLVPHWKRGLVVXSSRUWHGE\DOO
6SDQVLRQGHYLFHVLQJHQHUDOLWLVQRWUHFRPPHQGHGIRUGHYLFHVWKDWVXSSRUW:ULWH%XIIHU3UR
JUDPPLQJ6HH7DEOHIRUWKHUHTXLUHGEXVF\FOHVDQG)LJXUHIRUWKHIORZFKDUW
:KHQWKH(PEHGGHG3URJUDPDOJRULWKPLVFRPSOHWHWKHGHYLFHWKHQUHWXUQVWRWKHUHDGPRGH
DQGDGGUHVVHVDUHQRORQJHUODWFKHG7KHV\VWHPFDQGHWHUPLQHWKHVWDWXVRIWKHSURJUDPRS
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WKHVHVWDWXVELWV
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December 3, 2005 S29WS-N_m0_I0
37
P r e l i m i n a r y
„
$KDUGZDUHUHVHWLPPHGLDWHO\WHUPLQDWHVWKHSURJUDPRSHUDWLRQ7KHSURJUDPFRPPDQGVH
TXHQFHVKRXOGEHUHLQLWLDWHGRQFHWKHGHYLFHKDVUHWXUQHGWRWKHUHDGPRGHWRHQVXUHGDWD
LQWHJULW\
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Polling Status
= Busy?
Yes
No
Yes
Polling Status
= Done?
No
PASS. Device is in
read mode.
Figure 12.3.
38
Error condition
(Exceeded Timing Limits)
FAIL. Issue reset command
to return to read array mode.
Single Word Program
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Software Functions and Sample Code
Table 12.14. Single Word Program
//')XQFWLRQ OOGB3URJUDP&PG
Cycle
Operation
Byte Address
Word Address
Data
8QORFN&\FOH
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN&\FOH
:ULWH
%DVHK
%DVH$$K
K
3URJUDP6HWXS
:ULWH
%DVH$$$K
%DVHK
$K
3URJUDP
:ULWH
:RUG$GGUHVV
:RUG$GGUHVV
'DWD:RUG
1RWH%DVH %DVH$GGUHVV
7KHIROORZLQJLVD&VRXUFHFRGHH[DPSOHRIXVLQJWKHVLQJOHZRUGSURJUDPIXQFWLRQ5HIHUWRWKH
6SDQVLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRU
JHQHUDOLQIRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 )
*( (UINT16 *)base_addr + 0x2AA )
*( (UINT16 *)base_addr + 0x555 )
*( (UINT16 *)pa )
/* Poll for program completion */
=
=
=
=
0x00AA;
0x0055;
0x00A0;
data;
/*
/*
/*
/*
write
write
write
write
unlock cycle 1
unlock cycle 2
program setup command
data to be programmed
*/
*/
*/
*/
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:ULWHEXIIHUSURJUDPPLQJLVDOORZHGLQDQ\VHTXHQFHRIPHPRU\RUDGGUHVVORFDWLRQV7KHVH
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40
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Software Functions and Sample Code
Table 12.15. Write Buffer Program
//')XQFWLRQV8VHG OOGB:ULWH7R%XIIHU&PGOOGB3URJUDP%XIIHU7R)ODVK&PG
Cycle
Description
Operation
Byte Address
Word Address
Data
8QORFN
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN
:ULWH
%DVHK
%DVH$$K
K
:ULWH%XIIHU/RDG&RPPDQG
:ULWH
3URJUDP$GGUHVV
K
:ULWH:RUG&RXQW
:ULWH
3URJUDP$GGUHVV
:RUG&RXQW1±K
1XPEHURIZRUGV1ORDGHGLQWRWKHZULWHEXIIHUFDQEHIURPWRZRUGV
WR
/RDG%XIIHU:RUG1
:ULWH
3URJUDP$GGUHVV:RUG1
:RUG1
/DVW
:ULWH%XIIHUWR)ODVK
:ULWH
6HFWRU$GGUHVV
K
1RWHV
%DVH %DVH$GGUHVV
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WKHKLJKHVWQXPEHURIZRUGV1ZRUGVSRVVLEOH
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6SDQVLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRU
JHQHUDOLQIRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
All addresses to be written to the flash in
*/
/*
one operation must be within the same flash
*/
/*
page. A flash page begins at addresses
*/
/*
evenly divisible by 0x20.
*/
UINT16 *src = source_of_data;
/* address of source data
*/
UINT16 *dst = destination_of_data;
/* flash destination address
*/
UINT16 wc
= words_to_program -1;
/* word count (minus 1)
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
/* write unlock cycle 1
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)sector_address )
= 0x0025;
/* write write buffer load command */
*( (UINT16 *)sector_address )
= wc;
/* write word count (minus 1)
*/
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++;
/* increment destination pointer
*/
src++;
/* increment source pointer
*/
if (wc == 0) goto confirm
/* done when word count equals zero */
wc--;
/* decrement word count
*/
goto loop;
/* do it again
*/
confirm:
*( (UINT16 *)sector_address )
= 0x0029;
/* write confirm command
*/
/* poll for completion */
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
December 3, 2005 S29WS-N_m0_I0
/* write unlock cycle 1
/* write unlock cycle 2
/* write buffer abort reset
*/
*/
*/
41
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
wc = number of words – 1
Yes
Confirm command:
SA = 0x29h
wc = 0?
No
Wait 4 µs
(Recommended)
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Write Buffer
Abort?
Polling Status
= Done?
No
FAIL. Issue reset command
to return to read array mode.
Yes
No
No
Error?
Yes
RESET. Issue Write Buffer
Abort Reset Command
Figure 12.4.
PASS. Device is in
read mode.
Write Buffer Programming Operation
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42
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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EHIURPRQHVHFWRUWRDOOVHFWRUV7KHWLPHEHWZHHQWKHVHDGGLWLRQDOF\FOHVPXVWEHOHVVWKDQ
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QRWEHDFFHSWHG$Q\FRPPDQGRWKHUWKDQ6HFWRU(UDVHRU(UDVH6XVSHQGGXULQJWKHWLPHRXW
SHULRGUHVHWVWKDWEDQNWRWKHUHDGPRGH7KHV\VWHPFDQPRQLWRU'4WRGHWHUPLQHLIWKHVHFWRU
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Software Functions and Sample Code
Table 12.16. Sector Erase
//')XQFWLRQ OOGB6HFWRU(UDVH&PG
Cycle
Description
Operation
Byte Address
Word Address
Data
8QORFN
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN
:ULWH
%DVHK
%DVH$$K
K
6HWXS&RPPDQG
:ULWH
%DVH$$$K
%DVHK
K
8QORFN
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN
:ULWH
%DVHK
%DVH$$K
K
6HFWRU(UDVH&RPPDQG
:ULWH
6HFWRU$GGUHVV
6HFWRU$GGUHVV
K
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7KHIROORZLQJLVD&VRXUFHFRGHH[DPSOHRIXVLQJWKHVHFWRUHUDVHIXQFWLRQ5HIHUWRWKH6SDQVLRQ
/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRUJHQHUDOLQ
IRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Sector Erase Command
*( (UINT16 *)base_addr + 0x555
*( (UINT16 *)base_addr + 0x2AA
*( (UINT16 *)base_addr + 0x555
*( (UINT16 *)base_addr + 0x555
*( (UINT16 *)base_addr + 0x2AA
*( (UINT16 *)sector_address )
December 3, 2005 S29WS-N_m0_I0
*/
) =
) =
) =
) =
) =
=
0x00AA;
0x0055;
0x0080;
0x00AA;
0x0055;
0x0030;
/*
/*
/*
/*
/*
/*
write
write
write
write
write
write
unlock cycle 1
*/
unlock cycle 2
*/
setup command
*/
additional unlock cycle 1 */
additional unlock cycle 2 */
sector erase command
*/
43
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
Sectors?
No
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
No
Yes
Poll DQ3.
DQ3 = 1?
Last Sector
Selected?
• No limit on number of sectors
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
No
Yes
Wait 4 µs
(Recommended)
Perform Write Operation
Status Algorithm
VHH)LJXUH
Yes
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Done?
No
DQ5 = 1?
No
Error condition (Exceeded Timing Limits)
Yes
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
1RWHV
6HH7DEOHIRUHUDVHFRPPDQGVHTXHQFH
6HHWKHVHFWLRQRQ'4IRULQIRUPDWLRQRQWKHVHFWRUHUDVHWLPHRXW
Figure 12.5.
44
Sector Erase Operation
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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GUHVVHVDUHQRORQJHUODWFKHG7KHV\VWHPFDQGHWHUPLQHWKHVWDWXVRIWKHHUDVHRSHUDWLRQE\
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VHTXHQFHVKRXOGEHUHLQLWLDWHGRQFHWKDWEDQNKDVUHWXUQHGWRUHDGLQJDUUD\GDWDWRHQVXUHGDWD
LQWHJULW\
Software Functions and Sample Code
Table 12.17.
Chip Erase
//')XQFWLRQ OOGB&KLS(UDVH&PG
Cycle
Description
Operation
Byte Address
Word Address
Data
8QORFN
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN
:ULWH
%DVHK
%DVH$$K
K
6HWXS&RPPDQG
:ULWH
%DVH$$$K
%DVHK
K
8QORFN
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN
:ULWH
%DVHK
%DVH$$K
K
&KLS(UDVH&RPPDQG
:ULWH
%DVH$$$K
%DVHK
K
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/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRUJHQHUDOLQ
IRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 )
*( (UINT16 *)base_addr + 0x2AA )
*( (UINT16 *)base_addr + 0x555 )
*( (UINT16 *)base_addr + 0x555 )
*( (UINT16 *)base_addr + 0x2AA )
*( (UINT16 *)base_addr + 0x000 )
=
=
=
=
=
=
0x00AA;
0x0055;
0x0080;
0x00AA;
0x0055;
0x0010;
/*
/*
/*
/*
/*
/*
write
write
write
write
write
write
unlock cycle 1
*/
unlock cycle 2
*/
setup command
*/
additional unlock cycle 1 */
additional unlock cycle 2 */
chip erase command
*/
(UDVH6XVSHQG(UDVH5HVXPH&RPPDQGV
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LPXPW6($ WLPHRXWSHULRG GXULQJWKHVHFWRUHUDVHFRPPDQGVHTXHQFH7KH(UDVH6XVSHQG
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December 3, 2005 S29WS-N_m0_I0
45
P r e l i m i n a r y
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Software Functions and Sample Code
Table 12.18. Erase Suspend
//')XQFWLRQ OOGB(UDVH6XVSHQG&PG
Cycle
Operation
Byte Address
Word Address
Data
:ULWH
%DQN$GGUHVV
%DQN$GGUHVV
%K
7KHIROORZLQJLVD&VRXUFHFRGHH[DPSOHRIXVLQJWKHHUDVHVXVSHQGIXQFWLRQ5HIHUWRWKH6SDQ
VLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRUJHQHUDO
LQIRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
/* write suspend command
Table 12.19.
*/
Erase Resume
//')XQFWLRQ OOGB(UDVH5HVXPH&PG
Cycle
Operation
Byte Address
Word Address
Data
:ULWH
%DQN$GGUHVV
%DQN$GGUHVV
K
7KHIROORZLQJLVD&VRXUFHFRGHH[DPSOHRIXVLQJWKHHUDVHUHVXPHIXQFWLRQ5HIHUWRWKH6SDQ
VLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRUJHQHUDO
LQIRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
/* The flash needs adequate time in the resume state */
46
*/
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
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FRGHVDUHQRWVWRUHGLQWKHPHPRU\DUUD\:KHQWKHGHYLFHH[LWVWKH$XWRVHOHFWPRGHWKHGHYLFH
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Software Functions and Sample Code
Table 12.20.
Program Suspend
//')XQFWLRQ OOGB3URJUDP6XVSHQG&PG
Cycle
Operation
Byte Address
Word Address
Data
:ULWH
%DQN$GGUHVV
%DQN$GGUHVV
%K
7KHIROORZLQJLVD&VRXUFHFRGHH[DPSOHRIXVLQJWKHSURJUDPVXVSHQGIXQFWLRQ5HIHUWRWKH
6SDQVLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRU
JHQHUDOLQIRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
/* write suspend command
*/
Table 12.21. Program Resume
//')XQFWLRQ OOGB3URJUDP5HVXPH&PG
Cycle
Operation
Byte Address
Word Address
Data
:ULWH
%DQN$GGUHVV
%DQN$GGUHVV
K
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6SDQVLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRU
JHQHUDOLQIRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
December 3, 2005 S29WS-N_m0_I0
/* write resume command
*/
47
P r e l i m i n a r y
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Software Functions and Sample Code
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Table 12.22.
Unlock Bypass Entry
//')XQFWLRQ OOGB8QORFN%\SDVV(QWU\&PG
48
Cycle
Description
Operation
Byte Address
Word Address
Data
8QORFN
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN
:ULWH
%DVHK
%DVH$$K
K
(QWU\&RPPDQG
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S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
/* Example: Unlock Bypass Entry Command
*/
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
/* write unlock
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
/* write unlock
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
/* write unlock
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
cycle 1
cycle 2
bypass command
*/
*/
*/
*/
*/
*/
*/
*/
Table 12.23. Unlock Bypass Program
//')XQFWLRQ OOGB8QORFN%\SDVV3URJUDP&PG
Cycle
Description
Operation
Byte Address
Word Address
Data
3URJUDP6HWXS&RPPDQG
:ULWH
%DVH[[[K
%DVH[[[K
$K
3URJUDP&RPPDQG
:ULWH
3URJUDP$GGUHVV
3URJUDP$GGUHVV
3URJUDP'DWD
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode!
*/
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
*( (UINT16 *)pa )
= data;
/* Poll until done or error.
*/
/* If done and more to program, */
/* do above two cycles again.
*/
/* write program setup command
/* write data to be programmed
*/
*/
Table 12.24. Unlock Bypass Reset
//')XQFWLRQ OOGB8QORFN%\SDVV5HVHW&PG
Cycle
Description
Operation
Byte Address
Word Address
Data
5HVHW&\FOH
:ULWH
%DVH[[[K
%DVH[[[K
K
5HVHW&\FOH
:ULWH
%DVH[[[K
%DVH[[[K
K
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
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,IDSURJUDPDGGUHVVIDOOVZLWKLQDSURWHFWHGVHFWRU'DWDSROOLQJRQ'4LVDFWLYHIRUDSSUR[L
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GHG(UDVHDOJRULWKPLVFRPSOHWHRULIWKHEDQNHQWHUVWKH(UDVH6XVSHQGPRGH'DWD3ROOLQJ
SURGXFHVD³´RQ'47KHV\VWHPPXVWSURYLGHDQDGGUHVVZLWKLQDQ\RIWKHVHFWRUVVHOHFWHG
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December 3, 2005 S29WS-N_m0_I0
49
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,IQRWDOOVHOHFWHGVHFWRUVDUHSURWHFWHGWKH(PEHGGHG(UDVHDOJRULWKPHUDVHVWKHXQSURWHFWHG
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-XVWSULRUWRWKHFRPSOHWLRQRIDQ(PEHGGHG3URJUDPRU(UDVHRSHUDWLRQ'4PD\FKDQJHDV\Q
FKURQRXVO\ZLWK'4'4ZKLOH2XWSXW(QDEOH2(LVDVVHUWHGORZ7KDWLVWKHGHYLFHPD\
FKDQJHIURPSURYLGLQJVWDWXVLQIRUPDWLRQWRYDOLGGDWDRQ'4'HSHQGLQJRQZKHQWKHV\VWHP
VDPSOHVWKH'4RXWSXWLWPD\UHDGWKHVWDWXVRUYDOLGGDWD(YHQLIWKHGHYLFHKDVFRPSOHWHG
WKHSURJUDPRUHUDVHRSHUDWLRQDQG'4KDVYDOLGGDWDWKHGDWDRXWSXWVRQ'4'4PD\EH
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6HHWKHIROORZLQJIRUPRUHLQIRUPDWLRQ7DEOH:ULWH2SHUDWLRQ6WDWXVVKRZVWKHRXWSXWV
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50
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
NO
Read 1
DQ5=1?
YES
YES
Read 2
Read3=
valid data?
NO
NO
Read 3
Read 2
YES
Program
Operation
Failed
Write Buffer
Programming?
YES
NO
Programming
Operation?
Read 3
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 1)
(Note 4)
(Note 1)
YES
DQ6
toggling?
DQ6
toggling?
TIMEOUT
NO
YES
DEVICE
ERROR
NO
Read3
DQ1=1?
(Note 2)
NO
(Note 5)
YES
Device BUSY,
Re-Poll
DQ2
toggling?
YES
NO
Read 2
Device BUSY,
Re-Poll
Erase
Operation
Complete
Read 3
Read3
DQ1=1
AND DQ7 ≠
Valid Data?
YES
Device in
Erase/Suspend
Mode
Write Buffer
Operation
Failed
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Device BUSY,
Re-Poll
Figure 12.6.
December 3, 2005 S29WS-N_m0_I0
Write Operation Status Flowchart
51
P r e l i m i n a r y
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,IDSURJUDPDGGUHVVIDOOVZLWKLQDSURWHFWHGVHFWRU'4WRJJOHVIRUDSSUR[LPDWHO\W3$3DIWHUWKH
SURJUDPFRPPDQGVHTXHQFHLVZULWWHQWKHQUHWXUQVWRUHDGLQJDUUD\GDWD
'4DOVRWRJJOHVGXULQJWKHHUDVHVXVSHQGSURJUDPPRGHDQGVWRSVWRJJOLQJRQFHWKH(PEHG
GHG3URJUDP$OJRULWKPLVFRPSOHWH
6HHWKHIROORZLQJIRUDGGLWLRQDOLQIRUPDWLRQ)LJXUH:ULWH2SHUDWLRQ6WDWXV)ORZFKDUW)LJ
XUH7RJJOH%LW7LPLQJV'XULQJ (PEHGGHG $OJRULWKPDQG7DEOHVDQG
7RJJOH%LW,RQ'4UHTXLUHVHLWKHU2(RU&(WREHGHDVVHUWHGDQGUHDVVHUWHGWRVKRZWKH
FKDQJHLQVWDWH
'47RJJOH%LW,,7KH³7RJJOH%LW,,´RQ'4ZKHQXVHGZLWK'4LQGLFDWHVZKHWKHUDSDU
WLFXODU VHFWRU LV DFWLYHO\ HUDVLQJ WKDW LV WKH (PEHGGHG(UDVH DOJRULWKPLV LQ SURJUHVV RU
ZKHWKHUWKDWVHFWRULVHUDVHVXVSHQGHG7RJJOH%LW,,LVYDOLGDIWHUWKHULVLQJHGJHRIWKHILQDO
:(SXOVHLQWKHFRPPDQGVHTXHQFH'4WRJJOHVZKHQWKHV\VWHPUHDGVDWDGGUHVVHVZLWKLQ
WKRVHVHFWRUVWKDWKDYHEHHQVHOHFWHGIRUHUDVXUH%XW'4FDQQRWGLVWLQJXLVKZKHWKHUWKHVHFWRU
LVDFWLYHO\HUDVLQJRULVHUDVHVXVSHQGHG'4E\FRPSDULVRQLQGLFDWHVZKHWKHUWKHGHYLFHLV
DFWLYHO\HUDVLQJRULVLQ(UDVH6XVSHQGEXWFDQQRWGLVWLQJXLVKZKLFKVHFWRUVDUHVHOHFWHGIRU
HUDVXUH7KXVERWKVWDWXVELWVDUHUHTXLUHGIRUVHFWRUDQGPRGHLQIRUPDWLRQ5HIHUWR7DEOH
WRFRPSDUHRXWSXWVIRU'4DQG'46HHWKHIROORZLQJIRUDGGLWLRQDOLQIRUPDWLRQ)LJXUH
WKH³'47RJJOH%LW,´VHFWLRQDQG)LJXUHV±
52
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 12.25.
DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
SURJUDPPLQJ
DWDQ\DGGUHVV
WRJJOHV
GRHVQRWWRJJOH
DWDQDGGUHVVZLWKLQDVHFWRU
VHOHFWHGIRUHUDVXUH
WRJJOHV
DOVRWRJJOHV
DWDQDGGUHVVZLWKLQVHFWRUVQRW
VHOHFWHGIRUHUDVXUH
WRJJOHV
GRHVQRWWRJJOH
DWDQDGGUHVVZLWKLQDVHFWRU
VHOHFWHGIRUHUDVXUH
GRHVQRWWRJJOH
WRJJOHV
DWDQDGGUHVVZLWKLQVHFWRUVQRW
VHOHFWHGIRUHUDVXUH
UHWXUQVDUUD\GDWD
UHWXUQVDUUD\GDWD7KHV\VWHPFDQ
UHDGIURPDQ\VHFWRUQRWVHOHFWHGIRU
HUDVXUH
DWDQ\DGGUHVV
WRJJOHV
LVQRWDSSOLFDEOH
DFWLYHO\HUDVLQJ
HUDVHVXVSHQGHG
SURJUDPPLQJLQ
HUDVHVXVSHQG
5HDGLQJ7RJJOH%LWV'4'4:KHQHYHUWKHV\VWHPLQLWLDOO\EHJLQVUHDGLQJWRJJOHELWVWDWXV
LWPXVWUHDG'4±'4DWOHDVWWZLFHLQDURZWRGHWHUPLQHZKHWKHUDWRJJOHELWLVWRJJOLQJ7\S
LFDOO\WKHV\VWHPZRXOGQRWHDQGVWRUHWKHYDOXHRIWKHWRJJOHELWDIWHUWKHILUVWUHDG$IWHUWKH
VHFRQGUHDGWKHV\VWHPZRXOGFRPSDUHWKHQHZYDOXHRIWKHWRJJOHELWZLWKWKHILUVW,IWKHWRJ
JOHELWLVQRWWRJJOLQJWKHGHYLFHKDVFRPSOHWHGWKHSURJUDPRUHUDVHVRSHUDWLRQ7KHV\VWHP
FDQUHDGDUUD\GDWDRQ'4±'4RQWKHIROORZLQJUHDGF\FOH+RZHYHULIDIWHUWKHLQLWLDOWZR
UHDGF\FOHVWKHV\VWHPGHWHUPLQHVWKDWWKHWRJJOHELWLVVWLOOWRJJOLQJWKHV\VWHPDOVRVKRXOG
QRWHZKHWKHUWKHYDOXHRI'4LVKLJKVHHWKHVHFWLRQRQ'4,ILWLVWKHV\VWHPVKRXOGWKHQ
GHWHUPLQHDJDLQZKHWKHUWKHWRJJOHELWLVWRJJOLQJVLQFHWKHWRJJOHELWPD\KDYHVWRSSHGWRJ
JOLQJMXVWDV'4ZHQWKLJK,IWKHWRJJOHELWLVQRORQJHUWRJJOLQJWKHGHYLFHKDVVXFFHVVIXOO\
FRPSOHWHGWKHSURJUDPRUHUDVHVRSHUDWLRQ,ILWLVVWLOOWRJJOLQJWKHGHYLFHGLGQRWFRPSOHWHWKH
RSHUDWLRQVXFFHVVIXOO\DQGWKHV\VWHPPXVWZULWHWKHUHVHWFRPPDQGWRUHWXUQWRUHDGLQJDUUD\
GDWD7KHUHPDLQLQJVFHQDULRLVWKDWWKHV\VWHPLQLWLDOO\GHWHUPLQHVWKDWWKHWRJJOHELWLVWRJJOLQJ
DQG'4KDVQRWJRQHKLJK7KHV\VWHPPD\FRQWLQXHWRPRQLWRUWKHWRJJOHELWDQG'4WKURXJK
VXFFHVVLYHUHDGF\FOHVGHWHUPLQLQJWKHVWDWXVDVGHVFULEHGLQWKHSUHYLRXVSDUDJUDSK$OWHUQD
WLYHO\LWPD\FKRRVHWRSHUIRUPRWKHUV\VWHPWDVNV,QWKLVFDVHWKHV\VWHPPXVWVWDUWDWWKH
EHJLQQLQJRIWKHDOJRULWKPZKHQLWUHWXUQVWRGHWHUPLQHWKHVWDWXVRIWKHRSHUDWLRQ5HIHUWR)LJ
XUHIRUPRUHGHWDLOV
1RWH
„
:KHQ YHULI\LQJ WKH VWDWXV RI D ZULWH RSHUDWLRQ HPEHGGHG SURJUDPHUDVH RI D PHPRU\
EDQN'4DQG'4WRJJOHEHWZHHQKLJKDQGORZVWDWHVLQDVHULHVRIFRQVHFXWLYHDQGFRQ
WLJXRXVVWDWXVUHDGF\FOHV,QRUGHUIRUWKLVWRJJOLQJEHKDYLRUWREHSURSHUO\REVHUYHGWKH
FRQVHFXWLYHVWDWXVELWUHDGVPXVWQRWEHLQWHUOHDYHGZLWKUHDGDFFHVVHVWRRWKHUPHPRU\
EDQNV,ILWLVQRWSRVVLEOHWRWHPSRUDULO\SUHYHQWUHDGVWRRWKHUPHPRU\EDQNVWKHQLWLV
UHFRPPHQGHGWRXVHWKH'4VWDWXVELWDVWKHDOWHUQDWLYHPHWKRGRIGHWHUPLQLQJWKHDFWLYH
RULQDFWLYHVWDWXVRIWKHZULWHRSHUDWLRQ
„
'DWDSROOLQJSURYLGHVHUURQHRXVUHVXOWVGXULQJHUDVHVXVSHQGRSHUDWLRQXVLQJ'4RU'4
IRUDQ\DGGUHVVFKDQJHVDIWHU&(DVVHUDWLRQRUZLWKRXW$9'SXOVLQJORZ7+HXVHULVUH
TXLUHGWRSXOVH$9'IROORZLQJDQDGGUHVVFKDQJHRUDVVHUW&(DIWHUDGGUHVVLVVWDEOHGXU
LQJVWDWXVSROOLQJ6HH)LJXUHWKURXJK
December 3, 2005 S29WS-N_m0_I0
53
P r e l i m i n a r y
'4([FHHGHG7LPLQJ/LPLWV'4LQGLFDWHVZKHWKHUWKHSURJUDPRUHUDVHWLPHKDVH[FHHGHG
DVSHFLILHGLQWHUQDOSXOVHFRXQWOLPLW8QGHUWKHVHFRQGLWLRQV'4SURGXFHVD³´LQGLFDWLQJWKDW
WKHSURJUDPRUHUDVHF\FOHZDVQRWVXFFHVVIXOO\FRPSOHWHG7KHGHYLFHPD\RXWSXWD³´RQ'4
LIWKHV\VWHPWULHVWRSURJUDPD³´WRDORFDWLRQWKDWZDVSUHYLRXVO\SURJUDPPHGWR³´2QO\
DQHUDVHRSHUDWLRQFDQFKDQJHD³´EDFNWRD³´8QGHUWKLVFRQGLWLRQWKHGHYLFHKDOWVWKH
RSHUDWLRQDQGZKHQWKHWLPLQJOLPLWKDVEHHQH[FHHGHG'4SURGXFHVD³´8QGHUERWKWKHVH
FRQGLWLRQVWKHV\VWHPPXVWZULWHWKHUHVHWFRPPDQGWRUHWXUQWRWKHUHDGPRGHRUWRWKH
HUDVHVXVSHQGUHDGPRGHLIDEDQNZDVSUHYLRXVO\LQWKHHUDVHVXVSHQGSURJUDPPRGH
'46HFWRU(UDVH7LPHRXW6WDWH,QGLFDWRU$IWHUZULWLQJDVHFWRUHUDVHFRPPDQGVHTXHQFH
WKHV\VWHPPD\UHDG'4WRGHWHUPLQHZKHWKHURUQRWHUDVXUHKDVEHJXQ7KHVHFWRUHUDVH
WLPHUGRHVQRWDSSO\WRWKHFKLSHUDVHFRPPDQG,IDGGLWLRQDOVHFWRUVDUHVHOHFWHGIRUHUDVXUH
WKHHQWLUHWLPHRXWDOVRDSSOLHVDIWHUHDFKDGGLWLRQDOVHFWRUHUDVHFRPPDQG:KHQWKHWLPHRXW
SHULRGLVFRPSOHWH'4VZLWFKHVIURPD³´WRD³´,IWKHWLPHEHWZHHQDGGLWLRQDOVHFWRUHUDVH
FRPPDQGVIURPWKHV\VWHPFDQEHDVVXPHGWREHOHVVWKDQW6($WKHV\VWHPQHHGQRWPRQLWRU
'46HH6HFWRU(UDVH&RPPDQG6HTXHQFHIRUPRUHGHWDLOV
$IWHUWKHVHFWRUHUDVHFRPPDQGLVZULWWHQWKHV\VWHPVKRXOGUHDGWKHVWDWXVRI'4'DWD
3ROOLQJRU'47RJJOH%LW,WRHQVXUHWKDWWKHGHYLFHKDVDFFHSWHGWKHFRPPDQGVHTXHQFH
DQGWKHQUHDG'4,I'4LV³´WKH(PEHGGHG(UDVHDOJRULWKPKDVEHJXQDOOIXUWKHUFRP
PDQGVH[FHSW(UDVH6XVSHQGDUHLJQRUHGXQWLOWKHHUDVHRSHUDWLRQLVFRPSOHWH,I'4LV³´
WKHGHYLFHDFFHSWVDGGLWLRQDOVHFWRUHUDVHFRPPDQGV7RHQVXUHWKHFRPPDQGKDVEHHQDF
FHSWHGWKHV\VWHPVRIWZDUHVKRXOGFKHFNWKHVWDWXVRI'4SULRUWRDQGIROORZLQJHDFKVXE
VHTXHQWVHFWRUHUDVHFRPPDQG,I'4LVKLJKRQWKHVHFRQGVWDWXVFKHFNWKHODVWFRPPDQG
PLJKWQRWKDYHEHHQDFFHSWHG7DEOHVKRZVWKHVWDWXVRI'4UHODWLYHWRWKHRWKHUVWDWXV
ELWV
'4:ULWHWR%XIIHU$ERUW'4LQGLFDWHVZKHWKHUD:ULWHWR%XIIHURSHUDWLRQZDVDERUWHG
8QGHUWKHVHFRQGLWLRQV'4SURGXFHVD³´7KHV\VWHPPXVWLVVXHWKH:ULWHWR%XIIHU$ERUW
5HVHWFRPPDQGVHTXHQFHWRUHWXUQWKHGHYLFHWRUHDGLQJDUUD\GDWD6HH:ULWH%XIIHU3URJUDP
PLQJ2SHUDWLRQIRUPRUHGHWDLOV
54
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 12.26. Write Operation Status
Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ1
(Note 4)
6WDQGDUG
0RGH
(PEHGGHG3URJUDP$OJRULWKP
'4
7RJJOH
1$
1RWRJJOH
(PEHGGHG(UDVH$OJRULWKP
7RJJOH
7RJJOH
1$
3URJUDP
6XVSHQG
0RGH
1RWH
,19$/,'
,19$/,'
,19$/,'
,19$/,'
,19$/,'
,19$/,'
5HDGLQJZLWKLQ3URJUDP6XVSHQGHG6HFWRU
1RW
$OORZHG
1RW
$OORZHG
1RW
$OORZHG
1RW
$OORZHG
1RW
$OORZHG
1RW
$OORZHG
'DWD
'DWD
'DWD
'DWD
'DWD
'DWD
1RWRJJOH
1$
7RJJOH
1$
'DWD
'DWD
'DWD
'DWD
'DWD
'DWD
(UDVH6XVSHQG3URJUDP
'4
7RJJOH
1$
1$
1$
%86<6WDWH
'4
7RJJOH
1$
1$
([FHHGHG7LPLQJ/LPLWV
'4
7RJJOH
1$
1$
$%2576WDWH
'4
7RJJOH
1$
1$
(UDVH
6XVSHQG
0RGH
1RWH
:ULWHWR
%XIIHU
1RWH
5HDGLQJZLWKLQ1RQ3URJUDP6XVSHQGHG
6HFWRU
(UDVH6XVSHQG
5HDG
(UDVH
6XVSHQGHG6HFWRU
1RQ(UDVH6XVSHQGHG
6HFWRU
1RWHV
'4VZLWFKHVWRµ¶ZKHQDQ(PEHGGHG3URJUDPRU(PEHGGHG(UDVHRSHUDWLRQKDVH[FHHGHGWKHPD[LPXPWLPLQJOLPLWV5HIHUWRWKH
VHFWLRQRQ'4IRUPRUHLQIRUPDWLRQ
'4DQG'4UHTXLUHDYDOLGDGGUHVVZKHQUHDGLQJVWDWXVLQIRUPDWLRQ5HIHUWRWKHDSSURSULDWHVXEVHFWLRQIRUIXUWKHUGHWDLOV
'DWDDUHLQYDOLGIRUDGGUHVVHVLQD3URJUDP6XVSHQGHGVHFWRU
'4LQGLFDWHVWKH:ULWHWR%XIIHU$%257VWDWXVGXULQJ:ULWH%XIIHU3URJUDPPLQJRSHUDWLRQV
7KHGDWDEDUSROOLQJDOJRULWKPVKRXOGEHXVHGIRU:ULWH%XIIHU3URJUDPPLQJRSHUDWLRQV1RWHWKDW'4GXULQJ:ULWH%XIIHU3URJUDPPLQJ
LQGLFDWHVWKHGDWDEDUIRU'4GDWDIRUWKH/$67/2$'(':5,7(%8))(5$''5(66ORFDWLRQ
)RUDQ\DGGUHVVFKDQJHVDIWHU&(DVVHUWLRQUHDVVHUWLRQRI&(PLJKWEHUHTXLUHGDIWHUWKHDGGUHVVHVEHFRPHVWDEOHIRUGDWDSROOLQJ
GXULQJWKHHUDVHVXVSHQGRSHUDWLRQXVLQJ'4'4
December 3, 2005 S29WS-N_m0_I0
55
P r e l i m i n a r y
12.7
Simultaneous Read/Write
7KHVLPXOWDQHRXVUHDGZULWHIHDWXUHDOORZVWKHKRVWV\VWHPWRUHDGGDWDIURPRQHEDQNRIPHP
RU\ZKLOHSURJUDPPLQJRUHUDVLQJDQRWKHUEDQNRIPHPRU\$QHUDVHRSHUDWLRQPD\DOVREH
VXVSHQGHGWRUHDGIURPRUSURJUDPDQRWKHUORFDWLRQZLWKLQWKHVDPHEDQNH[FHSWWKHVHFWRU
EHLQJHUDVHG)LJXUH%DFNWR%DFN5HDG:ULWH&\FOH7LPLQJVVKRZVKRZUHDGDQGZULWH
F\FOHVPD\EHLQLWLDWHGIRUVLPXOWDQHRXVRSHUDWLRQZLWK]HURODWHQF\5HIHUWRWKH'&&KDUDFWHU
LVWLFV &026 &RPSDWLEOH WDEOH IRU UHDGZKLOHSURJUDP DQG UHDGZKLOHHUDVH FXUUHQW
VSHFLILFDWLRQ
12.8
Writing Commands/Command Sequences
:KHQWKHGHYLFHLVFRQILJXUHGIRU$V\QFKURQRXVUHDGRQO\$V\QFKURQRXVZULWHRSHUDWLRQVDUH
DOORZHGDQG&/.LVLJQRUHG:KHQLQWKH6\QFKURQRXVUHDGPRGHFRQILJXUDWLRQWKHGHYLFHLV
DEOHWRSHUIRUPERWK$V\QFKURQRXVDQG6\QFKURQRXVZULWHRSHUDWLRQV&/.DQG$9'LQGXFHG
DGGUHVVODWFKHVDUHVXSSRUWHGLQWKH6\QFKURQRXVSURJUDPPLQJPRGH'XULQJDV\QFKURQRXV
ZULWHRSHUDWLRQWRZULWHDFRPPDQGRUFRPPDQGVHTXHQFHZKLFKLQFOXGHVSURJUDPPLQJGDWD
WRWKHGHYLFHDQGHUDVLQJVHFWRUVRIPHPRU\WKHV\VWHPPXVWGULYH$9'DQG&(WR9,/DQG
2(WR9,+ZKHQSURYLGLQJDQDGGUHVVWRWKHGHYLFHDQGGULYH:(DQG&(WR9,/DQG2(
WR9,+ZKHQZULWLQJFRPPDQGVRUGDWD'XULQJDQDV\QFKURQRXVZULWHRSHUDWLRQWKHV\VWHP
PXVWGULYH&(DQG:(WR9,/DQG2(WR9,+ZKHQSURYLGLQJDQDGGUHVVFRPPDQGDQGGDWD
$GGUHVVHVDUHODWFKHGRQWKHODVWIDOOLQJHGJHRI:(RU&(ZKLOHGDWDLVODWFKHGRQWKHVW
ULVLQJHGJHRI:(RU&($QHUDVHRSHUDWLRQFDQHUDVHRQHVHFWRUPXOWLSOHVHFWRUVRUWKH
HQWLUHGHYLFH7DEOHV ±LQGLFDWHWKHDGGUHVVVSDFHWKDWHDFKVHFWRURFFXSLHV7KHGHYLFH
DGGUHVVVSDFHLVGLYLGHGLQWRVL[WHHQEDQNV%DQNVWKURXJKFRQWDLQRQO\.ZRUGVHFWRUV
ZKLOH%DQNVDQGFRQWDLQERWK.ZRUGERRWVHFWRUVLQDGGLWLRQWR.ZRUGVHFWRUV$
³EDQNDGGUHVV´LVWKHVHWRIDGGUHVVELWVUHTXLUHGWRXQLTXHO\VHOHFWDEDQN6LPLODUO\D³VHFWRU
DGGUHVV´LVWKHDGGUHVVELWVUHTXLUHGWRXQLTXHO\VHOHFWDVHFWRU,&&LQ³'&&KDUDFWHULVWLFV´UHS
UHVHQWVWKHDFWLYHFXUUHQWVSHFLILFDWLRQIRUWKHZULWHPRGH³$&&KDUDFWHULVWLFV6\QFKURQRXV´
DQG³$&&KDUDFWHULVWLFV$V\QFKURQRXV´FRQWDLQWLPLQJVSHFLILFDWLRQWDEOHVDQGWLPLQJGLDJUDPV
IRUZULWHRSHUDWLRQV
12.9
Handshaking
7KHKDQGVKDNLQJIHDWXUHDOORZVWKHKRVWV\VWHPWRGHWHFWZKHQGDWDLVUHDG\WREHUHDGE\VLP
SO\PRQLWRULQJWKH5'<5HDG\SLQZKLFKLVDGHGLFDWHGRXWSXWDQGFRQWUROOHGE\&(
:KHQWKHGHYLFHLVFRQILJXUHGWRRSHUDWHLQV\QFKURQRXVPRGHDQG2(LVORZDFWLYHWKHLQL
WLDOZRUGRIEXUVWGDWDEHFRPHVDYDLODEOHDIWHUHLWKHUWKHIDOOLQJRUULVLQJHGJHRIWKH5'<SLQ
GHSHQGLQJRQWKHVHWWLQJIRUELWLQWKH&RQILJXUDWLRQ5HJLVWHU,WLVUHFRPPHQGHGWKDWWKH
KRVWV\VWHPVHW&5±&5LQWKH&RQILJXUDWLRQ5HJLVWHUWRWKHDSSURSULDWHQXPEHURIZDLW
VWDWHVWRHQVXUHRSWLPDOEXUVWPRGHRSHUDWLRQVHH7DEOH&RQILJXUDWLRQ5HJLVWHU
%LWLQWKH&RQILJXUDWLRQ5HJLVWHUDOORZVWKHKRVWWRVSHFLI\ZKHWKHU5'<LVDFWLYHDWWKHVDPH
WLPHWKDWGDWDLVUHDG\RURQHF\FOHEHIRUHGDWDLVUHDG\
56
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
12.10 Hardware Reset
7KH5(6(7LQSXWSURYLGHVDKDUGZDUHPHWKRGRIUHVHWWLQJWKHGHYLFHWRUHDGLQJDUUD\GDWD
:KHQ5(6(7LVGULYHQORZIRUDWOHDVWDSHULRGRIW53WKHGHYLFHLPPHGLDWHO\WHUPLQDWHVDQ\
RSHUDWLRQLQSURJUHVVWULVWDWHVDOORXWSXWVUHVHWVWKHFRQILJXUDWLRQUHJLVWHUDQGLJQRUHVDOOUHDG
ZULWHFRPPDQGVIRUWKHGXUDWLRQRIWKH5(6(7SXOVH7KHGHYLFHDOVRUHVHWVWKHLQWHUQDOVWDWH
PDFKLQHWRUHDGLQJDUUD\GDWD
7RHQVXUHGDWDLQWHJULW\WKHRSHUDWLRQWKDWZDVLQWHUUXSWHGVKRXOGEHUHLQLWLDWHGRQFHWKHGHYLFH
LVUHDG\WRDFFHSWDQRWKHUFRPPDQGVHTXHQFH
:KHQ5(6(7LVKHOGDW966WKHGHYLFHGUDZV&026VWDQGE\FXUUHQW,&&,I5(6(7LVKHOG
DW9,/EXWQRWDW966WKHVWDQGE\FXUUHQWLVJUHDWHU
5(6(7PD\EHWLHGWRWKHV\VWHPUHVHWFLUFXLWU\ZKLFKHQDEOHVWKHV\VWHPWRUHDGWKHERRWXS
ILUPZDUHIURPWKH)ODVKPHPRU\XSRQDV\VWHPUHVHW
6HH)LJXUHVDQGIRUWLPLQJGLDJUDPV
12.11 Software Reset
6RIWZDUHUHVHWLVSDUWRIWKHFRPPDQGVHWVHH7DEOHWKDWDOVRUHWXUQVWKHGHYLFHWRDUUD\
UHDGPRGHDQGPXVWEHXVHGIRUWKHIROORZLQJFRQGLWLRQV
WRH[LW$XWRVHOHFWPRGH
ZKHQ'4JRHVKLJKGXULQJZULWHVWDWXVRSHUDWLRQWKDWLQGLFDWHVSURJUDPRUHUDVHF\FOHZDV
QRWVXFFHVVIXOO\FRPSOHWHG
H[LWVHFWRUORFNXQORFNRSHUDWLRQ
WRUHWXUQWRHUDVHVXVSHQGUHDGPRGHLIWKHGHYLFHZDVSUHYLRXVO\LQ(UDVH6XVSHQGPRGH
DIWHUDQ\DERUWHGRSHUDWLRQV
Software Functions and Sample Code
Table 12.27.
Reset
//')XQFWLRQ OOGB5HVHW&PG
Cycle
Operation
Byte Address
Word Address
Data
5HVHW&RPPDQG
:ULWH
%DVH[[[K
%DVH[[[K
)K
1RWH%DVH %DVH$GGUHVV
7KHIROORZLQJLVD&VRXUFHFRGHH[DPSOHRIXVLQJWKHUHVHWIXQFWLRQ5HIHUWRWKH6SDQVLRQ/RZ
/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRUJHQHUDOLQIRUPD
WLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
7KHIROORZLQJDUHDGGLWLRQDOSRLQWVWRFRQVLGHUZKHQXVLQJWKHUHVHWFRPPDQG
„
7KLVFRPPDQGUHVHWVWKHEDQNVWRWKHUHDGDQGDGGUHVVELWVDUHLJQRUHG
„
5HVHWFRPPDQGVDUHLJQRUHGRQFHHUDVXUHKDVEHJXQXQWLOWKHRSHUDWLRQLVFRPSOHWH
„
2QFHSURJUDPPLQJEHJLQVWKHGHYLFHLJQRUHVUHVHWFRPPDQGVXQWLOWKHRSHUDWLRQLVFRP
SOHWH
„
7KHUHVHWFRPPDQGPD\EHZULWWHQEHWZHHQWKHF\FOHVLQDSURJUDPFRPPDQGVHTXHQFH
EHIRUHSURJUDPPLQJEHJLQVSULRUWRWKHWKLUGF\FOH7KLVUHVHWVWKHEDQNWRZKLFKWKHV\V
WHPZDVZULWLQJWRWKHUHDGPRGH
December 3, 2005 S29WS-N_m0_I0
57
P r e l i m i n a r y
58
„
,IWKHSURJUDPFRPPDQGVHTXHQFHLVZULWWHQWRDEDQNWKDWLVLQWKH(UDVH6XVSHQGPRGH
ZULWLQJWKHUHVHWFRPPDQGUHWXUQVWKDWEDQNWRWKHHUDVHVXVSHQGUHDGPRGH
„
7KHUHVHWFRPPDQGPD\EHDOVRZULWWHQGXULQJDQ$XWRVHOHFWFRPPDQGVHTXHQFH
„
,IDEDQNKDVHQWHUHGWKH$XWRVHOHFWPRGHZKLOHLQWKH(UDVH6XVSHQGPRGHZULWLQJWKH
UHVHWFRPPDQGUHWXUQVWKDWEDQNWRWKHHUDVHVXVSHQGUHDGPRGH
„
,I'4JRHVKLJKGXULQJD:ULWH%XIIHU3URJUDPPLQJRSHUDWLRQWKHV\VWHPPXVWZULWHWKH
:ULWHWR%XIIHU$ERUW5HVHWFRPPDQGVHTXHQFHWR5(6(7WKHGHYLFHWRUHDGLQJDUUD\GDWD
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„
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PDQGVHTXHQFH>VHHFRPPDQGWDEOHIRUGHWDLOV@
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
13 Advanced Sector Protection/Unprotection
7KH$GYDQFHG6HFWRU3URWHFWLRQ8QSURWHFWLRQIHDWXUHGLVDEOHVRUHQDEOHVSURJUDPPLQJRUHUDVH
RSHUDWLRQVLQDQ\RUDOO VHFWRUVDQGFDQEHLPSOHPHQWHGWKURXJKVRIWZDUHDQGRUKDUGZDUH
PHWKRGVZKLFKDUHLQGHSHQGHQWRIHDFKRWKHU7KLVVHFWLRQGHVFULEHVWKHYDULRXVPHWKRGVRI
SURWHFWLQJGDWDVWRUHGLQWKHPHPRU\DUUD\$QRYHUYLHZRIWKHVHPHWKRGVLQVKRZQLQ)LJXUH
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
ACC = VIL
(All sectors locked)
Password Method
Persistent Method
(DQ2)
(DQ1)
WP# = VIL
(All boot
sectors locked)
64-bit Password
(One Time Protect)
PPB Lock Bit1,2,3
0 = PPBs Locked
1 = PPBs Unlocked
1. Bit is volatile, and defaults to “1” on
reset.
2. Programming to “0” locks all PPBs to
their current state.
3. Once programmed to “0”, requires
hardware reset to unlock.
Memory Array
Persistent
Protection Bit
(PPB)4,5
Sector 0
PPB 0
DYB 0
Sector 1
PPB 1
DYB 1
Sector 2
PPB 2
DYB 2
Sector N-2
PPB N-2
DYB N-2
Sector N-1
PPB N-1
DYB N-1
Sector N3
PPB N
DYB N
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
Dynamic
Protection Bit
(DYB)6,7,8
6. 0 = Sector Protected,
1 = Sector Unprotected.
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Figure 13.1. Advanced Sector Protection/Unprotection
December 3, 2005 S29WS-N_m0_I0
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P r e l i m i n a r y
13.1
Lock Register
$VVKLSSHGIURPWKHIDFWRU\DOOGHYLFHVGHIDXOWWRWKHSHUVLVWHQWPRGHZKHQSRZHULVDSSOLHG
DQGDOOVHFWRUVDUHXQSURWHFWHGXQOHVVRWKHUZLVHFKRVHQWKURXJKWKH'<%RUGHULQJRSWLRQ7KH
GHYLFHSURJUDPPHURUKRVWV\VWHPPXVWWKHQFKRRVHZKLFKVHFWRUSURWHFWLRQPHWKRGWRXVH
3URJUDPPLQJVHWWLQJWR³´DQ\RQHRIWKHIROORZLQJWZRRQHWLPHSURJUDPPDEOHQRQYRODWLOH
ELWVORFNVWKHSDUWSHUPDQHQWO\LQWKDWPRGH
„
/RFN5HJLVWHU3HUVLVWHQW3URWHFWLRQ0RGH/RFN%LW'4
„
/RFN5HJLVWHU3DVVZRUG3URWHFWLRQ0RGH/RFN%LW'4
Table 13.1
Lock Register
Device
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
6:61
3DVVZRUG
3URWHFWLRQ
0RGH/RFN%LW
3HUVLVWHQW
3URWHFWLRQ
0RGH/RFN%LW
&XVWRPHU
6HF6L6HFWRU
3URWHFWLRQ%LW
3DVVZRUG
3URWHFWLRQ
0RGH/RFN%LW
3HUVLVWHQW
3URWHFWLRQ
0RGH/RFN%LW
6HF6L6HFWRU
3URWHFWLRQ%LW
'<%/RFN%RRW%LW
6:61
8QGHILQHG
VHFWRUV
SRZHUXS
SURWHFWHG
VHFWRUV
SRZHUXS
XQSURWHFWHG
33%2QH7LPH
3URJUDPPDEOH%LW
$OO33%HUDVH
FRPPDQGGLVDEOHG
$OO33%(UDVH
FRPPDQGHQDEOHG
)RUSURJUDPPLQJORFNUHJLVWHUELWVUHIHUWR7DEOH
1RWHV
,IWKHSDVVZRUGPRGHLVFKRVHQWKHSDVVZRUGPXVWEHSURJUDPPHGEHIRUHVHWWLQJWKHFRU
UHVSRQGLQJORFNUHJLVWHUELW
$IWHUWKH/RFN5HJLVWHU%LWV&RPPDQG6HW(QWU\FRPPDQGVHTXHQFHLVZULWWHQUHDGVDQG
ZULWHVIRU%DQNDUHGLVDEOHGZKLOHUHDGVIURPRWKHUEDQNVDUHDOORZHGXQWLOH[LWLQJWKLV
PRGH
,IERWKORFNELWVDUHVHOHFWHGWREHSURJUDPPHGWR]HURVDWWKHVDPHWLPHWKHRSHUDWLRQ
DERUWV
2QFHWKH3DVVZRUG 0RGH/RFN%LW LVSURJUDPPHGWKH3HUVLVWHQW 0RGH /RFN %LW LVSHUPD
QHQWO\GLVDEOHGDQGQRFKDQJHVWRWKHSURWHFWLRQVFKHPHDUHDOORZHG6LPLODUO\LIWKH3HU
VLVWHQW0RGH/RFN%LWLVSURJUDPPHGWKH3DVVZRUG0RGHLVSHUPDQHQWO\GLVDEOHG
'XULQJHUDVHSURJUDPVXVSHQG$63HQWU\FRPPDQGVDUHQRWDOORZHG
:KHQWKHGHYLFHORFNUHJLVWHULVSURJUDPPHG33%PRGHORFNELWLVSURJUDPPHGSDVVZRUG
PRGHORFNELWLVSURJUDPPHGRUWKH6HFXUHG6LOLFRQ6HFWRUORFNELWLVSURJUDPPHGDOO'<%V
UHYHUWWRWKHSRZHURQGHIDXOWVWDWH
/RFNUHJLVWHUSURJUDPPLQJRSHUDWLRQ
$'DWD3ROOLQJFDQEHGRQHLPPHGLDWHO\DIWHUWKHORFNUHJLVWHUSURJUDPPLQJFRPPDQG
VHTXHQFHQRGHOD\UHTXLUHG1RWHWKDWVWDWXVSROOLQJFDQEHGRQHRQO\LQEDQNDQG
WKHUHFRPPHQGHG—VGHOD\LVIRUEDFNZDUGFRPSDWLELOLW\DQGLVQRWUHTXLUHG7KLVUHF
RPPHQGDWLRQZLOOEHQRWHGDVVXFKLQWKHQH[WUHYLVLRQRIWKHGDWDVKHHW
%5HDGVIURPRWKHUEDQNVVLPXOWDQHRXVRSHUDWLRQDUHQRWDOORZHGGXULQJORFNUHJLVWHU
SURJUDPPLQJ7KLVUHVWULFWLRQDSSOLHVWRERWKV\QFKURQRXVDQGDV\QFKURQRXVUHDGRSHU
DWLRQV
&7KHDERYHFODULILFDWLRQVDUHWUXHIRUSURJUDPPLQJDQ\ELWVRIWKH/RFN5HJLVWHU
60
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
$IWHUVHOHFWLQJDVHFWRUSURWHFWLRQPHWKRGHDFKVHFWRUFDQRSHUDWHLQDQ\RIWKHIROORZLQJWKUHH
VWDWHV
&RQVWDQWO\ORFNHG7KHVHOHFWHGVHFWRUVDUHSURWHFWHGDQGFDQQRWEHUHSURJUDPPHGXQOHVV
33%ORFNELWLVFOHDUHGYLDDSDVVZRUGKDUGZDUHUHVHWRUSRZHUF\FOH
'\QDPLFDOO\ ORFNHG 7KH VHOHFWHG VHFWRUV DUH SURWHFWHG DQG FDQ EH DOWHUHG YLD VRIWZDUH
FRPPDQGV
8QORFNHG7KHVHFWRUVDUHXQSURWHFWHGDQGFDQEHHUDVHGDQGRUSURJUDPPHG
7KHVHVWDWHVDUHFRQWUROOHGE\WKHELWW\SHVGHVFULEHGLQ6HFWLRQV±
13.2
Persistent Protection Bits
7KH3HUVLVWHQW3URWHFWLRQ%LWVDUHXQLTXHDQGQRQYRODWLOHIRUHDFKVHFWRUDQGKDYHWKHVDPHHQ
GXUDQFHVDVWKH)ODVKPHPRU\3UHSURJUDPPLQJDQGYHULILFDWLRQSULRUWRHUDVXUHDUHKDQGOHGE\
WKHGHYLFHDQGWKHUHIRUHGRQRWUHTXLUHV\VWHPPRQLWRULQJ
1RWHV
(DFK33%LVLQGLYLGXDOO\SURJUDPPHGDQGDOODUHHUDVHGLQSDUDOOHO
33%SURJUDPHUDVHRSHUDWLRQ5HDGVIURPRWKHUEDQNVVLPXOWDQHRXVRSHUDWLRQDUHQRWDO
ORZHG GXULQJ 33% SURJUDPPLQJHUDVH RSHUDWLRQ 7KLV UHVWULFWLRQ DSSOLHV IRU ERWK
V\QFKURQRXVDQGDV\QFKURQRXVUHDGRSHUDWLRQV
(QWU\FRPPDQGGLVDEOHVUHDGVDQGZULWHVIRUWKHEDQNVHOHFWHG
5HDGVZLWKLQWKDWEDQNUHWXUQWKH33%VWDWXVIRUWKDWVHFWRU
$OO5HDGVPXVWEHSHUIRUPHGXVLQJWKH$V\QFKURQRXVPRGH
7KHVSHFLILFVHFWRUDGGUHVV$$:61$$:61DUHZULWWHQDWWKHVDPH
WLPHDVWKHSURJUDPFRPPDQG
,IWKH33%/RFN%LWLVVHWWKH33%3URJUDPRUHUDVHFRPPDQGGRHVQRWH[HFXWHDQGWLPHV
RXWZLWKRXWSURJUDPPLQJRUHUDVLQJWKH33%
7KHUHDUHQRPHDQVIRULQGLYLGXDOO\HUDVLQJDVSHFLILF33%DQGQRVSHFLILFVHFWRUDGGUHVVLV
UHTXLUHGIRUWKLVRSHUDWLRQ
([LWFRPPDQGPXVWEHLVVXHGDIWHUWKHH[HFXWLRQZKLFKUHVHWVWKHGHYLFHWRUHDGPRGHDQG
UHHQDEOHVUHDGVDQGZULWHVIRU%DQN
7KHSURJUDPPLQJVWDWHRIWKH33%IRUDJLYHQVHFWRUFDQEHYHULILHGE\ZULWLQJD33%
6WDWXV5HDG&RPPDQGWRWKHGHYLFHDVGHVFULEHGE\WKHIORZFKDUWVKRZQLQ)LJXUH
December 3, 2005 S29WS-N_m0_I0
61
P r e l i m i n a r y
Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte Twice
Addr = SA0
DQ6 =
Toggle?
No
Yes
No
DQ5 = 1?
Wait 500 µs
Yes
Read Byte Twice
Addr = SA0
DQ6 =
Toggle?
No
Read Byte.
Addr = SA
Yes
No
FAIL
DQ0 =
'1' (Erase)
'0' (Pgm.)?
Yes
PASS
Exit PPB
Command Set
Figure 13.2.
62
PPB Program/Erase Algorithm
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
13.3
Dynamic Protection Bits
'\QDPLF3URWHFWLRQ%LWVDUHYRODWLOHDQGXQLTXHIRUHDFKVHFWRUDQGFDQEHLQGLYLGXDOO\PRGLILHG
'<%VRQO\FRQWUROWKHSURWHFWLRQVFKHPHIRUXQSURWHFWHGVHFWRUVWKDWKDYHWKHLU33%VFOHDUHG
HUDVHGWR³´%\LVVXLQJWKH'<%6HWRU&OHDUFRPPDQGVHTXHQFHVWKH'<%VDUHVHWSUR
JUDPPHG WR ³´ RU FOHDUHG HUDVHG WR ³´ WKXV SODFLQJ HDFK VHFWRU LQ WKH SURWHFWHG RU
XQSURWHFWHGVWDWHUHVSHFWLYHO\7KLVIHDWXUHDOORZVVRIWZDUHWRHDVLO\SURWHFWVHFWRUVDJDLQVWLQ
DGYHUWHQW FKDQJHV \HW GRHV QRW SUHYHQW WKH HDV\ UHPRYDO RI SURWHFWLRQ ZKHQ FKDQJHV DUH
QHHGHG
1RWHV
7KH'<%VFDQEHVHWSURJUDPPHGWR³´RUFOHDUHGHUDVHGWR³´DVRIWHQDVQHHGHG
:KHQWKHSDUWVDUHILUVWVKLSSHGWKH33%VDUHFOHDUHGHUDVHGWR³´DQGXSRQSRZHUXSRU
UHVHWWKH'<%VFDQEHVHWRUFOHDUHGGHSHQGLQJXSRQWKHRUGHULQJRSWLRQFKRVHQ
13.4
,IWKHRSWLRQWRFOHDUWKH'<%VDIWHUSRZHUXSLVFKRVHQHUDVHGWR³´WKHQWKHVHFWRUV
PD\EHPRGLILHGGHSHQGLQJXSRQWKH33%VWDWHRIWKDWVHFWRUVHH7DEOH
7KHVHFWRUVZRXOGEHLQWKHSURWHFWHGVWDWH,IWKHRSWLRQWRVHWWKH'<%VDIWHUSRZHUXSLV
FKRVHQSURJUDPPHGWR³´
,WLVSRVVLEOHWR KDYHVHFWRUVWKDWDUHSHUVLVWHQWO\ORFNHGZLWKVHFWRUVWKDW DUHOHIWLQWKH
G\QDPLFVWDWH
7KH'<%6HWRU&OHDUFRPPDQGVIRUWKHG\QDPLFVHFWRUVVLJQLI\SURWHFWHGRUXQSURWHFWHG
VWDWHRIWKHVHFWRUVUHVSHFWLYHO\+RZHYHULIWKHUHLVDQHHGWRFKDQJHWKHVWDWXVRIWKHSHU
VLVWHQWO\ ORFNHGVHFWRUVDIHZPRUH VWHSVDUHUHTXLUHG)LUVWWKH33%/RFN%LWPXVWEH
FOHDUHGE\HLWKHUSXWWLQJWKHGHYLFHWKURXJKDSRZHUF\FOHRUKDUGZDUHUHVHW7KH33%VFDQ
WKHQEHFKDQJHGWRUHIOHFWWKHGHVLUHGVHWWLQJV6HWWLQJWKH33%/RFN%LWRQFHDJDLQORFNV
WKH33%VDQGWKHGHYLFHRSHUDWHVQRUPDOO\DJDLQ
7RDFKLHYHWKHEHVWSURWHFWLRQLWLVUHFRPPHQGHGWRH[HFXWHWKH33%/RFN%LW6HWFRPPDQG
HDUO\LQWKHERRWFRGHDQGSURWHFWWKHERRWFRGHE\KROGLQJ:3 9,/1RWHWKDWWKH33%
DQG'<%ELWVKDYHWKHVDPHIXQFWLRQZKHQ$&& 9++DVWKH\GRZKHQ$&& 9,+
Persistent Protection Bit Lock Bit
7KH 3HUVLVWHQW 3URWHFWLRQ %LW /RFN %LW LV D JOREDO YRODWLOH ELW IRU DOO VHFWRUV :KHQ VHW SUR
JUDPPHGWR³´LWORFNVDOO33%VDQGZKHQFOHDUHGSURJUDPPHGWR³´DOORZVWKH33%VWREH
FKDQJHG7KHUHLVRQO\RQH33%/RFN%LWSHUGHYLFH
1RWHV
13.5
1RVRIWZDUHFRPPDQGVHTXHQFHXQORFNVWKLVELWXQOHVVWKHGHYLFHLVLQWKHSDVVZRUGSUR
WHFWLRQPRGHRQO\DKDUGZDUHUHVHWRUDSRZHUXSFOHDUVWKLVELW
7KH33%/RFN%LWPXVWEHVHWSURJUDPPHGWR³´RQO\DIWHUDOO33%VDUHFRQILJXUHGWRWKH
GHVLUHGVHWWLQJV
Password Protection Method
7KH3DVVZRUG3URWHFWLRQ0HWKRGDOORZVDQHYHQKLJKHUOHYHORIVHFXULW\WKDQWKH3HUVLVWHQW6HF
WRU3URWHFWLRQ0RGHE\UHTXLULQJDELWSDVVZRUGIRUXQORFNLQJWKHGHYLFH33%/RFN%LW,Q
DGGLWLRQWRWKLVSDVVZRUGUHTXLUHPHQWDIWHUSRZHUXSDQGUHVHWWKH33%/RFN%LWLVVHW³´WR
PDLQWDLQWKHSDVVZRUGPRGHRIRSHUDWLRQ6XFFHVVIXOH[HFXWLRQRIWKH3DVVZRUG8QORFNFRP
PDQG E\ HQWHULQJ WKH HQWLUH SDVVZRUG FOHDUV WKH 33% /RFN %LW DOORZLQJ IRU VHFWRU 33%V
PRGLILFDWLRQV
December 3, 2005 S29WS-N_m0_I0
63
P r e l i m i n a r y
1RWHV
7KHUHLVQRVSHFLDODGGUHVVLQJRUGHUUHTXLUHGIRUSURJUDPPLQJWKHSDVVZRUG2QFHWKH3DVV
ZRUGLVZULWWHQDQGYHULILHGWKH3DVVZRUG0RGH/RFNLQJ%LWPXVWEHVHWLQRUGHUWRSUHYHQW
DFFHVV
7KH3DVVZRUG3URJUDP&RPPDQGLVRQO\FDSDEOHRISURJUDPPLQJ³´V3URJUDPPLQJD³´
DIWHUDFHOOLVSURJUDPPHGDVD³´UHVXOWVLQDWLPHRXWZLWKWKHFHOODVD³´
7KHSDVVZRUGLVDOO³´VZKHQVKLSSHGIURPWKHIDFWRU\
$OOELWSDVVZRUGFRPELQDWLRQVDUHYDOLGDVDSDVVZRUG
7KHUHLVQRPHDQVWRYHULI\ZKDWWKHSDVVZRUGLVDIWHULWLVVHW
7KH3DVVZRUG0RGH/RFN%LWRQFHVHWSUHYHQWVUHDGLQJWKHELWSDVVZRUGRQWKHGDWD
EXVDQGIXUWKHUSDVVZRUGSURJUDPPLQJ
7KH3DVVZRUG0RGH/RFN%LWLVQRWHUDVDEOH
7KHORZHUWZRDGGUHVVELWV$±$DUHYDOLGGXULQJWKH3DVVZRUG5HDG3DVVZRUG3URJUDP
DQG3DVVZRUG8QORFN
7KHH[DFWSDVVZRUGPXVWEHHQWHUHGLQRUGHUIRUWKHXQORFNLQJIXQFWLRQWRRFFXU
7KH3DVVZRUG8QORFNFRPPDQGFDQQRWEHLVVXHGDQ\IDVWHUWKDQ—VDWDWLPHWRSUHYHQW
DKDFNHUIURPUXQQLQJWKURXJKDOOWKHELWFRPELQDWLRQVLQDQDWWHPSWWRFRUUHFWO\PDWFK
DSDVVZRUG
$SSUR[LPDWHO\—VLVUHTXLUHGIRUXQORFNLQJWKHGHYLFHDIWHUWKHYDOLGELWSDVVZRUGLV
JLYHQWRWKHGHYLFH
3DVVZRUGYHULILFDWLRQLVRQO\DOORZHGGXULQJWKHSDVVZRUGSURJUDPPLQJRSHUDWLRQ
$OOIXUWKHUFRPPDQGVWRWKHSDVVZRUGUHJLRQDUHGLVDEOHGDQGDOORSHUDWLRQVDUHLJQRUHG
,IWKHSDVVZRUGLVORVWDIWHUVHWWLQJWKH3DVVZRUG0RGH/RFN%LWWKHUHLVQRZD\WRFOHDUWKH
33%/RFN%LW
(QWU\FRPPDQGVHTXHQFHPXVWEHLVVXHGSULRUWRDQ\RIDQ\RSHUDWLRQDQGLWGLVDEOHVUHDGV
DQGZULWHVIRU%DQN5HDGVDQGZULWHVIRURWKHUEDQNVH[FOXGLQJ%DQNDUHDOORZHG
,IWKHXVHUDWWHPSWVWRSURJUDPRUHUDVHDSURWHFWHGVHFWRUWKHGHYLFHLJQRUHVWKHFRPPDQG
DQGUHWXUQVWRUHDGPRGH
$SURJUDPRUHUDVHFRPPDQGWRDSURWHFWHGVHFWRUHQDEOHVVWDWXVSROOLQJDQGUHWXUQVWRUHDG
PRGHZLWKRXWKDYLQJPRGLILHGWKHFRQWHQWVRIWKHSURWHFWHGVHFWRU
7KHSURJUDPPLQJRIWKH'<%33%DQG33%/RFNIRUDJLYHQVHFWRUFDQEHYHULILHGE\ZULWLQJ
LQGLYLGXDOVWDWXVUHDGFRPPDQGV'<%6WDWXV33%6WDWXVDQG33%/RFN6WDWXVWRWKHGHYLFH
64
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
* Not on future devices
Program Data (PD): See text for Lock Register
definitions
Caution: Lock register can only be progammed
once.
Wait 4 µs
(Recommended)
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
DQ5 = 1?
No
Error condition (Exceeded Timing Limits)
Yes
PASS. Write Lock Register
Exit Command:
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
FAIL. Write rest command
to return to reading array.
Figure 13.3. Lock Register Program Algorithm
December 3, 2005 S29WS-N_m0_I0
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P r e l i m i n a r y
13.6
Advanced Sector Protection Software Examples
Table 13.2 Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked
1 = unlocked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Sector Protection Status
$Q\6HFWRU
[
3URWHFWHGWKURXJK33%
$Q\6HFWRU
[
3URWHFWHGWKURXJK33%
$Q\6HFWRU
8QSURWHFWHG
$Q\6HFWRU
3URWHFWHGWKURXJK'<%
$Q\6HFWRU
[
3URWHFWHGWKURXJK33%
$Q\6HFWRU
[
3URWHFWHGWKURXJK33%
$Q\6HFWRU
3URWHFWHGWKURXJK'<%
$Q\6HFWRU
8QSURWHFWHG
7DEOHFRQWDLQVDOOSRVVLEOHFRPELQDWLRQVRIWKH'<%33%DQG33%/RFN%LWUHODWLQJWRWKH
VWDWXVRIWKHVHFWRU,QVXPPDU\LIWKH33%/RFN%LWLVORFNHGVHWWR³´QRFKDQJHVWRWKH
33%VDUHDOORZHG7KH33%/RFN%LWFDQRQO\EHXQORFNHGUHVHWWR³´WKURXJKDKDUGZDUHUHVHW
RUSRZHUF\FOH6HHDOVR)LJXUHIRUDQRYHUYLHZRIWKH$GYDQFHG6HFWRU3URWHFWLRQIHDWXUH
13.7
Hardware Data Protection Methods
7KHGHYLFHRIIHUVWZRPDLQW\SHVRIGDWDSURWHFWLRQDWWKHVHFWRUOHYHOYLDKDUGZDUHFRQWURO
„
:KHQ:3LVDW9,/WKHIRXURXWHUPRVWVHFWRUVDUHORFNHGGHYLFHVSHFLILF
„ :KHQ$&&LVDW9,/DOOVHFWRUVDUHORFNHG
7KHUHDUHDGGLWLRQDOPHWKRGVE\ZKLFKLQWHQGHGRUDFFLGHQWDOHUDVXUHRIDQ\VHFWRUVFDQEHSUH
YHQWHGYLDKDUGZDUHPHDQV7KHIROORZLQJVXEVHFWLRQVGHVFULEHVWKHVHPHWKRGV
:30HWKRG
7KH:ULWH3URWHFWIHDWXUHSURYLGHVDKDUGZDUHPHWKRGRISURWHFWLQJWKHIRXURXWHUPRVWVHFWRUV
7KLVIXQFWLRQLVSURYLGHGE\WKH:3SLQDQGRYHUULGHVWKHSUHYLRXVO\GLVFXVVHG6HFWRU3URWHF
WLRQ8QSURWHFWLRQPHWKRG
,IWKHV\VWHPDVVHUWV9,/RQWKH:3SLQWKHGHYLFHGLVDEOHVSURJUDPDQGHUDVHIXQFWLRQVLQWKH
³RXWHUPRVW´ERRWVHFWRUV7KHRXWHUPRVWERRWVHFWRUVDUHWKHVHFWRUVFRQWDLQLQJERWKWKHORZHU
DQGXSSHUVHWRIVHFWRUVLQDGXDOERRWFRQILJXUHGGHYLFH
,IWKHV\VWHPDVVHUWV9,+RQWKH:3SLQWKHGHYLFHUHYHUWVWRZKHWKHUWKHERRWVHFWRUVZHUH
ODVWVHWWREHSURWHFWHGRUXQSURWHFWHG7KDWLVVHFWRUSURWHFWLRQRUXQSURWHFWLRQIRUWKHVHVHF
WRUVGHSHQGVRQZKHWKHUWKH\ZHUHODVWSURWHFWHGRUXQSURWHFWHG
1RWHWKDWWKH:3SLQPXVWQRWEHOHIWIORDWLQJRUXQFRQQHFWHGDVLQFRQVLVWHQWEHKDYLRURIWKH
GHYLFHPD\UHVXOW
7KH:3SLQPXVWEHKHOGVWDEOHGXULQJDFRPPDQGVHTXHQFHH[HFXWLRQ
$&&0HWKRG
7KLVPHWKRGLVVLPLODUWRDERYHH[FHSWLWSURWHFWVDOOVHFWRUV2QFH$&&LQSXWLVVHWWR9,/DOO
SURJUDPDQGHUDVHIXQFWLRQVDUHGLVDEOHGDQGKHQFHDOOVHFWRUVDUHSURWHFWHG
66
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
/RZ9&&:ULWH,QKLELW
:KHQ9&&LVOHVVWKDQ9/.2WKHGHYLFHGRHVQRWDFFHSWDQ\ZULWHF\FOHV7KLVSURWHFWVGDWDGXU
LQJ9&&SRZHUXSDQGSRZHUGRZQ
7KHFRPPDQGUHJLVWHUDQGDOOLQWHUQDOSURJUDPHUDVHFLUFXLWVDUHGLVDEOHGDQGWKHGHYLFHUHVHWV
WRUHDGLQJDUUD\GDWD6XEVHTXHQWZULWHVDUHLJQRUHGXQWLO9&&LVJUHDWHUWKDQ9/.27KHV\VWHP
PXVWSURYLGHWKHSURSHUVLJQDOVWRWKHFRQWUROLQSXWVWRSUHYHQWXQLQWHQWLRQDOZULWHVZKHQ9&&
LVJUHDWHUWKDQ9/.2
:ULWH3XOVH³*OLWFK3URWHFWLRQ´
1RLVHSXOVHVRIOHVVWKDQQVW\SLFDORQ2(&(RU:(GRQRWLQLWLDWHDZULWHF\FOH
3RZHU8S:ULWH,QKLELW
,I:( &( 5(6(7 9,/DQG2( 9,+GXULQJSRZHUXSWKHGHYLFHGRHVQRWDFFHSW
FRPPDQGVRQWKHULVLQJHGJHRI:(7KHLQWHUQDOVWDWHPDFKLQHLVDXWRPDWLFDOO\UHVHWWRWKH
UHDGPRGHRQSRZHUXS
December 3, 2005 S29WS-N_m0_I0
67
P r e l i m i n a r y
14 Power Conservation Modes
14.1
Standby Mode
:KHQWKHV\VWHPLVQRWUHDGLQJRUZULWLQJWRWKHGHYLFHLWFDQSODFHWKHGHYLFHLQWKHVWDQGE\
PRGH,QWKLVPRGHFXUUHQWFRQVXPSWLRQLVJUHDWO\UHGXFHGDQGWKHRXWSXWVDUHSODFHGLQWKH
KLJKLPSHGDQFHVWDWHLQGHSHQGHQWRIWKH2(LQSXW7KHGHYLFHHQWHUVWKH&026VWDQGE\PRGH
ZKHQWKH&(DQG5(6(7LQSXWVDUHERWKKHOGDW9&&“97KHGHYLFHUHTXLUHVVWDQGDUG
DFFHVVWLPHW&(IRUUHDGDFFHVVEHIRUHLWLVUHDG\WRUHDGGDWD,IWKHGHYLFHLVGHVHOHFWHGGXU
LQJHUDVXUHRUSURJUDPPLQJWKHGHYLFHGUDZVDFWLYHFXUUHQWXQWLOWKHRSHUDWLRQLVFRPSOHWHG
,&&LQ³'&&KDUDFWHULVWLFV´UHSUHVHQWVWKHVWDQGE\FXUUHQWVSHFLILFDWLRQ
14.2
Automatic Sleep Mode
7KHDXWRPDWLFVOHHSPRGHPLQLPL]HV)ODVKGHYLFHHQHUJ\FRQVXPSWLRQZKLOHLQDV\QFKURQRXV
PRGHWKHGHYLFHDXWRPDWLFDOO\HQDEOHVWKLVPRGHZKHQDGGUHVVHVUHPDLQVWDEOHIRUW$&&
QV7KHDXWRPDWLFVOHHSPRGHLVLQGHSHQGHQWRIWKH&(:(DQG2(FRQWUROVLJQDOV6WDQ
GDUG DGGUHVVDFFHVVWLPLQJVSURYLGHQHZGDWD ZKHQDGGUHVVHV DUHFKDQJHG:KLOHLQVOHHS
PRGHRXWSXWGDWDLVODWFKHGDQGDOZD\VDYDLODEOHWRWKHV\VWHP:KLOHLQV\QFKURQRXVPRGH
WKHDXWRPDWLFVOHHSPRGHLVGLVDEOHG1RWHWKDWDQHZEXUVWRSHUDWLRQLVUHTXLUHGWRSURYLGHQHZ
GDWD,&&LQ'&&KDUDFWHULVWLFV&026&RPSDWLEOHUHSUHVHQWVWKHDXWRPDWLFVOHHSPRGHFXU
UHQWVSHFLILFDWLRQ
14.3
Hardware RESET# Input Operation
7KH5(6(7LQSXWSURYLGHVDKDUGZDUHPHWKRGRIUHVHWWLQJWKHGHYLFHWRUHDGLQJDUUD\GDWD
:KHQ5(6(7LVGULYHQORZIRUDWOHDVWDSHULRGRIW53WKHGHYLFHLPPHGLDWHO\WHUPLQDWHVDQ\
RSHUDWLRQLQSURJUHVVWULVWDWHVDOORXWSXWVUHVHWVWKHFRQILJXUDWLRQUHJLVWHUDQGLJQRUHVDOOUHDG
ZULWHFRPPDQGVIRUWKHGXUDWLRQRIWKH5(6(7SXOVH7KHGHYLFHDOVRUHVHWVWKHLQWHUQDOVWDWH
PDFKLQHWRUHDGLQJDUUD\GDWD7KHRSHUDWLRQWKDWZDVLQWHUUXSWHGVKRXOGEHUHLQLWLDWHGRQFHWKH
GHYLFHLVUHDG\WRDFFHSWDQRWKHUFRPPDQGVHTXHQFHWRHQVXUHGDWDLQWHJULW\
:KHQ5(6(7LVKHOGDW966“9WKHGHYLFHGUDZV&026VWDQGE\FXUUHQW,&&,I5(6(7
LVKHOGDW9,/EXWQRWZLWKLQ966“9WKHVWDQGE\FXUUHQWLVJUHDWHU
5(6(7PD\EHWLHGWRWKHV\VWHPUHVHWFLUFXLWU\DQGWKXVDV\VWHPUHVHWZRXOGDOVRUHVHWWKH
)ODVKPHPRU\HQDEOLQJWKHV\VWHPWRUHDGWKHERRWXSILUPZDUHIURPWKH)ODVKPHPRU\
14.4
Output Disable (OE#)
:KHQWKH2(LQSXWLVDW9,+RXWSXWIURPWKHGHYLFHLVGLVDEOHG7KHRXWSXWVDUHSODFHGLQWKH
KLJKLPSHGDQFHVWDWH
68
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
15 Secured Silicon Sector Flash Memory Region
7KH6HFXUHG6LOLFRQ6HFWRUSURYLGHVDQH[WUD)ODVKPHPRU\UHJLRQWKDWHQDEOHVSHUPDQHQWSDUW
LGHQWLILFDWLRQWKURXJKDQ(OHFWURQLF6HULDO1XPEHU(617KH6HFXUHG6LOLFRQ6HFWRULV
ZRUGVLQOHQJWKWKDWFRQVLVWVRIZRUGVIRUIDFWRU\GDWDDQGZRUGVIRUFXVWRPHUVHFXUHG
DUHDV$OO6HFXUHG6LOLFRQUHDGVRXWVLGHRIWKHZRUGDGGUHVVUDQJHUHWXUQVLQYDOLGGDWD7KH
)DFWRU\,QGLFDWRU%LW'4DW$XWRVHOHFWDGGUHVVKLVXVHGWRLQGLFDWHZKHWKHURUQRWWKH
)DFWRU\6HFXUHG6LOLFRQ6HFWRULVORFNHGZKHQVKLSSHGIURPWKHIDFWRU\7KH&XVWRPHU,QGLFDWRU
%LW'4LVXVHGWRLQGLFDWHZKHWKHURUQRWWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRULVORFNHGZKHQ
VKLSSHGIURPWKHIDFWRU\
3OHDVHQRWHWKHIROORZLQJJHQHUDOFRQGLWLRQV
„
:KLOH6HFXUHG6LOLFRQ6HFWRUDFFHVVLVHQDEOHGVLPXOWDQHRXVRSHUDWLRQVDUHDOORZHGH[FHSW
IRU%DQN
„
2QSRZHUXSRUIROORZLQJDKDUGZDUHUHVHWWKHGHYLFHUHYHUWVWRVHQGLQJFRPPDQGVWRWKH
QRUPDODGGUHVVVSDFH
„
5HDGVFDQEHSHUIRUPHGLQWKH$V\QFKURQRXVRU6\QFKURQRXVPRGH
„
%XUVWPRGHUHDGVZLWKLQ6HFXUHG6LOLFRQ6HFWRUZUDSIURPDGGUHVV))KEDFNWRDGGUHVVK
„
5HDGVRXWVLGHRIVHFWRUUHWXUQPHPRU\DUUD\GDWD
„
&RQWLQXRXVEXUVWUHDGSDVWWKHPD[LPXPDGGUHVVLVXQGHILQHG
„
6HFWRULVUHPDSSHGIURPPHPRU\DUUD\WR6HFXUHG6LOLFRQ6HFWRUDUUD\
„
2QFHWKH6HFXUHG6LOLFRQ6HFWRU(QWU\&RPPDQGLVLVVXHGWKH6HFXUHG6LOLFRQ6HFWRU([LW
FRPPDQGPXVWEHLVVXHGWRH[LW6HFXUHG6LOLFRQ6HFWRU0RGH
„
7KH6HFXUHG6LOLFRQ6HFWRULVQRWDFFHVVLEOHZKHQWKHGHYLFHLVH[HFXWLQJDQ(PEHGGHG3UR
JUDPRU(PEHGGHG(UDVHDOJRULWKP
Table 15.1
Sector
&XVWRPHU
)DFWRU\
15.1
Secured Silicon Sector Addresses
Sector Size
ZRUGV
ZRUGV
Address Range
K))K
K)K
Factory Secured Silicon Sector
7KH)DFWRU\6HFXUHG6LOLFRQ6HFWRULVDOZD\VSURWHFWHGZKHQVKLSSHGIURPWKHIDFWRU\DQGKDV
WKH)DFWRU\,QGLFDWRU%LW'4SHUPDQHQWO\VHWWRD³´7KLVSUHYHQWVFORQLQJRIDIDFWRU\ORFNHG
SDUWDQGHQVXUHVWKHVHFXULW\RIWKH(61DQGFXVWRPHUFRGHRQFHWKHSURGXFWLVVKLSSHGWRWKH
ILHOG
7KHVHGHYLFHVDUHDYDLODEOHSUHSURJUDPPHGZLWKRQHRIWKHIROORZLQJ
„
$UDQGRP:RUGVHFXUH(61RQO\ZLWKLQWKH)DFWRU\6HFXUHG6LOLFRQ6HFWRU
„
&XVWRPHUFRGHZLWKLQWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUWKURXJKWKH6SDQVLRQ70SURJUDP
PLQJVHUYLFH
„
%RWKDUDQGRPVHFXUH(61DQGFXVWRPHUFRGHWKURXJKWKH6SDQVLRQSURJUDPPLQJVHUYLFH
&XVWRPHUVPD\RSWWRKDYHWKHLUFRGHSURJUDPPHGWKURXJKWKH6SDQVLRQSURJUDPPLQJVHU
YLFHV6SDQVLRQSURJUDPVWKHFXVWRPHU
VFRGHZLWKRUZLWKRXWWKHUDQGRP(617KHGHYLFHVDUH
WKHQVKLSSHGIURPWKH6SDQVLRQIDFWRU\ZLWKWKH)DFWRU\6HFXUHG6LOLFRQ6HFWRUDQG&XVWRPHU
6HFXUHG6LOLFRQ6HFWRUSHUPDQHQWO\ORFNHG&RQWDFW\RXUORFDOUHSUHVHQWDWLYHIRUGHWDLOVRQXVLQJ
6SDQVLRQSURJUDPPLQJVHUYLFHV
December 3, 2005 S29WS-N_m0_I0
69
P r e l i m i n a r y
15.2
Customer Secured Silicon Sector
7KH&XVWRPHU6HFXUHG6LOLFRQ6HFWRULVW\SLFDOO\VKLSSHGXQSURWHFWHG'4VHWWR³´DOORZLQJ
FXVWRPHUVWRXWLOL]HWKDWVHFWRULQDQ\PDQQHUWKH\FKRRVH,IWKHVHFXULW\IHDWXUHLVQRWUHTXLUHG
WKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUFDQEHWUHDWHGDVDQDGGLWLRQDO)ODVKPHPRU\VSDFH
3OHDVHQRWHWKHIROORZLQJ
15.3
„
2QFHWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUDUHDLVSURWHFWHGWKH&XVWRPHU,QGLFDWRU%LWLV
SHUPDQHQWO\VHWWR³´
„
7KH &XVWRPHU 6HFXUHG 6LOLFRQ 6HFWRU FDQ EH UHDG DQ\ QXPEHU RI WLPHV EXW FDQ EH SUR
JUDPPHGDQGORFNHGRQO\RQFH7KH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUORFNPXVWEHXVHGZLWK
FDXWLRQDVRQFHORFNHGWKHUHLVQRSURFHGXUHDYDLODEOHIRUXQORFNLQJWKH&XVWRPHU6HFXUHG
6LOLFRQ6HFWRUDUHDDQGQRQHRIWKHELWVLQWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUPHPRU\
VSDFHFDQEHPRGLILHGLQDQ\ZD\
„
7KH DFFHOHUDWHG SURJUDPPLQJ $&& DQG XQORFN E\SDVV IXQFWLRQV DUH QRW DYDLODEOH ZKHQ
SURJUDPPLQJWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRUEXWUHDGLQJLQ%DQNVWKURXJKLV
DYDLODEOH
„
2QFHWKH&XVWRPHU6HFXUHG6LOLFRQ6HFWRULVORFNHGDQGYHULILHGWKHV\VWHPPXVWZULWHWKH
([LW6HFXUHG6LOLFRQ6HFWRU5HJLRQFRPPDQGVHTXHQFHZKLFKUHWXUQWKHGHYLFHWRWKHPHP
RU\DUUD\DWVHFWRU
Secured Silicon Sector Entry/Exit Command Sequences
7KHV\VWHPFDQDFFHVVWKH6HFXUHG6LOLFRQ6HFWRUUHJLRQE\LVVXLQJWKHWKUHHF\FOH(QWHU6H
FXUHG6LOLFRQ6HFWRUFRPPDQGVHTXHQFH7KHGHYLFHFRQWLQXHVWRDFFHVVWKH6HFXUHG6LOLFRQ
6HFWRU UHJLRQ XQWLO WKH V\VWHP LVVXHV WKH IRXUF\FOH ([LW 6HFXUHG 6LOLFRQ 6HFWRU FRPPDQG
VHTXHQFH
6HH&RPPDQG'HILQLWLRQ7DEOH>6HFXUHG6LOLFRQ6HFWRU&RPPDQG7DEOH$SSHQGL[
7DEOHIRUDGGUHVVDQGGDWDUHTXLUHPHQWVIRUERWKFRPPDQGVHTXHQFHV
7KH6HFXUHG6LOLFRQ6HFWRU(QWU\&RPPDQGDOORZVWKHIROORZLQJFRPPDQGVWREHH[HFXWHG
„
5HDGFXVWRPHUDQGIDFWRU\6HFXUHG6LOLFRQDUHDV
„
3URJUDPWKHFXVWRPHU6HFXUHG6LOLFRQ6HFWRU
$IWHUWKHV\VWHPKDVZULWWHQWKH(QWHU6HFXUHG6LOLFRQ6HFWRUFRPPDQGVHTXHQFHLWPD\UHDG
WKH6HFXUHG6LOLFRQ6HFWRUE\XVLQJWKHDGGUHVVHVQRUPDOO\RFFXSLHGE\VHFWRU6$ZLWKLQWKH
PHPRU\DUUD\7KLVPRGHRIRSHUDWLRQFRQWLQXHVXQWLOWKHV\VWHPLVVXHVWKH([LW6HFXUHG6LOLFRQ
6HFWRUFRPPDQGVHTXHQFHRUXQWLOSRZHULVUHPRYHGIURPWKHGHYLFH
Software Functions and Sample Code
7KHIROORZLQJDUH&IXQFWLRQVDQGVRXUFHFRGHH[DPSOHVRIXVLQJWKH6HFXUHG6LOLFRQ6HFWRU(QWU\
3URJUDPDQGH[LWFRPPDQGV5HIHUWRWKH6SDQVLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOH
VRRQRQZZZDPGFRPDQGZZZIXMLWVXFRPIRUJHQHUDOLQIRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\
VRIWZDUHGHYHORSPHQWJXLGHOLQHV
70
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 15.2.
Secured Silicon Sector Entry
//')XQFWLRQ OOGB6HF6L6HFWRU(QWU\&PG
Cycle
Operation
Byte Address
Word Address
Data
8QORFN&\FOH
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN&\FOH
:ULWH
%DVHK
%DVH$$K
K
(QWU\&\FOH
:ULWH
%DVH$$$K
%DVHK
K
1RWH%DVH %DVH$GGUHVV
/* Example: SecSi Sector
*( (UINT16 *)base_addr
*( (UINT16 *)base_addr
*( (UINT16 *)base_addr
Entry Command */
+ 0x555 ) = 0x00AA;
+ 0x2AA ) = 0x0055;
+ 0x555 ) = 0x0088;
Table 15.3.
/* write unlock cycle 1
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
*/
*/
*/
Secured Silicon Sector Program
//')XQFWLRQ OOGB3URJUDP&PG
Cycle
Operation
Byte Address
Word Address
Data
8QORFN&\FOH
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN&\FOH
:ULWH
%DVHK
%DVH$$K
K
3URJUDP6HWXS
:ULWH
%DVH$$$K
%DVHK
$K
3URJUDP
:ULWH
:RUG$GGUHVV
:RUG$GGUHVV
'DWD:RUG
1RWH%DVH %DVH$GGUHVV
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm.
*/
Table 15.4.
Secured Silicon Sector Exit
//')XQFWLRQ OOGB6HF6L6HFWRU([LW&PG
Cycle
Operation
Byte Address
Word Address
Data
8QORFN&\FOH
:ULWH
%DVH$$$K
%DVHK
$$K
8QORFN&\FOH
:ULWH
%DVHK
%DVH$$K
K
([LW&\FOH
:ULWH
%DVH$$$K
%DVHK
K
1RWH%DVH %DVH$GGUHVV
/* Example: SecSi Sector
*( (UINT16 *)base_addr
*( (UINT16 *)base_addr
*( (UINT16 *)base_addr
*( (UINT16 *)base_addr
December 3, 2005 S29WS-N_m0_I0
Exit Command */
+ 0x555 ) = 0x00AA;
+ 0x2AA ) = 0x0055;
+ 0x555 ) = 0x0090;
+ 0x000 ) = 0x0000;
/*
/*
/*
/*
write
write
write
write
unlock cycle
unlock cycle
SecSi Sector
SecSi Sector
1
2
Exit cycle 3
Exit cycle 4
*/
*/
*/
*/
71
P r e l i m i n a r y
16 Electrical Specifications
16.1
Absolute Maximum Ratings
6WRUDJH7HPSHUDWXUH
3ODVWLF3DFNDJHV±ƒ&WRƒ&
$PELHQW7HPSHUDWXUH
ZLWK3RZHU$SSOLHG ±ƒ&WRƒ&
9ROWDJHZLWK5HVSHFWWR*URXQG
$OO,QSXWVDQG,2VH[FHSW
DVQRWHGEHORZ1RWH ±9WR9&&9
9&&1RWH±9WR9
$&&1RWH ±9WR9
2XWSXW6KRUW&LUFXLW&XUUHQW1RWH P$
1RWHV
0LQLPXP'&YROWDJHRQLQSXWRU,2VLV±9'XULQJYROWDJHWUDQVLWLRQVLQSXWVRU
,2VPD\XQGHUVKRRW966WR±9IRUSHULRGVRIXSWRQV6HH)LJXUH
0D[LPXP'&YROWDJHRQLQSXWRU,2VLV9&&9'XULQJYROWDJHWUDQVLWLRQV
RXWSXWVPD\RYHUVKRRWWR9&&9IRUSHULRGVXSWRQV6HH)LJXUH
0LQLPXP'&LQSXWYROWDJHRQSLQ$&&LV9'XULQJYROWDJHWUDQVLWLRQV$&&PD\
RYHUVKRRW966WR±9IRUSHULRGVRIXSWRQV6HH)LJXUH0D[LPXP'&
YROWDJHRQSLQ$&&LV9ZKLFKPD\RYHUVKRRWWR9IRUSHULRGVXSWRQV
1RPRUHWKDQRQHRXWSXWPD\EHVKRUWHGWRJURXQGDWDWLPH'XUDWLRQRIWKHVKRUW
FLUFXLWVKRXOGQRWEHJUHDWHUWKDQRQHVHFRQG
6WUHVVHVDERYHWKRVHOLVWHGXQGHU³$EVROXWH0D[LPXP5DWLQJV´PD\FDXVHSHUPDQHQW
GDPDJHWRWKHGHYLFH7KLVLVDVWUHVVUDWLQJRQO\IXQFWLRQDORSHUDWLRQRIWKHGHYLFHDW
WKHVHRUDQ\RWKHUFRQGLWLRQVDERYHWKRVHLQGLFDWHGLQWKHRSHUDWLRQDOVHFWLRQVRIWKLV
GDWDVKHHWLVQRWLPSOLHG([SRVXUHRIWKHGHYLFHWRDEVROXWHPD[LPXPUDWLQJFRQGLWLRQV
IRUH[WHQGHGSHULRGVPD\DIIHFWGHYLFHUHOLDELOLW\
20 ns
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
+0.8 V
–0.5 V
–2.0 V
1.0 V
20 ns
Figure 16.1. Maximum Negative Overshoot
Waveform
20 ns
20 ns
Figure 16.2. Maximum Positive Overshoot
Waveform
1RWH7KHFRQWHQWLQWKLVGRFXPHQWLV$GYDQFHLQIRUPDWLRQIRUWKH6:61&RQWHQWLQWKLVGRFX
PHQWLV3UHOLPLQDU\IRUWKH6:1
72
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
16.2
Operating Ranges
:LUHOHVV:'HYLFHV
$PELHQW7HPSHUDWXUH7$ ±ƒ&WRƒ&
6XSSO\9ROWDJHV
9&&6XSSO\9ROWDJHV 9WR9
1RWHV 2SHUDWLQJUDQJHVGHILQHWKRVHOLPLWVEHWZHHQZKLFKWKHIXQFWLRQDOLW\RIWKHGHYLFH
LVJXDUDQWHHG
16.3
Test Conditions
Device
Under
Test
CL
Figure 16.3.
Table 16.1
Test Specifications
Test Condition
All Speed Options
Unit
2XWSXW/RDG&DSDFLWDQFH&/
LQFOXGLQJMLJFDSDFLWDQFH
S)
,QSXW5LVHDQG)DOO7LPHV
#0+]
#0+]
QV
±9&&
9
,QSXWWLPLQJPHDVXUHPHQW
UHIHUHQFHOHYHOV
9&&
9
2XWSXWWLPLQJPHDVXUHPHQW
UHIHUHQFHOHYHOV
9&&
9
,QSXW3XOVH/HYHOV
December 3, 2005 S29WS-N_m0_I0
Test Setup
73
P r e l i m i n a r y
16.4
Key to Switching Waveforms
Waveform
Inputs
Outputs
6WHDG\
&KDQJLQJIURP+WR/
&KDQJLQJIURP/WR+
16.5
'RQ¶W&DUH$Q\&KDQJH3HUPLWWHG
&KDQJLQJ6WDWH8QNQRZQ
'RHV1RW$SSO\
&HQWHU/LQHLV+LJK,PSHGDQFH6WDWH+LJK=
Switching Waveforms
VCC
All Inputs and Outputs
Input
VCC/2
VCC/2
Measurement Level
Output
0.0 V
Figure 16.4. Input Waveforms and Measurement Levels
16.6
VCC Power-up
Parameter
Description
Test Setup
Speed
Unit
W9&6
9&&6HWXS7LPH
0LQ
PV
1RWHV
$OO9&&VLJQDOVPXVWEHUDPSHGVLPXOWDQHRXVO\WRHQVXUHFRUUHFWSRZHUXS
6:619&&UDPSUDWHLV!9 —VDQGIRU9&&UDPSUDWHRI 9
—VDKDUGZDUHUHVHWLVUHTXLUHG
tVCS
VCC
RESET#
Figure 16.5. VCC Power-up Diagram
74
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
16.7
DC Characteristics (CMOS Compatible)
3DUDPHWHU
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7HVW&RQGLWLRQV1RWHV
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&( 9,/2( 9,+
:( 9,+EXUVWOHQJWK
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&( 9,/2( 9,+
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9&&$FWLYH$V\QFKURQRXV
5HDG&XUUHQW
&( 9,/2( 9,+
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&(PXVWEHVHWKLJKZKHQPHDVXULQJWKH5'<SLQ
7KH,&&FXUUHQWOLVWHGLVW\SLFDOO\OHVVWKDQP$0+]ZLWK2(DW9,+
,&&DFWLYHZKLOH(PEHGGHG(UDVHRU(PEHGGHG3URJUDPLVLQSURJUHVV
'HYLFHHQWHUVDXWRPDWLFVOHHSPRGHZKHQDGGUHVVHVDUHVWDEOHIRUW$&&QV
7\SLFDOVOHHSPRGHFXUUHQWLVHTXDOWR,&&
9,+ 9&&“9DQG9,/!±9
7RWDOFXUUHQWGXULQJDFFHOHUDWHGSURJUDPPLQJLVWKHVXPRI9$&&DQG9&&
FXUUHQWV
9$&& 9++RQ$&&LQSXW
December 3, 2005 S29WS-N_m0_I0
75
P r e l i m i n a r y
16.8
AC Characteristics
&/.&KDUDFWHUL]DWLRQ
Parameter
Description
54 MHz
66 MHz
80 MHz
Unit
I&/.
&/.)UHTXHQF\
0D[
0+]
W&/.
&/.3HULRG
0LQ
QV
W&+
&/.+LJK7LPH
W&/
&/./RZ7LPH
0LQ
QV
W&5
&/.5LVH7LPH
W&)
&/.)DOO7LPH
0D[
QV
1RWH 1RWWHVWHG
tCLK
tCH
CLK
tCR
tCL
tCF
Figure 16.6. CLK Characterization
76
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
6\QFKURQRXV%XUVW5HDG
Parameter
JEDEC
Standard
Description
54 MHz
66 MHz
80 MHz
W,$&&
/DWHQF\
0D[
W%$&&
%XUVW$FFHVV7LPH9DOLG&ORFNWR2XWSXW'HOD\
0D[
W$&6
$GGUHVV6HWXS7LPHWR&/.1RWH
0LQ
QV
W$&+
$GGUHVV+ROG7LPHIURP&/.1RWH
0LQ
QV
W%'+
'DWD+ROG7LPHIURP1H[W&ORFN&\FOH
0LQ
QV
W&5
&KLS(QDEOHWR5'<9DOLG
0D[
W2(
2XWSXW(QDEOHWR2XWSXW9DOLG
0D[
W&(=
&KLS(QDEOHWR+LJK=1RWH
0D[
QV
W2(=
2XWSXW(QDEOHWR+LJK=1RWH
0D[
QV
W&(6
&(6HWXS7LPHWR&/.
0LQ
QV
W5'<6
5'<6HWXS7LPHWR&/.
0LQ
QV
W5$&&
5HDG\$FFHVV7LPHIURP&/.
0D[
QV
W&$6
&(6HWXS7LPHWR$9'
0LQ
QV
W$9&
$9'/RZWR&/.
0LQ
QV
W$9'
$9'3XOVH
0LQ
QV
W$9'+
$9'+ROG
0LQ
QV
0LQLPXPFORFNIUHTXHQF\
0LQ
I&/.
Unit
QV
QV
QV
QV
0+]
1RWHV
$GGUHVVHVDUHODWFKHGRQWKHILUVWULVLQJHGJHRI&/.
1RWWHVWHG
Table 16.2 Synchronous Wait State Requirements
0D[)UHTXHQF\
:DLW6WDWH5HTXLUHPHQW
0+])UHT≤ 0+]
0+])UHT≤ 0+]
0+])UHT≤ 0+]
0+])UHT≤ 0+]
0+])UHT≤ 0+]
0+])UHT≤ 0+]
December 3, 2005 S29WS-N_m0_I0
77
P r e l i m i n a r y
7LPLQJ'LDJUDPV
5 cycles for initial access shown.
tCES
tCEZ
18.5 ns typ. (54 MHz)
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tAVDH
tACS
Addresses
Aa
tBACC
tACH
Hi-Z
Data (n)
tIACC
Da
Da + 1
Da + 2
Da + n
Da + 3
tOEZ
tBDH
OE#
tRACC
tOE
RDY (n)
Hi-Z
Hi-Z
tCR
tRDYS
Hi-Z
Data (n + 1)
Da
RDY (n + 1)
Da + 1
Da + 2
Da + n
Da + 2
Hi-Z
Hi-Z
Hi-Z
Data (n + 2)
Da
RDY (n + 2)
Da + 1
Da + 1
Da + n
Da + 1
Hi-Z
Hi-Z
Hi-Z
Data (n + 3)
Da
RDY (n + 3)
Da
Da
Da + n
Da
Hi-Z
Hi-Z
1RWHV
)LJXUHVKRZVWRWDOQXPEHURIZDLWVWDWHVVHWWRILYHF\FOHV7KHWRWDOQXPEHURI
ZDLWVWDWHVFDQEHSURJUDPPHGIURPWZRF\FOHVWRVHYHQF\FOHV
,IDQ\EXUVWDGGUHVVRFFXUVDW³DGGUHVV´³DGGUHVV´RU³DGGUHVV´
DGGLWLRQDOFORFNGHOD\F\FOHVDUHLQVHUWHGDQGDUHLQGLFDWHGE\5'<
7KHGHYLFHLVLQV\QFKURQRXVPRGH
Figure 16.7.
78
CLK Synchronous Burst Mode Read
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
7 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVDH
tAVD
tACS
Addresses
Ac
tBACC
tACH
Data
tIACC
DC
DE
DD
DF
DB
D8
tBDH
OE#
tCR
RDY
tRACC
tRACC
tOE
Hi-Z
tRDYS
1RWHV
)LJXUHVKRZVWRWDOQXPEHURIZDLWVWDWHVVHWWRVHYHQF\FOHV7KHWRWDOQXPEHURIZDLWVWDWHVFDQEHSURJUDPPHGIURPWZRF\FOHVWRVHYHQ
F\FOHV
,IDQ\EXUVWDGGUHVVRFFXUVDW³DGGUHVV´³DGGUHVV´RU³DGGUHVV´DGGLWLRQDOFORFNGHOD\F\FOHVDUHLQVHUWHGDQGDUHLQGLFDWHG
E\5'<
7KHGHYLFHLVLQV\QFKURQRXVPRGHZLWKZUDSDURXQG
'±')LQGDWDZDYHIRUPLQGLFDWHWKHRUGHURIGDWDZLWKLQDJLYHQZRUGDGGUHVVUDQJHIURPORZHVWWRKLJKHVW6WDUWLQJDGGUHVVLQILJXUH
LVWKHWKDGGUHVVLQUDQJH)
Figure 16.8.
tCES
7
8-word Linear Burst with Wrap Around
cycles for initial access shown.
CE#
1
2
3
4
5
6
7
CLK
tAVC
tAVDH
AVD#
tAVD
tACS
Addresses
Ac
tBACC
tACH
Data
tIACC
DC
DD
DE
DF
D8
DB
tBDH
OE#
tCR
RDY
tOE
tRACC
tRACC
Hi-Z
tRDYS
1RWHV
)LJXUHVKRZVWRWDOQXPEHURIZDLWVWDWHVVHWWRVHYHQF\FOHV7KHWRWDOQXPEHURIZDLWVWDWHVFDQEHSURJUDPPHGIURPWZRF\FOHVWRVHYHQ
F\FOHV&ORFNLVVHWIRUDFWLYHULVLQJHGJH
,IDQ\EXUVWDGGUHVVRFFXUVDW³DGGUHVV´³DGGUHVV´RU³DGGUHVV´DGGLWLRQDOFORFNGHOD\F\FOHVDUHLQVHUWHGDQGDUHLQGLFDWHG
E\5'<
7KHGHYLFHLVLQDV\QFKURQRXVPRGHZLWKRXWZUDSDURXQG
'&±'LQGDWDZDYHIRUPLQGLFDWHWKHRUGHURIGDWDZLWKLQDJLYHQZRUGDGGUHVVUDQJHIURPORZHVWWRKLJKHVW6WDUWLQJDGGUHVVLQILJXUH
LVWKHVWDGGUHVVLQUDQJHF
Figure 16.9.
December 3, 2005 S29WS-N_m0_I0
8-word Linear Burst without Wrap Around
79
P r e l i m i n a r y
tCES
tCEZ
6 wait cycles for initial access shown.
CE#
~
~
5
6
7
~
~
tAVC
~
~
~
~
1
CLK
tAVDH
AVD#
tAVD
tACS
Addresses
Aa
tBACC
tACH
Hi-Z
Data
tIACC
Da
Da+1
Da+2
Da+3
Da + n
tBDH
tRACC
OE#
tCR
RDY
tOEZ
tOE
Hi-Z
Hi-Z
tRDYS
1RWHV
)LJXUHDVVXPHVZDLWVWDWHVIRULQLWLDODFFHVVDQGV\QFKURQRXVUHDG
7KH6HW&RQILJXUDWLRQ5HJLVWHUFRPPDQGVHTXHQFHKDVEHHQZULWWHQZLWK&5 GHYLFHRXWSXWV5'<RQHF\FOHEHIRUHYDOLGGDWD
Figure 16.10.
Linear Burst with RDY Set One Cycle Before Data
$&&KDUDFWHULVWLFV²$V\QFKURQRXV5HDG
3DUDPHWHU
-('(&
'HVFULSWLRQ
6WDQGDUG
0+]
0+]
0+]
8QLW
W&(
$FFHVV7LPHIURP&(/RZ
0D[
QV
W$&&
$V\QFKURQRXV$FFHVV7LPH
0D[
QV
W$9'3
$9'/RZ7LPH
0LQ
QV
W$$9'6
$GGUHVV6HWXS7LPHWR5LVLQJ(GJHRI$9'
0LQ
QV
W$$9'+
$GGUHVV+ROG7LPHIURP5LVLQJ(GJHRI$9'
0LQ
W2(
2XWSXW(QDEOHWR2XWSXW9DOLG
0D[
QV
5HDG
0LQ
QV
W2(+
2XWSXW(QDEOH+ROG7LPH
7RJJOHDQG
'DWD3ROOLQJ
0LQ
QV
W2(=
2XWSXW(QDEOHWR+LJK=VHH1RWH
0D[
QV
W&$6
&(6HWXS7LPHWR$9'
0LQ
QV
W3$&&
3DJH$FFHVV7LPH
0D[
QV
W2+
2XWSXW+ROG7LPH)URP$GGUHVVHV&(
RU2(ZKLFKHYHURFFXUVILUVW1RWH
0LQ
QV
&KLS(QDEOHWR2XWSXW7ULVWDWH
0D[
QV
W&(=
QV
1RWHV
80
1RWWHVWHG
W2(+ QVIRU6:61
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
CE#
tOE
OE#
tOEH
WE#
tCE
tOEZ
Data
Valid RD
tACC
RA
Addresses
tAAVDH
tCAS
AVD#
tAVDP
tAAVDS
1RWH 5$ 5HDG$GGUHVV5' 5HDG'DWD
Same Page Address
A0
A1
~
~
A1-A0
~
~
~
~
A22-A2
~
~
Figure 16.11. Asynchronous Mode Read
A2
A3
tCE
~
~
CE#
tCOEZ
tACC
~
~
AVD#
Optional
tOE
tPACC
OE#
Data
tOH
~
~
WE#
~
~
~
~
tOEZ
D0
tPACC
tOEZ
D1
D1
tOH
tPACC
D2
D3
tOH
Figure 16.12. Four-Word Page-Mode Operation
December 3, 2005 S29WS-N_m0_I0
81
P r e l i m i n a r y
+DUGZDUH5HVHW5(6(7
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
W53
5(6(73XOVH:LGWK
0LQ
—V
W5+
5HVHW+LJK7LPH%HIRUH5HDG6HH1RWH
0LQ
QV
1RWH1RWWHVWHG
CE#, OE#
tRH
RESET#
tRP
Figure 16.13.
82
Reset Timings
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
(UDVH3URJUDP7LPLQJ
Parameter
JEDEC
Standard
W$9$9
W:&
W$9:/
W:/$;
W$6
W$+
Description
54 MHz
:ULWH&\FOH7LPH1RWH
$GGUHVV6HWXS7LPH1RWHV
$GGUHVV+ROG7LPH1RWHV
0LQ
6\QFKURQRXV
$V\QFKURQRXV
6\QFKURQRXV
$V\QFKURQRXV
0LQ
66 MHz
80 MHz
QV
QV
QV
0LQ
Unit
QV
W$9'3
$9'/RZ7LPH
0LQ
W'9:+
W'6
'DWD6HWXS7LPH
0LQ
W:+';
W'+
'DWD+ROG7LPH
0LQ
W*+:/
W*+:/
5HDG5HFRYHU\7LPH%HIRUH:ULWH
0LQ
QV
W&$6
&(6HWXS7LPHWR$9'
0LQ
QV
W:+(+
W&+
&(+ROG7LPH
0LQ
QV
W:/:+
W:3
:ULWH3XOVH:LGWK
0LQ
QV
W:3+
:ULWH3XOVH:LGWK+LJK
0LQ
QV
W65:
/DWHQF\%HWZHHQ5HDGDQG:ULWH2SHUDWLRQV
0LQ
QV
W:+:/
W(/:/
QV
QV
QV
W9,'
9$&&5LVHDQG)DOO7LPH
0LQ
QV
W9,'6
9$&&6HWXS7LPH'XULQJ$FFHOHUDWHG3URJUDPPLQJ
0LQ
—V
QV
&(6HWXS7LPHWR:(
0LQ
W$96:
W&6
$9'6HWXS7LPHWR:(
0LQ
QV
W$9+:
$9'+ROG7LPHWR:(
0LQ
QV
W$96&
$9'6HWXS7LPHWR&/.
0LQ
QV
W$9+&
$9'+ROG7LPHWR&/.
0LQ
QV
W&6:
&ORFN6HWXS7LPHWR:(
0LQ
QV
W:(3
1RLVH3XOVH0DUJLQRQ:(
0D[
QV
W6($
6HFWRU(UDVH$FFHSW7LPHRXW
0D[
—V
W(6/
(UDVH6XVSHQG/DWHQF\
0D[
—V
W36/
3URJUDP6XVSHQG/DWHQF\
0D[
—V
W$63
7RJJOH7LPH'XULQJ(UDVHZLWKLQD3URWHFWHG6HFWRU
7\S
—V
W363
7RJJOH7LPH'XULQJ3URJUDPPLQJ:LWKLQD3URWHFWHG6HFWRU
7\S
—V
1RWHV
1RWWHVWHG
$V\QFKURQRXVUHDGPRGHDOORZV$V\QFKURQRXVSURJUDPRSHUDWLRQRQO\6\QFKURQRXVUHDGPRGHDOORZVERWK$V\QFKURQRXVDQG
6\QFKURQRXVSURJUDPRSHUDWLRQ
,QDV\QFKURQRXVSURJUDPRSHUDWLRQWLPLQJDGGUHVVHVDUHODWFKHGRQWKHIDOOLQJHGJHRI:(,QV\QFKURQRXVSURJUDPRSHUDWLRQWLPLQJ
DGGUHVVHVDUHODWFKHGRQWKHULVLQJHGJHRI&/.
6HHWKH³(UDVHDQG3URJUDPPLQJ3HUIRUPDQFH´VHFWLRQIRUPRUHLQIRUPDWLRQ
'RHVQRWLQFOXGHWKHSUHSURJUDPPLQJWLPH
December 3, 2005 S29WS-N_m0_I0
83
P r e l i m i n a r y
Erase Command Sequence (last two cycles)
VIH
Read Status Data
CLK
VIL
tAVDP
AVD#
tAH
tAS
Addresses
555h for
chip erase
Data
VA
SA
2AAh
55h
VA
10h for
chip erase
In
Progress
30h
Complete
tDS
tDH
CE#
tCH
OE#
tWP
WE#
tCS
tVCS
tWHWH2
tWPH
tWC
VCC
Figure 16.14. Chip/Sector Erase Operation Timings
84
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Program Command Sequence (last two cycles)
Read Status Data
VIH
CLK
VIL
tAVSW
tAVHW
tAVDP
AVD#
tAS
tAH
Addresses
555h
VA
PA
Data
A0h
VA
In
Progress
PD
Complete
tDS
tCAS
tDH
CE#
tCH
OE#
tWP
WE#
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
1RWHV
3$ 3URJUDP$GGUHVV3' 3URJUDP'DWD9$ 9DOLG$GGUHVVIRUUHDGLQJVWDWXVELWV
³,QSURJUHVV´DQG³FRPSOHWH´UHIHUWRVWDWXVRISURJUDPRSHUDWLRQ
$±$IRUWKH:61$±$IRUWKH:61DUHGRQ¶WFDUHGXULQJFRPPDQGVHTXHQFHXQORFNF\FOHV
&/.FDQEHHLWKHU9,/RU9,+
7KH$V\QFKURQRXVSURJUDPPLQJRSHUDWLRQLVLQGHSHQGHQWRIWKH6HW'HYLFH5HDG0RGHELWLQWKH
&RQILJXUDWLRQ5HJLVWHU
Figure 16.15.
December 3, 2005 S29WS-N_m0_I0
Program Operation Timing Using AVD#
85
P r e l i m i n a r y
Program Command Sequence (last two cycles)
Read Status Data
tAVCH
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
Addresses
VA
PA
555h
Data
In
Progress
PD
A0h
VA
Complete
tDS
tDH
tCAS
CE#
OE#
tCH
tCSW
tWP
WE#
tWHWH1
tWPH
tWC
tVCS
VCC
1RWHV
3$ 3URJUDP$GGUHVV3' 3URJUDP'DWD9$ 9DOLG$GGUHVVIRUUHDGLQJVWDWXVELWV
³,QSURJUHVV´DQG³FRPSOHWH´UHIHUWRVWDWXVRISURJUDPRSHUDWLRQ
$±$IRUWKH:61$±$IRUWKH:61DUHGRQ¶WFDUHGXULQJFRPPDQGVHTXHQFHXQORFNF\FOHV
$GGUHVVHVDUHODWFKHGRQWKHILUVWULVLQJHGJHRI&/.
(LWKHU&(RU$9'LVUHTXLUHGWRJRIURPORZWRKLJKLQEHWZHHQSURJUDPPLQJFRPPDQGVHTXHQFHV
7KH6\QFKURQRXVSURJUDPPLQJRSHUDWLRQLVGHSHQGHQWRIWKH6HW'HYLFH5HDG0RGHELWLQWKH&RQILJXUDWLRQ
5HJLVWHU7KH&RQILJXUDWLRQ5HJLVWHUPXVWEHVHWWRWKH6\QFKURQRXV5HDG0RGH
Figure 16.16. Program Operation Timing Using CLK in Relationship to AVD#
86
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
CE#
AVD#
WE#
Addresses
PA
Data
Don't Care
OE#
tVIDS
ACC
A0h
Don't Care
PD
Don't Care
VID
tVID
VIL or VIH
1RWH 8VHVHWXSDQGKROGWLPHVIURPFRQYHQWLRQDOSURJUDPRSHUDWLRQ
Figure 16.17. Accelerated Unlock Bypass Programming Timing
AVD#
tCEZ
tCE
CE#
tCH
tOEZ
tOE
OE#
tOEH
WE#
tACC
Addresses
VA
High Z
VA
High Z
Status Data
Data
Status Data
1RWHV
6WDWXVUHDGVLQILJXUHDUHVKRZQDVDV\QFKURQRXV
9$ 9DOLG$GGUHVV7ZRUHDGF\FOHVDUHUHTXLUHGWRGHWHUPLQHVWDWXV:KHQWKH(PEHGGHG$OJRULWKPRSHUDWLRQLVFRPSOHWHDQG'DWD
3ROOLQJRXWSXWVWUXHGDWD
Figure 16.18.
December 3, 2005 S29WS-N_m0_I0
Data# Polling Timings (During Embedded Algorithm)
87
P r e l i m i n a r y
AVD#
tCEZ
tCE
CE#
tCH
tOEZ
tOE
OE#
tOEH
WE#
tACC
Addresses
VA
High Z
VA
High Z
Data
Status Data
Status Data
1RWHV
6WDWXVUHDGVLQILJXUHDUHVKRZQDVDV\QFKURQRXV
9$ 9DOLG$GGUHVV7ZRUHDGF\FOHVDUHUHTXLUHGWRGHWHUPLQHVWDWXV:KHQWKH(PEHGGHG$OJRULWKPRSHUDWLRQLVFRPSOHWHWKHWRJJOHELWV
VWRSWRJJOLQJ
Figure 16.19. Toggle Bit Timings (During Embedded Algorithm)
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC
tIACC
Data
Status Data
Status Data
RDY
1RWHV
7KHWLPLQJVDUHVLPLODUWRV\QFKURQRXVUHDGWLPLQJV
9$ 9DOLG$GGUHVV7ZRUHDGF\FOHVDUHUHTXLUHGWRGHWHUPLQHVWDWXV:KHQWKH(PEHGGHG$OJRULWKPRSHUDWLRQLVFRPSOHWHWKHWRJJOHELWV
VWRSWRJJOLQJ
5'<LVDFWLYHZLWKGDWD' LQWKH&RQILJXUDWLRQ5HJLVWHU:KHQ' LQWKH&RQILJXUDWLRQ5HJLVWHU5'<LVDFWLYHRQHFORFNF\FOHEHIRUH
GDWD
Figure 16.20. Synchronous Data Polling Timings/Toggle Bit Timings
88
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
ADDR
CE#
AVD#
OE#
1RWH'4GRHVQRWWRJJOHFRUUHFWO\GXULQJHUDVHVXVSHQGLI$9'RU&(DUHKHOGORZDIWHUYDOLG
DGGUHVV
Figure 16.21.
0ns
Conditions for Incorrect DQ2 Polling During Erase Suspend
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
2
ADDR
CE#
AVD#
OE#
1RWH'4SROOLQJGXULQJHUDVHVXVSHQGEHKDYHVQRUPDOO\LI&(SXOVHVORZDWRUDIWHUYDOLG$GGUHVV
HYHQLI$9'GRHVQRW
Figure 16.22.
0ns
20ns
Correct DQ2 Polling during Erase Suspend #1
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
ADDR
CE#
AVD#
OE#
1RWH'4SROOLQJGXULQJHUDVHVXVSHQGEHKDYHVQRUPDOO\LI$9'SXOVHVORZDWRUDIWHUYDOLG$GGUHVV
HYHQLI&(GRHVQRW
Figure 16.23. Correct DQ2 Polling during Erase Suspend #2
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
ADDR
CE#
AVD#
OE#
1RWH'4SROOLQJGXULQJHUDVHVXVSHQGEHKDYHVQRUPDOO\LIERWK$9'DQG&(SXOVHORZDWRUDIWHU
YDOLG$GGUHVV
Figure 16.24.
December 3, 2005 S29WS-N_m0_I0
Correct DQ2 Polling during Erase Suspend #3
89
P r e l i m i n a r y
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase
Complete
Erase
Erase Suspend
Read
DQ6
DQ2
1RWH'4WRJJOHVRQO\ZKHQUHDGDWDQDGGUHVVZLWKLQDQHUDVHVXVSHQGHGVHFWRU7KHV\VWHPPD\XVH2(RU&(
WRWRJJOH'4DQG'4
Figure 16.25. DQ2 vs. DQ6
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
C126
7C
7D
7E
C127
C127
C128
C129
7F
7F
80
81
C130
C131
CLK
Address (hex)
AVD#
tRACC
RDY(1)
latency
tRACC
RDY(2)
OE#,
CE#
83
(stays high)
tRACC
Data
82
tRACC
latency
D124
D125
D126
D127
D128
D129
D130
(stays low)
1RWHV
5'<DFWLYHZLWKGDWD' LQWKH&RQILJXUDWLRQ5HJLVWHU
5'<DFWLYHRQHFORFNF\FOHEHIRUHGDWD' LQWKH&RQILJXUDWLRQ5HJLVWHU
&[[LQGLFDWHVWKHFORFNWKDWWULJJHUV'[[RQWKHRXWSXWVIRUH[DPSOH&WULJJHUV'
)LJXUHVKRZVWKHGHYLFHQRWFURVVLQJDEDQNLQWKHSURFHVVRISHUIRUPLQJDQHUDVHRUSURJUDP
5'<GRHVQRWJRORZDQGQRDGGLWLRQDOZDLWVWDWHVDUHUHTXLUHGIRU:6≤
Figure 16.26. Latency with Boundary Crossing when Frequency > 66 MHz
90
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
C126
7C
7D
7E
C127
C127
7F
7F
CLK
Address (hex)
AVD#
(stays high)
tRACC
tRACC
RDY(1)
latency
tRACC
RDY(2)
Data
OE#,
CE#
tRACC
latency
D124
D125
D126
D127
Read Status
(stays low)
1RWHV
5'<DFWLYHZLWKGDWD' LQWKH&RQILJXUDWLRQ5HJLVWHU
5'<DFWLYHRQHFORFNF\FOHEHIRUHGDWD' LQWKH&RQILJXUDWLRQ5HJLVWHU
&[[LQGLFDWHVWKHFORFNWKDWWULJJHUV'[[RQWKHRXWSXWVIRUH[DPSOH&WULJJHUV'
)LJXUHVKRZVWKHGHYLFHFURVVLQJDEDQNLQWKHSURFHVVRISHUIRUPLQJDQHUDVHRUSURJUDP
5'<GRHVQRWJRORZDQGQRDGGLWLRQDOZDLWVWDWHVDUHUHTXLUHGIRU:6≤
Figure 16.27. Latency with Boundary Crossing into Program/Erase Bank
December 3, 2005 S29WS-N_m0_I0
91
P r e l i m i n a r y
Data
D0
D1
Rising edge of next clock cycle
following last wait state triggers
next burst data
AVD#
total number of clock cycles
following addresses being latched
OE#
1
2
3
0
1
4
5
6
7
3
4
5
CLK
2
number of clock cycles
programmed
:DLW6WDWH&RQILJXUDWLRQ5HJLVWHU6HWXS
''' ³´⇒5HVHUYHG
''' ³´⇒5HVHUYHG
''' ³´⇒SURJUDPPHGWRWDO
''' ³´⇒SURJUDPPHGWRWDO
''' ³´⇒ SURJUDPPHGWRWDO
1RWH )LJXUHDVVXPHVDGGUHVV'LVQRWDWDQDGGUHVVERXQGDU\DQGZDLWVWDWHLVVHWWR³´
Figure 16.28.
92
Example of Wait States Insertion
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Last Cycle in
Program or
Sector Erase
Command Sequence
Read status (at least two cycles) in same bank
and/or array data from other bank
tWrite Cycle
Begin another
write or program
command sequence
tWrite Cycle
tRead Cycle
tRead Cycle
CE#
OE#
tOE
tOEH
tGHWL
WE#
tWPH
Data
tWP
tDS
tOEZ
tACC
tOEH
tDH
RD
PD/30h
AAh
RD
tSR/W
Addresses
PA/SA
RA
RA
555h
tAS
AVD#
tAH
1RWH %UHDNSRLQWVLQZDYHIRUPVLQGLFDWHWKDWV\VWHPPD\DOWHUQDWHO\UHDGDUUD\GDWDIURPWKH³QRQEXV\EDQN´ZKLOH
FKHFNLQJWKHVWDWXVRIWKHSURJUDPRUHUDVHRSHUDWLRQLQWKH³EXV\´EDQN7KHV\VWHPVKRXOGUHDGVWDWXVWZLFHWRHQVXUH
YDOLGLQIRUPDWLRQ
Figure 16.29.
December 3, 2005 S29WS-N_m0_I0
Back-to-Back Read/Write Cycle Timings
93
P r e l i m i n a r y
(UDVHDQG3URJUDPPLQJ3HUIRUPDQFH
Parameter
6HFWRU(UDVH7LPH
Typ (Note 1)
Max (Note 2)
.ZRUG
9&&
.ZRUG
9&&
:61
:61
:61
9&&
&KLS(UDVH7LPH
(IIHFWLYH:RUG3URJUDPPLQJ7LPH
XWLOL]LQJ3URJUDP:ULWH%XIIHU
7RWDO:RUG%XIIHU3URJUDPPLQJ
7LPH
:61
:61
:61
:61
9&&
$&&
9&&
$&&
9&&
$&&
:61
:61
:61
:61
:61
:61
:61
:61
$&&
6LQJOH:RUG3URJUDPPLQJ7LPH
1RWH
:61
9&&
&KLS3URJUDPPLQJ7LPH1RWH
$&&
Unit
Comments
V
V
([FOXGHVK
SURJUDPPLQJSULRU
WRHUDVXUH1RWH
—V
—V
—V
V
([FOXGHVV\VWHP
OHYHORYHUKHDG
1RWH
1RWHV
7\SLFDOSURJUDPDQGHUDVHWLPHVDVVXPHWKHIROORZLQJFRQGLWLRQV°&99&&
F\FOHVFKHFNHUERDUGGDWDSDWWHUQ
8QGHUZRUVWFDVHFRQGLWLRQVRIƒ&9&& 9F\FOHV
7\SLFDOFKLSSURJUDPPLQJWLPHLVFRQVLGHUDEO\OHVVWKDQWKHPD[LPXPFKLSSURJUDPPLQJ
WLPHOLVWHGDQGLVEDVHGRQXWLOL]LQJWKH:ULWH%XIIHU
,QWKHSUHSURJUDPPLQJVWHSRIWKH(PEHGGHG(UDVHDOJRULWKPDOOZRUGVDUHSURJUDPPHG
WRKEHIRUHHUDVXUH
6\VWHPOHYHORYHUKHDGLVWKHWLPHUHTXLUHGWRH[HFXWHWKHWZRRUIRXUEXVF\FOHVHTXHQFH
IRUWKHSURJUDPFRPPDQG6HHWKH$SSHQGL[IRUIXUWKHULQIRUPDWLRQRQFRPPDQG
GHILQLWLRQV
5HIHUWR$SSOLFDWLRQ1RWH³(UDVH6XVSHQG5HVXPH7LPLQJ´IRUPRUHGHWDLOV
:RUGSURJUDPPLQJVSHFLILFDWLRQLVEDVHGXSRQDVLQJOHZRUGSURJUDPPLQJRSHUDWLRQQRW
XWLOL]LQJWKHZULWHEXIIHU
94
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
%*$%DOO&DSDFLWDQFH
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max
Unit
&,1
,QSXW&DSDFLWDQFH
9,1 S)
&287
2XWSXW&DSDFLWDQFH
9287 S)
&,1
&RQWURO3LQ&DSDFLWDQFH
9,1 S)
1RWHV
6DPSOHGQRWWHVWHG
7HVWFRQGLWLRQV7$ °&I 0+]
December 3, 2005 S29WS-N_m0_I0
95
P r e l i m i n a r y
17 Appendix
7KLVVHFWLRQFRQWDLQVLQIRUPDWLRQUHODWLQJWRVRIWZDUHFRQWURORULQWHUIDFLQJZLWKWKH)ODVKGHYLFH
)RUDGGLWLRQDOLQIRUPDWLRQDQGDVVLVWDQFHUHJDUGLQJVRIWZDUHVHHWKH$GGLWLRQDO5HVRXUFHVVHF
WLRQRQSDJHRUH[SORUHWKH:HEDWZZZDPGFRPDQGZZZIXMLWVXFRP
96
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
$XWR
VHOHFW
&RPPDQG6HTXHQFH
1RWHV
$V\QFKURQRXV5HDG
5HVHW
0DQXIDFWXUHU,'
'HYLFH,'
&\FOHV
Table 17.1
)LUVW
$GGU
'DWD
5$
5'
;;;
)
$$
$$
Memory Array Commands
6HFRQG
$GGU
'DWD
%XV&\FOHV1RWHV±
7KLUG
)RXUWK
$GGU
'DWD
$GGU
'DWD
$$
$$
>%$@
>%$@
>%$@;
>%$@;
(
'DWD
%$;)
3'
:&
3$
3'
:%/
3'
$$
$$
$$
$$
6$
;
;
&5
&5
$
3$
3'
;;;
$$
$$
>%$@
>%$@;
'DWD
3URJUDP
:ULWHWR%XIIHU
3URJUDP%XIIHUWR)ODVK
:ULWHWR%XIIHU$ERUW5HVHW
&KLS(UDVH
6HFWRU(UDVH
(UDVH3URJUDP6XVSHQG
(UDVH3URJUDP5HVXPH
6HW&RQILJXUDWLRQ5HJLVWHU
5HDG&RQILJXUDWLRQ5HJLVWHU
&),4XHU\
(QWU\
3URJUDP
&),
6$
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;;;
;;;
$$
$$
$$
$$
$$
%
$$
$$
$$
$
$$
$$
3$
$
3$
3$
$$
$$
$$
)
$$
$$
'
&
$$
3$
3'
5HVHW
;;;
;;;
(QWU\
3URJUDP
5HDG
6$
$$
$$
'DWD
$$
$$
([LW
$$
$$
6HFXUHG6LOLFRQ 8QORFN%\SDVV
6HFWRU
0RGH
December 3, 2005 S29WS-N_m0_I0
6L[WK
$GGU
'DWD
%$;(
,QGLFDWRU%LWV
/HJHQG
; 'RQ¶WFDUH
5$ 5HDG$GGUHVV
5' 5HDG'DWD
3$ 3URJUDP$GGUHVV$GGUHVVHVODWFKRQWKHULVLQJHGJHRIWKH
$9'SXOVHRUDFWLYHHGJHRI&/.ZKLFKHYHURFFXUVILUVW
3' 3URJUDP'DWD'DWDODWFKHVRQWKHULVLQJHGJHRI:(RU&(
SXOVHZKLFKHYHURFFXUVILUVW
1RWHV
6HH7DEOHIRUGHVFULSWLRQRIEXVRSHUDWLRQV
$OOYDOXHVDUHLQKH[DGHFLPDO
6KDGHGFHOOVLQGLFDWHUHDGF\FOHV
$GGUHVVDQGGDWDELWVQRWVSHFLILHGLQWDEOHOHJHQGRUQRWHVDUH
GRQ¶WFDUHVHDFKKH[GLJLWLPSOLHVELWVRIGDWD
:ULWLQJLQFRUUHFWDGGUHVVDQGGDWDYDOXHVRUZULWLQJWKHPLQWKH
LPSURSHUVHTXHQFHPD\SODFHWKHGHYLFHLQDQXQNQRZQVWDWH
7KHV\VWHPPXVWZULWHWKHUHVHWFRPPDQGWRUHWXUQWKHGHYLFH
WRUHDGLQJDUUD\GDWD
1RXQORFNRUFRPPDQGF\FOHVUHTXLUHGZKHQEDQNLVUHDGLQJ
DUUD\GDWD
5HVHWFRPPDQGLVUHTXLUHGWRUHWXUQWRUHDGLQJDUUD\GDWDRUWR
WKHHUDVHVXVSHQGUHDGPRGHLISUHYLRXVO\LQ(UDVH6XVSHQG
ZKHQDEDQNLVLQWKHDXWRVHOHFWPRGHRULI'4JRHVKLJK
ZKLOHWKHEDQNLVSURYLGLQJVWDWXVLQIRUPDWLRQRUSHUIRUPLQJ
VHFWRUORFNXQORFN
7KHV\VWHPPXVWSURYLGHWKHEDQNDGGUHVV6HH$XWRVHOHFW
VHFWLRQIRUPRUHLQIRUPDWLRQ
'DWDLQF\FOHLV:61RU:61
6HH7DEOHIRULQGLFDWRUELWYDOXHV
7RWDOQXPEHURIF\FOHVLQWKHFRPPDQGVHTXHQFHLVGHWHUPLQHG
E\WKHQXPEHURIZRUGVZULWWHQWRWKHZULWHEXIIHU
&RPPDQGVHTXHQFHUHVHWVGHYLFHIRUQH[WFRPPDQGDIWHUZULWH
WREXIIHURSHUDWLRQ
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6$ 6HFWRU$GGUHVV:61 $±$:61 $±$
%$ %DQN$GGUHVV:61 $±$:61 $±$
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:%/ :ULWH%XIIHU/RFDWLRQ$GGUHVVPXVWEHZLWKLQWKHVDPHZULWH
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6\VWHPPD\UHDGDQGSURJUDPLQQRQHUDVLQJVHFWRUVRUHQWHU
WKHDXWRVHOHFWPRGHZKHQLQWKH(UDVH6XVSHQGPRGH7KH
(UDVH6XVSHQGFRPPDQGLVYDOLGRQO\GXULQJDVHFWRUHUDVH
RSHUDWLRQDQGUHTXLUHVWKHEDQNDGGUHVV
(UDVH5HVXPHFRPPDQGLVYDOLGRQO\GXULQJWKH(UDVH6XVSHQG
PRGHDQGUHTXLUHVWKHEDQNDGGUHVV
&RPPDQGLVYDOLGZKHQGHYLFHLVUHDG\WRUHDGDUUD\GDWDRU
ZKHQGHYLFHLVLQDXWRVHOHFWPRGH$GGUHVVHTXDOVKRQDOO
IXWXUHGHYLFHVEXWKIRU:611
5HTXLUHV(QWU\FRPPDQGVHTXHQFHSULRUWRH[HFXWLRQ8QORFN
%\SDVV5HVHWFRPPDQGLVUHTXLUHGWRUHWXUQWRUHDGLQJDUUD\
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5HTXLUHV(QWU\FRPPDQGVHTXHQFHSULRUWRH[HFXWLRQ6HFXUHG
6LOLFRQ6HFWRU([LW5HVHWFRPPDQGLVUHTXLUHGWRH[LWWKLVPRGH
GHYLFHPD\RWKHUZLVHEHSODFHGLQDQXQNQRZQVWDWH
5HTXLUHVUHVHWFRPPDQGWRFRQILJXUHWKH&RQILJXUDWLRQ5HJLVWHU
97
P r e l i m i n a r y
&RPPDQG6HTXHQFH
1RWHV
&RPPDQG6HW(QWU\
/RFN
3URJUDP
5HJLVWHU
5HDG
%LWV
&RPPDQG6HW([LW
&RPPDQG6HW(QWU\
3URJUDP>@
3DVVZRUG
5HDG
3URWHFWLRQ
8QORFN
&RPPDQG6HW([LW
&RPPDQG6HW(QWU\
1RQ9RODWLOH 33%3URJUDP
6HFWRU
$OO33%(UDVH
3URWHFWLRQ33% 33%6WDWXV5HDG
&RPPDQG6HW([LW
*OREDO
&RPPDQG6HW(QWU\
9RODWLOH6HFWRU 33%/RFN%LW6HW
3URWHFWLRQ
33%/RFN%LW6WDWXV5HDG
)UHH]H
&RPPDQG6HW([LW
33%/RFN
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3URWHFWLRQ
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&RPPDQG6HW(QWU\
'<%6HW
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&RPPDQG6HW([LW
&\FOHV
Table 17.2. Sector Protection Commands
)LUVW
$GGU 'DWD
$$
;;
$
GDWD
;;
$$
;;
$
3:'
;;
$$
;;
$
;;
6$
5'
;;
$$
;;
$
%$
5'
;;
$$
3:'>@
3:'
3:'
3:'
;;
$$
>%$@
&
6$
;;
$$
;;
;;
;;
;;
;;
6$
;;
$$
$
$
5'
$$
6$
6$
;;
/HJHQG
; 'RQ¶WFDUH
5$ $GGUHVVRIWKHPHPRU\ORFDWLRQWREHUHDG
3' 6HFXUHG6LOLFRQ6HFWRU/RFN%LW3'RUELW>@
3' 3HUVLVWHQW3URWHFWLRQ0RGH/RFN%LW3'RUELW>@PXVW
EHVHWWRµ¶IRUSURWHFWLRQZKLOH3'ELW>@PXVWEHOHIWDVµ¶
3' 3DVVZRUG3URWHFWLRQ0RGH/RFN%LW3'RUELW>@PXVW
EHVHWWRµ¶IRUSURWHFWLRQZKLOH3'ELW>@PXVWEHOHIWDVµ¶
3' 3URWHFWLRQ0RGH273%LW3'RUELW>@
6$ 6HFWRU$GGUHVV:61 $±$:61 $±$
1RWHV
$OOYDOXHVDUHLQKH[DGHFLPDO
6KDGHGFHOOVLQGLFDWHUHDGF\FOHV
$GGUHVVDQGGDWDELWVQRWVSHFLILHGLQWDEOHOHJHQGRUQRWHVDUH
GRQ¶WFDUHVHDFKKH[GLJLWLPSOLHVELWVRIGDWD
:ULWLQJLQFRUUHFWDGGUHVVDQGGDWDYDOXHVRUZULWLQJWKHPLQWKH
LPSURSHUVHTXHQFHPD\SODFHWKHGHYLFHLQDQXQNQRZQVWDWH
7KHV\VWHPPXVWZULWHWKHUHVHWFRPPDQGWRUHWXUQWKHGHYLFH
WRUHDGLQJDUUD\GDWD
(QWU\FRPPDQGVDUHUHTXLUHGWRHQWHUDVSHFLILFPRGHWRHQDEOH
LQVWUXFWLRQVRQO\DYDLODEOHZLWKLQWKDWPRGH
,IERWKWKH3HUVLVWHQW3URWHFWLRQ0RGH/RFNLQJ%LWDQGWKH
3DVVZRUG3URWHFWLRQ0RGH/RFNLQJ%LWDUHVHWDWWKHVDPHWLPH
WKHFRPPDQGRSHUDWLRQDERUWVDQGUHWXUQVWKHGHYLFHWRWKH
GHIDXOW3HUVLVWHQW6HFWRU3URWHFWLRQ0RGHGXULQJQGEXVF\FOH
1RWHWKDWRQDOOIXWXUHGHYLFHVDGGUHVVHVHTXDOKEXWLV
FXUUHQWO\KIRUWKH:61RQO\6HH7DEOHVDQGIRU
H[SODQDWLRQRIORFNELWV
([LWFRPPDQGPXVWEHLVVXHGWRUHVHWWKHGHYLFHLQWRUHDG
PRGHGHYLFHPD\RWKHUZLVHEHSODFHGLQDQXQNQRZQVWDWH
98
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7KLUG
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3:'
6HYHQWK
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%$ %DQN$GGUHVV:61 $±$:61 $±$
3:'±3:' 3DVVZRUG'DWD3'±3'SUHVHQWIRXUELW
FRPELQDWLRQVWKDWUHSUHVHQWWKHELW3DVVZRUG
3:$ 3DVVZRUG$GGUHVV$GGUHVVELWV$DQG$DUHXVHGWRVHOHFW
HDFKELWSRUWLRQRIWKHELWHQWLW\
3:' 3DVVZRUG'DWD
5'5'5' '4'4RU'4SURWHFWLRQLQGLFDWRUELW,I
SURWHFWHG'4'4RU'4 ,IXQSURWHFWHG'4'4
'4
(QWLUHWZREXVF\FOHVHTXHQFHPXVWEHHQWHUHGIRUHDFKSRUWLRQ
RIWKHSDVVZRUG
)XOODGGUHVVUDQJHLVUHTXLUHGIRUUHDGLQJSDVVZRUG
6HH)LJXUHIRUGHWDLOV
³$OO33%(UDVH´FRPPDQGSUHSURJUDPVDOO33%VEHIRUHHUDVXUH
WRSUHYHQWRYHUHUDVXUH
7KHVHFRQGF\FOHDGGUHVVIRUWKHORFNUHJLVWHUSURJUDPRSHUDWLRQ
LVIRU6:61KRZHYHUIRU:61WKLVDGGUHVVLV
S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
17.1
Common Flash Memory Interface
7KH&RPPRQ)ODVK,QWHUIDFH&),VSHFLILFDWLRQRXWOLQHVGHYLFHDQGKRVWV\VWHPVRIWZDUHLQWHU
URJDWLRQKDQGVKDNHZKLFKDOORZVVSHFLILFYHQGRUVSHFLILHGVRIWZDUHDOJRULWKPVWREHXVHGIRU
HQWLUHIDPLOLHVRIGHYLFHV6RIWZDUHVXSSRUWFDQWKHQEHGHYLFHLQGHSHQGHQW-('(&,'LQGHSHQ
GHQW DQG IRUZDUG DQG EDFNZDUGFRPSDWLEOH IRU WKH VSHFLILHG IODVK GHYLFH IDPLOLHV )ODVK
YHQGRUVFDQVWDQGDUGL]HWKHLUH[LVWLQJLQWHUIDFHVIRUORQJWHUPFRPSDWLELOLW\
7KLVGHYLFHHQWHUVWKH&),4XHU\PRGHZKHQWKHV\VWHPZULWHVWKH&),4XHU\FRPPDQGK
WRDGGUHVV%$KDQ\WLPHWKHGHYLFHLVUHDG\WRUHDGDUUD\GDWD7KHV\VWHPFDQUHDG&),
LQIRUPDWLRQDWWKHDGGUHVVHVJLYHQLQ7DEOHV±ZLWKLQWKDWEDQN$OOUHDGVRXWVLGHRI
WKH&),DGGUHVVUDQJHZLWKLQWKHEDQNUHWXUQVQRQYDOLGGDWD5HDGVIURPRWKHUEDQNVDUHDO
ORZHGZULWHVDUHQRW7RWHUPLQDWHUHDGLQJ&),GDWDWKHV\VWHPPXVWZULWHWKHUHVHWFRPPDQG
7KHIROORZLQJLVD&VRXUFHFRGHH[DPSOHRIXVLQJWKH&),(QWU\DQG([LWIXQFWLRQV5HIHUWRWKH
6SDQVLRQ/RZ/HYHO'ULYHU8VHU¶V*XLGHDYDLODEOHRQZZZDPGFRPDQGZZZIXMLWVXFRPIRU
JHQHUDOLQIRUPDWLRQRQ6SDQVLRQ)ODVKPHPRU\VRIWZDUHGHYHORSPHQWJXLGHOLQHV
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098;
/* write CFI entry command
*/
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0;
/* write cfi exit command
*/
)RUIXUWKHULQIRUPDWLRQSOHDVHUHIHUWRWKH&),6SHFLILFDWLRQVHH-('(&SXEOLFDWLRQV-(3$
DQG-(6'DQG&),3XEOLFDWLRQ3OHDVHFRQWDFW\RXUVDOHVRIILFHIRUFRSLHVRIWKHVH
GRFXPHQWV
Table 17.3.
CFI Query Identification String
Addresses
Data
K
K
K
K
K
K
Description
4XHU\8QLTXH$6&,,VWULQJ³45<´
K
K
K
K
3ULPDU\2(0&RPPDQG6HW
K
K
K
K
$GGUHVVIRU3ULPDU\([WHQGHG7DEOH
K
K
K
K
$OWHUQDWH2(0&RPPDQG6HWK QRQHH[LVWV
K
$K
K
K
$GGUHVVIRU$OWHUQDWH2(0([WHQGHG7DEOHK QRQHH[LVWV
Table 17.4.
Addresses
System Interface String
Data
Description
%K
K
9&&0LQZULWHHUDVH
'±'YROW'±'PLOOLYROW
&K
K
9&&0D[ZULWHHUDVH
'±'YROW'±'PLOOLYROW
'K
K
9330LQYROWDJHK QR933SLQSUHVHQW
(K
K
9330D[YROWDJHK QR933SLQSUHVHQW
)K
K
7\SLFDOWLPHRXWSHUVLQJOHE\WHZRUGZULWH1—V
K
K
7\SLFDOWLPHRXWIRU0LQVL]HEXIIHUZULWH1—VK QRWVXSSRUWHG
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December 3, 2005 S29WS-N_m0_I0
99
P r e l i m i n a r y
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S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
Table 17.6.
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Addresses
Data
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S29WS-N_m0_I0 December 3, 2005
P r e l i m i n a r y
18 Revisions
Revision F (October 29, 2004)
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December 3, 2005 S29WS-N_m0_I0
103
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Revision A
Amendment 3
Issue Date November 8, 2005
P r e l i m i n a r y
19 General Description
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November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
105
P r e l i m i n a r y
20 Functional Block Diagram
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106
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Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
21 Pin Descriptions
Symbol
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November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
107
P r e l i m i n a r y
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24 Mode Register Definition
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0RELOHFRPSRQHQW0RGH5HJLVWHUDQG([WHQGHG0RGH5HJLVWHU7KHPRGHUHJLV
WHU LVLOOXVWUDWHG LQ )LJXUH 0RGH 5HJLVWHU 'HILQLWLRQ RQ SDJH WKH
H[WHQGHGPRGHUHJLVWHULVLOOXVWUDWHGLQ)LJXUH 7KHPRGHUHJLVWHUGHILQHVWKHVSHFLILFPRGHRIRSHUDWLRQRIWKH6'5$0LQFOXGLQJ
EXUVWOHQJWKEXUVWW\SH&$6ODWHQF\RSHUDWLQJPRGHDQGZULWHEXUVWPRGH7KH
PRGHUHJLVWHULVSURJUDPPHGYLDWKH/RDG0RGH5HJLVWHUFRPPDQGDQGZLOOUH
WDLQWKH VWRUHG LQIRUPDWLRQ XQWLOLWLV SURJUDPPHGDJDLQ RUWKHGHYLFH ORVHV
SRZHU
0RGHUHJLVWHUELWV0±0VSHFLI\WKHEXUVWOHQJWK0VSHFLILHVWKHW\SHRIEXUVW
VHTXHQWLDORULQWHUOHDYHG0±0VSHFLI\WKH&$6ODWHQF\0DQG0VSHFLI\
WKHRSHUDWLQJPRGH0VSHFLILHVWKHZULWHEXUVWPRGHDQG0DQG0VKRXOG
EHVHWWR]HUR0DQG0VKRXOGEHVHWWR]HURWRSUHYHQWH[WHQGHGPRGH
UHJLVWHU
7KHPRGHUHJLVWHUPXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGWKHFRQWUROOHU
PXVWZDLWWKHVSHFLILHGWLPHEHIRUHLQLWLDWLQJWKHVXEVHTXHQWRSHUDWLRQ9LRODWLQJ
HLWKHURIWKHVHUHTXLUHPHQWVZLOOUHVXOWLQXQVSHFLILHGRSHUDWLRQ
108
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
25 Burst Length
5HDGDQGZULWHDFFHVVHVWRWKH6'5$0DUHEXUVWRULHQWHGZLWKWKHEXUVWOHQJWK
EHLQJSURJUDPPDEOHDVVKRZQLQ)LJXUH ³0RGH5HJLVWHU'HILQLWLRQ´VHFWLRQ
RQSDJH7KHEXUVWOHQJWKGHWHUPLQHVWKHPD[LPXPQXPEHURIFROXPQOR
FDWLRQVWKDWFDQEHDFFHVVHGIRUDJLYHQ5HDGRU:ULWHFRPPDQG%XUVWOHQJWKV
RIRUORFDWLRQVDUHDYDLODEOHIRUERWKWKHVHTXHQWLDODQGWKHLQWHUOHDYHG
EXUVWW\SHVDQGDIXOOSDJHEXUVWLVDYDLODEOHIRUWKHVHTXHQWLDOW\SH7KHIXOO
SDJHEXUVWLVXVHGLQFRQMXQFWLRQZLWKWKH%XUVW7HUPLQDWHFRPPDQGWRJHQHUDWH
DUELWUDU\EXUVWOHQJWKV
5HVHUYHGVWDWHVVKRXOGQRWEHXVHGDVXQNQRZQRSHUDWLRQRULQFRPSDWLELOLW\ZLWK
IXWXUHYHUVLRQVPD\UHVXOW
:KHQD5HDGRU:ULWHFRPPDQGLVLVVXHGDEORFNRIFROXPQVHTXDOWRWKHEXUVW
OHQJWKLVHIIHFWLYHO\VHOHFWHG$OODFFHVVHVIRUWKDWEXUVWWDNHSODFHZLWKLQWKLV
EORFNPHDQLQJWKDWWKHEXUVWZLOOZUDSZLWKLQWKHEORFNLIDERXQGDU\LVUHDFKHG
7KHEORFNLVXQLTXHO\VHOHFWHGE\$±$ZKHQWKHEXUVWOHQJWKLVVHWWRWZRE\
$±$ZKHQWKHEXUVWOHQJWKLVVHWWRIRXUDQGE\$±$ZKHQWKHEXUVWOHQJWK
LVVHWWRHLJKW
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
109
P r e l i m i n a r y
Table 25.1
%XUVW/HQJWK
Burst Definition
2UGHURI$FFHVVHV:LWKLQ$%XUVW
6WDUWLQJ&ROXPQ$GGUHVV
7\SH 6HTXHQWLDO
7\SH ,QWHUOHDYHG
$
$
$
$
$
$
&Q&Q
&Q&Q
&Q«&Q
&Q«
1RW6XSSRUWHG
)XOO3DJH\
Q $±$ORFDWLRQ\
1RWHV
)RUIXOOSDJHDFFHVVHV\ )RUDEXUVWOHQJWKRIWZR$±$VHOHFWWKHEORFNRIWZREXUVW$VHOHFWVWKH
VWDUWLQJFROXPQZLWKLQWKHEORFN
)RUDEXUVWOHQJWKRIIRXU$±$VHOHFWWKHEORFNRIIRXUEXUVW$±$VHOHFWWKH
VWDUWLQJFROXPQZLWKLQWKHEORFN
)RUDEXUVWOHQJWKRIHLJKW$±$VHOHFWWKHEORFNRIHLJKWEXUVW$±$VHOHFWWKH
VWDUWLQJFROXPQZLWKLQWKHEORFN
)RUDIXOOSDJHEXUVWWKHIXOOURZLVVHOHFWHGDQG$±$VHOHFWWKHVWDUWLQJFROXPQ
:KHQHYHUDERXQGDU\RIWKHEORFNLVUHDFKHGZLWKLQDJLYHQVHTXHQFHDERYHWKH
IROORZLQJDFFHVVZUDSVZLWKLQWKHEORFN
)RUDEXUVWOHQJWKRIRQH$±$VHOHFWWKHXQLTXHFROXPQWREHDFFHVVHGDQG
PRGHUHJLVWHUELW0LVLJQRUHG
110
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
BA1 BA0 A11 A10
A9
A8
M13 M12 M11 M10 M9 M8
13
12
11
10
Reserved** Reserved*
9
WB
8
A7
A6
M7 M6
6
7
Op Mode
A5
A4
A3
M5
M4
5
4
CAS Latency
A2
M3
M2
3
M1
1
2
BT
A1
Address Bus
A0
M0
0
Mode Register (Mx)
Burst Length
Burst Length
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
** BA1, BA0 = “0, 0”
to prevent Extended
Mode Register.
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
Burst Type
M3
M9
M3 = 0
0
Sequential
1
Interleaved
M6 M5 M4
CAS Latency
0
0
0
Reserved
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
All other states reserved
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
Figure 25.1
Mode Register Definition
7KHUHPDLQLQJOHDVWVLJQLILFDQWDGGUHVVELWVLVDUHXVHGWRVHOHFWWKHVWDUWLQJ
ORFDWLRQZLWKLQWKHEORFN)XOOSDJHEXUVWVZUDSZLWKLQWKHSDJHLIWKHERXQGDU\
LVUHDFKHG
26 Burst Type
$FFHVVHVZLWKLQDJLYHQEXUVWPD\EHSURJUDPPHGWREHHLWKHUVHTXHQWLDORULQ
WHUOHDYHGWKLVLVUHIHUUHGWRDVWKHEXUVWW\SHDQGLVVHOHFWHGYLDELW0
7KHRUGHULQJRIDFFHVVHVZLWKLQDEXUVWLVGHWHUPLQHGE\WKHEXUVWOHQJWKWKH
EXUVWW\SHDQGWKHVWDUWLQJFROXPQDGGUHVVDVVKRZQLQ7DEOH 27 CAS Latency
7KH&$6ODWHQF\LVWKHGHOD\LQFORFNF\FOHVEHWZHHQWKHUHJLVWUDWLRQRID5HDG
FRPPDQGDQGWKHDYDLODELOLW\RIWKHILUVWSLHFHRIRXWSXWGDWD7KHODWHQF\FDQEH
VHWWRRQHWZRRUWKUHHFORFNV
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
111
P r e l i m i n a r y
,ID5HDGFRPPDQGLVUHJLVWHUHGDWFORFNHGJHQDQGWKHODWHQF\LVPFORFNVWKH
GDWDZLOOEHDYDLODEOHE\FORFNHGJHQP7KH'4VZLOOVWDUWGULYLQJDVDUHVXOW
RIWKHFORFNHGJHRQHF\FOHHDUOLHUQPDQGSURYLGHGWKDWWKHUHOHYDQW
DFFHVVWLPHVDUHPHWWKHGDWDZLOOEHYDOLGE\FORFNHGJHQP)RUH[DPSOH
DVVXPLQJWKDWWKHFORFNF\FOHWLPHLVVXFKWKDWDOOUHOHYDQWDFFHVVWLPHVDUHPHW
LIDUHDGFRPPDQGLVUHJLVWHUHGDW7DQGWKHODWHQF\LVSURJUDPPHGWRWZR
FORFNVWKH'4VZLOOVWDUWGULYLQJDIWHU7DQGWKHGDWDZLOOEHYDOLGE\7DV
VKRZQLQ)LJXUH &$6/DWHQF\7DEOH &$6/DWHQF\LQGLFDWHVWKHRSHU
DWLQJIUHTXHQFLHVDWZKLFKHDFK&$6ODWHQF\VHWWLQJFDQEHXVHG
5HVHUYHGVWDWHVVKRXOGQRWEHXVHGDVXQNQRZQRSHUDWLRQRULQFRPSDWLELOLW\ZLWK
IXWXUHYHUVLRQVPD\UHVXOW
T0
T1
T2
NOP
NOP
T3
CLK
COMMAND
READ
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 2
T0
T1
T2
T3
T4
NOP
NOP
NOP
CLK
COMMAND
READ
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
Figure 27.1 CAS Latency
Table 27.1
Speed
CAS Latency
Allowable Operating Frequency MHz
CAS Latency = 2
CAS Latency = 3
≤ ≤ ≤ ≤ 28 Operating Mode
7KHQRUPDORSHUDWLQJPRGHLVVHOHFWHGE\VHWWLQJ0DQG0WR]HURWKHRWKHU
FRPELQDWLRQVRIYDOXHVIRU0DQG0DUHUHVHUYHGIRUIXWXUHXVHDQGRUWHVW
PRGHV7KHSURJUDPPHGEXUVWOHQJWKDSSOLHVWRERWKUHDGDQGZULWHEXUVWV
7HVWPRGHVDQGUHVHUYHGVWDWHVVKRXOGQRWEHXVHGEHFDXVHXQNQRZQRSHUDWLRQ
RULQFRPSDWLELOLW\ZLWKIXWXUHYHUVLRQVPD\UHVXOW
112
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
29 Write Burst Mode
:KHQ0 WKHEXUVWOHQJWKSURJUDPPHGYLD00DSSOLHVWRERWK5HDGDQG
:ULWHEXUVWVZKHQ0 WKHSURJUDPPHGEXUVWOHQJWKDSSOLHVWR5HDGEXUVWV
EXWZULWHDFFHVVHVDUHVLQJOHORFDWLRQQRQEXUVWDFFHVVHV
30 Extended Mode Register
7KH([WHQGHG0RGH5HJLVWHUFRQWUROVWKHIXQFWLRQVEH\RQGWKRVHFRQWUROOHGE\
WKH0RGH5HJLVWHU7KHVHDGGLWLRQDOIXQFWLRQVDUHVSHFLDOIHDWXUHVRIWKH0RELOH
GHYLFH7KH\LQFOXGH7HPSHUDWXUH&RPSHQVDWHG6HOI5HIUHVK7&65&RQWURO
3DUWLDO$UUD\6HOI5HIUHVK3$65DQG2XWSXW'ULYH6WUHQJWK1RWSURJUDPPLQJ
WKH([WHQGHG0RGH5HJLVWHUXSRQLQLWLDOL]DWLRQZLOOUHVXOWLQGHIDXOWVHWWLQJVIRU
WKH/RZ3RZHUIHDWXUHV7KH([WHQGHG0RGHZLOOGHIDXOWWRWKHƒ&VHWWLQJIRU
7&65IXOOGULYHVWUHQJWKDQGIXOODUUD\UHIUHVK
7KH([WHQGHG0RGH5HJLVWHULVSURJUDPPHGYLDWKH0RGH5HJLVWHU6HWFRPPDQG
%$ %$ DQGUHWDLQVWKHVWRUHGLQIRUPDWLRQXQWLOLWLVSURJUDPPHG
DJDLQRUWKHGHYLFHORVHVSRZHU
7KH([WHQGHG0RGH5HJLVWHUPXVWEHSURJUDPPHGZLWK(WKURXJK(VHWWR
³´,WPXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGQREXUVWVDUHLQSURJUHVVDQG
WKHFRQWUROOHUPXVWZDLWWKHVSHFLILHGWLPHEHIRUHLQLWLDWLQJDQ\VXEVHTXHQWRS
HUDWLRQ9LRODWLQJHLWKHURIWKHVHUHTXLUHPHQWVUHVXOWVLQXQVSHFLILHGRSHUDWLRQ
2QFHWKHYDOXHVDUHHQWHUHGWKH([WHQGHG0RGH5HJLVWHUVHWWLQJVZLOOEHUHWDLQHG
HYHQDIWHUH[LWLQJ'HHS3RZHU'RZQ
31 Temperature Compensated Self Refresh
7HPSHUDWXUH&RPSHQVDWHG6HOI5HIUHVK7&65DOORZVWKHFRQWUROOHUWRSURJUDP
WKH5HIUHVKLQWHUYDOGXULQJ6HOI5HIUHVKPRGHDFFRUGLQJWRWKHFDVHWHPSHUDWXUH
RIWKH0RELOHGHYLFH7KLVDOORZVJUHDWSRZHUVDYLQJVGXULQJ6HOI5HIUHVKGXULQJ
PRVWRSHUDWLQJWHPSHUDWXUHUDQJHV2QO\GXULQJH[WUHPHWHPSHUDWXUHVZRXOG
WKHFRQWUROOHUKDYHWRVHOHFWWKHPD[LPXP7&65OHYHO7KLVZRXOGJXDUDQWHHGDWD
GXULQJ6HOI5HIUHVK
(YHU\FHOOLQWKH6'5$0UHTXLUHVUHIUHVKLQJGXHWRWKHFDSDFLWRUORVLQJLWVFKDUJH
RYHUWLPH7KHUHIUHVKUDWHLVGHSHQGHQWRQWHPSHUDWXUH$WKLJKHUWHPSHUDWXUHV
DFDSDFLWRUORVHVFKDUJHTXLFNHUWKDQDWORZHUWHPSHUDWXUHVUHTXLULQJWKHFHOOV
WREHUHIUHVKHGPRUHRIWHQ+LVWRULFDOO\GXULQJ6HOI5HIUHVKWKHUHIUHVKUDWHKDV
EHHQ VHW WR DFFRPPRGDWH WKH ZRUVW FDVH RU KLJKHVW WHPSHUDWXUH UDQJH
H[SHFWHG
7KXVGXULQJDPELHQWWHPSHUDWXUHVWKHSRZHUFRQVXPHGGXULQJUHIUHVKZDVXQ
QHFHVVDULO\KLJKEHFDXVHWKHUHIUHVKUDWHZDVVHWWRDFFRPPRGDWHWKHKLJKHU
WHPSHUDWXUHV$GMXVWLQJWKHUHIUHVKUDWHE\VHWWLQJ(DQG(DOORZVWKH6'5$0
WRDFFRPPRGDWHPRUHVSHFLILFWHPSHUDWXUHUHJLRQVGXULQJ6HOI5HIUHVK7KHUH
DUHIRXUWHPSHUDWXUHVHWWLQJVZKLFKZLOOYDU\WKH6HOI5HIUHVKFXUUHQWDFFRUGLQJ
WRWKHVHOHFWHGWHPSHUDWXUH7KLVVHOHFWDEOHUHIUHVKUDWHZLOOVDYHSRZHUZKHQ
WKH6'5$0LVRSHUDWLQJDWQRUPDOWHPSHUDWXUHV
32 Partial Array Self Refresh
)RUIXUWKHU SRZHUVDYLQJVGXULQJ6HOI5HIUHVKWKH3DUWLDO$UUD\ 6HOI 5HIUHVK
3$65IHDWXUHDOORZVWKHFRQWUROOHUWRVHOHFWWKHDPRXQWRIPHPRU\WKDWZLOOEH
UHIUHVKHGGXULQJ6HOI5HIUHVK7KHUHIUHVKRSWLRQVDUHDOOEDQNVEDQNV
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
113
P r e l i m i n a r y
DQGWZREDQNVEDQNVDQGDQGRQHEDQNEDQN$OVRLQFOXGHGLQWKH
UHIUHVKRSWLRQVDUHWKHEDQNDQGEDQNSDUWLDODUUD\VHOIUHIUHVKEDQN
:ULWHDQG5HDGFRPPDQGVRFFXUWRDQ\EDQNVHOHFWHGGXULQJVWDQGDUGRSHUDWLRQ
EXWRQO\WKHVHOHFWHGEDQNVLQ3$65ZLOOEHUHIUHVKHGGXULQJ6HOI5HIUHVK,WLV
LPSRUWDQWWRQRWHWKDWGDWDLQXQXVHGEDQNVRUSRUWLRQVRIEDQNVZLOOEHORVW
ZKHQ3$65LVXVHG'DWDZLOOEHORVWLQEDQNVDQGZKHQWKHRQHEDQNRS
WLRQLVXVHG
33 Driver Strength
%LWV(DQG(RIWKHH[WHQGHGPRGHUHJLVWHUFDQEHXVHGWRVHOHFWWKHGULYHU
VWUHQJWKRIWKH'4RXWSXWV7KLVYDOXHVKRXOGEHVHWDFFRUGLQJWRWKHDSSOLFDWLRQ
UHTXLUHPHQWV)XOOGULYHVWUHQJWKZDVFDUULHGRYHUIURPVWDQGDUG6'5$0DQGLV
VXLWDEOHWRGULYHKLJKHUORDGV\VWHPV)XOOGULYHVWUHQJWKLVQRWUHFRPPHQGHGIRU
ORDGVXQGHUS)+DOIGULYHVWUHQJWKLVLQWHQGHGIRUPXOWLGURSV\VWHPVZLWKYDU
LRXVORDGV7KLVGULYHRSWLRQLVQRWUHFRPPHQGHGIRUORDGVXQGHUS)4XDUWHU
GULYHVWUHQJWKLVLQWHQGHGIRUOLJKWHUORDGVRUSRLQWWRSRLQWV\VWHPV
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
13 12 11 10 9
8
7
6
1 0 All must be set to "0"
E6 E5 Driver Strength
3
E4
5
DS
4
3
0
PASR
Extended Mode
Register (Ex)
E3 Maximum Case Temp
85°C 3
1
1
0 1 Half Strength
0
0
1 0 Quarter Strength
0
1
45°C
1 1 Reserved
1
0
15°C
0 0 Full Strength
2 1
TCSR
70°C
E2
E1
E0
0
0
0
Four Banks 3
0
0
1
Two Banks (Bank 0,1)
0
1
0
One Bank (Bank 0)
0
1
1
1
0
0
1
0
1
1/2 Bank (Bank 0) 4
1
1
0
1/4 Bank (Bank 0) 5
1
1
1
Figure 33.1
Self Refresh Coverage
RFU
RFU
RFU
Extended Mode Register
1RWHV
(DQG(%$DQG%$PXVWEH³´WRVHOHFWWKHH[WHQGHGPRGHUHJLVWHU
YVWKHEDVHPRGHUHJLVWHU
5)85HVHUYHGIRUIXWXUHXVH
'HIDXOW(05YDOXHVDUHIXOODUUD\IRU3$65)XOO'ULYH6WUHQJWKDQGƒIRU7&65
( (( 114
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
34 Commands
7DEOH SURYLGHVDTXLFNUHIHUHQFHRIDYDLODEOHFRPPDQGV7KLVLVIROORZHGE\
DZULWWHQGHVFULSWLRQRIHDFKFRPPDQG7KUHHDGGLWLRQDO7UXWK7DEOHVDSSHDUIRO
ORZLQJ WKH 2SHUDWLRQ VHFWLRQ WKHVH WDEOHV SURYLGH FXUUHQW VWDWHQH[W VWDWH
LQIRUPDWLRQ
Table 34.1
Truth Table 1 - Commands and DQM Operation
1DPH)XQFWLRQ
&RPPDQG,QKLELW123
+
;
;
;
;
;
;
1R2SHUDWLRQ
/
+
+
+
;
;
;
;
$FWLYH6HOHFWEDQNDQGDFWLYDWHURZ
/
/
+
+
;
%DQN
5RZ
5HDG6HOHFWEDQNDQGFROXPQDQGVWDUW5HDGEXUVW
/
+
/
+
/+
%DQN&RO
;
:ULWH6HOHFWEDQNDQGFROXPQDQGVWDUW:ULWHEXUVW
/
+
/
/
/+
%DQN&RO
9DOLG
%XUVW7HUPLQDWHRU'HHS3RZHU'RZQ
(QWHUGHHSSRZHUGRZQPRGH
/
+
+
/
;
;
;
3UHFKDUJH'HDFWLYDWHURZLQEDQNRUEDQNV
/
/
+
/
;
%DQN
$
;
$XWR5HIUHVKRU6HOI5HIUHVK(QWHUVHOIUHIUHVKPRGH
/
/
/
+
;
;
;
/RDG0RGH5HJLVWHU/RDG([WHQGHG0RGH5HJLVWHU
/
/
/
/
;
2S&RGH
;
:ULWH(QDEOH2XWSXW(QDEOH
;
;
;
;
/
;
$FWLYH
:ULWH,QKLELW2XWSXW+LJK=
;
;
;
;
+
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+LJK=
1RWHV
&.(LV+LJKIRUDOOFRPPDQGVVKRZQH[FHSW6HOI5HIUHVKDQG'HHS3RZHU'RZQ
$$GHILQHRSFRGHZULWWHQWRPRGHUHJLVWHU
$±$SURYLGHURZDGGUHVVDQG%$%$GHWHUPLQHZKLFKEDQNLVPDGHDFWLYH
$±$SURYLGHFROXPQDGGUHVV$+LJKHQDEOHVWKHDXWRSUHFKDUJHIHDWXUHQRQ
SHUVLVWHQWZKLOH$/RZGLVDEOHVWKHDXWRSUHFKDUJHIHDWXUH%$%$GHWHU
PLQHZKLFKEDQNLVEHLQJUHDGIURPRUZULWWHQWR
$/RZ%$%$GHWHUPLQHWKHEDQNEHLQJSUHFKDUJHG$+LJK$OOEDQNV
SUHFKDUJHGDQG%$%$DUH³'RQ¶W&DUH´
7KLVFRPPDQGLV$XWR5HIUHVKLI&.(LV+LJK6HOI5HIUHVKLI&.(LV/RZ
,QWHUQDOUHIUHVKFRXQWHUFRQWUROVURZDGGUHVVLQJDOOLQSXWVDQG,2VDUH³'RQ¶W
&DUH´H[FHSWIRU&.(
$FWLYDWHVRUGHDFWLYDWHVWKH'4VGXULQJ:ULWHV]HURFORFNGHOD\DQG5HDGVWZR
FORFNGHOD\'40/FRQWUROV'4'40+FRQWUROV'4
7KLVFRPPDQGLV%XUVW7HUPLQDWHZKHQ&.(LVKLJKDQG'HHS3RZHU'RZQZKHQ
&.(LVORZ
7KHSXUSRVHRIWKH%XUVW7HUPLQDWHFRPPDQGLVWRVWRSDGDWDEXUVWWKXVWKH
FRPPDQGFRXOGFRLQFLGHZLWKGDWDRQWKHEXV+RZHYHUWKH'4VFROXPQUHDGVD
GRQ¶WFDUHVWDWHWRLOOXVWUDWHWKDWWKH%XUVW7HUPLQDWHFRPPDQGFDQRFFXUZKHQ
WKHUHLVQRGDWDSUHVHQW
35 Command Inhibit
7KH&RPPDQG,QKLELWIXQFWLRQSUHYHQWVQHZFRPPDQGVIURPEHLQJH[HFXWHGE\
WKH6'5$0UHJDUGOHVVRIZKHWKHUWKH&/.VLJQDOLVHQDEOHG7KH6'5$0LVHI
IHFWLYHO\GHVHOHFWHG2SHUDWLRQVDOUHDG\LQSURJUHVVDUHQRWDIIHFWHG
36 No Operation (NOP)
7KH1R2SHUDWLRQ123FRPPDQGLVXVHGWRSHUIRUPD123WRDQ6'5$0ZKLFK
LVVHOHFWHG&6LV/RZ7KLVSUHYHQWVXQZDQWHGFRPPDQGVIURPEHLQJUHJLV
WHUHGGXULQJLGOHRUZDLWVWDWHV2SHUDWLRQVDOUHDG\LQSURJUHVVDUHQRWDIIHFWHG
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
115
P r e l i m i n a r y
37 Load Mode Register
7KHPRGHUHJLVWHULVORDGHGYLDLQSXWV$±$%$%$6HHPRGHUHJLVWHU
KHDGLQJLQWKH5HJLVWHU'HILQLWLRQVHFWLRQ7KH/RDG0RGH5HJLVWHUDQG/RDG([
WHQGHG0RGH5HJLVWHUFRPPDQGVFDQRQO\EHLVVXHGZKHQDOOEDQNVDUHLGOHDQG
DVXEVHTXHQWH[HFXWDEOHFRPPDQGFDQQRWEHLVVXHGXQWLOW05'LVPHW
7KHYDOXHVRIWKHPRGHUHJLVWHUDQGH[WHQGHGPRGHUHJLVWHUZLOOEHUHWDLQHGHYHQ
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38 Active
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RSHQIRUDFFHVVHVXQWLODSUHFKDUJHFRPPDQGLVLVVXHGWRWKDWEDQN$SUH
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EDQN
39 Read
7KH5HDGFRPPDQGLVXVHGWRLQLWLDWHDEXUVWUHDGDFFHVVWRDQDFWLYHURZ7KH
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SXWV $±$ VHOHFWV WKH VWDUWLQJ FROXPQ ORFDWLRQ 7KH YDOXH RQ LQSXW $
GHWHUPLQHVZKHWKHURUQRWDXWRSUHFKDUJHLVXVHG,IDXWRSUHFKDUJHLVVHOHFWHG
WKHURZEHLQJDFFHVVHGZLOOEHSUHFKDUJHGDWWKHHQGRIWKHUHDGEXUVWLIDXWR
SUHFKDUJHLVQRWVHOHFWHGWKHURZZLOOUHPDLQRSHQIRUVXEVHTXHQWDFFHVVHV
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FORFNVHDUOLHU,IDJLYHQ'40VLJQDOZDVUHJLVWHUHG+LJKWKHFRUUHVSRQGLQJ'4
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SURYLGHYDOLGGDWD
40 Write
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SXWV $±$ VHOHFWV WKH VWDUWLQJ FROXPQ ORFDWLRQ 7KH YDOXH RQ LQSXW $
GHWHUPLQHVZKHWKHURUQRWDXWRSUHFKDUJHLVXVHG,IDXWRSUHFKDUJHLVVHOHFWHG
WKHURZEHLQJDFFHVVHGZLOOEHSUHFKDUJHGDWWKHHQGRIWKHZULWHEXUVWLIDXWR
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,QSXWGDWDDSSHDULQJRQWKH'4LVZULWWHQWRWKHPHPRU\DUUD\VXEMHFWWRWKH
'40LQSXWORJLFOHYHODSSHDULQJFRLQFLGHQWZLWKWKHGDWD,IDJLYHQ'40VLJQDO
LVUHJLVWHUHG/RZWKHFRUUHVSRQGLQJGDWDZLOOEHZULWWHQWRPHPRU\LIWKH'40
VLJQDOLVUHJLVWHUHG+LJKWKHFRUUHVSRQGLQJGDWDLQSXWVZLOOEHLJQRUHGDQGD
ZULWHZLOOQRWEHH[HFXWHGWRWKDWE\WHFROXPQORFDWLRQ
41 Precharge
7KH3UHFKDUJHFRPPDQGLVXVHGWRGHDFWLYDWHWKHRSHQURZLQDSDUWLFXODUEDQN
RUWKHRSHQURZLQDOOEDQNV7KHEDQNVZLOOEHDYDLODEOHIRUDVXEVHTXHQWURZ
DFFHVVDVSHFLILHGWLPHW53DIWHUWKHSUHFKDUJHFRPPDQGLVLVVXHG,QSXW$
GHWHUPLQHVZKHWKHURQHRUDOOEDQNVDUHWREHSUHFKDUJHGDQGLQWKHFDVHZKHUH
RQO\RQHEDQNLVWREHSUHFKDUJHGLQSXWV%$%$VHOHFWWKHEDQN2WKHUZLVH
%$%$DUHWUHDWHGDV³'RQ¶W&DUH´2QFHDEDQNKDVEHHQSUHFKDUJHGLWLVLQ
116
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
WKHLGOHVWDWHDQGPXVWEHDFWLYDWHGSULRUWRDQ\5HDGRU:ULWHFRPPDQGVEHLQJ
LVVXHGWRWKDWEDQN
42 Auto Precharge
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IXQFWLRQGHVFULEHGDERYHZLWKRXWUHTXLULQJDQH[SOLFLWFRPPDQG7KLVLVDFFRP
SOLVKHGE\XVLQJ$WRHQDEOHDXWRSUHFKDUJHLQFRQMXQFWLRQZLWKDVSHFLILF5HDG
RU:ULWHFRPPDQG$SUHFKDUJHRIWKHEDQNURZWKDWLVDGGUHVVHGZLWKWKH5HDG
RU:ULWHFRPPDQGLVDXWRPDWLFDOO\SHUIRUPHGXSRQFRPSOHWLRQRIWKH5HDGRU
:ULWHEXUVWH[FHSWLQWKHIXOOSDJHEXUVWPRGHZKHUHDXWRSUHFKDUJHGRHVQRW
DSSO\$XWRSUHFKDUJHLVQRQSHUVLVWHQWLQWKDWLWLVHLWKHUHQDEOHGRUGLVDEOHGIRU
HDFKLQGLYLGXDO5HDGRU:ULWHFRPPDQG
$XWRSUHFKDUJHHQVXUHVWKDWWKHSUHFKDUJHLVLQLWLDWHGDWWKHHDUOLHVWYDOLGVWDJH
ZLWKLQDEXUVW7KHXVHUPXVWQRWLVVXHDQRWKHUFRPPDQGWRWKHVDPHEDQNXQWLO
WKHSUHFKDUJHWLPHW53LVFRPSOHWHG7KLVLVGHWHUPLQHGDVLIDQH[SOLFLW3UH
FKDUJHFRPPDQGZDVLVVXHGDWWKHHDUOLHVWSRVVLEOHWLPHDVGHVFULEHGIRUHDFK
EXUVWW\SHLQWKH2SHUDWLRQVHFWLRQRIWKLVGDWDVKHHW
43 Burst Terminate
7KH%XUVW7HUPLQDWHFRPPDQGLVXVHGWRWUXQFDWHHLWKHUIL[HGOHQJWKRUIXOOSDJH
EXUVWV7KHPRVWUHFHQWO\UHJLVWHUHG5HDGRU:ULWHFRPPDQGSULRUWRWKH%XUVW
7HUPLQDWHFRPPDQGZLOOEHWUXQFDWHGDVVKRZQLQWKH2SHUDWLRQVHFWLRQRIWKLV
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44 Auto Refresh
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IUHVKFRPPDQGVKRXOGQRWEHLVVXHGXQWLOWKHPLQLPXPW53KDVEHHQPHWDIWHU
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7KHDGGUHVVLQJLVJHQHUDWHGE\WKHLQWHUQDOUHIUHVKFRQWUROOHU7KLVPDNHVWKHDG
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$XWR5HIUHVKFRPPDQGHYHU\—VZLOOPHHWWKHUHIUHVKUHTXLUHPHQWDQG
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45 Self Refresh
7KH6HOI5HIUHVKFRPPDQGFDQEHXVHGWRUHWDLQGDWDLQWKH6'5$0HYHQLIWKH
UHVWRIWKHV\VWHPLVSRZHUHGGRZQDVORQJDVSRZHULVQRWFRPSOHWHO\UHPRYHG
IURPWKH6'5$0:KHQLQWKHVHOIUHIUHVKPRGHWKH6'5$0UHWDLQVGDWDZLWKRXW
H[WHUQDOFORFNLQJ7KH6HOI5HIUHVKFRPPDQGLVLQLWLDWHGOLNHDQ$XWR5HIUHVK
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FDXVLQJLWWRSHUIRUPLWVRZQDXWRUHIUHVKF\FOHV7KH6'5$0PXVWUHPDLQLQVHOI
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
117
P r e l i m i n a r y
UHIUHVKPRGHIRUDPLQLPXPSHULRGHTXDOWRW5$6DQGPD\UHPDLQLQVHOIUHIUHVK
PRGHIRUDQLQGHILQLWHSHULRGEH\RQGWKDW
7KHSURFHGXUHIRUH[LWLQJVHOIUHIUHVKUHTXLUHVDVHTXHQFHRIFRPPDQGV)LUVW
&/.PXVWEHVWDEOHVWDEOHFORFNLVGHILQHGDVDVLJQDOF\FOLQJZLWKLQWLPLQJFRQ
VWUDLQWVVSHFLILHGIRUWKHFORFNSLQSULRUWR&.(JRLQJEDFN+LJK2QFH&.(LV
+LJKWKH6'5$0PXVWKDYH123FRPPDQGVLVVXHGDPLQLPXPRIWZRFORFNV
IRUW;65EHFDXVHWLPHLVUHTXLUHGIRUWKHFRPSOHWLRQRIDQ\LQWHUQDOUHIUHVKLQ
SURJUHVV
8SRQH[LWLQJWKHVHOIUHIUHVKPRGH$XWR5HIUHVKFRPPDQGVPXVWEHLVVXHG
HYHU\—VRUOHVVDVERWK6HOI5HIUHVKDQG$XWR5HIUHVKXWLOL]HWKHURZUH
IUHVKFRXQWHU
46 Deep Power-down
7KHRSHUDWLQJPRGHGHHSSRZHUGRZQDFKLHYHVPD[LPXPSRZHUUHGXFWLRQE\
HOLPLQDWLQJWKHSRZHURIWKHZKROHPHPRU\DUUD\RIWKHGHYLFH$UUD\GDWDZLOO
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7KLVPRGHLVHQWHUHGE\KDYLQJDOOEDQNVLGOHWKHQ&6DQG:(KHOGORZZLWK
5$6DQG&$6KHOGKLJKDWWKHULVLQJHGJHRIWKHFORFNZKLOH&.(LVORZ7KLV
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47 Operation
47.1
Bank/Row Activation
%HIRUHDQ\5HDGRU:ULWHFRPPDQGVFDQEHLVVXHGWRDEDQNZLWKLQWKH6'5$0
DURZLQWKDWEDQNPXVWEH³RSHQHG´7KLVLVDFFRPSOLVKHGYLDWKH$FWLYHFRP
PDQGZKLFKVHOHFWVERWKWKHEDQNDQGWKHURZWREHDFWLYDWHGVHH)LJXUH $FWLYDWLQJD6SHFLILF5RZLQD6SHFLILF%DQN5HJLVWHU
$IWHURSHQLQJDURZLVVXLQJDQ$FWLYHFRPPDQGD5HDGRU:ULWHFRPPDQGPD\
EHLVVXHGWRWKDWURZVXEMHFWWRWKHW5&'VSHFLILFDWLRQW5&'0,1VKRXOGEHGL
YLGHGE\WKHFORFNSHULRGDQGURXQGHGXSWRWKHQH[WZKROHQXPEHUWRGHWHUPLQH
WKHHDUOLHVWFORFNHGJHDIWHUWKH$FWLYHFRPPDQGRQZKLFKD5HDGRU:ULWHFRP
PDQGFDQEHHQWHUHG)RUH[DPSOHDW5&'VSHFLILFDWLRQRIQVZLWKD0+]
FORFN QV SHULRG UHVXOWV LQ FORFNV URXQGHG WR 7KLV LV UHIOHFWHG LQ
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LVVXHGDIWHUWKHSUHYLRXVDFWLYHURZKDVEHHQ³FORVHG´SUHFKDUJHG7KHPLQL
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GHILQHGE\W5&
$VXEVHTXHQW$FWLYHFRPPDQGWRDQRWKHUEDQNFDQEHLVVXHGZKLOHWKHILUVWEDQN
LVEHLQJDFFHVVHGZKLFKUHVXOWVLQDUHGXFWLRQRIWRWDOURZDFFHVVRYHUKHDG7KH
PLQLPXPWLPHLQWHUYDOEHWZHHQVXFFHVVLYH$FWLYHFRPPDQGVWRGLIIHUHQWEDQNV
LVGHILQHGE\W55'
118
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A10, A11
BANK
ADDRESS
BA0, BA1
DON’T CARE
Figure 47.1 Activating a Specific Row in a Specific Bank Register
T0
T1
T2
NOP
NOP
T3
T4
CLK
COMMAND
ACTIVE
READ or
WRITE
tRCD
DON’T CARE
Figure 47.2.
Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK≤ 3
47.2 Reads
5HDGEXUVWVDUHLQLWLDWHGZLWKD5HDGFRPPDQGDV
VKRZQLQ)LJXUH 7KHVWDUWLQJFROXPQDQGEDQNDGGUHVVHVDUHSURYLGHGZLWKWKH5HDGFRPPDQG
DQGDXWRSUHFKDUJHLVHLWKHUHQDEOHGRUGLVDEOHGIRUWKDWEXUVWDFFHVV,IDXWRSUH
FKDUJHLVHQDEOHGWKHURZEHLQJDFFHVVHGLVSUHFKDUJHGDWWKHFRPSOHWLRQRIWKH
EXUVW)RUWKHJHQHULF5HDGFRPPDQGVXVHGLQWKHIROORZLQJLOOXVWUDWLRQVDXWR
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ZLOOEHDYDLODEOHIROORZLQJWKH&$6ODWHQF\DIWHUWKH5HDGFRPPDQG(DFKVXEVH
TXHQWGDWDRXWHOHPHQWZLOOEHYDOLGE\WKHQH[WSRVLWLYHFORFNHGJH)LJXUH ³&$6/DWHQF\´RQSDJH VKRZVJHQHUDOWLPLQJIRUHDFKSRVVLEOH&$6ODWHQF\
VHWWLQJ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
119
P r e l i m i n a r y
8SRQFRPSOHWLRQRIDEXUVWDVVXPLQJQRRWKHUFRPPDQGVKDYHEHHQLQLWLDWHG
WKH'4ZLOOJR+LJK=$IXOOSDJHEXUVWZLOOFRQWLQXHXQWLOWHUPLQDWHG$WWKHHQG
RIWKHSDJHLWZLOOZUDSWRFROXPQDQGFRQWLQXH
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IURPD5HDGFRPPDQG,QHLWKHUFDVHDFRQWLQXRXVIORZRIGDWDFDQEHPDLQ
WDLQHG7KHILUVWGDWDHOHPHQWIURPWKHQHZEXUVWIROORZVHLWKHUWKHODVWHOHPHQW
RIDFRPSOHWHGEXUVWRUWKHODVWGHVLUHGGDWDHOHPHQWRIDORQJHUEXUVWWKDWLV
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FORFNHGJHDWZKLFKWKHODVWGHVLUHGGDWDHOHPHQWLVYDOLGZKHUH[HTXDOVWKH&$6
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7KLVLVVKRZQLQ)LJXUH ³&RQVHFXWLYH5HDG%XUVWV´RQSDJH IRU&$6
ODWHQFLHVRIWZRDQGWKUHHGDWDHOHPHQWQLVHLWKHUWKHODVWRIDEXUVWRIIRXU
RUWKHODVWGHVLUHGRIDORQJHUEXUVW7KH0E6'5$0XVHVDSLSHOLQHGDUFKL
WHFWXUHDQGWKHUHIRUHGRHVQRWUHTXLUHWKHQUXOHDVVRFLDWHGZLWKDSUHIHWFK
DUFKLWHFWXUH$5HDGFRPPDQGFDQEHLQLWLDWHGRQDQ\FORFNF\FOHIROORZLQJDSUH
YLRXV5HDGFRPPDQG)XOOVSHHGUDQGRPUHDGDFFHVVHVFDQEHSHUIRUPHGWRWKH
VDPHEDQNDVVKRZQLQ)LJXUH ³5DQGRP5HDG$FFHVVHV´RQSDJH RU
HDFKVXEVHTXHQW5HDGPD\EHSHUIRUPHGWRDGLIIHUHQWEDQN
'DWDIURPDQ\5HDGEXUVWPD\EHWUXQFDWHGZLWKDVXEVHTXHQW:ULWHFRPPDQG
DQGGDWDIURPDIL[HGOHQJWK5HDGEXUVWPD\EHLPPHGLDWHO\IROORZHGE\GDWD
IURPD:ULWHFRPPDQGVXEMHFWWREXVWXUQDURXQGOLPLWDWLRQV7KH:ULWHEXUVW
PD\EHLQLWLDWHGRQWKHFORFNHGJHLPPHGLDWHO\IROORZLQJWKHODVWRUODVWGHVLUHG
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,QDJLYHQV\VWHPGHVLJQWKHUHPD\EHDSRVVLELOLW\WKDWWKHGHYLFHGULYLQJWKH
LQSXWGDWDZLOOJR/RZ=EHIRUHWKH6'5$0'4JR+LJK=,QWKLVFDVHDWOHDVW
D VLQJOH F\FOH GHOD\ VKRXOG RFFXU EHWZHHQ WKH ODVW UHDG GDWD DQG WKH :ULWH
FRPPDQG
120
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0-A8
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0,1
DON’T CARE
Figure 47.1
November 8, 2005 SDRAM_01_A3
Read Command
Mobile SDRAM Type 1
121
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
READ
NOP
NOP
NOP
X = 1 cycle
BANK,
COL n
ADDRESS
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+ 3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
READ
NOP
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK,
COL n
BANK,
COL b
DOUT
n+ 1
DOUT
n
DQ
DOUT
n+ 2
DOUT
n+ 3
DOUT
b
CAS Latency = 3
TRANSITIONING DATA
Figure 47.2.
DON’T CARE
Consecutive Read Bursts
1RWH(DFK5HDGFRPPDQGPD\EHWRDQ\EDQN'40LV/RZ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
READ
READ
READ
READ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
READ
READ
READ
READ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
a
NOP
NOP
DOUT
x
DOUT
m
CAS Latency = 3
TRANSITIONING DATA
Figure 47.3.
DON’T CARE
Random Read Accesses
1RWH(DFK5HDGFRPPDQGPD\EHWRDQ\EDQN'40LVORZ
7KH'40LQSXWLVXVHGWRDYRLG,2FRQWHQWLRQDVVKRZQLQ)LJXUH DQG
)LJXUH 7KH'40VLJQDOPXVWEHDVVHUWHG+LJKDWOHDVWWZRFORFNVSULRUWR
WKH:ULWHFRPPDQG'40ODWHQF\LVWZRFORFNVIRURXWSXWEXIIHUVWRVXSSUHVV
122
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
GDWDRXWIURPWKH5HDG2QFHWKH:ULWHFRPPDQGLVUHJLVWHUHGWKH'4ZLOOJR
+LJK=RUUHPDLQ+LJK=UHJDUGOHVVRIWKHVWDWHRIWKH'40VLJQDOSURYLGHG
WKH'40ZDVDFWLYHRQWKHFORFNMXVWSULRUWRWKH:ULWHFRPPDQGWKDWWUXQFDWHG
WKH5HDGFRPPDQG,IQRWWKHVHFRQG:ULWHZLOOEHDQLQYDOLG:ULWH)RUH[DPSOH
LI'40ZDV/RZGXULQJ7LQ)LJXUH WKHQWKH:ULWHVDW7DQG7ZRXOGEH
YDOLGZKLOHWKH:ULWHDW7ZRXOGEHLQYDOLG
7KH'40VLJQDOPXVWEHGHDVVHUWHGSULRUWRWKH:ULWHFRPPDQG'40ODWHQF\
LV]HURFORFNVIRULQSXWEXIIHUVWRHQVXUHWKDWWKHZULWWHQGDWDLVQRWPDVNHG
)LJXUH VKRZVWKHFDVHZKHUHWKHFORFNIUHTXHQF\DOORZVIRUEXVFRQWHQWLRQ
WREHDYRLGHGZLWKRXWDGGLQJD123F\FOHDQGVKRZVWKHFDVHZKHUHWKHDGGL
WLRQDO123LVQHHGHG$IL[HGOHQJWK5HDGEXUVWPD\EHIROORZHGE\RUWUXQFDWHG
ZLWKD3UHFKDUJHFRPPDQGWRWKHVDPHEDQNSURYLGHGWKDWDXWRSUHFKDUJHZDV
QRWDFWLYDWHGDQGDIXOOSDJHEXUVWPD\EHWUXQFDWHGZLWKD3UHFKDUJHFRP
PDQGWRWKHVDPHEDQN7KH3UHFKDUJHFRPPDQG VKRXOGEHLVVXHG[F\FOHV
EHIRUHWKHFORFNHGJHDWZKLFKWKHODVWGHVLUHGGDWDHOHPHQWLVYDOLGZKHUH[
HTXDOVWKH&$6ODWHQF\PLQXVRQH7KLVLVVKRZQLQ)LJXUH IRUHDFKSRVVLEOH
&$6ODWHQF\GDWDHOHPHQWQLVHLWKHUWKHODVWRIDEXUVWRIIRXURUWKHODVW
GHVLUHGRIDORQJHUEXUVW)ROORZLQJWKH3UHFKDUJHFRPPDQGDVXEVHTXHQWFRP
PDQGWRWKHVDPHEDQNFDQQRWEHLVVXHGXQWLOW53LVPHW1RWHWKDWSDUWRIWKH
URZSUHFKDUJHWLPHLVKLGGHQGXULQJWKHDFFHVVRIWKHODVWGDWDHOHPHQWV
,QWKHFDVHRIDIL[HGOHQJWKEXUVWEHLQJH[HFXWHGWRFRPSOHWLRQD3UHFKDUJH
FRPPDQGLVVXHGDWWKHRSWLPXPWLPHDVGHVFULEHGDERYHSURYLGHVWKHVDPH
RSHUDWLRQWKDW ZRXOGUHVXOWIURPWKHVDPH IL[HGOHQJWK EXUVW ZLWKDXWRSUH
FKDUJH7KHGLVDGYDQWDJHRIWKH3UHFKDUJHFRPPDQGLVWKDWLWUHTXLUHVWKDWWKH
FRPPDQGDQGDGGUHVVEXVHVEHDYDLODEOHDWWKHDSSURSULDWHWLPHWRLVVXHWKH
FRPPDQGWKHDGYDQWDJHRIWKH3UHFKDUJHFRPPDQGLVWKDWLWFDQEHXVHGWR
WUXQFDWHIL[HGOHQJWKRUIXOOSDJHEXUVWV
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
ADDRESS
READ
NOP
NOP
NOP
BANK,
COL n
WRITE
BANK,
COL b
tCK
tHZ
DQ
DOUT n
DIN b
tDS
Figure 47.4.
November 8, 2005 SDRAM_01_A3
Read to Write
Mobile SDRAM Type 1
123
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
READ
ADDRESS
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
BANK,
COL n
tHZ
DQ
DIN b
DOUT n
tDS
DON’T CARE
Figure 47.5. Read to Write with Extra Clock Cycle
1RWH$&$6ODWHQF\RIWKUHHLVXVHGIRULOOXVWUDWLRQ7KH5HDGFRPPDQGPD\EHWR
DQ\EDQNDQGWKH:ULWHFRPPDQGPD\EHWRDQ\EDQN
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
BANK a,
ROW
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CAS Latency = 3
TRANSITIONING DATA
Figure 47.6.
DON’T CARE
Read to Precharge
1RWH'40LVORZ
124
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
ADDRESS
BANK,
COL n
DOUT
n
DQ
DOUT
n+ 2
DOUT
n+ 1
DOUT
n+ 3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK,
COL n
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
Figure 47.7. Terminating a Read Burst
1RWH'40LVORZ
)XOOSDJH5HDGEXUVWVFDQEHWUXQFDWHGZLWKWKH%XUVW7HUPLQDWHFRPPDQGDQG
IL[HGOHQJWK5HDGEXUVWVPD\EHWUXQFDWHGZLWKD%XUVW7HUPLQDWHFRPPDQG
SURYLGHGWKDWDXWRSUHFKDUJHZDVQRWDFWLYDWHG7KH%XUVW7HUPLQDWHFRPPDQG
VKRXOGEHLVVXHG[F\FOHVEHIRUHWKHFORFNHGJHDWZKLFKWKHODVWGHVLUHGGDWDHO
HPHQWLVYDOLGZKHUH[HTXDOVWKH&$6ODWHQF\PLQXVRQH7KLVLV VKRZQLQ
)LJXUH IRUHDFKSRVVLEOH&$6ODWHQF\GDWDHOHPHQWQLVWKHODVWGHVLUHG
GDWDHOHPHQWRIDORQJHUEXUVW
47.3
Writes
:ULWHEXUVWVDUHLQLWLDWHGZLWKD:ULWHFRPPDQGDVVKRZQLQ)LJXUH 7KHVWDUWLQJFROXPQDQGEDQNDGGUHVVHVDUHSURYLGHGZLWKWKH:ULWHFRPPDQG
DQGDXWRSUHFKDUJHLVHLWKHUHQDEOHGRUGLVDEOHGIRUWKDWDFFHVV,IDXWRSUH
FKDUJHLVHQDEOHGWKHURZEHLQJDFFHVVHGLVSUHFKDUJHGDWWKHFRPSOHWLRQRIWKH
EXUVW)RUWKHJHQHULF:ULWHFRPPDQGVXVHGLQWKHIROORZLQJLOOXVWUDWLRQVDXWR
SUHFKDUJHLVGLVDEOHG
'XULQJ:ULWHEXUVWVWKHILUVWYDOLGGDWDLQHOHPHQWZLOOEHUHJLVWHUHGFRLQFLGHQW
ZLWKWKH:ULWHFRPPDQG6XEVHTXHQWGDWDHOHPHQWVZLOOEHUHJLVWHUHGRQHDFK
VXFFHVVLYHSRVLWLYHFORFNHGJH8SRQFRPSOHWLRQRIDIL[HGOHQJWKEXUVWDVVXP
LQJQRRWKHUFRPPDQGVKDYHEHHQLQLWLDWHGWKH'4ZLOOUHPDLQ+LJK=DQGDQ\
DGGLWLRQDOLQSXWGDWDZLOOEHLJQRUHGVHH)LJXUH $IXOOSDJHEXUVWZLOOFRQ
WLQXHXQWLOWHUPLQDWHG$WWKHHQGRIWKHSDJHLWZLOOZUDSWRFROXPQDQG
FRQWLQXH
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
125
P r e l i m i n a r y
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0-A8
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0,1
VALID ADDRESS
Figure 47.1
DON’T CARE
Write Command
'DWDIRUDQ\:ULWHEXUVWPD\EHWUXQFDWHGZLWKDVXEVHTXHQW:ULWHFRPPDQG
DQGGDWDIRUDIL[HGOHQJWK:ULWHEXUVWPD\EHLPPHGLDWHO\IROORZHGE\GDWDIRU
D:ULWHFRPPDQG7KHQHZ:ULWHFRPPDQGFDQEHLVVXHGRQDQ\FORFNIROORZLQJ
WKHSUHYLRXV:ULWHFRPPDQGDQGWKHGDWDSURYLGHGFRLQFLGHQWZLWKWKHQHZ
FRPPDQGDSSOLHVWRWKHQHZFRPPDQG$QH[DPSOHLVVKRZQLQ)LJXUH 'DWDQLVHLWKHUWKHODVWRIDEXUVWRIWZRRUWKHODVWGHVLUHGRIDORQJHUEXUVW
7KH0E6'5$0XVHVDSLSHOLQHGDUFKLWHFWXUHDQGWKHUHIRUHGRHVQRWUHTXLUH
WKHQUXOHDVVRFLDWHGZLWKDSUHIHWFKDUFKLWHFWXUH$:ULWHFRPPDQGFDQEHLQL
WLDWHGRQDQ\FORFNF\FOHIROORZLQJDSUHYLRXV:ULWHFRPPDQG)XOOVSHHGUDQGRP
ZULWHDFFHVVHVZLWKLQDSDJHFDQEHSHUIRUPHGWRWKHVDPHEDQNDVVKRZQLQ
)LJXUH RUHDFKVXEVHTXHQW:ULWHPD\EHSHUIRUPHGWRDGLIIHUHQWEDQN
126
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
WRITE
NOP
NOP
NOP
CLK
COMMAND
ADDRESS
BANK,
COL n
DIN
n
DQ
DIN
n+1
DON’T CARE
Figure 47.2. Write Burst
1RWH%XUVWOHQJWK '40LVORZ
T0
T1
T2
WRITE
NOP
WRITE
CLK
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL b
DIN
n+1
DIN
n
DIN
b
DON’T CARE
Figure 47.3.
Write to Write
1RWH'40LVORZ(DFK:ULWHFRPPDQGPD\EHWRDQ\EDQN
'DWDIRUDQ\:ULWHEXUVWPD\EHWUXQFDWHGZLWKDVXEVHTXHQW5HDGFRPPDQG
DQGGDWDIRUDIL[HGOHQJWK:ULWHEXUVWPD\EHLPPHGLDWHO\IROORZHGE\D5HDG
FRPPDQG2QFHWKH5HDGFRPPDQGLVUHJLVWHUHGWKHGDWDLQSXWVZLOOEHLJQRUHG
DQGZULWHVZLOOQRWEHH[HFXWHG$QH[DPSOHLVVKRZQLQ)LJXUH 'DWDQ
LVHLWKHUWKHODVWRIDEXUVWRIWZRRUWKHODVWGHVLUHGRIDORQJHUEXUVW
'DWDIRUDIL[HGOHQJWK:ULWHEXUVWPD\EHIROORZHGE\RUWUXQFDWHGZLWKD3UH
FKDUJH FRPPDQG WR WKH VDPH EDQN SURYLGHG WKDW DXWR SUHFKDUJH ZDV QRW
DFWLYDWHGDQGDIXOOSDJH:ULWHEXUVWPD\EHWUXQFDWHGZLWKD3UHFKDUJHFRP
PDQGWRWKHVDPHEDQN7KH3UHFKDUJHFRPPDQGVKRXOGEHLVVXHGW:5DIWHUWKH
FORFNHGJHDWZKLFKWKHODVWGHVLUHGLQSXWGDWDHOHPHQWLVUHJLVWHUHG7KHDXWR
SUHFKDUJHPRGHUHTXLUHVDW:5RIDWOHDVWRQHFORFNSOXVWLPHUHJDUGOHVVRI
IUHTXHQF\
,QDGGLWLRQZKHQWUXQFDWLQJD:ULWHEXUVWWKH'40VLJQDOPXVWEHXVHGWRPDVN
LQSXWGDWDIRUWKHFORFNHGJHSULRUWRDQGWKHFORFNHGJHFRLQFLGHQWZLWKWKH3UH
FKDUJHFRPPDQG$QH[DPSOHLVVKRZQLQ)LJXUH 'DWDQLVHLWKHUWKH
ODVWRIDEXUVWRIWZRRUWKHODVWGHVLUHGRIDORQJHUEXUVW)ROORZLQJWKH3UHFKDUJH
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
127
P r e l i m i n a r y
FRPPDQGDVXEVHTXHQWFRPPDQGWRWKHVDPHEDQNFDQQRWEHLVVXHGXQWLOW53
LVPHW
T0
T1
T2
T3
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DIN
n
DIN
a
DIN
x
DIN
m
CLK
COMMAND
ADDRESS
DQ
DON’T CARE
Figure 47.4.
Random Write Cycles
1RWH(DFK:ULWHFRPPDQGPD\EHWRDQ\EDQN'40LVORZ
T0
T1
T2
T3
T4
T5
WRITE
NOP
READ
NOP
NOP
NOP
DOUT
b
DOUT
b+1
CLK
COMMAND
ADDRESS
DQ
BANK,
COL n
DIN
n
BANK,
COL b
DIN
n+1
DON’T CARE
Figure 47.5.
Write to Read
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DQ\EDQN'40LVORZ&$6ODWHQF\ IRULOOXVWUDWLRQ
,QWKHFDVHRIDIL[HGOHQJWKEXUVWEHLQJH[HFXWHGWRFRPSOHWLRQD3UHFKDUJH
FRPPDQGLVVXHGDWWKHRSWLPXPWLPHDVGHVFULEHGDERYHSURYLGHVWKHVDPH
RSHUDWLRQWKDW ZRXOGUHVXOWIURPWKHVDPH IL[HGOHQJWK EXUVW ZLWKDXWRSUH
FKDUJH7KHGLVDGYDQWDJHRIWKH3UHFKDUJHFRPPDQGLVWKDWLWUHTXLUHVWKDWWKH
FRPPDQGDQGDGGUHVVEXVHVEHDYDLODEOHDWWKHDSSURSULDWHWLPHWRLVVXHWKH
FRPPDQGWKHDGYDQWDJHRIWKH3UHFKDUJHFRPPDQGLVWKDWLWFDQEHXVHGWR
WUXQFDWHIL[HGOHQJWKRUIXOOSDJHEXUVWV
)L[HGOHQJWKRUIXOOSDJH:ULWHEXUVWVFDQEHWUXQFDWHGZLWKWKH%XUVW7HUPLQDWH
FRPPDQG:KHQWUXQFDWLQJD:ULWHEXUVWWKHLQSXWGDWDDSSOLHGFRLQFLGHQWZLWK
WKH%XUVW7HUPLQDWHFRPPDQGZLOOEHLJQRUHG7KHODVWGDWDZULWWHQSURYLGHG
WKDW'40LV/RZDWWKDWWLPHZLOOEHWKHLQSXWGDWDDSSOLHGRQHFORFNSUHYLRXVWR
WKH%XUVW7HUPLQDWHFRPPDQG7KLVLVVKRZQLQ)LJXUH ZKHUHGDWDQLVWKH
ODVWGHVLUHGGDWDHOHPHQWRIDORQJHUEXUVW
128
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
T1
T2
T3
WRITE
NOP
PRECHARGE
NOP
T4
T5
T6
NOP
ACTIVE
NOP
CLK
tWR@ tCK 15ns
DQM
t RP
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
tWR@ tCK < 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
BANK a,
COL n
ACTIVE
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
DON’T CARE
Figure 47.6.
Write to Precharge
1RWH'40FRXOGUHPDLQORZLQWKLVH[DPSOHLIWKH:ULWHEXUVWLVDIL[HGOHQJWKRIWZR
47.4 Precharge
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DSDUWLFXODUEDQNRUWKHRSHQURZLQDOOEDQNV7KHEDQNVZLOOEHDYDLODEOHIRUD
VXEVHTXHQWURZDFFHVVVRPHVSHFLILHGWLPHW53DIWHUWKHSUHFKDUJHFRPPDQG
LVLVVXHG,QSXW$GHWHUPLQHVZKHWKHURQHRUDOOEDQNVDUHWREHSUHFKDUJHG
DQGLQWKHFDVHZKHUHRQO\RQHEDQNLVWREHSUHFKDUJHGLQSXWV%$%$VHOHFW
WKHEDQN:KHQDOOEDQNVDUHWREHSUHFKDUJHGLQSXWV%$%$DUHWUHDWHGDV
³'RQ¶W&DUH´2QFHDEDQNKDVEHHQSUHFKDUJHGLWLVLQWKHLGOHVWDWHDQGPXVW
EHDFWLYDWHGSULRUWRDQ\5HDGRU:ULWHFRPPDQGVEHLQJLVVXHGWRWKDWEDQN
47.5 Power-down
3RZHUGRZQRFFXUVLI&.(LVUHJLVWHUHGORZFRLQFLGHQWZLWKD123RU&RPPDQG
,QKLELWZKHQQRDFFHVVHVDUHLQSURJUHVV,ISRZHUGRZQRFFXUVZKHQDOOEDQNV
DUHLGOHWKLVPRGHLVUHIHUUHGWRDVSUHFKDUJHSRZHUGRZQLISRZHUGRZQRFFXUV
ZKHQWKHUHLVDURZDFWLYHLQDQ\EDQNWKLVPRGHLVUHIHUUHGWRDVDFWLYHSRZHU
GRZQ(QWHULQJSRZHUGRZQGHDFWLYDWHVWKHLQSXWDQGRXWSXWEXIIHUVH[FOXGLQJ
&.(IRUPD[LPXPSRZHUVDYLQJVZKLOHLQVWDQGE\7KHGHYLFHPD\QRWUHPDLQ
LQWKHSRZHUGRZQVWDWHORQJHUWKDQWKHUHIUHVKSHULRGPVVLQFHQRUHIUHVK
RSHUDWLRQVDUHSHUIRUPHGLQWKLVPRGH7KHSRZHUGRZQVWDWHLVH[LWHGE\UHJLV
WHULQJ D 123 RU &RPPDQG ,QKLELW DQG &.( +LJK DW WKH GHVLUHG FORFN HGJH
PHHWLQJW&.66HH)LJXUH November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
129
P r e l i m i n a r y
((
))
((
))
CLK
tCKS
CKE
> t CKS
((
))
COMMAND
((
))
((
))
NOP
All banks idle
NOP
ACTIVE
t RCD
Input buffers gated off
Enter power-down mode.
Figure 47.1.
t RAS
t RC
Exit power-down mode.
Power-Down
T0
T1
T2
WRITE
BURST
TERMINATE
NEXT
COMMAND
CLK
COMMAND
ADDRESS
DQ
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
TRANSITIONING DATA
DON’T CARE
Figure 47.2. Terminating a Write Burst
1RWH'40VDUHORZ
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A9, A11
All Banks
A10
Bank Selected
BANK
ADDRESS
BA0,1
VALID ADDRESS
Figure 47.3.
130
DON’T CARE
Precharge Command
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
47.6 Deep Power-down
'HHS3RZHU'RZQPRGHLVDPD[LPXPSRZHUVDYLQJVIHDWXUHDFKLHYHGE\VKXW
WLQJRIIWKHSRZHUWRWKHHQWLUHPHPRU\DUUD\RIWKHGHYLFH'DWDRQWKHPHPRU\
DUUD\ZLOOQRWEHUHWDLQHGRQFH'HHS3RZHU'RZQPRGHLVH[HFXWHG'HHS3RZHU
'RZQPRGHLVHQWHUHGE\KDYLQJDOOEDQNVLGOHWKHQ&6DQG:(KHOGORZZLWK
5$6DQG&$6KLJKDWWKHULVLQJHGJHRIWKHFORFNZKLOH&.(LVORZ&.(PXVW
EHKHOGORZGXULQJGHHSSRZHUGRZQ
,QRUGHUWRH[LW'HHS3RZHU'RZQPRGH&.(PXVWEHDVVHUWHGKLJK$IWHUH[LW
LQJWKHIROORZLQJVHTXHQFHLVQHHGHGLQRUGHUWRHQWHUDQHZFRPPDQG0DLQWDLQ
123LQSXWFRQGLWLRQVIRUDPLQLPXPRIXV,VVXH3UHFKDUJHFRPPDQGVIRUDOO
EDQNV,VVXHHLJKWRUPRUH$8725()5(6+FRPPDQGV7KHYDOXHVRIWKHPRGH
UHJLVWHUDQGH[WHQGHGPRGHUHJLVWHUZLOOEHUHWDLQHGXSRQH[LWLQJGHHSSRZHU
GRZQ
47.7 Clock Suspend
7KHFORFNVXVSHQGPRGHRFFXUVZKHQDFROXPQDFFHVVEXUVWLVLQSURJUHVVDQG
&.(LVUHJLVWHUHGORZ,QWKHFORFNVXVSHQGPRGHWKHLQWHUQDOFORFNLVGHDFWL
YDWHG³IUHH]LQJ´WKHV\QFKURQRXVORJLF
)RUHDFKSRVLWLYHFORFNHGJHRQZKLFK&.(LVVDPSOHG/RZWKHQH[WLQWHUQDOSRV
LWLYHFORFNHGJHLVVXVSHQGHG$Q\FRPPDQGRUGDWDSUHVHQWRQWKHLQSXWSLQVDW
WKHWLPHRIDVXVSHQGHGLQWHUQDOFORFNHGJHLVLJQRUHGDQ\GDWDSUHVHQWRQWKH
'4SLQVUHPDLQVGULYHQDQGEXUVWFRXQWHUVDUHQRWLQFUHPHQWHGDVORQJDVWKH
FORFNLVVXVSHQGHG6HHH[DPSOHVLQ)LJXUH DQG)LJXUH &ORFNVXVSHQGPRGHLVH[LWHGE\UHJLVWHULQJ&.(+LJKWKHLQWHUQDOFORFNDQGUH
ODWHGRSHUDWLRQZLOOUHVXPHRQWKHVXEVHTXHQWSRVLWLYHFORFNHGJH
47.8 Burst Read/Single Write
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PRGHELW0LQWKHPRGHUHJLVWHUWRDORJLF,QWKLVPRGHDOO:ULWHFRPPDQGV
UHVXOWLQWKHDFFHVVRIDVLQJOHFROXPQORFDWLRQEXUVWRIRQHUHJDUGOHVVRIWKH
SURJUDPPHGEXUVWOHQJWK5HDGFRPPDQGVDFFHVVFROXPQVDFFRUGLQJWRWKHSUR
JUDPPHGEXUVWOHQJWKDQGVHTXHQFHMXVWDVLQWKHQRUPDOPRGHRIRSHUDWLRQ
0 November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
131
P r e l i m i n a r y
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN
n+1
DIN
n+2
CLK
CKE
INTERNAL
CLOCK
COMMAND
BANK,
COL n
ADDRESS
DIN
n
DIN
DON’T CARE
Figure 47.4.
Clock Suspend During Write Burst
1RWH)RUWKLVH[DPSOHEXUVWOHQJWK RUJUHDWHUDQG'0LVORZ
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
BANK,
COL n
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DON’T CARE
Figure 47.5. Clock Suspend During Read Burst
1RWH)RUWKLVH[DPSOH&$6ODWHQF\ EXUVWOHQJWK RUJUHDWHUDQG'40LVORZ
47.9 Concurrent Auto Precharge
7KH6'5$0GHYLFHVVXSSRUW&RQFXUUHQW$XWRSUHFKDUJHZKLFKDOORZVDQDFFHVV
FRPPDQG5HDGRU:ULWHWRDQRWKHUEDQNZKLOHDQDFFHVVFRPPDQGZLWKDXWR
SUHFKDUJHHQDEOHGLVH[HFXWLQJ)RXUFDVHVZKHUHFRQFXUUHQWDXWRSUHFKDUJHRF
FXUVDUHGHILQHGEHORZ
132
5HDGZLWK$XWR3UHFKDUJH
,QWHUUXSWHGE\D5HDGZLWKRUZLWKRXWDXWRSUHFKDUJH$5HDGWREDQNP
ZLOOLQWHUUXSWD5HDGRQEDQNQWZRRUWKUHHFORFNVODWHUGHSHQGLQJRQ&$6
ODWHQF\7KHSUHFKDUJHWREDQNQZLOOEHJLQZKHQWKH5HDGWREDQNPLVUHJ
LVWHUHG)LJXUH ,QWHUUXSWHGE\D:ULWHZLWKRUZLWKRXWDXWRSUHFKDUJH:KHQD:ULWHWR
EDQNPUHJLVWHUVD5HDGRQEDQNQZLOOEHLQWHUUXSWHG'40VKRXOGEHXVHG
WZRFORFNVSULRUWRWKH:ULWHFRPPDQGWRSUHYHQWEXVFRQWHQWLRQ7KHSUH
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
FKDUJH WR EDQN Q ZLOO EHJLQ ZKHQ WKH :ULWH WR EDQN P LV UHJLVWHUHG
)LJXUH T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
NOP
Page Active
NOP
READ with Burst of 4
READ - AP
BANK m
NOP
NOP
NOP
Interrupt Burst, Precharge
NOP
Idle
tRP - BANKm
t RP - BANKn
Page Active
BANK m
BANK n,
COL a
ADDRESS
Precharge
READ with Burst of 4
BANK m,
COL d
DOUT
a
DQ
DOUT
a+1
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m )
DON’T CARE
Figure 47.6. Read with Auto Precharge Interrupted by a Read
1RWH'40LVORZ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
NOP
NOP
NOP
Page READ with Burst of 4
Active
WRITE - AP
BANK m
NOP
NOP
NOP
Interrupt Burst, Precharge
Idle
t WR -BANK m
tRP -BANK n
Page Active
BANK m
ADDRESS
Write-Back
WRITE with Burst of 4
BANK n,
COL a
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
DON’T CARE
Figure 47.7.
Read with Auto Precharge Interrupted by a Write
1RWH'40LVKLJKDW7WRSUHYHQW'287DIURPFRQWHQGLQJZLWK',1GDW7
47.10 Write with Auto Precharge
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EDQNPUHJLVWHUVLWZLOOLQWHUUXSWD:ULWHRQEDQNQZLWKWKHGDWDRXWDS
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EDQNQZLOOEHJLQDIWHUW:5LVPHWZKHUHW:5EHJLQVZKHQWKH5HDGWREDQN
PLVUHJLVWHUHG7KHODVWYDOLG:ULWHWREDQNQZLOOEHGDWDLQUHJLVWHUHGRQH
FORFNSULRUWRWKH5HDGWREDQNP)LJXUH ,QWHUUXSWHGE\D:ULWHZLWKRUZLWKRXWDXWRSUHFKDUJH:KHQD:ULWHWR
EDQNPUHJLVWHUVLWZLOOLQWHUUXSWD:ULWHRQEDQNQ7KHSUHFKDUJHWREDQN
QZLOOEHJLQDIWHUW:5LVPHWZKHUHW:5EHJLQVZKHQWKH:ULWHWREDQNPLV
UHJLVWHUHG7KHODVWYDOLGGDWD:ULWHWREDQNQZLOOEHGDWDUHJLVWHUHGRQH
FORFNSULRUWRD:ULWHWREDQNP)LJXUH November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
133
P r e l i m i n a r y
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
WRITE - AP
BANK n
NOP
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
NOP
NOP
Page Active
tRP - BANK n
BANK m,
COL d
DIN
a
DQ
tRP - BANKm
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
Interrupt Burst, Write-Back Precharge
tWR - BANKn
BANK m
NOP
DOUT
d+ 1
DOUT
d
DIN
a+1
CAS Latency = 3 (BANK m)
DON’T CARE
Figure 47.8. Write with Auto Precharge Interrupted by a Read
1RWH'40LVORZ
T0
T1
NOP
WRITE - AP
BANK n
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
Page Active
NOP
NOP
WRITE with Burst of 4
WRITE - AP
BANK m
NOP
Interrupt Burst, Write-Back
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
NOP
Precharge
tRP - BANKn
t WR - BANKm
Write-Back
WRITE with Burst of 4
BANK n,
COL a
DIN
a
NOP
BANK m,
COL d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
Figure 47.9.
Write with Auto Precharge Interrupted by a Write
1RWH'40LVORZ
134
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
Table 47.1
&.(Q
/
/
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/
+
+
/
+
+
Truth Table 2 - CKE
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3RZHU'RZQ
;
0DLQWDLQ3RZHU'RZQ
1RWHV
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;
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LQWLPHIRUFORFNHGJHQSURYLGHGWKDWW&.6LVPHW
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RQFHW;65LVPHW&RPPDQG,QKLELWRU123FRPPDQGVVKRXOGEHLVVXHGRQDQ\
FORFNHGJHVRFFXUULQJGXULQJWKHW;65SHULRG$PLQLPXPRIWZR123FRPPDQGV
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FRPPDQGLV%XUVW7HUPLQDWHZKHQ&.(LVKLJKDQG'HHS3RZHU'RZQZKHQ&.(
LVORZ
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
135
P r e l i m i n a r y
Table 47.2 Truth Table 3 - Current State Bank n, Command to Bank n
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/
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/
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/
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5HDG$5HDGEXUVWKDVEHHQLQLWLDWHGZLWKDXWRSUHFKDUJHGLVDEOHGDQGKDVQRW
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EDQNZLOOEHLQWKHLGOHVWDWH
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PDQGDQGHQGVZKHQW05'KDVEHHQPHW
2QFHW05'LVPHWWKH6'5$0ZLOOEHLQWKHDOOEDQNVLGOHVWDWH
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
3UHFKDUJLQJ$OO6WDUWVZLWKUHJLVWUDWLRQRID3UHFKDUJH$OOFRPPDQGDQGHQGV
ZKHQW53LVPHW2QFHW53LVPHWDOOEDQNVZLOOEHLQWKHLGOHVWDWH
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Table 47.3
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5HDG
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Truth Table 4 - Current State Bank n, Command to Bank m
&6
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5HDGZ$XWR3UHFKDUJH(QDEOHG6WDUWVZLWKUHJLVWUDWLRQRID5HDGFRPPDQGZLWK
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
137
P r e l i m i n a r y
DXWRSUHFKDUJHHQDEOHGDQGHQGVZKHQW53KDVEHHQPHW2QFHW53LVPHWWKH
EDQNZLOOEHLQWKHLGOHVWDWH
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138
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
48 Absolute Maximum Ratings
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Table 48.1
DC Electrical Characteristics and Operating Conditions
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$OORWKHUSLQVQRWXQGHUWHVW 9
2XWSXW/HDNDJH&XUUHQW'4GLVDEOHG
9≤9287≤ 9''4
[9''4 9'' [9''4 9''
9
1RWHV
1RWHV
$OOYROWDJHVUHIHUHQFHGWR9669'' 9''4 9“9
7KHPLQLPXPVSHFLILFDWLRQVDUHXVHGRQO\WRLQGLFDWHF\FOHWLPHDWZKLFKSURSHU
RSHUDWLRQRYHUWKHIXOOWHPSHUDWXUHUDQJHƒ&≤7$≤ƒ&IRUVWDQGDUGSDUWV
ƒ&≤7$≤ƒ&IRU,7SDUWVLVHQVXUHG
$QLQLWLDOSDXVHRI—VLVUHTXLUHGDIWHUSRZHUXSIROORZHGE\WZR$XWR5HIUHVK
FRPPDQGVEHIRUHSURSHUGHYLFHRSHUDWLRQLVHQVXUHG9''DQG9''4PXVWEH
SRZHUHGXSVLPXOWDQHRXVO\966DQG9664PXVWEHDWVDPHSRWHQWLDO7KHWZR
$XWR5HIUHVKFRPPDQGZDNHXSVVKRXOGEHUHSHDWHGDQ\WLPHWKHW5()UHIUHVK
UHTXLUHPHQWLVH[FHHGHG
9,+RYHUVKRRW9,+0$; 9''49IRUDSXOVHZLGWK≤QVDQGWKHSXOVHZLGWK
FDQQRWEHJUHDWHUWKDQRQHWKLUGRIWKHF\FOHUDWH9,/XQGHUVKRRW9,/0,1 9IRUDSXOVHZLGWK≤QV
(6',PPXQLW\6SDQVLRQ)ODVKPHPRU\0XOWL&KLS3URGXFWV0&3VPD\FRQ
WDLQFRPSRQHQWGHYLFHVWKDWDUHGHYHORSHGE\6SDQVLRQDQGFRPSRQHQWGHYLFHV
WKDWDUHGHYHORSHGE\DWKLUGSDUW\WKLUGSDUW\FRPSRQHQWV6SDQVLRQFRPSR
QHQWVDUHWHVWHGDQGJXDUDQWHHGWRWKH(6'LPPXQLW\OHYHOVOLVWHGLQWKHFRUUH
VSRQLQJ6SDQLRQ)ODVKPHPRU\4XDOLILFDWLRQ'DWDEDVH7KLUGSDUW\FRPSRQHQWV
DUHQHLWKHUWHVWHGQRUJXDUDQWHHGE\6SDQVLRQIRU(6'LPPXQLW\+RZHYHU(6'
WHVWUHVXOWVIRUWKLUGSDUW\FRPSRQHQWVPD\EHDYDLODEOHIURPWKHFRPSRQHQW
PDQXIDFWXUHU&RPSRQHQWPDQXIDFWXUHUFRQWDFWLQIRUPDWLRQLVOLVWHGLQWKH6SDQ
VLRQ0&34XDOLILFDWLRQ5HSRUWZKHQDYDLODEOH7KH6SDQLRQ)ODVKPHPRU\4XDO
LILFDWLRQ'DWDEDVHDQG6SDQVLRQ0&34XDOLILFDWLRQ5HSRUWDUHDYDLODEOHIURP
6SDQVLRQDQG)XMLWVXVDOHVRIILFHV
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
139
P r e l i m i n a r y
Table 48.2 AC Electrical Characteristics and Operating Conditions
Parameter
,QSXW+LJK9ROWDJH/RJLF$OOLQSXWV
Symbol
9,+
Min
Max
²
Units
9
,QSXW/RZ9ROWDJH/RJLF$OOLQSXWV
9,/
²
9
Table 48.3
Electrical Characteristics and Recommended AC Operating
Conditions
$&&KDUDFWHULVWLFV
-75
3DUDPHWHU
$FFHVVWLPHIURP&/.SRV
HGJH
Notes
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0LQ
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0LQ
0D[
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8QLWV
1RWH
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&/ W&.
&/ W&.
&ORFNF\FOHWLPH
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W&.+
&.(VHWXSWLPH
W&.6
&65$6&$6:('40KROG
WLPH
W&0+
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WLPH
W&06
'DWDLQKROGWLPH
W'+
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W'6
'DWDRXWKLJKLPSHGDQFHWLPH
QV
&/ W+=
&/ W+=
'DWDRXWORZLPSHGDQFHWLPH
W/=
'DWDRXWKROGWLPHORDG
W2+
'DWDRXWKROGWLPHQRORDG
W2+1
$FWLYHWR3UHFKDUJHFRPPDQG
W5$6
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W5&
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5HIUHVKSHULRGURZV
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2XWSXWVPHDVXUHGIRU9DW9ZLWKHTXLYDOHQWORDG
140
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
Q
30pF
$&WLPLQJDQG,''WHVWVKDYH9,/DQG9,+ZLWKWLPLQJUHIHUHQFHGWR9,+ FURVV
RYHUSRLQW,IWKHLQSXWWUDQVLWLRQWLPHLVORQJHUWKDQW70$;WKHQWKHWLPLQJLV
UHIHUHQFHGDW9,/0$;DQG9,+0,1DQGQRORQJHUDWWKH9,+FURVVRYHUSRLQW
7KHFORFNIUHTXHQF\PXVWUHPDLQFRQVWDQWVWDEOHFORFNLVGHILQHGDVDVLJQDOF\
FOLQJZLWKLQWLPLQJFRQVWUDLQWVVSHFLILHGIRUWKHFORFNSLQGXULQJDFFHVVRUSUH
FKDUJHVWDWHV5HDG:ULWHLQFOXGLQJW:5DQG3UHFKDUJHFRPPDQGV&.(PD\EH
XVHGWRUHGXFHWKHGDWDUDWH
W+=GHILQHVWKHWLPHDWZKLFKWKHRXWSXWDFKLHYHVWKHRSHQFLUFXLWFRQGLWLRQLWLV
QRWDUHIHUHQFHWR92+RU92/7KHODVWYDOLGGDWDHOHPHQWZLOOPHHWW2+EHIRUH
JRLQJ+LJK=
3DUDPHWHUJXDUDQWHHGE\GHVLJQ
$&FKDUDFWHULVWLFVDVVXPHW7 QV
$XWRSUHFKDUJHPRGHRQO\0D\QRWH[FHHGOLPLWVHWIRUSUHFKDUJHPRGH
3UHFKDUJHPRGHRQO\
&/.PXVWEHWRJJOHGDPLQLPXPRIWZRWLPHVGXULQJWKLVSHULRG
Table 48.4 AC Functional Characteristics
6\PERO
5HDG:ULWHFRPPDQGWR5HDG:ULWHFRPPDQG
W&&'
&.(WRFORFNGLVDEOHRUSRZHUGRZQHQWU\PRGH
W&.('
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'40WRGDWDPDVNGXULQJ:ULWHV
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W'4=
:ULWHFRPPDQGWRLQSXWGDWDGHOD\
W':'
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W'$/
'DWDLQWR3UHFKDUJHFRPPDQG
W'3/
/DVWGDWDLQWREXUVW6WRSFRPPDQG
W%'/
/DVWGDWDLQWRQHZ5HDG:ULWHFRPPDQG
W&'/
/DVWGDWDLQWR3UHFKDUJHFRPPDQG
W5'/
3DUDPHWHU
/RDG0RGH5HJLVWHUFRPPDQGWR$FWLYHRU5HIUHVKFRPPDQG
'DWDRXWWRKLJKLPSHGDQFHIURP3UHFKDUJHFRPPDQG
8QLWV
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W&.
W05'
&/ W52+
&/ W52+
1RWHV
7KHPLQLPXPVSHFLILFDWLRQVDUHXVHGRQO\WRLQGLFDWHF\FOHWLPHDWZKLFKSURSHU
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ƒ&≤7$≤ƒ&IRU,7SDUWVLVHQVXUHG
$QLQLWLDOSDXVHRI—VLVUHTXLUHGDIWHUSRZHUXSIROORZHGE\WZR$XWR5HIUHVK
FRPPDQGVEHIRUHSURSHUGHYLFHRSHUDWLRQLVHQVXUHG9''DQG9''4PXVWEH
SRZHUHGXSVLPXOWDQHRXVO\966DQG9664PXVWEHDWVDPHSRWHQWLDO7KHWZR
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
141
P r e l i m i n a r y
$XWR5HIUHVKFRPPDQGZDNHXSVVKRXOGEHUHSHDWHGDQ\WLPHWKHW5()UHIUHVKUH
TXLUHPHQWLVH[FHHGHG
$&FKDUDFWHULVWLFVDVVXPHW7 QV
,QDGGLWLRQWRPHHWLQJWKHWUDQVLWLRQUDWHVSHFLILFDWLRQWKHFORFNDQG&.(PXVW
WUDQVLWEHWZHHQ9,+DQG9,/RUEHWZHHQ9,/DQG9,+LQDPRQRWRQLFPDQQHU
2XWSXWVPHDVXUHGIRU9DW9ZLWKHTXLYDOHQWORDG
Q
30pF
$&WLPLQJDQG,''WHVWVKDYH9,/DQG9,+ZLWKWLPLQJUHIHUHQFHGWR9,+ FURVV
RYHUSRLQW,IWKHLQSXWWUDQVLWLRQWLPHLVORQJHUWKDQW70$;WKHQWKHWLPLQJLV
UHIHUHQFHGDW9,/0$;DQG9,+0,1DQGQRORQJHUDWWKH9,+FURVVRYHUSRLQW
5HTXLUHGFORFNVDUHVSHFLILHGE\-('(&IXQFWLRQDOLW\DQGDUHQRWGHSHQGHQWRQDQ\
WLPLQJSDUDPHWHU
7LPLQJDFWXDOO\VSHFLILHGE\W&.6FORFNVVSHFLILHGDVDUHIHUHQFHRQO\DWPLQL
PXPF\FOHUDWH
7LPLQJDFWXDOO\VSHFLILHGE\W:5SOXVW53FORFNVVSHFLILHGDVDUHIHUHQFHRQO\DW
PLQLPXPF\FOHUDWH
%DVHGRQW&. QVIRU
7LPLQJDFWXDOO\VSHFLILHGE\W:5
-('(&DQG3&VSHFLI\WKUHHFORFNV
Table 48.5
IDD Specifications and Conditions
6\PER
O
3DUDPHWHU&RQGLWLRQ
0D[
0D[
8QLWV
1RWHV
2SHUDWLQJ&XUUHQW$FWLYH0RGH
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1RDFFHVVHVLQSURJUHVV
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2SHUDWLQJ&XUUHQW%XUVW0RGH&RQWLQXRXVEXUVW
5HDGRU:ULWH$OOEDQNVDFWLYH
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,''
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&.( +LJK&6 +LJK
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7KHPLQLPXPVSHFLILFDWLRQVDUHXVHGRQO\WRLQGLFDWHF\FOHWLPHDWZKLFKSURSHU
RSHUDWLRQRYHUWKHIXOOWHPSHUDWXUHUDQJHƒ&≤7$≤ƒ&IRUVWDQGDUGSDUWV
ƒ&≤7$≤ƒ&IRU,7SDUWVLVHQVXUHG
$QLQLWLDOSDXVHRI—VLVUHTXLUHGDIWHUSRZHUXSIROORZHGE\WZR$XWR5HIUHVK
FRPPDQGVEHIRUHSURSHUGHYLFHRSHUDWLRQLVHQVXUHG9''DQG9''4PXVWEH
SRZHUHGXSVLPXOWDQHRXVO\966DQG9664PXVWEHDWVDPHSRWHQWLDO7KHWZR
142
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
$XWR5HIUHVKFRPPDQGZDNHXSVVKRXOGEHUHSHDWHGDQ\WLPHWKHW5()UHIUHVKUH
TXLUHPHQWLVH[FHHGHG
$&WLPLQJDQG,''WHVWVKDYH9,/DQG9,+ZLWKWLPLQJUHIHUHQFHGWR9,+ FURVV
RYHUSRLQW,IWKHLQSXWWUDQVLWLRQWLPHLVORQJHUWKDQW70$;WKHQWKHWLPLQJLV
UHIHUHQFHGDW9,/0$;DQG9,+0,1DQGQRORQJHUDWWKH9,+FURVVRYHUSRLQW
,''VSHFLILFDWLRQVDUHWHVWHGDIWHUWKHGHYLFHLVSURSHUO\LQLWLDOL]HG
,''LVGHSHQGHQWRQRXWSXWORDGLQJDQGF\FOHUDWHV6SHFLILHGYDOXHVDUHREWDLQHG
ZLWKPLQLPXPF\FOHWLPHDQGWKHRXWSXWVRSHQ
7KH,''FXUUHQWZLOOLQFUHDVHRUGHFUHDVHSURSRUWLRQDOO\DFFRUGLQJWRWKHDPRXQW
RIIUHTXHQF\DOWHUDWLRQIRUWKHWHVWFRQGLWLRQ
$GGUHVVWUDQVLWLRQVDYHUDJHRQHWUDQVLWLRQHYHU\WZRFORFNV
)RU&/ DQGW&. QV
&.(LV+LJKGXULQJUHIUHVKFRPPDQGSHULRGW5)&0,1HOVH&.(LV/RZ7KH,''
OLPLWLVDFWXDOO\DQRPLQDOYDOXHDQGGRHVQRWUHVXOWLQDIDLOYDOXH
'HHSSRZHUGRZQFXUUHQWLVDQRPLQDOYDOXHDWƒ&7KHSDUDPHWHULVQRWWHVWHG
Table 48.6
IDD7 - Self Refresh Current Options
7HPSHUDWXUH&RPSHQVDWHG6HOI5HIUHVK
3DUDPHWHU&RQGLWLRQ
0D[
7HPSHUDWXUH
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ƒ&
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ƒ&
ƒ&
7%'
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7%'
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7%'
ƒ&
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7%'
ƒ&
7%'
ƒ&
7%'
ƒ&
7%'
6HOI5HIUHVK&XUUHQW
&.(9±%DQNV2SHQ
6HOI5HIUHVK&XUUHQW
&.(9±%DQNV2SHQ
6HOI5HIUHVK&XUUHQW
&.(9±%DQN2SHQ
6HOI5HIUHVK&XUUHQW
&.(9±%DQN2SHQ
6HOI5HIUHVK&XUUHQW
&.(9±%DQN2SHQ
8QLWV
1RWHV
—$
1RWHV
9'' 9''4 9“9
(QDEOHVRQFKLSUHIUHVKDQGDGGUHVVFRXQWHUV
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
143
P r e l i m i n a r y
Table 48.7 Capacitance
Parameter
,QSXW&DSDFLWDQFH&/.
,QSXW&DSDFLWDQFH$OORWKHULQSXWRQO\SLQV
,QSXW2XWSXW&DSDFLWDQFH'4
Symbol
&,
Min
Max
Units
S)
Notes
&,
&,2
S)
S)
1RWHV
7KLVSDUDPHWHULVVDPSOHG9''9''4 97$ ƒ&SLQXQGHUWHVWELDVHG
DW9I 0+]
3&VSHFLILHVDPD[LPXPRIS)
3&VSHFLILHVDPD[LPXPRIS)
3&VSHFLILHVDPD[LPXPRIS)
CLK
((
))
((
))
CKE
((
))
((
))
T0
T1
T3
T5
T7
T9
T19
T29
((
))
((
tCK) )
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKS tCKH
tCMS tCMH
((
))
((
))
COMMAND 5
((
))
((
))
DQML, DQMU
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
A10
BA0, BA1
DQ
NOP
PRE
ALL BANKS
((
))
((
))
tAS tAH
((
))
((
))
High-Z
((
))
T = 100μs
Power-up:
VDD and
CLK stable
((
))
((
))
LMR4
((
))
((
))
tAS tAH
((
))
((
))
AR4
((
))
((
))
AR4
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ACT4
((
))
((
))
CODE
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
CODE
((
))
((
))
CODE
( ( ALL BANKS
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
tMRD
tRP
tRFC
tRFC
BA0 = L,
BA1 = H
tAS
((
))
((
))
((
))
((
))
tRP
tMRD
Load Extended
Mode Register
Figure 48.1
PRE3
CODE
tAS tAH
((
))
((
))
((
))
((
))
((
))
((
))
LMR4
BA0 = L,
BA1 = L
tAH
Load Mode
Register
DON’T CARE
Initialize and Load Mode Register
1RWHV
7KHWZR$XWR5HIUHVKFRPPDQGVDW7DQG7PD\EHDSSOLHGEHIRUHHLWKHU/RDG
0RGH5HJLVWHU/05FRPPDQG
35( 3UHFKDUJHFRPPDQG/05 /RDG0RGH5HJLVWHUFRPPDQG$5 $XWR5H
IUHVKFRPPDQG$&7 $FWLYHFRPPDQG5$ 5RZ$GGUHVV%$ %DQN$GGUHVV
2SWLRQDOUHIUHVKFRPPDQG
7KH/RDG0RGH5HJLVWHUIRUERWK05(05DQG$XWR5HIUHVKFRPPDQGVFDQEH
LQDQ\RUGHU+RZHYHUDOOPXVWRFFXUSULRUWRDQ$FWLYHFRPPDQG
'HYLFHWLPLQJLVZLWK0+]FORFN
144
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
tCKS
((
))
((
))
tCH
CKE
tCMS tCMH
PRECHARGE
NOP
tCKS
((
))
((
))
NOP
NOP
ACTIVE
((
))
((
))
DQML, DQMU
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
DQ
Tn + 2
((
))
tCKS tCKH
COMMAND
Tn + 1
tAH
BANK(S)
High-Z
ROW
((
))
((
))
ROW
((
))
((
))
BANK
((
))
Two clock cycles
Precharge all
active banks
((
))
((
))
Input buffers gated off while in
power-down mode
All banks idle, enter
power-down mode
All banks idle
Exit power-down mode
DON’T CARE
Figure 48.2.
Power Down Mode
1RWH9LRODWLQJUHIUHVKUHTXLUHPHQWVGXULQJSRZHUGRZQPD\UHVXOWLQDORVVRIGDWD
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
145
P r e l i m i n a r y
MOBILE SDRAM
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
T6
T7
T8
NOP
WRITE
T9
tCH
tCKS tCKH
CKE
tCKS tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m2
tAS
COLUMN e2
tAH
A10
tAS
BA0, BA1
tAH
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
DOUT m
tHZ
DOUT m + 1
tDS
tDH
DOUT e
DOUT e + 1
DON’T CARE
UNDEFINED
Figure 48.3.
Clock Suspend Mode
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK WKH&$6ODWHQF\ DQGDXWRSUHFKDUJH
LVGLVDEOHG
$DQG$ ³'RQ¶W&DUH´
146
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
CLK
T1
tCK
T2
((
))
((
))
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
AUTO
REFRESH
((
))
( ( NOP
))
NOP
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS
DQ
tAH
BANK(S)
High-Z
tRP
To + 1
((
))
AUTO
REFRESH
NOP
((
))
((
))
DQMU, DQML
BA0, BA1
((
))
((
))
((
))
CKE
COMMAND
Tn + 1
tCL
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
((
))
((
))
tRFC1
BANK
tRFC1
Precharge all
active banks
DON’T CARE
Figure 48.4. Auto Refresh Mode
1RWH(DFK$XWR5HIUHVKFRPPDQGSHUIRUPVDUHIUHVKF\FOH%DFNWREDFNFRP
PDQGVDUHQRWUHTXLUHG
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
147
P r e l i m i n a r y
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
> tRAS
CKE
tCMS tCMH
PRECHARGE
NOP
DQMU, DQML
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
DQ
AUTO
REFRESH
((
))
((
))
To + 1
To + 2
((
))
((
))
((
))
tCKS tCKH
COMMAND
Tn + 1
((
))
((
))
((
))
((
))
((
))
NOP ( (
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
AUTO
REFRESH
tAH
BANK(S)
High-Z
tRP
Precharge all
active banks
((
))
Enter self refresh mode
((
))
tXSR
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
Figure 48.5. Self Refresh Mode
1RWH(DFK$XWR5HIUHVKFRPPDQGSHUIRUPVDUHIUHVKF\FOH%DFNWREDFNFRP
PDQGVDUHQRWUHTXLUHG
148
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
PRECHARGE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
ROW
COLUMN m2
tAH
ALL BANKS
ROW
tAS
BA0, BA1
tAH
ROW
ROW
SINGLE BANKS
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK(S)
tAC
tAC
DQ
tLZ
tRCD
tAC
tOH
tOH
DOUT m
DOUT m+1
CAS Latency
BANK
tAC
tOH
DOUT m+2
tOH
DOUT m+3
tRP
tHZ
tRAS
tRC
DON’T CARE
UNDEFINED
Figure 48.6.
Read - Without Auto Precharge
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK WKH&$6ODWHQF\ DQGWKH5HDGEXUVW
LVIROORZHGE\D³PDQXDO´3UHFKDUJH
$DQG$ ³'RQ¶W&DUH´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
149
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
DQ
tLZ
tRCD
tAC
tOH
DOUT m
tAC
tOH
tAC
tOH
DOUT m + 1
DOUT m + 2
CAS Latency
tOH
DOUT m + 3
tHZ
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Figure 48.7. Read - With Auto Precharge
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK WKH&$6ODWHQF\ $DQG$ ³'RQ¶W&DUH´
150
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
NOP 3
NOP 3
T6
T7
T8
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
ROW
COLUMN m2
tAH
ALL BANKS
ROW
tAS
BA0, BA1
tAH
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANKS
BANK
BANK(S)
tAC
DQ
tLZ
tRCD
BANK
tOH
DOUT m
tHZ
CAS Latency
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Figure 48.8.
Single Read - Without Auto Precharge
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK WKH&$6ODWHQF\ DQGWKH5HDGEXUVW
LVIROORZHGE\D³PDQXDO´3UHFKDUJH
$DQG$ ³'RQ¶W&DUH´
3UHFKDUJHFRPPDQGQRWDOORZHGRUW5$6ZRXOGEHYLRODWHG
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
151
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
T6
READ
NOP
T7
T8
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
NOP3
NOP3
NOP
ACTIVE
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
t OH
DQ
DOUT m
tRCD
CAS Latency
tHZ
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Figure 48.9. Single Read - With Auto Precharge
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK WKH&$6ODWHQF\ DQGWKH5HDGEXUVW
LVIROORZHGE\D³PDQXDO´3UHFKDUJH
$DQG$ ³'RQ¶W&DUH´
3UHFKDUJHFRPPDQGQRWDOORZHGRUW5$6ZRXOGEHYLRODWHG
152
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCH
tCKS tCKH
CKE
tCMS
COMMAND
tCMH
ACTIVE
NOP
READ
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m2
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
tAC
DQ
DOUT m
tLZ
tRCD - BANK 0
BANK 3
tAC
tOH
BANK 0
tAC
tOH
tAC
tOH
DOUT m + 1
DOUT m + 2
tAC
tOH
DOUT m + 3
tRP - BANK 0
CAS Latency - BANK 0
tAC
tOH
DOUT b
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 3
tRRD
CAS Latency - BANK 3
DON’T CARE
UNDEFINED
Figure 48.10.
Alternating Bank Read Accesses
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK WKH&$6ODWHQF\ $DQG$ ³'RQ¶W&DUH´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
153
P r e l i m i n a r y
T0
tCL
CLK
T1
tCH
tCK
T2
T3
T4
T5
T6
((
))
((
))
tCKS tCKH
tCMS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAS
A10
Tn + 4
((
))
((
))
NOP
BURST TERM
NOP
NOP
((
))
((
))
COLUMN m2
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
Tn + 3
((
))
((
))
DQMU, DQML
A0-A9, A11
Tn + 2
((
))
((
))
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
DQ
tAC
tOH
tOH
DOUT m
tLZ
tRCD
CAS Latency
DOUT m+1
tAC ( (
tOH ) )
DOUT
((
))
m+2
((
))
tAC
tAC
tOH
tOH
DOUT m-1
DOUT m
tOH
DOUT m+1
tHZ
256 (x16) locations within same row
Full page completed
DON’T CARE
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
UNDEFINED
Figure 48.11. Read - Full-Page Burst
1RWHV
)RUWKLVH[DPSOHWKH&$6ODWHQF\ $DQG$ ³'RQ¶W&DUH´
3DJHOHIWRSHQQRW53
154
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m2
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
DQ
tLZ
tRCD
tOH
tAC
DOUT m
tHZ
tAC
tOH
DOUT m + 2
tLZ
tOH
DOUT m + 3
tHZ
CAS Latency
DON’T CARE
UNDEFINED
Figure 48.12. Read - DQM Operation
1RWHV
)RUWKLVH[DPSOHWKH&$6ODWHQF\ $DQG$ ³'RQ¶W&DUH´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
155
P r e l i m i n a r y
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
tCH
tCKS tCKH
CKE
tCMS
COMMAND
tCMH
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
tAS
A10
ROW
tAH
ALL BANKS
ROW
tAS
BA0, BA1
COLUMN m3
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANK
BANK
tDS
tDS
DIN m
DQ
BANK
BANK
tDH
tDH
tDS
DIN m + 1
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 2
tRCD
tRAS
tRP
tRC
DON’T CARE
Figure 48.13.
Write - Without Auto Precharge
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK DQGWKH:ULWHEXUVWLVIROORZHGE\D
³PDQXDO´3UHFKDUJH
QVLVUHTXLUHGEHWZHHQ',1P!DQGWKH3UHFKDUJHFRPPDQGUHJDUGOHVV
RIIUHTXHQF\
$DQG$ ³'RQ¶W&DUH´
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
tDS
DIN m
DQ
BANK
tDH
tDS
tDH
DIN m + 1
tDS
tDH
tDS
DIN m + 2
tRCD
tRAS
tDH
DIN m + 3
tWR
tRP
tRC
DON’T CARE
Figure 48.14. Write - With Auto Precharge
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK $DQG$ ³'RQ¶W&DUH´
156
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
tCH
tCKS tCKH
CKE
tCMS
COMMAND
tCMH
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m3
ROW
tAH
ALL BANKS
ROW
tAS
BA0, BA1
tAH
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANK
BANK
tDS
tDH
tDS
DIN m
DQ
BANK
BANK
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 2
tRCD
tRAS
tRP
tRC
DON’T CARE
Figure 48.15.
Single Write - Without Auto Precharge
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK DQGWKH:ULWHEXUVWLVIROORZHGE\D
³PDQXDO´3UHFKDUJH
QVLVUHTXLUHGEHWZHHQ',1P!DQGWKH3UHFKDUJHFRPPDQGUHJDUGOHVVRI
IUHTXHQF\
$DQG$ ³'RQ¶W&DUH´
3UHFKDUJHFRPPDQGQRWDOORZHGHOVHW5$6ZRXOGEHYLRODWHG
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
157
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
T6
T7
WRITE
NOP
NOP
NOP
T8
T9
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
NOP3
ACTIVE
NOP3
NOP3
tCMS
ACTIVE
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tWR
tRP
tRC
DON’T CARE
Figure 48.16. Single Write with Auto Precharge
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK DQGWKH:ULWHEXUVWLVIROORZHGE\D
³PDQXDO´3UHFKDUJH
QVLVUHTXLUHGEHWZHHQ',1P!DQGWKH3UHFKDUJHFRPPDQGUHJDUGOHVVRI
IUHTXHQF\
$DQG$ ³'RQ¶W&DUH´
:ULWHFRPPDQGQRWDOORZHGHOVHW5$6ZRXOGEHYLRODWHG
158
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS tCKH
CKE
tCMS
COMMAND
tCMH
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m2
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
tDS
DIN m
DQ
BANK 1
tDH
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tDS
tDH
DIN b
tWR - BANK 0
tRCD - BANK 0
BANK 0
tDS
tDH
tDS
DIN b + 1
tRP - BANK 0
tDH
DIN b + 2
tDS
tDH
DIN b + 3
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 1
tRRD
tWR - BANK 1
DON’T CARE
Figure 48.17. Alternating Bank Write Accesses
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK $DQG$ ³'RQ¶W&DUH´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
159
P r e l i m i n a r y
T0
tCL
CLK
T1
tCH
tCK
T2
T3
T4
T5
tCKS tCKH
tCMS
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
((
))
((
))
NOP
tCMS tCMH
tAS
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m1
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
tAS
A10
Tn + 3
((
))
((
))
DQMU, DQML
A0-A9, A11
Tn + 2
((
))
((
))
CKE
COMMAND
Tn + 1
((
))
((
))
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tDS
tDH
DIN m +
((
))
3 ((
))
tDS
tDH
DIN m - 1
512 (x16) locations within same row
DON’T CARE
Figure 48.18.
Full page completed
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
2, 3
command to stop.
Write - Full Page Burst
1RWHV
$DQG$ ³'RQ¶W&DUH´
W:5PXVWEHVDWLVILHGSULRUWR3UHFKDUJHFRPPDQG
3DJHOHIWRSHQQRW53
160
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
P r e l i m i n a r y
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCH
tCKS tCKH
CKE
tCMS
COMMAND
tCMH
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m2
ROW
tAS
A10
tAH
tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
DQ
tDH
DIN m
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
Figure 48.19. Write - DQM Operation
1RWHV
)RUWKLVH[DPSOHWKHEXUVWOHQJWK $DQG$ ³'RQ¶W&DUH´
November 8, 2005 SDRAM_01_A3
Mobile SDRAM Type 1
161
P r e l i m i n a r y
49 Revision Summary
49.1
Revision A0 (April 1, 2005)
,QLWLDO5HOHDVH
49.2 Revision A1 (April 25, 2005)
$GGHG 0+]VSHHGJUDGHRSWLRQ
49.3 Revision A2 (April 25, 2005)
$GGHGUHYLVLRQKLVWRU\
49.4 Revision A3 (April 25, 2005)
$GGHGDQRWHRQ(6',PPXQLW\WRWKH'&(OHFWULFDO&KDUDFWHULVWLFVDQG2SHUDWLQJ
&RQGLWLRQVWDEOH
162
Mobile SDRAM Type 1
SDRAM_01_A3 November 8, 2005
Mobile SDRAM Type 2
2M x 16Bit x 4 Banks SDRAM
PRELIMINARY
Features
„
„
„
„
„
„
„
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² &$6ODWHQF\
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Publication Number SDRAM_00
Revision A
Amendment 0
Issue Date May 25, 2004
P r e l i m i n a r y n
50 Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
9ROWDJHRQDQ\SLQUHODWLYHWR966
9,19287
a
9
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9''9''4
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51 DC Operating Conditions
5HFRPPHQGHGRSHUDWLQJFRQGLWLRQV9ROWDJHUHIHUHQFHGWR966 97$ ƒ&aƒ&
Parameter
6XSSO\YROWDJH
Symbol
Min
Typ
Max
9''
Unit
9''4
,QSXWORJLFKLJKYROWDJH
9,+
[9''4
9''4
,QSXWORJLFORZYROWDJH
9,/
2XWSXWORJLFKLJKYROWDJH
92+
9''4
²
²
2XWSXWORJLFORZYROWDJH
92/
²
²
,QSXWOHDNDJHFXUUHQW
,/,
²
Note
9
,2+ P$
,2/ P$
—$
1RWHV
9,+PD[ 9$&7KHRYHUVKRRWYROWDJHGXUDWLRQLV≤QV
9,/PLQ 9$&7KHXQGHUVKRRWYROWDJHGXUDWLRQLV≤QV
$Q\LQSXW9≤9,1≤9''4,QSXWOHDNDJHFXUUHQWVLQFOXGH+L=RXWSXWOHDNDJHIRUDOOELGLUHFWLRQDO
EXIIHUVZLWKWULVWDWHRXWSXWV
'RXWLVGLVDEOHG9≤ 9287≤9''4
52 Capacitance
9'' 97$ ƒ&I 0+]95() 9“P9
164
Pin
Symbol
Min
Max
&ORFN
5$6&$6:(&6&.('40
&&/.
&,1
$GGUHVV
'4a'4
&$''
&287
S73WS256N Based MCPs
Unit
Note
S)
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
53 DC Characteristics
Parameter
Symbol
Test Condition
Value
%XUVWOHQJWK W5&≥ W5&PLQ
,2 P$
Unit Note
P$
2SHUDWLQJ&XUUHQW2QH%DQN$FWLYH
,&&
3UHFKDUJH6WDQGE\&XUUHQWLQSRZHU
GRZQPRGH
&.(≤ 9,/PD[W&& QV
P$
,&&36
&.(&/.≤9,/PD[W&& ∞
P$
,&&1
&.(≥9,+PLQ&6≥9,+PLQW&& QV,QSXW
VLJQDOVDUHFKDQJHGRQHWLPHGXULQJQV
P$
P$
3UHFKDUJH6WDQGE\&XUUHQWLQQRQ
SRZHUGRZQPRGH
,&&3
,&&16
,&&3
$FWLYH6WDQGE\&XUUHQWLQSRZHU
GRZQPRGH
$FWLYH6WDQGE\&XUUHQWLQQRQSRZHU
GRZQPRGH2QH%DQN$FWLYH
&.(≥9,+PLQ&/.≤9,/PD[W&& ∞
,QSXWVLJQDOVDUHVWDEOH
&.(≤9,/PD[W&& QV
P$
,&&36
&.(&/.≤9,/PD[W&& ∞
P$
,&&1
&.(≥9,+PLQ&6≥9,+PLQW&& QV
,QSXWVLJQDOVDUHFKDQJHGRQHWLPHGXULQJQV
P$
P$
P$
,&&16
&.(≥9,+PLQ&/.≤9,/PD[W&& ∞
,QSXWVLJQDOVDUHVWDEOH
2SHUDWLQJ&XUUHQW%XUVW0RGH
,&&
,2 P$
3DJHEXUVW
%DQNV$FWLYDWHG
W&&' &/.V
5HIUHVK&XUUHQW
,&&
W$5)&≥W$5)&PLQ
,&&
6HOI5HIUHVK&XUUHQW
&.(≤9
P$
Internal TCSR
Max 40
°C
)XOO$UUD\
RIIXOODUUD\
RIIXOODUUD\
—$
1RWHV
0HDVXUHGZLWKRXWSXWVRSHQ
5HIUHVKSHULRGLVPV
8QOHVVRWKHUZLVHQRWHGLQSXWVZLQJ,HYH,LV&0269,+9,/ 9''49664
54 AC Operating Test Conditions
9'' 9“97$ ƒ&aƒ&
Parameter
$&LQSXWOHYHOV9,+9,/
,QSXWWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHO
Value
Unit
[9''4
[9''4
9
WUWI [9''4
QV
9
,QSXWULVHDQGIDOOWLPH
2XWSXWWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHO
2XWSXWORDGFRQGLWLRQ
6HH)LJXUH
1.8V
13.9K
VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA
Output
VOL (DC) = 0.2V, IOL = 0.1mA
10.6K
30pF
Figure 54.1 DC Output Load Circuit
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
165
P r e l i m i n a r y n
Vtt=0.5 x VDDQ
50
Output
Z0=50
30pF
Figure 54.2 AC Output Load Circuit
55 Operating AC Parameter
$&RSHUDWLQJFRQGLWLRQVXQOHVVRWKHUZLVHQRWHG
Symbol
Value
5RZDFWLYHWRURZDFWLYHGHOD\
Parameter
W55'PLQ
5$6WR&$6GHOD\
W5&'PLQ
5RZSUHFKDUJHWLPH
W53PLQ
Unit
Note
QV
W5$6PLQ
W5$6PD[
5RZF\FOHWLPH
W5&PLQ
QV
/DVWGDWDLQWRURZSUHFKDUJH
W5'/PLQ
QV
/DVWGDWDLQWR$FWLYHGHOD\
W'$/PLQ
W5'/W53
²
/DVWGDWDLQWRQHZFRODGGUHVVGHOD\
W&'/PLQ
&/.
/DVWGDWDLQWREXUVWVWRS
W%'/PLQ
&/.
$XWRUHIUHVKF\FOHWLPH
W$5)&PLQ
QV
([LWVHOIUHIUHVKWRDFWLYHFRPPDQG
W65);PLQ
QV
&/.
HD
5RZDFWLYHWLPH
&RODGGUHVVWRFRODGGUHVVGHOD\
W&&'PLQ
1XPEHURIYDOLGRXWSXWGDWD
&$6ODWHQF\ 1XPEHURIYDOLGRXWSXWGDWD
&$6ODWHQF\ 1XPEHURIYDOLGRXWSXWGDWD
&$6ODWHQF\ —V
1RWHV
7KHPLQLPXPQXPEHURIFORFNF\FOHVLVGHWHUPLQHGE\GLYLGLQJWKHPLQLPXPWLPHUHTXLUHGZLWK
FORFNF\FOHWLPHDQGWKHQURXQGLQJRIIWRWKHQH[WKLJKHULQWHJHU
0LQLPXPGHOD\LVUHTXLUHGWRFRPSOHWHZULWH
$OOSDUWVDOORZHYHU\F\FOHFROXPQDGGUHVVFKDQJH
,QFDVHRIURZSUHFKDUJHLQWHUUXSWDXWRSUHFKDUJHDQGUHDGEXUVWVWRS
166
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
56 AC Characteristics
$&RSHUDWLQJFRQGLWLRQVXQOHVVRWKHUZLVHQRWHG
Parameter
Symbol
&/.F\FOHWLPH
&$6ODWHQF\ &/.F\FOHWLPH
&$6ODWHQF\ &/.F\FOHWLPH
&$6ODWHQF\ &/.WRYDOLGRXWSXWGHOD\
&$6ODWHQF\ &/.WRYDOLGRXWSXWGHOD\
&$6ODWHQF\ &/.WRYDOLGRXWSXWGHOD\
&$6ODWHQF\ 2XWSXWGDWDKROGWLPH
&$6ODWHQF\ 2XWSXWGDWDKROGWLPH
&$6ODWHQF\ 2XWSXWGDWDKROGWLPH
&$6ODWHQF\ Min
W&&
Note
QV
QV
QV
W6$&
W2+
W&+
&/.ORZSXOVHZLGWK
W&/
W66
,QSXWKROGWLPH
W6+
&/.WRRXWSXWLQ/RZ=
W6/=
&$6ODWHQF\ ,QSXWVHWXSWLPH
&$6ODWHQF\ Unit
&/.KLJKSXOVHZLGWK
&/.WRRXWSXWLQ+L=
Max
QV
W6+=
&$6ODWHQF\ 1RWHV
3DUDPHWHUVGHSHQGRQSURJUDPPHG&$6ODWHQF\
,IFORFNULVLQJWLPHLVORQJHUWKDQQVWUQVVKRXOGEHDGGHGWRWKHSDUDPHWHU
$VVXPHGLQSXWULVHDQGIDOOWLPHWUWI QV
,IWUWILVORQJHUWKDQQVWUDQVLHQWWLPHFRPSHQVDWLRQVKRXOGEHFRQVLGHUHG
LH>WUWI@QVVKRXOGEHDGGHGWRWKHSDUDPHWHU
May 25, 2004 SDRAM_00_A0
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Command
5HJLVWHU
CKEn-1 CKEn CS# RAS# CAS# WE# DQM
0RGH5HJLVWHU6HW
$XWR5HIUHVK
5HIUHVK
6HOI
5HIUHVK
(QWU\
([LW
%DQN$FWLYH5RZ$GGU
5HDG
&ROXPQ
$GGUHVV
:ULWH
&ROXPQ
$GGUHVV
$XWR3UHFKDUJH
'LVDEOH
$XWR3UHFKDUJH
(QDEOH
$XWR3UHFKDUJH
'LVDEOH
$XWR3UHFKDUJH
(QDEOH
%XUVW6WRS
3UHFKDUJH
+
+
3UHFKDUJH3RZHU
'RZQ0RGH
/
/
;
23&2'(
/
/
/
+
;
;
;
;
+
+
;
;
;
;
/
/
+
+
;
9
;
/
+
/
+
;
9
+
/
/
/
/
;
;
+
/
([LW
/
+
(QWU\
+
/
([LW
/
+
/
+
/
/
/
+
/
+
;
;
;
/
9
9
9
;
;
;
;
+
;
;
;
/
+
+
+
+
;
;
;
/
9
9
9
+
+
+
;
;
;
;
;
;
/
+
+
+
;
9
/
;
+
;
;
;
;
;
;
;
;
+
&ROXPQ
$GGUHVV
$a$
9
+
(QWU\
1R2SHUDWLRQ&RPPDQG
+
&ROXPQ
$GGUHVV
$a$
+
;
Note
5RZ$GGUHVV
/
+
A11, A9 ~ A0
/
+
+
A10/AP
/
/
;
'40
BA0,1
/
+
+
+
$OO%DQNV
&ORFN6XVSHQGRU
$FWLYH3RZHU'RZQ
+
/
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%DQN6HOHFWLRQ
;
9
;
;
;
/HJHQG9 9DOLG; 'RQ¶W&DUH+ /RJLF+LJK/ /RJLF/RZ
1RWHV
23&RGH2SHUDQG&RGH
$a$%$a%$3URJUDPNH\V#056
056FDQEHLVVXHGRQO\DWDOOEDQNVSUHFKDUJHVWDWH
$QHZFRPPDQGFDQEHLVVXHGDIWHU&/.F\FOHVRI056
$XWRUHIUHVKIXQFWLRQVDUHWKHVDPHDV&%5UHIUHVKRI'5$0
7KHDXWRPDWLFSUHFKDUJHZLWKRXWURZSUHFKDUJHFRPPDQGLVPHDQWE\³$XWR´
$XWRVHOIUHIUHVKFDQEHLVVXHGRQO\DWDOOEDQNVSUHFKDUJHVWDWH
3DUWLDOVHOIUHIUHVKFDQEHLVVXHGRQO\DIWHUVHWWLQJSDUWLDOVHOIUHIUHVKPRGHRI(056
%$a%$%DQNVHOHFWDGGUHVVHV
'XULQJEXUVWUHDGRUZULWHZLWKDXWRSUHFKDUJHQHZUHDGZULWHFRPPDQGFDQQRWEHLVVXHG
$QRWKHUEDQNUHDGZULWHFRPPDQGFDQEHLVVXHGDIWHUWKHHQGRIEXUVW
1HZURZDFWLYHRIWKHDVVRFLDWHGEDQNFDQEHLVVXHGDWW53DIWHUWKHHQGRIEXUVW
%XUVWVWRSFRPPDQGLVYDOLGDWHYHU\EXUVWOHQJWK
'40VDPSOHGDWWKHSRVLWLYHJRLQJHGJHRI&/.PDVNVWKHGDWDLQDWWKDWVDPH&/.LQZULWH
RSHUDWLRQ:ULWH'40ODWHQF\LVEXWLQUHDGRSHUDWLRQLWPDNHVWKHGDWDRXW+L=VWDWHDIWHU
&/.F\FOHV5HDG'40ODWHQF\LV
58 Mode Register Field Table to Program Modes
168
Address
BA0 ~ BA1
A11 ~ A10/AP
A9 (Note 2)
)XQFWLRQ
³´6HWWLQJIRU1RUPDO
056
5)8
:%/
S73WS256N Based MCPs
A8
A7
7HVW0RGH
A6
A5
A4
A3
A2
A1
A0
&$6/DWHQF\
%7
%XUVW/HQJWK
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
59 Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
0RGH5HJLVWHU6HW
5HVHUYHG
6HTXHQWLDO
5HVHUYHG
,QWHUOHDYH
5HVHUYHG
5HVHUYHG
Write Burst Length
5HVHUYHG
A9
Length
5HVHUYHG
%XUVW
5HVHUYHG
6LQJOH%LW
5HVHUYHG
BA1
BT=1
Mode Select
BA0
Mode
5HVHUYHG
5HVHUYHG
6HWWLQJ
IRU1RUPDO
056
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
)XOO3DJH
5HVHUYHG
1RWH)XOO3DJH/HQJWK[0E0E0E0E
5HJLVWHU3URJUDPPHGZLWK([WHQGHG056
Address
BA1
)XQFWLRQ
0RGH6HOHFW
BA0
A11 ~ A10/AP
A9
A8
A7
A6 A5
5)81RWH
'6
A4
A3
A2
5)81RWH
A1
A0
3$65
60 EMRS for PASR (Partial Array Self Ref) & DS (Driver Strength)
Mode Select
Driver Strength
BA1
BA0
Mode
A6 A5
1RUPDO056
5HVHUYHG
PASR
Driver Strength
A2
A1
A0
)XOO
)XOO$UUD\
RIIXOODUUD\
(056IRU0RELOH6'5$0
RIIXOODUUD\
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
Reserved Address
A11~A10/AP
A9
A8 A7
A4
A3
Refreshed Area
1RWHV
5)85HVHUYHGIRUIXWXUHXVHVKRXOGVWD\³´GXULQJ056F\FOH
,I$LVKLJKGXULQJ056F\FOH³%XUVW5HDG6LQJOH%LW:ULWH´IXQFWLRQZLOOEHHQDEOHG
61 Partial Array Self Refresh
,QRUGHUWRVDYHSRZHUFRQVXPSWLRQ0RELOH6'5$0KDV3$65RSWLRQ
0RELOH6'5$0VXSSRUWVNLQGVRI3$65LQVHOIUHIUHVKPRGH)XOO$UUD\
RIIXOODUUD\DQGRIIXOODUUD\
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- Full Array
- 1/2 of full Array
- 1/4 of full Array
Partial Self Refresh Area
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
169
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62 Internal Temperature Compensated Self Refresh (TCSR)
Self Refresh Current (Icc 6)
Temperature Range
0D[ƒ&
Full Array
1/2 of full array
1/4 of full array
0D[ƒ&
Unit
—$
1RWHV
,QRUGHUWRVDYHSRZHUFRQVXPSWLRQ0RELOH6'5$0LQFOXGHVWKHLQWHUQDOWHPSHUDWXUHVHQVRUDQG
FRQWUROXQLWVWRFRQWUROWKHVHOIUHIUHVKF\FOHDXWRPDWLFDOO\DFFRUGLQJWRWKHWZRWHPSHUDWXUHUDQJHV
0D[ƒ&0D[ƒ&
,IWKH(056IRUH[WHUQDO7&65LVLVVXHGE\WKHFRQWUROOHUWKLV(056FRGHIRU7&65LVLJQRUHG
63 Power Up Sequence
$SSO\SRZHUDQGDWWHPSWWRPDLQWDLQ&.(DWDKLJKVWDWHDQGDOORWKHULQSXWVPD\EHXQGH
ILQHG
$SSO\9''EHIRUHRUDWWKHVDPHWLPHDV9''4
0DLQWDLQVWDEOHSRZHUVWDEOHFORFNDQG123LQSXWFRQGLWLRQIRUDPLQLPXPRIXV
,VVXHSUHFKDUJHFRPPDQGVIRUDOOEDQNVRIWKHGHYLFHV
,VVXHRUPRUHDXWRUHIUHVKFRPPDQGV
,VVXHDPRGHUHJLVWHUVHWFRPPDQGWRLQLWLDOL]HWKHPRGHUHJLVWHU
,VVXHDH[WHQGHGPRGHUHJLVWHUVHWFRPPDQGWRGHILQH'6RU3$65RSHUDWLQJW\SHRI
WKHGHYLFHDIWHUQRUPDO056
(056F\FOHLVQRWPDQGDWRU\DQGWKH(056FRPPDQGQHHGVWREHLVVXHGRQO\ZKHQ'6RU3$65
LVXVHG
7KH GHIDXOW VWDWH ZLWKRXW (056 FRPPDQG LVVXHG LV KDOI GULYHU VWUHQJWK DQG DOO IXOO DUUD\
UHIUHVKHG
7KHGHYLFHLVQRZUHDG\IRUWKHRSHUDWLRQVHOHFWHGE\(056
)RURSHUDWLQJZLWK'6RU3$65VHW'6RU3$65PRGHLQ(056VHWWLQJVWDJH
,QRUGHUWRDGMXVWDQRWKHUPRGHLQWKHVWDWHRI'6RU3$65PRGHDGGLWLRQDO(056VHWLVUHTXLUHG
EXWSRZHUXSVHTXHQFHLVQRW
QHHGHGDJDLQDWWKLVWLPH,QWKDWFDVHDOOEDQNVKDYHWREHLQLGOHVWDWHSULRUWRDGMXVWLQJ(056
VHW
64 Burst Sequence
64.1
Burst Length = 4
Initial Address
170
A1
A0
Sequential
Interleave
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
64.2 Burst Length = 8
Initial Address
A2
A1
A0
Sequential
Interleave
65 Device Operations
65.1
Addresses of 64Mb
%DQN$GGUHVVHV%$a%$
,QFDVH[7KLV6'5$0LVRUJDQL]HGDVIRXULQGHSHQGHQWEDQNVRIZRUGV[ELWV
PHPRU\DUUD\V7KH%$a%$LQSXWVDUHODWFKHGDWWKHWLPHRIDVVHUWLRQRI5$6DQG&$6WR
VHOHFWWKHEDQNWREHXVHGIRUWKHRSHUDWLRQ7KHEDQNDGGUHVVHV%$a%$DUHODWFKHGDWEDQN
DFWLYHUHDGZULWHPRGHUHJLVWHUVHWDQGSUHFKDUJHRSHUDWLRQV
,QFDVH[7KLV6'5$0LVRUJDQL]HGDVIRXULQGHSHQGHQWEDQNVRIZRUGV[ELWV
PHPRU\DUUD\V7KH%$a%$LQSXWVDUHODWFKHGDWWKHWLPHRIDVVHUWLRQRI5$6DQG&$6WR
VHOHFWWKHEDQNWREHXVHGIRUWKHRSHUDWLRQ7KHEDQNDGGUHVVHV%$a%$DUHODWFKHGDWEDQN
DFWLYHUHDGZULWHPRGHUHJLVWHUVHWDQGSUHFKDUJHRSHUDWLRQV
$GGUHVV,QSXWV$a$
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5$6DQG%$a%$GXULQJEDQNDFWLYDWHFRPPDQG7KHELWFROXPQDGGUHVVHVDUHODWFKHG
DORQJZLWK&$6:(DQG%$a%$GXULQJUHDGRUZULWHFRPPDQG
,QFDVH[7KHDGGUHVVELWVDUHUHTXLUHGWRGHFRGHWKHZRUGORFDWLRQVDUHPXO
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DORQJZLWK&$6:(DQG%$a%$GXULQJUHDGRUZULWHFRPPDQG
65.2 Addresses of 128Mb
%DQN$GGUHVVHV%$a%$
,QFDVH[7KLV6'5$0LVRUJDQL]HGDVIRXULQGHSHQGHQWEDQNVRIZRUGV[ELWV
PHPRU\DUUD\V7KH%$a%$LQSXWVDUHODWFKHGDWWKHWLPHRIDVVHUWLRQRI5$6DQG&$6WR
VHOHFWWKHEDQNWREHXVHGIRUWKHRSHUDWLRQ7KHEDQNDGGUHVVHV%$a%$DUHODWFKHGDWEDQN
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PHPRU\DUUD\V7KH%$a%$LQSXWVDUHODWFKHGDWWKHWLPHRIDVVHUWLRQRI5$6DQG&$6WR
VHOHFWWKHEDQNWREHXVHGIRUWKHRSHUDWLRQ7KHEDQNDGGUHVVHV%$a%$DUHODWFKHGDWEDQN
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May 25, 2004 SDRAM_00_A0
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$GGUHVV,QSXWV$a$
,QFDVH[7KHDGGUHVVELWVDUHUHTXLUHGWRGHFRGHWKHZRUGORFDWLRQVDUHPXO
WLSOH[HGLQWRDGGUHVVLQSXWSLQV$a$7KHELWURZDGGUHVVHVDUHODWFKHGDORQJZLWK
5$6DQG%$a%$GXULQJEDQNDFWLYDWHFRPPDQG7KHELWFROXPQDGGUHVVHVDUHODWFKHG
DORQJZLWK&$6:(DQG%$a%$GXULQJUHDGRUZULWHFRPPDQG
,QFDVH[7KHDGGUHVVELWVDUHUHTXLUHGWRGHFRGHWKHZRUGORFDWLRQVDUHPXO
WLSOH[HGLQWRDGGUHVVLQSXWSLQV$a$7KHELWURZDGGUHVVHVDUHODWFKHGDORQJZLWK
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DORQJZLWK&$6:(DQG%$a%$GXULQJUHDGRUZULWHFRPPDQG
65.3 Clock
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WRWKHSRVLWLYHJRLQJHGJHRIWKHFORFN7KHFORFNWUDQVLWLRQVPXVWEHPRQRWRQLFEHWZHHQ9,/DQG
9,+'XULQJRSHUDWLRQZLWK&.(KLJKDOOLQSXWVDUHDVVXPHGWREHLQDYDOLGVWDWHORZRUKLJKIRU
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SHUIRUPDQG,&&VSHFLILFDWLRQV
65.4 Clock Enable (CKE)
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65.5 NOP and Device Deselect
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65.6 DQM Operation
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65.7 Mode Register Set (MRS)
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172
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
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SLQV$a$QDQG%$a%$LQWKHVDPHF\FOHDV&65$6&$6DQG:(JRLQJORZLVWKH
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EXUVWW\SHXVHV$&$6ODWHQF\UHDGODWHQF\IURPFROXPQDGGUHVVXVH$a$YHQGRUVSHFLILF
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65.8 Extended Mode Register Set (EMRS)
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65.9 Bank Activate
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65.10 Burst Read
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
173
P r e l i m i n a r y n
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SURJUDPPHG7KHEXUVWUHDGFDQEHLQLWLDWHGRQDQ\FROXPQDGGUHVVRIWKHDFWLYHURZ7KHDG
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JRHVLQWRKLJKLPSHGDQFHDWWKHHQGRIWKHEXUVWXQOHVVDQHZEXUVWUHDGZDVLQLWLDWHGWRNHHS
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ZULWHLQWKHVDPHEDQNRUWKHRWKHUDFWLYHEDQNRUDSUHFKDUJHFRPPDQGWRWKHVDPHEDQN7KH
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65.11 Burst Write
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65.12 All Banks Precharge
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65.13 Precharge
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65.14 Auto Precharge
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65.15 Auto Refresh
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174
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
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:(7KHDXWRUHIUHVKFRPPDQGFDQRQO\EHDVVHUWHGZLWKDOOEDQNVEHLQJLQLGOHVWDWHDQGWKH
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KLJKHULQWHJHU7KHDXWRUHIUHVKFRPPDQGPXVWEHIROORZHGE\123
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65.16 Self Refresh
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65.17 Basic Feature and Function Descriptions
2) Clock Suspended During Read (BL=4)
1) Clock Suspended During Write
CLK
CLK
CMD
CMD
WR
CKE
RD
CKE
Masked by CKE
Internal
CLK
DQ(CL2)
DQ(CL3)
Masked by CKE
Internal
CLK
D0
D0
D1
D1
D2
D2
D3
DQ(CL2)
D3
DQ(CL3)
Not Written
D
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Suspended Dout
Figure 65.1
May 25, 2004 SDRAM_00_A0
Q0
S73WS256N Based MCPs
Clock Suspend
175
P r e l i m i n a r y n
1) Write Mask (BL=4)
2) Read Mask (BL=4)
CLK
CLK
CMD
CMD
WR
DQM
RD
DQM
Masked by CKE
DQ(CL2)
D0
D1
D3
DQ(CL2)
DQ(CL3)
D0
D1
D3
DQ(CL3)
Masked by CKE
Hi-Z
Q0
Hi-Z
DQM to Data-in Mask = 0
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read) -Note 2
CLK
CMD
RD
CKE
DQM
DQ(CL2)
DQ(CL3)
Q0
Hi-Z
Hi-Z
Q2
Q1
Hi-Z
Hi-Z
Q4
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
Figure 65.2 DQM Operation
1RWHV
&.(WR&/.GLVDEOHHQDEOH &/.
'40PDNHVGDWDRXW+L=DIWHU&/.VZKLFKVKRXOGPDVNHGE\&.(³/´
'40PDVNVERWKGDWDLQDQGGDWDRXW
176
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
1) Read interrupted by Read (BL=4) -Note 1
CLK
CMD
RD
RD
ADD
A
B
QA0 QB0 QB1 QB1 QB3
DQ(CL2)
QA0 QB0 QB1 QB1 QB3
DQ(CL3)
tCCD Note 2
2) Write interrupted by Write (BL=2)
3) Write interrupted by Read (BL=2)
CLK
CLK
CMD
WR WR
CMD
WR
tCCD *2
tCCD *2
ADD
DQ
A
tCDL
ADD
B
DA0 DB0 DB1
Note 3
RD
A
B
DQ(CL2)
DA0
DQ(CL3)
DA0
QB0 QB1
QB0 QB1
tCDL Note 3
Figure 65.3 CAS# Interrupt (1)
1RWHV
%\³,QWHUUXSW´LWLVPHDQWWRVWRSEXUVWUHDGZULWHE\H[WHUQDOFRPPDQGEHIRUHWKHHQGRIEXUVW
%\³&$6,QWHUUXSW´WRVWRSEXUVWUHDGZULWHE\&$6DFFHVVUHDGDQGZULWH
W&&'&$6WR&$6GHOD\ &/.
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
177
P r e l i m i n a r y n
(a) CL=2, BL=4
CLK
i) CMD
RD
WR
DQM
DQ
ii) CMD
D0
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
iii) CMD
D0
RD
WR
DQM
Hi-Z
DQ
iv) CMD
D0
RD
WR
DQM
Q0
DQ
Hi-Z
Note 1
D0
D3
(b) CL=3, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
DQ
iii) CMD
D0
RD
WR
DQM
DQ
iv) CMD
D0
RD
WR
DQM
Hi-Z
DQ
v) CMD
D0
RD
WR
DQM
DQ
Q0
Hi-Z
Note 1
D0
D3
Figure 65.4 CAS# Interrupt (2): Read Interrupted by Write & DQM
1RWHV
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178
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
1) tRDL = 2CLK
CLK
CMD
WR
PRE
Note 2
DQM
DQ
Note 3
D0
D1
D2
Masked by DQM
Figure 65.5 Write Interrupted by Precharge & DQM
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1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
DQ
D0
PRE
D1
D2
D3
tRDLNote 1
2) Normal Read (BL=4)
CLK
Note 2
CMD
RD
PRE
Q0
DQ(CL2)
DQ(CL3)
Q1
Q2
Q3
Q0
Q1
Q2
Note 1
Q3
Note 2
Figure 65.6 Precharge
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
179
P r e l i m i n a r y n
1) Normal Write (BL=4)
2) Normal Read (BL=4)
CLK
CLK
CMD
WR
DQ
D0
ACT
D1
D2
CMD
RD
DQ(CL2)
D3
tRDL =2CLK
tDAL =tRDL + tRPNote 4
Q0
DQ(CL3)
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Auto Precharge Starts Note 3
Auto Precharge Starts@tRDL=2CLK Note 3
Figure 65.7 Auto Precharge
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1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
PRE
DQM
DQ
D1
D0
D2
tRDLNote 1
2) Write Burst Stop (BL=8)
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
CLK
WR
STOP
CMD
DQ(CL2)
DQM
DQ
D0
D1
D2
D3
DQ(CL3)
RD
PRE
Q0
Q1
Q0
1
Q1
2
tBDL Note 2
4) Read Burst Stop (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
STOP
Q0
Q1
Q0
1
Q1
2
Figure 65.8 Burst Stop and Interrupted by Precharge
180
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
1) Mode Register Set
CLK
Note 4
CMD
PRE
MRS
t
RP
ACT
2CLK
Figure 65.9 MRS
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EXUVWOHQJWK
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35($OOEDQNVSUHFKDUJHLVQHFHVVDU\056FDQEHLVVXHGRQO\DWDOOEDQNVSUHFKDUJHVWDWH
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
CLK
CLK
CKE
Internal
CLK
CKE
tSS
Internal
CLK
Note 1
RD
CMD
tSS
Note 2
CMD
NOP ACT
Figure 65.10 Clock Suspend Exit and Power Down Exit
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CLK
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Auto
Refresh
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tRP
tARFC(min)
Figure 65.11 Auto Refresh
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
181
P r e l i m i n a r y n
CLK
Stable Clock
Self
Refresh
Command
ACT
NOP
tSRFX(min)
CKE
tSS
tSS
Figure 65.12 Self Refresh
66 About Burst Type Control
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S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
68 Function Truth Table (1)
Current State
,GOH
5RZ$FWLYH
5HDG
:ULWH
5HDGZLWK$XWR
3UHFKDUJH
:ULWHZLWK$XWR
3UHFKDUJH
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May 25, 2004 SDRAM_00_A0
CS# RAS#
CAS#
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BA
Address
+
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123
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S73WS256N Based MCPs
183
P r e l i m i n a r y n
Current State
CS# RAS#
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184
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
69 Function Truth Table (2)
Current State
6HOI5HIUHVK
$OO%DQNV
3UHFKDUJH
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
185
P r e l i m i n a r y n
70 AC Characteristics
0
1
2
3
4
5
6
7
8
9
10 11
12
13 14 15
16
17 18
19
20
21 22
23 24
25
CLOCK
CKE
Hi
CS#
RAS#
CAS#
Key
ADDR
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High level is necessary
tRP
Precharge
(All Bank)
tARFC
Auto
Refresh
tARFC
Auto
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Normal
MRS
Extended
MRS
Row Active
(A-Bank)
: Don’t care
Figure 70.1
Power Up Sequence for Mobile SDRAM
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S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
QHHGHGDJDLQDWWKLVWLPH,QWKDWFDVHDOOEDQNVKDYHWREHLQLGOHVWDWHSULRUWRDGMXVWLQJ(056
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1
2
tCH
4
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCC
tCL
CKE
HIGH
tRAS
tRC
tRP
tSH
*Note 1
CS#
tRCD
tSS
tSH
RAS#
tSS
tSH
CAS#
tSH
ADDR
Ra
tSS
Ca
Cb
Cc
*Note 2,3
*Note 2,3
Rb
tSS
*Note 2
BA0,BA1
BS
A10/AP
Ra
BS
BS
*Note 3
*Note 2,3 *Note 4
BS
*Note 3
*Note 2
BS
*Note 3
BS
*Note 4
Rb
tSAC
Qa
DQ
tSLZ
tOH
tSH
Db
Qc
tSS
tSS tSH
WE#
tSS tSH
DQM
Row Active
Read
Write
Read
Row Active
Precharge
: Don’t care
Figure 70.2 Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3,
Burst Length=1
1RWHV
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WFDUHZKHQ&6LVKLJKDWWKH&/.KLJKJRLQJHGJH
%DQNDFWLYHDQGUHDGZULWHDUHFRQWUROOHGE\%$%$
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
187
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
tRC
*Note 1
CS#
RAS#
*Note 2
CAS#
ADDR
Ra
Rb
Ca
Cb
BA0
BA1
A10/AP
Rb
Ra
tOH
{
CL=2
Qa0
tRCD
DQ
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
tOH
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
Figure 70.3 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
1RWHV
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5RZSUHFKDUJHFDQLQWHUUXSWEXUVWRQDQ\F\FOH>&$6/DWHQF\@QXPEHURIYDOLGRXWSXWGDWDLV
DYDLODEOHDIWHU5RZSUHFKDUJH/DVWYDOLGRXWSXWZLOOEH+L=W6+=DIWHUWKHFORFN
2XWSXWZLOOEH+L=DIWHUWKHHQGRIEXUVW)XOOSDJHELWEXUVW
188
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
*Note 2
CAS#
ADDR
Ra
Ca
Cb
Cc
Cd
Rb
BA0
BA1
A10/AP
Rb
Ra
tRDL
{
CL=2
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
tRCD
DQ
tDAL
*Note 4
CL=3
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
tCDL
WE#
*Note 1
*Note 3
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
: Don’t care
Figure 70.4 Page Read & Write Cycle at Same Bank @Burst Length=4,
tRDL=2CLK
1RWHV
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WRDYRLGEXVFRQWHQWLRQ
5RZSUHFKDUJHZLOOLQWHUUXSWZULWLQJ/DVWGDWDLQSXWW5'/EHIRUH5RZSUHFKDUJHZLOOEHZULWWHQ
'40VKRXOGPDVNLQYDOLGLQSXWGDWDRQSUHFKDUJHFRPPDQGF\FOHZKHQDVVHUWLQJSUHFKDUJHEHIRUH
HQGRIEXUVW,QSXWGDWDDIWHU5RZSUHFKDUJHF\FOHZLOOEHPDVNHGLQWHUQDOO\
W'$/ODVWGDWDLQWRDFWLYHGHOD\LV&/.W53
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
189
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
CS#
RAS#
*Note 2
CAS#
ADDR
RAa
RBb
RAa
RBb
CAa
RCc
CBb
RDd
CCc
CDd
BA0
BA1
A10/AP
RCc
{
CL=2
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQ
CL=3
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Row Active
(D-Bank)
Precharge
(A-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Precharge
(C-Bank)
Precharge
(B-Bank)
: Don’t care
Figure 70.5 Page Read Cycle at Different Bank @Burst Length=4
1RWHV
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7RLQWHUUXSWDEXUVWUHDGE\URZSUHFKDUJHERWKWKHUHDGDQGWKHSUHFKDUJHEDQNVPXVWEHWKH
VDPH
190
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
*Note 2
CAS#
ADDR
RAa
RAb
RAa
RBb
CAa
CBb
RCc
RDd
RCc
RDd
CCc
CDd
BA0
BA1
A10/AP
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
DQ
tCDL
tRDL
WE#
*Note 1
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Row Active
(C-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Precharge
(All Banks)
Write
(C-Bank)
: Don’t care
Figure 70.6 Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
1RWHV
7RLQWHUUXSWEXUVWZULWHE\5RZSUHFKDUJH'40VKRXOGEHDVVHUWHGWRPDVNLQYDOLGLQSXWGDWD
7RLQWHUUXSWEXUVWZULWHE\5RZSUHFKDUJHERWKWKHZULWHDQGWKHSUHFKDUJHEDQNVPXVWEHWKH
VDPH
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
191
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
RAa
CAa
RDb
CDb
RBc
CBc
BA0
BA1
A10/AP
RAa
RBc
RDb
tCDL
{
CL=2
QAa0 QAa1 QAa2 QAa3
*Note 1
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1
DQ
CL=3
QAa0 QAa1 QAa2 QAa3
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Read
(B-Bank)
Row Active
(B-Bank)
: Don’t care
Figure 70.7 Read & Write Cycle at Different Bank @Burst Length=4
1RWHV
W&'/VKRXOGEHPHWWRFRPSOHWHZULWH
192
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
RAa
RBb
RAa
RBb
CAa
CBb
RAc
CAc
BA0
BA1
A10/AP
RAc
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DQ CL=2
CL=3
DAc0 DAc1
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DAc0 DAc1
WE#
DQM
Row Active
(A-Bank)
Read with
Auto Pre
charge
(A-Bank)
Row Active
(B-Bank)
Read without Auto
Precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank) *Note1
Precharge
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(A-Bank)
: Don’t care
Figure 70.8 Read & Write Cycle with Auto Precharge 1 @Burst Length=4
1RWHV
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LI5HDG:ULWHFRPPDQGZLWKRXWDXWRSUHFKDUJHLVLVVXHGDW%%DQNEHIRUH$%DQNDXWR
SUHFKDUJHVWDUWV$%DQNDXWRSUHFKDUJHZLOOVWDUWDW%%DQNUHDGFRPPDQGLQSXWSRLQW
DQ\FRPPDQGFDQQRWEHLVVXHGDW$%DQNGXULQJW53DIWHU$%DQNDXWRSUHFKDUJHVWDUWV
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
193
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Qb0
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
Rb
DQ CL=2
Qa0
CL=3
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
Qb3
WE#
DQM
*Note1
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don’t care
Figure 70.9 Read & Write Cycle with Auto Precharge 2 @Burst Length=4
1RWHV
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SRLQW
194
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS#
RAS#
CAS#
ADDR
Ra
Ca
Cc
Cb
BA0
BA1
A10/AP
Ra
Qa0
DQ
Qa1
Qa2
Qa3
Qb0
tSHZ
Qb1
Dc0
Dc2
tSHZ
WE#
*Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Read DQM
Write
DQM
Write
Write
DQM
Clock
Suspension
: Don’t care
Figure 70.10 Clock Suspension & DQM Operation Cycle @CAS Latency=2,
Burst Length=4
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
195
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
{
RAa
CL=2
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
DQ
CL=3
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don’t care
Figure 70.11 Read Interrupted by Precharge Command & Read Burst Stop
Cycle @Full Page Burst
1RWHV
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$ERXWWKHYDOLG'4VDIWHUEXUVWVWRSLWLVVDPHDVWKHFDVHRI5$6LQWHUUXSW
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%XWDWEXUVWZULWH%XUVWVWRSDQG5$6LQWHUUXSWVKRXOGEHFRPSDUHGFDUHIXOO\
5HIHUWKHWLPLQJGLDJUDPRI³)XOOSDJHZULWHEXUVWVWRSF\FOH´
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196
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
*Note 1
tBDL
DAa0 DAa1 DAa2 DAa3 DAa4
DQ
*Note 1,2
tRDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE#
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
Figure 70.12 Write Interrupted by Precharge Command & Write Burst Stop
Cycle @ Full Page Burst, tRDL=2CLK
1RWHV
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'40DWZULWHLQWHUUXSWHGE\SUHFKDUJHFRPPDQGLVQHHGHGWRSUHYHQWLQYDOLGZULWH
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HQGRIEXUVW,QSXWGDWDDIWHU5RZSUHFKDUJHF\FOHZLOOEHPDVNHGLQWHUQDOO\
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
197
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
*Note 2
CAS#
ADDR
RAa
CAa
RBb
CAb
RCc
CBc
CCd
BA0
BA1
A10/AP
{
RAa
RBb
CL=2
DAa0
CL=3
DAa0
RCc
QAb0 QAb1
DBc0
QCd0 QCd1
DQ
QAb0 QAb1
DBc0
QCd0 QCd1
WE#
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
Read with
(A-Bank) Auto Precharge
(A-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Precharge
(C-Bank)
Write with
Auto Precharge
(B-Bank)
: Don’t care
Figure 70.13 Burst Read Single bit Write Cycle @Burst Length=2
1RWHV
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:KHQ%56:ZULWHFRPPDQGZLWKDXWRSUHFKDUJHLVH[HFXWHGNHHSLWLQPLQGWKDWW5$6VKRXOGQRW
EHYLRODWHG$XWRSUHFKDUJHLVH[HFXWHGDWWKHEXUVWHQGF\FOHVRLQWKHFDVHRI%56:ZULWH
FRPPDQGWKHQH[WF\FOHVWDUWVWKHSUHFKDUJH
198
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tSS
CKE
tSS
*Note 1
tSS
*Note 2
*Note 2
*Note 3
CS#
RAS#
CAS#
Ra
ADDR
Ca
BA
Ra
A10/AP
Qa0
DQ
Qa1
Qa2
tSHZ
WE#
DQM
Precharge
Power-down
Entry
Row Active
Precharge
Power-down
Exit
Active
Power-down
Entry
Read
Precharge
Active
Power-down
Exit
: Don’t care
Figure 70.14 Active/Precharge Power Down Mode @CAS Latency=2, Burst
Length=4
1RWHV
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
199
P r e l i m i n a r y n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note 2
*Note 4
tSRFX
*Note 1
*Note 6
CKE
*Note 3
tSS
CS#
RAS#
CAS#
ADDR
BA0,BA1
A10/AP
DQ
Hi-Z
Hi-Z
WE#
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don’t care
Figure 70.15 Self Refresh Entry & Exit Cycle
1RWHV
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WFDUHH[FHSWIRU&.(
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UHIUHVKPRGHPLQLPXPW5$6LVUHTXLUHGEHIRUHH[LWIURPVHOIUHIUHVK
72(;,76(/)5()5(6+02'(
200
6\VWHPFORFNUHVWDUWDQGEHVWDEOHEHIRUHUHWXUQLQJ&.(KLJK
&6VWDUWVIURPKLJK
0LQLPXPW65);LVUHTXLUHGDIWHU&.(JRLQJKLJKWRFRPSOHWHVHOIUHIUHVKH[LW
.F\FOHRIEXUVWDXWRUHIUHVKLVUHTXLUHGEHIRUHVHOIUHIUHVKHQWU\DQGDIWHUVHOIUHIUHVKH[LWLIWKH
V\VWHPXVHVEXUVWUHIUHVK
S73WS256N Based MCPs
SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
HIGH
CKE
HIGH
CS
tARFC
*Note 2
RAS
*Note 1
CAS
*Note 3
ADDR
Key
Ra
BA0
BA1
Hi-Z
DQ
Hi-Z
WE
DQM
MRS
New Command
Auto Refresh
New Command
: Don’t care
Figure 70.16 Mode Register Set Cycle and Auto Refresh Cycle
1RWH$OOEDQNVSUHFKDUJHVKRXOGEHFRPSOHWHGEHIRUH0RGH5HJLVWHU6HWF\FOHDQGDXWRUHIUHVKF\FOH
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May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
201
P r e l i m i n a r y n
0
1
2
3
4
5
6
CLOCK
HIGH
CKE
CS#
*Note 2
RAS#
*Note 1
CAS#
*Note 3
ADDR
Key
Ra
BA0
BA1
Hi-Z
DQ
WE#
DQM
EMRS
New Command
: Don’t care
Figure 70.17 Extended Mode Register Set Cycle
1RWHV
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LQWHUQDOPRGHUHJLVWHU
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202
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SDRAM_00_A0 May 25, 2004
P r e l i m i n a r y
71 SDRAM Type 2 Revision Summary
Revision A0 (May 25, 2004)
,QLWLDO5HOHDVH
May 25, 2004 SDRAM_00_A0
S73WS256N Based MCPs
203
Mobile SDRAM Type 2
256Mbit (16M x 16 bit) SDRAM
PRELIMINARY
Features
„
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General Description
7KH0RELOH6'5$07\SHLVELWVV\QFKURQRXVKLJKGDWDUDWH'\QDPLF5$0RUJDQL]HGDV[
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WHPFORFNDQG,2WUDQVDFWLRQVDUHSRVVLEOHRQHYHU\FORFNF\FOH5DQJHRIRSHUDWLQJIUHTXHQFLHVSURJUDPPDEOHEXUVW
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Publication Number SDRAM_04
Revision A
Amendment 0
Issue Date May 12, 2005
7KLVGRFXPHQWVWDWHVWKHFXUUHQWWHFKQLFDOVSHFLILFDWLRQVUHJDUGLQJWKH6SDQVLRQSURGXFWVGHVFULEHGKHUHLQ7KH3UHOLPLQDU\VWDWXVRIWKLVGRFXPHQWLQGLFDWHVWKDW
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P r e l i m i n a r y
72 Address Table
16M x 16
&RQILJXUDWLRQ
0[[EDQNV
5HIUHVK&RXQW
.
5RZ$GGUHVVLQJ
.$±$
%DQN$GGUHVVLQJ
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73 Functional Block Diagram
I/O Control
Data Input Register
Bank Select
4M x 16
4M x 16
Output Buffer
Sense AMP
Row Decoder
Row Buffer
Refresh Counter
ADD
Address Register
CLK
4M x 16
LWE
LDQM
DQi
4M x 16
Col. Buffer
LCBR
LRAS
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LCAS
LWE
LWCBR
LDQM
Timing Register
CLK
May 12, 2005 SDRAM_04_A0
CKE
CS
RAS
CAS
WE
S73WS256N Based MCPs
L(U)DQM
205
P r e l i m i n a r y
74 Absolute Maximum Ratings
Symbol
Value
Unit
9ROWDJHRQDQ\SLQUHODWLYHWR966
Parameter
9,19287
a
9
9ROWDJHRQ9''VXSSO\UHODWLYHWR966
9''9''4
a
9
767*
a
ƒ&
3RZHUGLVVLSDWLRQ
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)XQFWLRQDORSHUDWLRQVKRXOGEHUHVWULFWHGWRUHFRPPHQGHGRSHUDWLQJFRQGLWLRQ
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UHOLDELOLW\
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SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
75 DC Operating Conditions
5HFRPPHQGHGRSHUDWLQJFRQGLWLRQV9ROWDJHUHIHUHQFHGWR966 97$ ƒ&WRƒ&IRU
([WHQGHGƒ&WRƒ&IRU&RPPHUFLDO
Parameter
6XSSO\YROWDJH
,QSXWORJLFKLJKYROWDJH
,QSXWORJLFORZYROWDJH
2XWSXWORJLFKLJKYROWDJH
2XWSXWORJLFORZYROWDJH
,QSXWOHDNDJHFXUUHQW
Symbol
Min
Typ
Max
Unit
9''
9''4
9,+
9,/
92+
92/
,/,
9
Note
9
[9''4
9''4
9
9
9''4
9
,2+ P$
9
,2/ P$
—$
1RWHV
9,+PD[ 9$&7KHRYHUVKRRWYROWDJHGXUDWLRQLV≤QV
9,/PLQ 9$&7KHXQGHUVKRRWYROWDJHGXUDWLRQLV≤QV
$Q\LQSXW9≤9,1≤9''4,QSXWOHDNDJHFXUUHQWVLQFOXGH+L=RXWSXWOHDNDJHIRUDOOELGLUHFWLRQDO
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76 Capacitance
9'' 97$ ƒ&I 0+]95() 9“P9
Pin
&ORFN
5$6&$6:(&6&.('40
Symbol
Min
Max
Unit
&&/.
S)
&,1
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May 12, 2005 SDRAM_04_A0
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207
P r e l i m i n a r y
77 DC Characteristics
5HFRPPHQGHGRSHUDWLQJFRQGLWLRQV9ROWDJHUHIHUHQFHGWR966 97$ ƒ&WRƒ&IRU
([WHQGHGƒ&WRƒ&IRU&RPPHUFLDO
Parameter
Symbol
2SHUDWLQJ&XUUHQW
2QH%DQN$FWLYH
3UHFKDUJH6WDQGE\&XUUHQW
LQSRZHUGRZQPRGH
3UHFKDUJH6WDQGE\&XUUHQW
LQQRQSRZHUGRZQPRGH
$FWLYH6WDQGE\&XUUHQWLQ
SRZHUGRZQPRGH
$FWLYH6WDQGE\&XUUHQWLQ
QRQSRZHUGRZQPRGH
2QH%DQN$FWLYH
Value
Unit
Note
,&&
%XUVWOHQJWK W5&≥ W5&PLQ
,2 P$
Test Condition
P$
,&&3
&.(≤ 9,/PD[W&& QV
,&&36
&.(&/.≤ 9,/PD[W&& ∞
,&&1
&.(≥ 9,+PLQ&6≥ 9,+PLQW&& QV
,QSXWVLJQDOVDUHFKDQJHGRQHWLPHGXULQJ
QV
,&&16
&.(≥ 9,+PLQ&/.≤ 9,/PD[W&& ∞
,QSXWVLJQDOVDUHVWDEOH
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&.(≤ 9,/PD[W&& QV
&.(&/.≤ 9,/PD[W&& ∞
,&&1
&.(≥ 9,+PLQ&6≥ 9,+PLQW&& QV
,QSXWVLJQDOVDUHFKDQJHGRQHWLPHGXULQJ
QV
,&&16
&.(≥ 9,+PLQ&/.≤ 9,/PD[W&& ∞
,QSXWVLJQDOVDUHVWDEOH
2SHUDWLQJ&XUUHQW
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,&&
5HIUHVK&XUUHQW
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W$5)&≥ W$5)&PLQ
6HOI5HIUHVK&XUUHQW
P$
,&&36
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3DJHEXUVW
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W&&' &/.V
,&&
&.(≤ 9
P$
P$
P$
P$
P$
P$
Internal TCSR
0D[
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RI)XOO$UUD\
RI)XOO$UUD\
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1RWHV
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78 AC Operating Test Conditions
9'' 9WR97$ ƒ&WRƒ&IRU([WHQGHGƒ&WRƒ&IRU&RPPHUFLDO
Parameter
$&LQSXWOHYHOV9,+9,/
Value
Unit
[9''4
9
,QSXWWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHO
[9''4
9
,QSXWULVHDQGIDOOWLPH
WUWI QV
[9''4
9
2XWSXWWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHO
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9
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Figure 78.1 DC Output Load Circuit
208
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SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
9WW [9''4
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2XWSXW
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Figure 78.2 AC Output Load Circuit
79 Operating AC Parameters
$&RSHUDWLQJFRQGLWLRQVXQOHVVRWKHUZLVHQRWHG
Symbol
Value
Unit
Note
5RZDFWLYHWRURZDFWLYHGHOD\
Parameter
W55'PLQ
QV
5$6WR&$6GHOD\
W5&'PLQ
QV
5RZSUHFKDUJHWLPH
W53PLQ
QV
W5$6PLQ
QV
W5$6PD[
XV
5RZF\FOHWLPH
W5&PLQ
QV
/DVWGDWDLQWRURZSUHFKDUJH
W5'/PLQ
QV
/DVWGDWDLQWR$FWLYHGHOD\
W'$/PLQ
W5'/W53
/DVWGDWDLQWRQHZFRODGGUHVVGHOD\
W&'/PLQ
&/.
/DVWGDWDLQWREXUVWVWRS
W%'/PLQ
&/.
$XWRUHIUHVKF\FOHWLPH
W$5)&PLQ
QV
([LWVHOIUHIUHVKWRDFWLYHFRPPDQG
W65);PLQ
QV
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W&&'PLQ
&/.
HD
5RZDFWLYHWLPH
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&$6ODWHQF\ 1XPEHURIYDOLGRXWSXWGDWD
&$6ODWHQF\ 1XPEHURIYDOLGRXWSXWGDWD
&$6ODWHQF\ ²
1RWHV
7KHPLQLPXPQXPEHURIFORFNF\FOHVLVGHWHUPLQHGE\GLYLGLQJWKHPLQLPXPWLPHUHTXLUHGZLWK
FORFNF\FOHWLPHDQGWKHQURXQGLQJRIIWRWKHQH[WKLJKHULQWHJHU
0LQLPXPGHOD\LVUHTXLUHGWRFRPSOHWHZULWH
$OOSDUWVDOORZHYHU\F\FOHFROXPQDGGUHVVFKDQJH
,QFDVHRIURZSUHFKDUJHLQWHUUXSWDXWRSUHFKDUJHDQGUHDGEXUVWVWRS
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
209
P r e l i m i n a r y
80 AC Characteristics
$&RSHUDWLQJFRQGLWLRQVXQOHVVRWKHUZLVHQRWHG
Parameter
&/.F\FOHWLPH
&/.WRYDOLGRXWSXWGHOD\
Symbol
Min
&$6ODWHQF\ W&&
&$6ODWHQF\ W&&
Max
Unit
Note
QV
QV
V
QV
&$6ODWHQF\ W6$&
&$6ODWHQF\ W6$&
&$6ODWHQF\ W2+
&$6ODWHQF\ W2+
&/.KLJKSXOVHZLGWK
W&+
QV
&/.ORZSXOVHZLGWK
W&/
QV
,QSXWVHWXSWLPH
W66
QV
,QSXWKROGWLPH
W6+
QV
&/.WRRXWSXWLQ/RZ=
W6/=
QV
2XWSXWGDWDKROGWLPH
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&$6ODWHQF\ &$6ODWHQF\ W6+=
QV
1RWHV
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,IFORFNULVLQJWLPHLVORQJHUWKDQQVWUQVVKRXOGEHDGGHGWRWKHSDUDPHWHU
$VVXPHGLQSXWULVHDQGIDOOWLPHWUWI QV,IWUWILVORQJHUWKDQQVWUDQVLHQWWLPH
FRPSHQVDWLRQVKRXOGEHFRQVLGHUHGLH>WUWI@QVVKRXOGEHDGGHGWRWKHSDUDPHWHU
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SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
81 Simplified Truth Table
Command
5HJLVWHU
CKEn-1
0RGH5HJLVWHU6HW
$XWR5HIUHVK
5HIUHVK
(QWU\
6HOI
5HIUHVK
([LW
+
CS#
;
/
/
/
/
;
23&2'(
/
/
/
+
;
;
/
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;
;
;
;
;
+
+
/
RAS# CAS# WE#
DQM
BA0,1
/
+
%DQN$FWLYH5RZ$GGU
+
;
/
/
+
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;
9
$XWR3UHFKDUJH'LVDEOH
5HDG
&ROXPQ$GGUHVV $XWR3UHFKDUJH(QDEOH
+
;
/
+
/
+
;
9
$XWR3UHFKDUJH'LVDEOH
:ULWH
&ROXPQ$GGUHVV $XWR3UHFKDUJH(QDEOH
+
;
/
+
/
/
;
9
%XUVW6WRS
+
;
/
+
+
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;
%DQN6HOHFWLRQ
3UHFKDUJH
+
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+
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([LW
/
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3UHFKDUJH3RZHU'RZQ0RGH
'40
/
/
+
/
+
;
;
;
/
9
9
9
;
;
;
;
+
;
;
;
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+
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;
;
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9
9
9
/
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1R2SHUDWLRQ&RPPDQG
;
;
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;
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A10/AP
Note
5RZ$GGUHVV
/
&ROXPQ
$GGUHVV
$$
+
/
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$GGUHVV
$$
+
;
9
/
;
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;
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;
;
;
;
;
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A12, A11,
A9 ~ A0
CKEn
9
;
;
;
/HJHQG9 9DOLG; 'RQ¶W&DUH+ /RJLF+LJK/ /RJLF/RZ
1RWHV
23&RGH2SHUDQG&RGH$$%$%$3URJUDPNH\V#056
056FDQEHLVVXHGRQO\DWDOOEDQNVSUHFKDUJHVWDWH$QHZFRPPDQGFDQEHLVVXHGDIWHU&/.
F\FOHVRI056
$XWRUHIUHVKIXQFWLRQVDUHWKHVDPHDV&%5UHIUHVKRI'5$07KHDXWRPDWLFDOO\SUHFKDUJHZLWKRXW
URZSUHFKDUJHFRPPDQGLVPHDQWE\$XWR$XWRVHOIUHIUHVKFDQEHLVVXHGRQO\DWDOOEDQNV
SUHFKDUJHVWDWH3DUWLDOVHOIUHIUHVKFDQEHLVVXHGRQO\DIWHUVHWWLQJSDUWLDOVHOIUHIUHVKPRGHRI
(056
%$%$%DQNVHOHFWDGGUHVVHV
'XULQJEXUVWUHDGRUZULWHZLWKDXWRSUHFKDUJHQHZUHDGZULWHFRPPDQGFDQQRWEHLVVXHG
$QRWKHUEDQNUHDGZULWHFRPPDQGFDQEHLVVXHGDIWHUWKHHQGRIEXUVW1HZURZDFWLYHRIWKH
DVVRFLDWHGEDQNFDQEHLVVXHGDWW53DIWHUWKHHQGRIEXUVW
%XUVWVWRSFRPPDQGLVYDOLGDWHYHU\EXUVWOHQJWK
'40VDPSOHGDWWKHSRVLWLYHJRLQJHGJHRI&/.PDVNVWKHGDWDLQDWWKDWVDPH&/.LQZULWH
RSHUDWLRQ:ULWH'40ODWHQF\LVEXWLQUHDGRSHUDWLRQLWPDNHVWKHGDWDRXW+L=VWDWHDIWHU
&/.F\FOHV5HDG'40ODWHQF\LV
82 Mode Register Field Table to Program Modes
Address
)XQFWLRQ
BA0 ~ BA1
A12 ~ A10/AP
A9*2
6HWWLQJIRU
1RUPDO056
5)8
:%/
A8
A7
7HVW0RGH
A6
A5
A4
&$6/DWHQF\
A3
%7
A2
A1
A0
%XUVW/HQJWK
1RWH5HJLVWHU3URJUDPPHGZLWK1RUPDO056
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
211
P r e l i m i n a r y
82.1
Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
0
0
0RGH5HJLVWHU6HW
5HVHUYHG
6HTXHQWLDO
0
1
5HVHUYHG
,QWHUOHDYH
1
0
5HVHUYHG
1
1
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
Write Burst Length
Mode Select
BA1
A9
Length
5HVHUYHG
%XUVW
5HVHUYHG
6LQJOH%LW
5HVHUYHG
BA0
Mode
6HWWLQJ
IRU
1RUPDO
056
BT=1
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
)XOO3DJH
5HVHUYHG
1RWH)XOO3DJH/HQJWK[0E0E0E0E
Table 82.1
BA1
BA0
BA0
0RGH6HOHFW
Address
)XQFWLRQ
Register Programmed with Extended MRS
A12 ~ A10/AP
A10
A9
A8
A7
A6
5)8
A5
A4
'6
A3
A2
5)8
A1
A0
3$65
82.2 EMRS for PASR (Partial Array Self Refresh) and DS (Driver Strength)
Mode Select
Driver Strength
PASR
BA1
BA0
Mode
A6
A5
Driver Strength
A2
A1
A0
1RUPDO056
)XOO
)XOO$UUD\
5HVHUYHG
RI)XOO$UUD\
(056IRU0RELOH6'5$0
RI)XOO$UUD\
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
5HVHUYHG
Reserved Address
A12-A10/AP
A9
A8
A7
A4
A3
Size of Refreshed Array
1RWHV
5)85HVHUYHGIRUIXWXUHXVHVKRXOGVWD\GXULQJ056F\FOH
,I$LVKLJKGXULQJ056F\FOH%XUVW5HDG6LQJOH%LW:ULWHIXQFWLRQZLOOEHHQDEOHG
83 Partial Array Self Refresh
,QRUGHUWRVDYHSRZHUFRQVXPSWLRQ0RELOH6'5$0KDVD3$65RSWLRQ0RELOH6'5$0VXS
SRUWVNLQGVRI3$65LQVHOIUHIUHVKPRGHIXOODUUD\RIIXOODUUD\RIIXOODUUD\6HH
)LJXUH
212
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- Full Array
- 1/2 of full Array
- 1/4 of full Array
Partial Self Refresh Area
Figure 83.1
83.1
Partial Array Self Refresh Areas
Internal Temperature Compensated Self Refresh (TCSR)
Temperature Range
Self Refresh Current (Icc 6)
Full Array
1/2 of Full Array
1/4 of Full Array
0D[°&
0D[°&
Unit
—$
1RWHV
,QRUGHUWRVDYHSRZHUFRQVXPSWLRQ0RELOH6'5$0LQFOXGHVWKHLQWHUQDOWHPSHUDWXUHVHQVRUDQG
FRQWUROXQLWVWRFRQWUROWKHVHOIUHIUHVKF\FOHDXWRPDWLFDOO\DFFRUGLQJWRWKHWZRWHPSHUDWXUHUDQJHV
0D[ƒ&DQG0D[ƒ&IRU([WHQGHG0D[ƒ&IRU&RPPHUFLDO
,IWKH(056IRUH[WHUQDO7&65LVLVVXHGE\WKHFRQWUROOHUWKLV(056FRGHIRU7&65LVLJQRUHG
84 Power Up Sequence
$SSO\SRZHUDQGDWWHPSWWRPDLQWDLQ&.(DWDKLJKVWDWHDQGDOORWKHULQSXWVPD\EH
XQGHILQHG
$SSO\9''EHIRUHRUDWWKHVDPHWLPHDV9''4
0DLQWDLQVWDEOHSRZHUVWDEOHFORFNDQG123LQSXWFRQGLWLRQIRUDPLQLPXPRIXV
,VVXHSUHFKDUJHFRPPDQGVIRUDOOEDQNVRIWKHGHYLFHV
,VVXHRUPRUHDXWRUHIUHVKFRPPDQGV
,VVXHDPRGHUHJLVWHUVHWFRPPDQGWRLQLWLDOL]HWKHPRGHUHJLVWHU
,VVXHDH[WHQGHGPRGHUHJLVWHUVHWFRPPDQGWRGHILQH'6RU3$65RSHUDWLQJW\SHRI
WKHGHYLFHDIWHUQRUPDO056
(056F\FOHLVQRWPDQGDWRU\DQGWKH(056FRPPDQGQHHGVWREHLVVXHGRQO\ZKHQ'6RU
3$65LVXVHG
7KH GHIDXOW VWDWH ZLWKRXW (056 FRPPDQG LVVXHG LV KDOI GULYHU VWUHQJWK DQG IXOO DUUD\
UHIUHVKHG
7KHGHYLFHLVQRZUHDG\IRUWKHRSHUDWLRQVHOHFWHGE\(056
)RURSHUDWLQJZLWK'6RU3$65VHW'6RU3$65PRGHLQ(056VHWWLQJVWDJH
,QRUGHUWRDGMXVWDQRWKHUPRGHLQWKHVWDWHRI'6RU3$65PRGHDGGLWLRQDO(056VHWLVUH
TXLUHGEXWSRZHUXSVHTXHQFHLVQRWQHHGHGDJDLQDWWKLVWLPH,QWKDWFDVHDOOEDQNVKDYH
WREHLQLGOHVWDWHSULRUWRDGMXVWLQJ(056VHW
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
213
P r e l i m i n a r y
85 Burst Sequence
85.1
Burst Length = 4
Initial Address
Sequential
Interleave
A1
A0
85.2 Burst Length = 8
Initial Address
Sequential
Interleave
A2
A1
A0
86 Device Operations
86.1
Addresses of 256Mb
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P r e l i m i n a r y
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S73WS256N Based MCPs
217
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EXUVWDXWRUHIUHVKF\FOHVIRU0EDQG0ELPPHGLDWHO\EHIRUHHQWHULQJVHOIUHIUHVK
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218
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
87 Basic Feature and Function Descriptions
87.1
Clock Suspend
CLK
CMD
WR
CKE
Masked by CKE
Internal
CLK
DQ(CL2)
D0
D1
D2
D3
DQ(CL3)
D0
D1
D2
D3
Not Written
Figure 87.1
Clock Suspend During Write
CLK
CMD
RD
CKE
Masked by CKE
Internal
CLK
DQ(CL2)
Q0
DQ(CL3)
D
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Suspended Dout
Figure 87.2
Clock Suspend During Read (BL = 4)
87.2 DQM Operation
CLK
CMD
WR
DQM
Masked by CKE
DQ(CL2)
D0
D1
D3
DQ(CL3)
D0
D1
D3
DQM to Data-in Mask = 0
Figure 87.1
Write Mask (BL = 4)
CLK
CMD
RD
DQM
DQ(CL2)
DQ(CL3)
Q0
Masked by CKE
Hi-Z
Hi-Z
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask= 2
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
219
P r e l i m i n a r y
Figure 87.2 Read Mask (BL = 4)
CLK
CMD
RD
CKE
DQM
Hi-Z
Q0
DQ(CL2)
Hi-Z
DQ(CL3)
Hi-Z
Q2
Q4
Hi-Z
Q1
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
1RWHV
&.(WR&/.GLVDEOHHQDEOH &/.
'40PDNHVGDWDRXW+L=DIWHU&/.VZKLFKVKRXOGPDVNHGE\&.(/
'40PDVNVERWKGDWDLQDQGGDWDRXW
Figure 87.3
DQM with CLock Suspended (Full Page Read)
87.3 CAS# Interrupt 1
CLK
CMD
RD
RD
ADD
A
B
QA0 QB0 QB1 QB1 QB3
DQ(CL2)
QA0 QB0 QB1 QB1 QB3
DQ(CL3)
tCCD Note 2
1RWHV
%\,QWHUUXSW,WLVPHDQWWRVWRSEXUVWUHDGZULWHE\H[WHUQDOFRPPDQGEHIRUHWKHHQGRIEXUVW%\
&$6,QWHUUXSWWRVWRSEXUVWUHDGZULWHE\&$6DFFHVVUHDGDQGZULWH
W&&'&$6WR&$6GHOD\ &/.
W&'//DVWGDWDLQWRQHZFROXPQDGGUHVVGHOD\ &/.
Figure 87.4
Read Interrupted by Read (BL = 4)
CLK
CMD
WR WR
tCCD Note 2
ADD
DQ
A
B
DA0 DB0 DB1
tCDL Note 3
1RWHV
%\,QWHUUXSW,WLVPHDQWWRVWRSEXUVWUHDGZULWHE\H[WHUQDOFRPPDQGEHIRUHWKHHQGRIEXUVW%\
&$6,QWHUUXSWWRVWRSEXUVWUHDGZULWHE\&$6DFFHVVUHDGDQGZULWH
W&&'&$6WR&$6GHOD\ &/.
W&'//DVWGDWDLQWRQHZFROXPQDGGUHVVGHOD\ &/.
Figure 87.5
220
Write Interrupted by Write (BL = 2)
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
CLK
WR
CMD
RD
tCCD Note 2
A
ADD
B
DQ(CL2)
DA0
DQ(CL3)
DA0
QB0 QB1
QB0 QB1
tCDL Note 3
1RWHV
%\,QWHUUXSW,WLVPHDQWWRVWRSEXUVWUHDGZULWHE\H[WHUQDOFRPPDQGEHIRUHWKHHQGRIEXUVW%\
&$6,QWHUUXSWWRVWRSEXUVWUHDGZULWHE\&$6DFFHVVUHDGDQGZULWH
W&&'&$6WR&$6GHOD\ &/.
W&'//DVWGDWDLQWRQHZFROXPQDGGUHVVGHOD\ &/.
Figure 87.6
May 12, 2005 SDRAM_04_A0
Write Interrupted by Read (BL = 2)
S73WS256N Based MCPs
221
P r e l i m i n a r y
87.4 CAS# Interrupt 2
(a) CL=2, BL=4
CLK
1) CMD
RD
WR
DQM
DQ
D0
2) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
D0
RD
3) CMD
WR
DQM
Hi-Z
DQ
4) CMD
D0
RD
WR
DQM
Q0
DQ
Hi-Z
Note 1
D0
D3
(b) C L=3, BL=4
CLK
1) CMD
RD
WR
DQM
D0
DQ
2) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
DQ
3) CMD
D0
RD
WR
DQM
DQ
4) CMD
D0
RD
WR
DQM
Hi-Z
DQ
5) CMD
D0
RD
WR
DQM
DQ
Q0
Hi-Z
Note 1
D0
D3
1RWHV
7RSUHYHQWEXVFRQWHQWLRQWKHUHVKRXOGEHDWOHDVWRQHJDSEHWZHHQGDWDLQDQGGDWDRXW
Figure 87.7 Read Interrupted by Write and DQM
222
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
tRDL = 2CLK
CLK
CMD
WR
PRE
Note 2
DQM
DQ
Note 3
D0
D1
D2
Masked by DQM
1RWHV
7RSUHYHQWEXVFRQWHQWLRQ'40VKRXOGEHLVVXHGZKLFKPDNHVDWOHDVWRQHJDSEHWZHHQGDWDLQ
DQGGDWDRXW
7RLQKLELWLQYDOLGZULWH'40VKRXOGEHLVVXHG
7KLVSUHFKDUJHFRPPDQGDQGEXUVWZULWHFRPPDQGVKRXOGEHRIWKHVDPHEDQNRWKHUZLVHLWLVQRW
SUHFKDUJHLQWHUUXSWEXWRQO\DQRWKHUEDQNSUHFKDUJHRIIRXUEDQNVRSHUDWLRQ
Figure 87.8
Write Interrupted by Precharge and DQM
1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
DQ
D0
PRE
D1
D2
D3
tRDLNote 1
2) Normal Read (BL=4)
CLK
CMD
RD
PRE
Q0
DQ(CL2)
DQ(CL3)
Note 2
Q1
Q2
Q3
Q0
Q1
Q2
1
Q3
2
1RWHV
W5'/ &/.LVVXSSRUWHG
1XPEHURIYDOLGRXWSXWGDWDDIWHUURZSUHFKDUJHIRU&$6/DWHQF\ UHVSHFWLYHO\
7KHURZDFWLYHFRPPDQGRIWKHSUHFKDUJHEDQNFDQEHLVVXHGDIWHUW53IURPWKLVSRLQW7KHQHZ
UHDGZULWHFRPPDQGRIRWKHUDFWLYDWHGEDQNFDQEHLVVXHGIURPWKLVSRLQW$WEXUVWUHDGZULWHZLWK
DXWRSUHFKDUJH&$6LQWHUUXSWRIWKHVDPHEDQNLVLOOHJDO
W'$/GHILQHG/DVWGDWDLQWR$FWLYHGHOD\W'$/ W5'/W53LVVXSSRUWHG
Figure 87.9
May 12, 2005 SDRAM_04_A0
Precharge
S73WS256N Based MCPs
223
P r e l i m i n a r y
1) Normal Write (BL=4)
2) Normal Read (BL=4)
CLK
CLK
CMD
WR
DQ
D0
ACT
D1
D2
CMD
RD
DQ(CL2)
D3
DQ(CL3)
tRDL =2CLK
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
tDAL=tRDL +tRP Note 4
Auto Precharge Starts Note 3
Auto Precharge Starts@tRDL=2CLK *3
1RWHV
W5'/ &/.LVVXSSRUWHG
1XPEHURIYDOLGRXWSXWGDWDDIWHUURZSUHFKDUJHIRU&$6/DWHQF\ UHVSHFWLYHO\
7KHURZDFWLYHFRPPDQGRIWKHSUHFKDUJHEDQNFDQEHLVVXHGDIWHUW53IURPWKLVSRLQW7KHQHZ
UHDGZULWHFRPPDQGRIRWKHUDFWLYDWHGEDQNFDQEHLVVXHGIURPWKLVSRLQW$WEXUVWUHDGZULWHZLWK
DXWRSUHFKDUJH&$6LQWHUUXSWRIWKHVDPHEDQNLVLOOHJDO
W'$/GHILQHG/DVWGDWDLQWR$FWLYHGHOD\W'$/ W5'/W53LVVXSSRUWHG
Figure 87.10
224
Auto Precharge
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
1) Normal Write
BL=4 & tRDL=2CLK
CLK
CMD
WR
PRE
DQM
DQ
D0
D1
D2
tRDLNote 1
2) Write Burst Stop (BL=8)
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
CLK
WR
STOP
CMD
DQ(CL2)
DQM
DQ
RD
D0
D1
D2
D3
PRE
Q0
Q1
Q0
DQ(CL3)
1
Q1
2
tBDL Note 2
4) ReadBurst Stop (BL=4)
CLK
CMD
RD
STOP
Q0
DQ(CL2)
Q1
Q0
DQ(CL3)
1
Q1
2
1RWHV
W5'/ &/.LVVXSSRUWHG
W%'/&/./DVWGDWDLQWREXUVWVWRSGHOD\5HDGRUZULWHEXUVWVWRSFRPPDQGLVYDOLGDWHYHU\
EXUVWOHQJWK
1XPEHURIYDOLGRXWSXWGDWDDIWHUURZSUHFKDUJHRUEXUVWVWRSIRU&$6ODWHQF\ UHVSHF
WLYHO\
35($OOEDQNVSUHFKDUJHLVQHFHVVDU\056FDQEHLVVXHGRQO\DWDOOEDQNVSUHFKDUJHVWDWH
Figure 87.11
Burst Stop and Interrupted by Precharge
1) Mode Register Set
CLK
CMD
Note 4
PRE
MRS
tRP
ACT
2CLK
1RWHV
W5'/ &/.LVVXSSRUWHG
W%'/&/./DVWGDWDLQWREXUVWVWRSGHOD\5HDGRUZULWHEXUVWVWRSFRPPDQGLVYDOLGDWHYHU\
EXUVWOHQJWK
1XPEHURIYDOLGRXWSXWGDWDDIWHUURZSUHFKDUJHRUEXUVWVWRSIRU&$6ODWHQF\ UHVSHF
WLYHO\
35($OOEDQNVSUHFKDUJHLVQHFHVVDU\056FDQEHLVVXHGRQO\DWDOOEDQNVSUHFKDUJHVWDWH
Figure 87.12 Mode Register Set
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
225
P r e l i m i n a r y
1) Clock Suspend (= Active Power Down) Exit
2) Power Down (= Precharge Power Down) Exit
CLK
CLK
CKE
Internal
CLK
CKE
tSS
Internal
CLK
Note 1
RD
CMD
tSS
Note 2
NOP ACT
CMD
Figure 87.13 Clock Suspend Exit and Power Down Exit
87.5 Auto Refresh
$QDXWRUHIUHVKFRPPDQGLVLVVXHGE\KDYLQJ&65$6DQG&$6KHOGORZZLWK&.(DQG
:(KLJKDWWKHULVLQJHGJHRIWKHFORFN&/.$OOEDQNVPXVWEHSUHFKDUJHGDQGLGOHIRU
W53PLQEHIRUHWKHDXWRUHIUHVKFRPPDQGLVDSSOLHG1RFRQWURORIWKHH[WHUQDODGGUHVVSLQV
LVUHTXLUHGRQFHWKLVF\FOHKDVVWDUWHGEHFDXVHRIWKHLQWHUQDODGGUHVVFRXQWHU:KHQWKHUH
IUHVKF\FOHKDVFRPSOHWHGDOOEDQNVZLOOEHLQWKHLGOHVWDWH$GHOD\EHWZHHQWKHDXWRUHIUHVK
FRPPDQGDQGWKHQH[WDFWLYDWHFRPPDQGRUVXEVHTXHQWDXWRUHIUHVKFRPPDQGPXVWEH
JUHDWHUWKDQRUHTXDOWRWKHW$5)&PLQ
CKE = High
CMD
~
~
Auto
Refresh
PRE
~
~
Command
~
~
CLK
tRP
tARFC(min)
Figure 87.14 Auto Refresh
87.6 Self Refresh
Stable Clock
NOP
~
~
Self
Refresh
~
~
Command
~
~
CLK
~
~
~
~
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KHOGORZWRNHHSWKHGHYLFHLQ6HOI5HIUHVKPRGH$IWHUFORFNF\FOHIURPWKHVHOIUHIUHVK
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OHFWRU123FRPPDQGDQGWKHQDVVHUW&.(KLJK,QFDVHWKDWWKHV\VWHPXVHVEXUVWDXWR
UHIUHVKGXULQJQRUPDORSHUDWLRQLWLVUHFRPPHQGHGWRXVHEXUVWDXWRUHIUHVKF\FOHLPPHGL
DWHO\EHIRUHHQWHULQJVHOIUHIUHVKPRGHDQGDIWHUH[LWLQJLQVHOIUHIUHVKPRGH2QWKHRWKHU
KDQGLIWKHV\VWHPXVHVWKHGLVWULEXWHGDXWRUHIUHVKWKHV\VWHPRQO\KDVWRNHHSWKHUHIUHVK
GXW\F\FOH
ACT
~
~
tSRFX(min)
~
~
CKE
tSS
tSS
Figure 87.15
226
Self Refresh
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
88 Burst Type Control
%DVLF
0RGH
5DQGRP
0RGH
6HTXHQWLDO&RXQWLQJ
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5DQGRPFROXPQ$FFHVV
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(YHU\F\FOH5HDG:ULWH&RPPDQGZLWKUDQGRPFROXPQDGGUHVVFDQUHDOL]H
5DQGRP
&ROXPQ$FFHVV
7KDWLVVLPLODUWR([WHQGHG'DWD2XW('22SHUDWLRQRIFRQYHQWLRQDO'5$0
89 Burst Length Control
%DVLF
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$W056$ $WDXWRSUHFKDUJHW5$6VKRXOGQRWEHYLRODWHG
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0RGH
May 12, 2005 SDRAM_04_A0
$W056$ $W056$ :UDSDURXQGPRGHLQILQLWHEXUVWOHQJWKVKRXOGEHVWRSSHGE\EXUVWVWRS
5$6LQWHUUXSWRU&$6LQWHUUXSW
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&$6,QWHUUXSW
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S73WS256N Based MCPs
227
P r e l i m i n a r y
90 Function Truth Table 1
Current
State
,'/(
5RZ
$FWLYH
5HDG
:ULWH
5HDGZLWK
$XWR
3UHFKDUJH
:ULWHZLWK
$XWR
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228
CS#
RAS#
CAS#
WE#
BA
Address
Action
Note
+
;
;
;
;
;
123
/
+
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;
;
123
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S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
5RZ
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GUHVV$3 $XWR3UHFKDUJH
1RWHV
$OOHQWULHVDVVXPHWKH&.(ZDVDFWLYH+LJKGXULQJWKHSUHFKDUJHFORFNDQGWKHFXUUHQWFORFNF\FOH
,OOHJDOWREDQNLQVSHFLILHGVWDWH)XQFWLRQPD\EHOHJDOLQWKHEDQNLQGLFDWHGE\%$GHSHQGLQJRQ
WKHVWDWHRIWKDWEDQN
0XVWVDWLVI\EXVFRQWHQWLRQEXVWXUQDURXQGDQGRUZULWHUHFRYHU\UHTXLUHPHQWV
123WREDQNSUHFKDUJLQJRULQLGOHVWDWH0D\SUHFKDUJHEDQNLQGLFDWHGE\%$DQG$$3
,OOHJDOLIDQ\EDQNLVQRWLGOH
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
229
P r e l i m i n a r y
91 Function Truth Table 2
Current
State
6HOI
5HIUHVK
$OO
%DQNV
3UHFKDUJH
3RZHU
'RZQ
$OO
%DQNV
,GOH
$Q\6WDWH
RWKHU
WKDQ/LVWHGD
ERYH
CKE
(n-1)
CKE
n
CS#
RAS#
CAS#
WE#
Address
Action
Note
+
;
;
;
;
;
;
([LW6HOI5HIUHVK!,GOHDIWHU
/
+
+
;
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;
;
([LW6HOI5HIUHVK!,GOHDIWHUWV5);
/
+
/
+
+
+
;
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/
+
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+
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;
,//(*$/
/
+
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;
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/
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5RZ%DQN$FWLYH
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/HJHQG$%, $OO%DQNV,GOH5$ 5RZ$GGUHVV
1RWHV
&.(ORZWRKLJKWUDQVLWLRQLVDV\QFKURQRXV
&.(ORZWRKLJKWUDQVLWLRQLVDV\QFKURQRXVLIUHVWDUWVLQWHUQDOFORFN$PLQLPXPVHWXSWLPH&/.
W66PXVWEHVDWLVILHGEHIRUHDQ\FRPPDQGRWKHUWKDQH[LW
3RZHUGRZQDQGVHOIUHIUHVKFDQEHHQWHUHGRQO\IURPWKHDOOEDQNVLGOHVWDWH
0XVWEHDOHJDOFRPPDQG
230
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
92 Timing Diagrams
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CLOCK
CKE
Hi
CS#
RAS#
CAS#
ADDR
Key
Key
RAa
BA0
BA1
A10/AP
RAa
Hi-Z
DQ
Hi-Z
WE#
DQM
High level is necessar y
tRP
Precharge
(All Bank)
tARFC
Auto
Refresh
tARFC
Auto
Refresh
Normal
MRS
Extended
MRS
Row Active
(A-Bank)
: Don’t care
1RWHV
$SSO\SRZHUDQGDWWHPSWWRPDLQWDLQ&.(DWDKLJKVWDWHDQGDOORWKHULQSXWVPD\EHXQGHILQHG
$SSO\9''EHIRUHRUDWWKHVDPHWLPHDV9''4
0DLQWDLQVWDEOHSRZHUVWDEOHFORFNDQG123LQSXWFRQGLWLRQIRUDPLQLPXPRI—V
,VVXHSUHFKDUJHFRPPDQGVIRUDOOEDQNVRIWKHGHYLFHV
,VVXHRUPRUHDXWRUHIUHVKFRPPDQGV
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,VVXHDH[WHQGHGPRGHUHJLVWHUVHWFRPPDQGWRGHILQH'6RU3$65RSHUDWLQJW\SHRIWKHGHYLFH
DIWHUQRUPDO056
(056F\FOHLVQRWPDQGDWRU\DQGWKH(056FRPPDQGQHHGVWREHLVVXHGRQO\ZKHQ
'6RU3$65LVXVHG
7KHGHIDXOWVWDWHZLWKRXW(056FRPPDQGLVVXHGLVKDOIGULYHUVWUHQJWKDQGIXOODUUD\
UHIUHVKHG
7KHGHYLFHLVQRZUHDG\IRUWKHRSHUDWLRQVHOHFWHGE\(056
)RURSHUDWLQJZLWK'6RU3$65VHW'6RU3$65PRGHLQ(056VHWWLQJVWDJH
,QRUGHUWRDGMXVWDQRWKHUPRGHLQWKHVWDWHRI'6RU3$65PRGHDGGLWLRQDO(056
VHWLVUHTXLUHGEXWSRZHUXSVHTXHQFHLVQRWQHHGHGDJDLQDWWKLVWLPH,QWKDWFDVH
DOOEDQNVKDYHWREHLQLGOHVWDWHSULRUWRDGMXVWLQJ(056VHW
Figure 92.1
May 12, 2005 SDRAM_04_A0
Power Up Sequence
S73WS256N Based MCPs
231
P r e l i m i n a r y
0
1
2
tCH
4
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCC
tCL
CKE
HIGH
tRAS
tRC
tRP
tSH
*Note 1
CS#
tRCD
tSS
tSH
RAS#
tSS
tSH
CAS#
tSH
ADDR
Ra
tSS
Ca
Cb
Cc
*Note 2,3
*Note 2,3
Rb
tSS
*Note 2
BA0,BA1
BS
A10/AP
Ra
BS
*Note 2,3 *Note 4
BS
*Note 3
BS
*Note 3
*Note 2
BS
*Note 3
BS
*Note 4
Rb
tSAC
Qa
DQ
tSLZ
tOH
tSH
Db
Qc
tSS
tSS tSH
WE#
tSS tSH
DQM
Row Active
Read
Write
Read
Row Active
Precharge
: Don’t care
1RWHV
$OOLQSXWH[FHSW&.('40FDQEHGRQ
WFDUHZKHQ&6LVKLJKDWWKH&/.KLJKJRLQJHGJH
%DQNDFWLYHUHDGZULWHDUHFRQWUROOHGE\%$%$
Figure 92.2 Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst
Length=1
232
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
tRC
*Note 1
CS#
RAS#
*Note 2
CAS#
ADDR
Ra
Rb
Ca
Cb
BA0
BA1
A10/AP
Rb
Ra
tOH
CL=2
Qa0
tRCD
DQ
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
tOH
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
1RWHV
0LQLPXPURZF\FOHWLPHVLVUHTXLUHGWRFRPSOHWHLQWHUQDO'5$0RSHUDWLRQ
5RZSUHFKDUJHFDQLQWHUUXSWEXUVWRQDQ\F\FOH>&$6/DWHQF\@QXPEHURIYDOLGRXWSXWGDWDLV
DYDLODEOHDIWHU5RZSUHFKDUJH/DVWYDOLGRXWSXWZLOOEH+L=W6+=DIWHUWKHFORFN
2XWSXWZLOOEH+L=DIWHUWKHHQGRIEXUVW)XOOSDJHELWEXUVW
Figure 92.3
May 12, 2005 SDRAM_04_A0
Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
S73WS256N Based MCPs
233
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
tRC *Note 1
CS#
RAS#
*Note 2
CAS#
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Rb
Ra
tOH
CL=2
Qa0
tRCD
DQ
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
tOH
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
tSHZ
tSAC
Db1
Db2
Db3
tRDL
*Note 4
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
1RWHV
7RZULWHGDWDEHIRUHEXUVWUHDGHQGV'40VKRXOGEHDVVHUWHGWKUHHF\FOHSULRUWRZULWHFRPPDQG
WRDYRLGEXVFRQWHQWLRQ
5RZSUHFKDUJHZLOOLQWHUUXSWZULWLQJ/DVWGDWDLQSXWW5'/EHIRUH5RZSUHFKDUJHZLOOEHZULWWHQ
'40VKRXOGPDVNLQYDOLGLQSXWGDWDRQSUHFKDUJHFRPPDQGF\FOHZKHQDVVHUWLQJSUHFKDUJHEHIRUH
HQGRIEXUVW,QSXWGDWDDIWHU5RZSUHFKDUJHF\FOHZLOOEHPDVNHGLQWHUQDOO\
W'$/ODVWGDWDLQWRDFWLYHGHOD\LV&/.W53
Figure 92.4 Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
234
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
CS#
RAS#
*Note 2
CAS#
ADDR
RAa
RBb
RAa
RBb
CAa
RCc
CBb
RDd
CCc
CDd
BA0
BA1
A10/AP
RCc
CL=2
RDd
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQ
CL=3
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Row Active
(D-Bank)
Precharge
(A-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Precharge
(C-Bank)
Precharge
(B-Bank)
: Don’t care
1RWHV
&6FDQEHGRQ
WFDUHGZKHQ5$6&$6DQG:(DUHKLJKDWWKHFORFNKLJKJRLQJHGJH
7RLQWHUUXSWDEXUVWUHDGE\URZSUHFKDUJHERWKWKHUHDGDQGWKHSUHFKDUJHEDQNVPXVWEHWKH
VDPH
Figure 92.5
May 12, 2005 SDRAM_04_A0
Page Read Cycle at Different Bank @Burst Length=4
S73WS256N Based MCPs
235
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
*Note 2
CAS#
ADDR
RAa
RAb
RAa
RBb
CAa
CBb
RCc
RDd
RCc
RDd
CCc
CDd
BA0
BA1
A10/AP
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
DQ
tCDL
tRDL
WE#
*Note 1
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Row Active
(C-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Precharge
(All Banks)
Write
(C-Bank)
: Don’t care
1RWHV
7RLQWHUUXSWEXUVWZULWHE\5RZSUHFKDUJH'40VKRXOGEHDVVHUWHGWRPDVNLQYDOLGLQSXWGDWD
7RLQWHUUXSWEXUVWZULWHE\5RZSUHFKDUJHERWKWKHZULWHDQGWKHSUHFKDUJHEDQNVPXVWEHWKH
VDPH
Figure 92.6
236
Page Write Cycle at Different Bank @Burst Length=4, tRDL=2CLK
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
RAa
CAa
RDb
CDb
RBc
CBc
BA0
BA1
A10/AP
RAa
RDb
RBc
tCDL
CL=2
DQ
QAa0 QAa1 QAa2 QAa3
{
CL=3
QAa0 QAa1 QAa2 QAa3
*Note 1
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Read
(B-Bank)
Row Active
(B-Bank)
: Don’t care
1RWHV
W&'/VKRXOGEHPHWWRFRPSOHWHZULWH
Figure 92.7 Read & Write Cycle at Different Bank @Burst Length=4
May 12, 2005 SDRAM_04_A0
S73WS256N Based MCPs
237
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
RAa
RBb
RAa
RBb
CAa
CBb
RAc
CAc
BA0
BA1
A10/AP
RAc
DAc0 DAc1
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DQ CL=2
CL=3
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DAc0 DAc1
WE#
DQM
Row Active
(A-Bank)
Read with
Auto Pre
charge
(A-Bank)
Row Active
(B-Bank)
Read without Auto
Precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank) *Note1
Precharge
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(A-Bank)
: Don’t care
1RWHV
:KHQ5HDG:ULWHFRPPDQGZLWKDXWRSUHFKDUJHLVLVVXHGDW$%DQNDIWHU$DQG%%DQNDFWLYDWLRQ
,I5HDG:ULWHFRPPDQGZLWKRXWDXWRSUHFKDUJHLVLVVXHGDW%%DQNEHIRUH$%DQNDXWRSUHFKDUJH
VWDUWV$%DQNDXWRSUHFKDUJHZLOOVWDUWDW%%DQNUHDGFRPPDQGLQSXWSRLQW
$Q\FRPPDQGFDQQRWEHLVVXHGDW$%DQNGXULQJW53DIWHU$%DQNDXWRSUHFKDUJHVWDUWV
Figure 92.8
238
Read & Write Cycle with Auto Precharge I @Burst Length=4
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Qb0
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
Ra
Ca
Rb
Cb
BA0
BA1
A10/AP
Ra
Rb
DQ CL=2
Qa0
CL=3
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
Qb3
WE#
DQM
*Note1
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don’t care
1RWHV
$Q\FRPPDQGWR$EDQNLVQRWDOORZHGLQWKLVSHULRGW53LVGHWHUPLQHGIURPDWDXWRSUHFKDUJHVWDUW
SRLQW
Figure 92.9
May 12, 2005 SDRAM_04_A0
Read & Write Cycle with Auto Precharge 2 @Burst Length=4
S73WS256N Based MCPs
239
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS#
RAS#
CAS#
ADDR
Ra
Ca
Cb
Cc
BA0
BA1
A10/AP
Ra
Qa0
DQ
Qa1
Qa2
Qb0
Qa3
tSHZ
Qb1
Dc0
Dc2
tSHZ
WE#
*Note 1
DQM
Row Active
Read
Clock
Suspension
Read
Read DQM
Write
DQM
Write
Write
DQM
Clock
Suspension
: Don’t care
1RWHV
'40LVQHHGHGWRSUHYHQWEXVFRQWHQWLRQ
Figure 92.10
240
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
{
CL=2
DQ
CL=3
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE#
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don’t care
1RWHV
$WIXOOSDJHPRGHEXUVWLVILQLVKHGE\EXUVWVWRSRUSUHFKDUJH
$ERXWWKHYDOLG'4VDIWHUEXUVWVWRSLWLVVDPHDVWKHFDVHRI5$6LQWHUUXSW
%RWKFDVHVDUHLOOXVWUDWHGDERYHWLPLQJGLDJUDP6HHWKHODEHORQWKHP
%XWDWEXUVWZULWH%XUVWVWRSDQG5$6LQWHUUXSWVKRXOGEHFRPSDUHGFDUHIXOO\
%XUVWVWRSLVYDOLGDWHYHU\EXUVWOHQJWK
Figure 92.11
May 12, 2005 SDRAM_04_A0
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Full Page
Burst
S73WS256N Based MCPs
241
P r e l i m i n a r y
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA0
BA1
A10/AP
RAa
*Note 1
tBDL
DAa0 DAa1 DAa2 DAa3 DAa4
DQ
*Note 1,2
tRDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don’t care
1RWHV
$WIXOOSDJHPRGHEXUVWLVILQLVKHGE\EXUVWVWRSRUSUHFKDUJH
'DWDLQDWWKHF\FOHRILQWHUUXSWHGE\SUHFKDUJHFDQQRWEHZULWWHQLQWRWKHFRUUHVSRQGLQJPHPRU\
FHOO,WLVGHILQHGE\$&SDUDPHWHURIW5'/'40DWZULWHLQWHUUXSWHGE\SUHFKDUJHFRPPDQGLV
QHHGHGWRSUHYHQWLQYDOLGZULWH'40VKRXOGPDVNLQYDOLGLQSXWGDWDRQSUHFKDUJHFRPPDQGF\FOH
ZKHQDVVHUWLQJSUHFKDUJHEHIRUHHQGRIEXUVW,QSXWGDWDDIWHU5RZSUHFKDUJHF\FOHZLOOEHPDVNHG
LQWHUQDOO\
%XUVWVWRSLVYDOLGDWHYHU\EXUVWOHQJWK
Figure 92.12 Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Full
Page Burst, tRDL=2CLK
242
S73WS256N Based MCPs
SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
0
1
2
3
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May 12, 2005 SDRAM_04_A0
Burst Read Single bit Write Cycle @Burst Length=2
S73WS256N Based MCPs
243
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SDRAM_04_A0 May 12, 2005
P r e l i m i n a r y
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May 12, 2005 SDRAM_04_A0
Self Refresh Entry & Exit Cycle
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Mode Register Set Cycle
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May 12, 2005 SDRAM_04_A0
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93 SDRAM Type 2 Revision Summary
Revision A (May 12, 2005)
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SDRAM_04_A0 May 12, 2005
A d v a n c e
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Revision A (October 19, 2004)
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Revision A3 (December 16, 2005)
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and
product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
December 16, 2005 S73WS256N_00_A3
S73WS256N Based MCPs
249