SPANSION S72WS256NEGKFW4Y0

S72WS-N Based MCP/PoP Products
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus
256/512 Mb Simultaneous Read/Write, Burst Mode Flash Memory
512 Mb NAND Flash
1024 Mb NAND Interface ORNAND Flash Memory on Bus 1
512/256/128 Mb (8M/4M/2M x 16-bit x 4 Banks) Mobile SDRAM on Bus 2
ADVANCE
INFORMATION
Data Sheet
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. Each product described
herein may be designated as Advance Information, Preliminary, or Full
Production. See “Notice On Data Sheet Designations” for definitions.
Publication Number S72WS-N_00
Revision A
Amendment 8
Issue Date June 1, 2006
A d v a n c e
I n f o r m a t i o n
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to
highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Spansion LLC. The
information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product
life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon
Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with the DC Characteristics table and the AC Erase and Program table (in the
table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or VIO range. Changes
may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local AMD or Fujitsu
sales office.
ii
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
S72WS-N based MCP/PoP Products
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus
256/512 Mb Simultaneous Read/Write, Burst Mode Flash Memory
512 Mb NAND Flash
1024 Mb NAND Interface ORNAND Flash Memory on Bus 1
512/256/128 Mb (8M/4M/2M x 16-bit x 4 Banks) Mobile SDRAM on Bus 2
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
MCP Features
„ Power supply voltage of 1.7 to 1.95V
High Performance
„ Flash access time: 80 ns for NOR Flash, 25 ns for ORNAND Flash
„ Flash burst frequencies: 54 MHz, 66MHz, 80MHz
„ Mobile SDRAM burst frequency: 104 MHz, 133 MHz (DDR)
„ Package:
— 9.0 x 12.0 mm MCP BGA
— 11.0 x 13.0 mm MCP BGA
— 15.0 x 15.0 x 1.2 mm MCP Package-on-Package (PoP)
„ Operating Temperature
— –25°C to +85°C (wireless)
General Description
The S72WS series is a product line of stacked Multi-Chip Product (MCP) packages and consists of:
„ One or two NOR flash memory dies
„ One NAND Interface ORNAND die
„ Separate bus for one or more Mobile SDRAM die
The products covered by this document are listed in the table below.
NOR Flash Density
Device
512Mb
256Mb
S72WS256ND0
128Mb
NAND Flash Density
1024Mb
512Mb
SDRAM Density
512Mb
256Mb
X
S72WS256NDE
X
S72WS256NEE
X
128Mb
X
X
X
S72WS512NFG
X
X
S72WS512NEG
X
X
X
S72WS512NEF
X
X
S72WS512NFF
X
X
X
X
X
Note: For a list of PoP OPNs, please contact the local sales representative or refer to the Ordering Information valid combinations tables.
For detailed specifications, please refer to the individual data sheets.
Document
Publication Identification Number (PID)
S29WS256N
S29WS-N_00
S30MS01GP/512P
S30MS-P_00
128 Mb Mobile SDRAM Type 1
SDRAM_01
128 Mb Mobile SDRAM Type 2
SDRAM_05
128 Mb Mobile DDR-DRAM Type 5
SDRAM_07
256 Mb Mobile SDRAM Type 2
SDRAM_05
512 Mb Mobile DDR-DRAM Type 1
SDRAM_09
512 Mb Mobile SDRAM Type 4
SDRAM_06
512 Mb NAND Type 1
NAND_01
512 Mb Mobile DDR-DRAM Type 5
DRAM_04
512 Mb Mobile DDR-DRAM Type 2
DRAM_05
Publication Number S72WS-N_00
Revision A
Amendment 8
Issue Date June 1, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice
A d v a n c e
I n f o r m a t i o n
Table of Contents
S72WS-N Based MCP/PoP Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
1
2
3
4
5
6
2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 NOR Flash + DRAM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 NOR Flash + ORNAND Flash + DRAM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 NOR Flash + ORNAND Flash + DRAM Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 2 x 256Mb NOR Flash with 256Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 2 x 256Mb NOR Flash with 128Mb SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 256Mb NOR Flash with 128Mb SDR/DDR-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 512 Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256-Mb SDRAM on Bus 2 . . . . . . . . . . . . . . . 9
3.4.1 x16 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 512Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256 Mb SDRAM on Bus 2 . . . . . . . . . . . . . . . .10
3.5.1 x8 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 512Mb NOR Flash with 512-Mb NAND on Bus 1 and 512-Mb SDRAM on Bus 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6.1 x16 ORNAND-based MCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6.2 Connection Diagram for 15 x 15 Package-on-Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Lookahead Diagram on Split Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8 NOR Flash and DRAM Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.8.1 ORNAND Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 FEA137—137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 FVD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 11 x 13 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4 BWA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5 BWB160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6 BTA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.7 ALH160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MCP Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
1
1.1
I n f o r m a t i o n
Product Selector Guide
NOR Flash + DRAM Products
Device-Model#
S72WS256ND0BAWB7
S72WS256ND0BAWBB
Flash
Density
(Code)
Flash
Density
(Data)
Burst
Speed
(MHz)
SDRAM
Density
SDRAM burst
Speed (MHz)
256 Mb
—
54 MHz
128
104 MHz
S72WS256NDEBAWU7
S72WS256NDEBAWUB
S72WS256NEEBAWU7
256 Mb
54 MHz
S72WS256ND0BFWB7
S72WS256ND0BFWBB
256 Mb
—
54 MHz
S72WS256NDEBFWU7
S72WS256NDEBFWUB
S72WS256NEEBFWU7
104 MHz
256
S72WS256NEEBAWUB
128
256 Mb
54 MHz
256 Mb
June 1, 2006 S72WS-N_00_A8
66 MHz
128
sector
unprotected
9x12x1.2
2
1
sector
unprotected
9x12x1.4
1
2
sector
unprotected
9x12x1.2
sector
unprotected
9x12x1.4
sector
unprotected
15x15x1.25
sector
unprotected
9x12x1.2
1
104 MHz
S72WS256ND0KFWD3
S72WS256ND0BFW93
104 MHz
256
S72WS256NEEBFWUB
Package
2
128
256 Mb
1
2
DYB
1
128
256 Mb
DRAM
Supplier
2
1
2
133 MHz
(DDR)
133 MHz
(DDR)
S72WS-N Based MCP/PoP Products
5
3
A d v a n c e
1.2
I n f o r m a t i o n
NOR Flash + ORNAND Flash + DRAM Products
Device-Model#
NOR ORNAND
SDRAM
Flash
Flash
Density
Density
Density
Flash
Speed
DRAM
Speed
512Mb
(NAND)
66MHz
133MHz
(DDR)
S72WS512NFFBFWZ2
S72WS512NFFBFWZJ
S72WS512NFG-L7
54MHz
S72WS512NFG-L6
66MHz
S72WS512NFG-L5
80MHz
S72WS512NFG-47
54MHz
S72WS512NFG-46
66MHz
S72WS512NFG-45
80MHz
S72WS512NFG-LZ
54MHz
S72WS512NFG-LY
66MHz
S72WS512NFG-LW
80MHz
S72WS512NFG-4Z
80MHz
S72WS512NFG-N7
54MHz
S72WS512NFG-N6
66MHz
S72WS512NFG-N5
80MHz
S72WS512NFG-67
S72WS512NFG-66
S72WS512NFG-65
80MHz
54MHz
S72WS512NFG-NY
66MHz
S72WS512NFG-NW
80MHz
S72WS512NFG-6Z
54MHz
S72WS512NFG-6Y
66MHz
S72WS512NFG-6W
80MHz
S72WS512NEG-LZ
54MHz
S72WS512NEG-LY
66MHz
S72WS512NEG-LW
80MHz
S72WS512NEG-4Z
54MHz
S72WS512NEG-4Y
66MHz
S72WS512NEG-4W
80MHz
256 Mb
S72WS512NEG-NZ
66MHz
S72WS512NEG-NW
80MHz
S72WS512NEG-6Z
54MHz
S72WS512NEG-6Y
66MHz
S72WS512NEG-6W
80MHz
S72WS512NFFKFWZ2
512Mb
(NAND)
X16
X8
X16
DRAM
Type 4
X8
Yes
104MHz
11x13x1.4mm
X16
X8
X16
DRAM
Type 2
No
X8
X16
Yes
X8
133MHz
(DDR)
S72WS512NFFKFWZJ
4
X16
DRAM
Type2
66MHz
512Mb
11x13x1.4mm
DRAM
Type 2
256Mb
512Mb
Yes
54MHz
S72WS512NEG-NY
S72WS512NEFKFWHJ
Package
No
66MHz
1024Mb
S72WS512NFG-NZ
DRAM
Type 5
ECC
required?
X8
54MHz
512Mb
DRAM
Type 1
66MHz
S72WS512NFG-4W
ORNAND
Bus
Width
DRAM
Type 4
54MHz
512Mb
S72WS512NFG-4Y
Supplier
S72WS-N Based MCP/PoP Products
DRAM
Type 1
DRAM
Type 5
15x15x1.25mm
x16
Yes
15x15x1.25mm
15x15x1.25mm
S72WS-N_00_A8 June 1, 2006
A d v a n c e
2
2.1
I n f o r m a t i o n
MCP Block Diagram
NOR Flash + ORNAND Flash + DRAM Products
F-AVD#
AVD#
F-CLK
CLK
F-ACC
ACC
F-WP#
WP#
F-RESET#
RESET#
F1-CE#
CE#
F-WE#
WE#
F-OE#
OE#
F-A23:A0
F-VCCQ
F2-CE#
F-Vcc
RDY
WS256N
RDY
DQ8:15
DQ8:15
DQ0:7
DQ0:7
A23-A0
Vss
CE#
N-Vcc
N-WP#
WP#
N-CE#
CE#
N-WE#
WE#
N-RE#
RE#
N-ALE
ALE
N-CLE
CLE
N-PRE
PRE
MS01GP
IO0:7
RY/BY#
RY/BY#
Vss
D-Vcc
D-A12-A0
D-CE#
D-WE#
D-BA0
D-BA1
D-CKE
D-RAS#
D-CAS#
D-DM0
D-DM1
A12-A0
CE#
WE#
BA0
BA1
CKE
RAS#
CAS#
DM0
DM1
V-Vccq
DQ0:15
D-DQ15-DQ0
SDRAM
D-Vss
D-Vssq
Notes:
1. For a one-Flash configuration, F1-CE# = CE#.
For a two-Flash configuration, F1-CE# = CE for Flash 1 and F2-CE# = CE for Flash 2; F2-CE# is the
chip-enable pin for the second Flash.
2. If ORNAND is not present in the MCP, then the MS01GP block will not be present in the figure above. In
that case, the common signals go only to the WS256N flash, while the SDRAM signals remain unchanged.
3. If ORNAND supports a x16 bus, then NOR DQ0-DQ15 is shared with ORNAND I/O0-I/O15.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
5
A d v a n c e
3
3.1
I n f o r m a t i o n
Connection Diagram
2 x 256Mb NOR Flash with 256Mb SDRAM
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
RFU
RFU
D-VSS
D-VCC
D-A12
D-A11
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-A9
D-A8
D-A7
D-A6
RFU
D-CAS#
D-RAS# D-WE#
D-VSSQ D-VCCQ
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D-A10
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
RFU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D-A0
F-WP#
A7
D-DM0
F-ACC
WE#
A8
A11
F2-CE#
D-A5
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D-VCCQ
A3
A6
D-DM1
F-RST#
RFU
A19
A12
A15
D-VCCQ
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
D-VSSQ
A2
A5
A18
F-RDY
A20
A9
A13
A21
D-VSSQ
G1
G2
G3
G4
G6
G7
G8
G9
G10
D-DQ0
A1
A4
A17
A23
A10
A14
A22
D-DQ15
H1
H2
H3
H4
H7
H8
H9
H10
D-DQ1
A0
VSS
DQ1
DQ6
RFU
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
D-DQ13
D-DQ2 F1-CE#
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
RFU
DQ0
DQ10
F-VCC
RFU
DQ12
DQ7
VSS
D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU
D-DQ10
N5
N6
N1
N2
N3
N4
RFU
D-BA0
D-DQ6
D-DQ7
D-VSSQ D-VCCQ
N7
N8
N9
N10
D-DQ8
D-DQ9
D-BA1
RFU
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
D-VSS
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
RFU
RFU
Legend
Flash 1 only
SDRAM only
Reserved for
Future Use
Flash 2 only
Flash Shared
Note: M8 is RFU for SDR-DRAM and F-VCCQ for DDR-DRAM, as indicated in subsequent connection
diagrams.
6
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
3.2
I n f o r m a t i o n
2 x 256Mb NOR Flash with 128Mb SDRAM
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
RFU
RFU
D-VSS
D-VCC
RFU
D-A11
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-A9
D-A8
D-A7
D-A6
RFU
D-CAS#
D-RAS# D-WE#
D-VSSQ D-VCCQ
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D-A10
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
RFU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D-A0
F-WP#
A7
D-DM0
F-ACC
WE#
A8
A11
F2-CE#
D-A5
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D-VCCQ
A3
A6
D-DM1
F-RST#
RFU
A19
A12
A15
D-VCCQ
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
D-VSSQ
A2
A5
A18
F-RDY
A20
A9
A13
A21
D-VSSQ
G1
G2
G3
G4
G6
G7
G8
G9
G10
D-DQ0
A1
A4
A17
A23
A10
A14
A22
D-DQ15
H1
H2
H3
H4
H7
H8
H9
H10
D-DQ1
A0
VSS
DQ1
DQ6
RFU
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
D-DQ13
D-DQ2 F1-CE#
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
RFU
DQ0
DQ10
F-VCC
RFU
DQ12
DQ7
VSS
D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
RFU
RFU
RFU
D-DQ10
N5
N6
N1
N2
N3
N4
RFU
D-BA0
D-DQ6
D-DQ7
D-VSSQ D-VCCQ
N7
N8
N9
N10
D-DQ8
D-DQ9
D-BA1
RFU
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
D-VSS
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
RFU
RFU
Legend
Flash 1 only
SDRAM only
Reserved for
Future Use
Flash 2 only
Flash Shared
Note: M8 is RFU for SDR-DRAM and F-VCCQ for DDR-DRAM, as indicated in subsequent connection
diagrams.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
7
A d v a n c e
3.3
I n f o r m a t i o n
256Mb NOR Flash with 128Mb SDR/DDR-DRAM
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
D-CLK#
RFU
D-VSS
D-VCC
RFU
D-A11
D-VSS
D-CE#
B1
B2
D-RAS# D-WE#
B3
B4
B5
B6
B7
B8
B9
B10
D-A9
D-A8
D-VSSQ
D-VCCQ
D-A7
D-A6
RFU
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D-A10
AVD#
VSS
CLK
RFU
RFU
RFU
RFU
RFU
RFU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D-A0
F-WP#
A7
D-DM0
F-ACC
WE#
A8
A11
RFU
D-A5
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D-VCCQ
A3
A6
D-DM1
F-RST#
RFU
A19
A12
A15
D-VCCQ
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
D-VSSQ
A2
A5
A18
F-RDY
A20
A9
A13
A21
D-VSSQ
G1
G2
G3
G4
G6
G7
G8
G9
G10
D-DQ0
A1
A4
A17
A23
A10
A14
A22
D-DQ15
H1
H2
H3
H4
H7
H8
H9
H10
D-DQ1
A0
VSS
DQ1
DQ6
RFU
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
D-DQ13
D-DQ2 F1-CE#
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
RFU
DQ0
DQ10
F-VCC
RFU
DQ12
DQ7
VSS
D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
RFU
F-VCCQ
RFU
D-DQ10
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
RFU
D-BA0
D-DQ6
D-DQ7
D-VSSQ
D-VCCQ
D-DQ8
D-DQ9
D-BA1
RFU
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
RFU
D-DQS1
D-DQS0 D-VSS
Legend
Flash 1 only
SDRAM only
Reserved for
Future Use
Flash 2 only
Flash Shared
DDR only
Note: DDR-only signals are RFUs in the case of the SDR-DRAM based MCPs.
8
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
3.4
I n f o r m a t i o n
512 Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256-Mb SDRAM
on Bus 2
3.4.1
x16 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls
A1
A2
D-CKE
D-CLK
A3
A4
A5
A6
A7
A8
A9
A10
RFU
RFU
D-VSS
D-VCC
D-A12
D-A11
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-RAS#
D-WE#
D-A9
D-A8
D-VSSQ
D-VCCQ
D-A7
D-A6
RFU
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D-A10
AVD#
VSS
CLK
F2-CE#
F-VCC
N-PRE
N-ALE
N-CLE
RFU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D-A0
F-WP#
A7
D-DM0
F-ACC
WE#
A8
A11
N-CE#
D-A5
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D-VCCQ
A3
A6
D-DM1
F-RST#
DNU
A19
A12
A15
D-VCCQ
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
D-VSSQ
A2
A5
A18
RDY
A20
A9
A13
A21
D-VSSQ
G1
G2
G3
G4
G6
G7
G8
G9
G10
D-DQ0
A1
A4
A17
A23
A10
A14
A22
D-DQ15
H1
H2
H3
H4
H7
H8
H9
H10
D-DQ1
A0
VSS
DQ1
DQ6
RFU
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D-DQ2
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
DNU
DQ0
DQ10
F-VCC
N-VCC
DQ12
DQ7
VSS
D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
N-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
N-WP#
D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
DNU
F-VCCQ
RFU
D-DQ10
N5
N6
N1
N2
N3
N4
N-WE#
D-BA0
D-DQ6
D-DQ7
P1
P2
P3
P4
P5
RFU
D-VSS
D-A1
D-A2
D-VSS
N7
N8
N9
N10
D-DQ8
D-DQ9
D-BA1
N-RE#
P6
P7
P8
P9
P10
D-VCC
D-A3
D-A4
N-RY/BY#
RFU
D-VSSQ D-VCCQ
Legend
Reserved for
Future Use
Do Not Use
NOR Flash 1
Only
NOR Flash 2
Only
NAND Flash 1
Only
DRAM Only
NOR Flash
Shared
All Flash
Shared
Note: 1.DDR-only signals are RFU in the case of SDR-DRAM based MCPs.
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
9
A d v a n c e
3.5
I n f o r m a t i o n
512Mb NOR Flash with 1024-Mb ORNAND on Bus 1 and 512 or 256 Mb SDRAM
on Bus 2
3.5.1
x8 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
RFU
RFU
D-VSS
D-VCC
D-A12
D-A11
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-RAS#
D-WE#
D-A9
D-A8
D-VSSQ
D-VCCQ
D-A7
D-A6
RFU
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D-A10
AVD#
VSS
CLK
F2-CE#
F-VCC
N-PRE
N-ALE
N-CLE
RFU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D-A0
F-WP#
A7
D-DM0
F-ACC
WE#
A8
A11
N-CE#
D-A5
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D-VCCQ
A3
A6
D-DM1
F-RST#
DNU
A19
A12
A15
D-VCCQ
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
D-VSSQ
A2
A5
A18
RDY
A20
A9
A13
A21
D-VSSQ
G1
G2
G3
G4
G6
G7
G8
G9
G10
D-DQ0
A1
A4
A17
A23
A10
A14
A22
D-DQ15
H1
H2
H3
H4
H7
H8
H9
H10
D-DQ1
A0
VSS
DQ1
DQ6
RFU
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D-DQ2
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
DNU
DQ0
DQ10
F-VCC
N-VCC
DQ12
DQ7
VSS
D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
N-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
N-WP#
D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
DNU
F-VCCQ
RFU
D-DQ10
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N-WE#
D-BA0
D-DQ6
D-DQ7
D-DQ8
D-DQ9
D-BA1
N-RE#
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
RFU
D-VSS
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
DNU
RFU
D-VSSQ D-VCCQ
S72WS-N Based MCP/PoP Products
Legend
Reserved for
Future Use
Do Not Use
NOR Flash 1
Only
NOR Flash 2
Only
NAND Flash 1
Only
DRAM Only
NOR Flash
Shared
All Flash
Shared
S72WS-N_00_A8 June 1, 2006
A d v a n c e
3.6
I n f o r m a t i o n
512Mb NOR Flash with 512-Mb NAND on Bus 1 and 512-Mb SDRAM on Bus 2
3.6.1
x16 ORNAND-based MCP
137-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
June 1, 2006 S72WS-N_00_A8
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
D-CLK#
RFU
D-VSS
D-VCC
D-A12
D-A11
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-RAS#
D-WE#
D-A9
D-A8
D-VSSQ
D-VCCQ
D-A7
D-A6
RFU
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D-A10
AVD#
VSS
CLK
F2-CE#
F-VCC
N-PRE
N-ALE
N-CLE
RFU
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D-A0
F-WP#
A7
D-DM0
F-ACC
WE#
A8
A11
N-CE#
D-A5
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D-VCCQ
A3
A6
D-DM1
F-RST#
DNU
A19
A12
A15
D-VCCQ
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
D-VSSQ
A2
A5
A18
RDY
A20
A9
A13
A21
D-VSSQ
G1
G2
G3
G4
G6
G7
G8
G9
G10
D-DQ0
A1
A4
A17
A23
A10
A14
A22
D-DQ15
H1
H2
H3
H4
H7
H8
H9
H10
D-DQ1
A0
VSS
DQ1
DQ6
RFU
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D-DQ2
F1-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
DNU
DQ0
DQ10
F-VCC
N-VCC
DQ12
DQ7
VSS
D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
N-VCC
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
N-WP#
D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
RFU
RFU
VSS
F-VCC
RFU
DNU
F-VCCQ
RFU
D-DQ10
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N-WE#
D-BA0
D-DQ6
D-DQ7
D-DQ8
D-DQ9
D-BA1
N-RE#
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
D-DQS0
D-VSS
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
D-VSSQ D-VCCQ
S72WS-N Based MCP/PoP Products
Legend
Reserved for
Future Use
Do Not Use
NOR Flash 1
Only
NOR Flash 2
Only
NAND Flash 1
Only
DRAM Only
NOR Flash
Shared
All Flash
Shared
DDR only
N-RY/BY# D-DQS1
11
A d v a n c e
I n f o r m a t i o n
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of time.
3.6.2
Connection Diagram for 15 x 15 Package-on-Package
5
6
7
8
9
SS
F-A3
F-A5
F-A7
F-A9
F-V
CC
F-A2
F-A4
F-A6
F-A8
F-V
10
11
12
13
14
15
N-V
SS
NC
D-V
SS
F-A1
F-V
B
D-V
SS
D-V
DD
F-A0
F-V
C
N-WE#
N-RY/BY#
F-RST#
RFU
D
D-DQ1
D-DQ0
F1-CE#
F2-CE#
E
D-V
SSQ
D-V
DDQ
N1-CE#
RFU
F
D-DQ3
D-DQ2
N-RE# N-WP#
G
D-DQ5
D-DQ4
F-WE#
H
D-V
SSQ
D-V
DDQ
D-WE# F-OE#
J
D-DQ7
D-DQ6
F-A11
F-A13
F-A15
F-A17
F-V
CCQ
N-ALE
F-A10
F-A12
F-A14
F-A16
F-V
18
22
NC
N-CLE
17
21
3
SSQ
16
20
2
A
4
19
1
SSQ
F-A19
F-A21
F-A23
RFU
RFU
CCQ
F-A18
F-A20
F-A22
RFU
N-V
CC
F-V
CCQ
F-V
Legend
SSQ
No Connect
Reserved for
Future Use
Control for
NOR/PS/NAND
F-WP#
B: Data
D-V
D-V
DD
SS
K
D-DM0 D-DQS0
D-A0
D-A1
L
D-DM1 D-DQS1
D-A2
D-A3
M
D-V
SSQ
D-V
DDQ
D-A4
D-A5
N
D-DQ9
D-DQ8
D-A6
D-A7
P
D-V
SS
D-V
DD
R
D-DQ11
D-DQ10
D1-CS#
T
D-DQ13
D-DQ12
D-RAS# D-CAS#
U
D-V
D-V
SSQ
DDQ
V
D-DQ15
W
A: Addr
12
D-BA0 D-BA1
D-A9
D-DQ14
D-A10
D-A11
D-CKE
D-CLK
D-A12
RFU
Y
RFU
D-CLK#
AA
RFU
AB
NC
F-V
SS
D-V
DD
/
PP
N-ACC
CC
F-DQ0/
N-ADQ0
F-V
SSQ
F-DQ1/
N-ADQ1
F-V
F-V
F-V
CCQ
F-DQ10/
N-ADQ10
F-DQ12/
N-ADQ12
F-V
SSQ
F-DQ11/
N-ADQ11
F-DQ13/
N-ADQ13
F-V
CCQ
F-DQ6/
N-ADQ6
RFU
F-CLK
N-V
CC
RFU
F-DQ8/
N-ADQ8
F-V
SSQ
F-DQ7/
N-ADQ7
RFU
RFU
N-V
SS
RFU
F-DQ9/
N-ADQ9
F-V
CCQ
F-DQ2/
N-ADQ2
F-DQ4/
N-ADQ4
F-V
SSQ
F-DQ3/
N-ADQ3
F-DQ5/
N-ADQ5
F-V
S72WS-N Based MCP/PoP Products
CCQ
F-DQ14/
N-ADQ14
F-ADV#
D-V
SSQ
F-DQ15/
N-ADQ15
F-WAIT
F-V
B: Addr
RFU
D-A8
F-V
A: A/D.
B: Data
D-V
SS
DD
RFU
CCQ
NC
Ground
Power
Control for
DDR, PS
S72WS-N_00_A8 June 1, 2006
A d v a n c e
3.7
I n f o r m a t i o n
Lookahead Diagram on Split Bus
June 1, 2006 S72WS-N_00_A8
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D-CKE
D-CLK
D-CLK#
D-A14
D-VSS
D-VCC
D-A12
D-A11
D-VSS
D-CE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D-RAS#
D-WE#
D-A9
D-A8
D-VSSQ
D-VCCQ
D-A7
D-A6
D-A13
D-CAS#
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D-A10
F-AVD#
VSS
F-CLK
F2-CE#
F-VCC
N-PRE
N-ALE
N-CLE
D-A15
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D-A0
F-WP#
A7
D-DM0
F-ACC
F-WE#
A8
A11
N1-CE#
D-A5
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
D-VCCQ
A3
A6
D-DM1
F-RST#
DNU
A19
A12
A15
D-VCCQ
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
D-VSSQ
A2
A5
A18
F-RDY
A20
A9
A13
A21
D-VSSQ
G1
G2
G3
G4
G6
G7
G8
G9
G10
D-DQ0
A1
A4
A17
A23
A10
A14
A22
D-DQ15
H1
H2
H3
H4
H7
H8
H9
H10
D-DQ1
A0
VSS
DQ1
DQ6
A24
A16
D-DQ14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
D-DQ2
F1-CE#
F-OE#
DQ9
DQ3
DQ4
DQ13
DQ15
DNU
D-DQ13
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
D-DQ3
DNU
DQ0
DQ10
F-VCC
N-VCC
DQ12
DQ7
VSS
D-DQ12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
D-DQ4
N-VCC
DQ8
DQ2
DQ11
A25
DQ5
DQ14
N-WP#
D-DQ11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
D-DQ5
A27
A26
VSS
F-VCC
N2-CE#
DNU
F-VCCQ
D-CLK#
D-DQ10
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N-WE#
D-BA0
D-DQ6
D-DQ7
D-DQ8
D-DQ9
D-BA1
N-RE#
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
D-DQS0
D-VSS
D-A1
D-A2
D-VSS
D-VCC
D-A3
D-A4
D-VSSQ D-VCCQ
S72WS-N Based MCP/PoP Products
Legend
x16 DRAM
NOR Flash
NAND Flash
Flash
Shared
Do Not Use
DDR Only
N-RY/BY# D-DQS1
13
A d v a n c e
3.8
14
I n f o r m a t i o n
NOR Flash and DRAM Input/Output Descriptions
A23-A0
DQ15-DQ0
=
=
F2-CE#
=
F1-CE#
=
OE#
=
F-WE#
F-VCC
F-VCCq
VSS
RFU
RDY
=
=
=
=
=
=
CLK
=
AVD#
=
F-RST#
=
F-WP#
=
F-ACC
=
D-A12-D-A0
D-DQ15-D-DQ0
D-CLK
D-CE#
D-CKE
D-BA1-BA0
D-RAS#
D-CAS#
D-DM1-D-DM0
D-WE#
D-VSS
D-VSSQ
D-VCCQ
D-VCC
=
=
=
=
=
=
=
=
=
=
=
=
=
=
NOR Flash Address inputs
Flash Data input/output, shared between NOR and ORNAND
Flash. DQ0-DQ7 shared for x8 ORNAND
NOR Flash Chip-enable input # 2. Asynchronous relative to CLK
for burst mode.
NOR Flash Chip-enable input #1. Asynchronous relative to CLK
for Burst Mode.
NOR Flash Output Enable input. Asynchronous relative to CLK
for Burst mode.
NOR Flash Write Enable input.
NOR Flash device power supply (1.7 V - 1.95V).
Input/Output Buffer power supply.
Ground
Reserved for Future Use
Flash ready output. Indicates the status of the Burst read. VOL
= data valid. Shared between NOR and ORNAND Flash.
NOR Flash Clock. The first rising edge of CLK in conjunction with
AVD# low latches the address input and activates burst mode
operation. After the initial word is output, subsequent rising
edges of CLK increment the internal address counter. CLK
should remain low during asynchronous access.
NOR Flash Address Valid input. Indicates to device that the valid
address is present on the address inputs.
VIL = for asynchronous mode, indicates valid address; for burst
mode, causes starting address to be latched on rising edge of
CLK.
VIH= device ignores address inputs
NOR Flash hardware reset input. VIL= device resets and returns
to reading array data
NOR Flash hardware write protect input. VIL = disables program
and erase functions in the four outermost sectors.
NOR Flash accelerated input. At VHH, accelerates
programming; automatically places device in unlock bypass
mode. At VIL, disables all program and erase functions. Should
be at VIH for all other conditions.
SDRAM Address inputs
SDRAM Data input/output
SDRAM System Clock
SDRAM Chip Select
SDRAM Clock Enable
SDRAM Bank Select
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Data Input/Output Mask
SDRAM Write Enable input
SDRAM Ground
SDRAM Input/Output Buffer ground
SDRAM Input/Output Buffer power supply
SDRAM device power supply
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
3.8.1
I n f o r m a t i o n
ORNAND Signal Descriptions
N-PRE
=
N-ALE
N-CLE
N-CE#
N-WP#
N-WE#
N-RE#
N-RY/BY#
N-I/O0-N-I/O15
N-VCC
=
=
=
=
=
=
=
=
=
June 1, 2006 S72WS-N_00_A8
ORNAND Power-On Read Enable. Tie to VSS on
customer board if not used
ORNAND Address Latch Enable
ORNAND Command Latch Enable
ORNAND Chip-enablE
ORNAND Write-protect
ORNAND Write-enable
ORNAND Read-enable
ORNAND Ready-Busy—this is shared with NOR RDY
ORNAND I/O Signals (I/O0-I/O7 for x8 bus width)
ORNAND Power Supply
S72WS-N Based MCP/PoP Products
15
A d v a n c e
4
I n f o r m a t i o n
Ordering Information
The order number is formed by a valid combinations of the following:
S72WS
512
N
EG
BA
W
4
Y
0
PACKING TYPE
0
= Tray
2
= 7” Tape and Reel
3
= 13” Tape and Reel
MODEL NUMBER
Refer to the Valid Combinations Tables
PACKAGE MODIFIER
Refer to the Valid Combinations Tables
TEMPERATURE RANGE
W
= Wireless (-25°C to +85°C)
PACKAGE TYPE
BA
= Very-thin Fine-pitch BGA Lead (Pb)-free compliant package
BF
= Very-thin Fine-pitch BGA Lead (Pb)-free package
KF
= Fine-pitch Package-on-Package (PoP) Lead (Pb)-free
SDRAM
EE
=
DE
=
D0
=
FG
=
EG
=
EF
=
FF
=
& DATA FLASH DENSITY
256 Mb SDRAM, 256 Mb Data Flash
128 Mb SDRAM, 256 Mb Data Flash
128 Mb SDRAM, No Data Flash
512 Mb SDRAM, 1024 Mb ORNAND Flash
256 Mb SDRAM, 1024 Mb ORNAND Flash
256Mb SDRAM, 512Mb NAND Flash
512Mb SDRAM, 512Mb NAND Flash
PROCESS TECHNOLOGY
N
= 110 nm, MirrorBitTM Technology
CODE FLASH DENSITY
256 = 256Mb
512 = 512Mb
PRODUCT FAMILY
S72WS Multi-chip Product (MCP)
1.8-volt Simultaneous Read/Write, Burst Mode Flash Memory and Mobile
SDRAM on Split Bus
16
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
I n f o r m a t i o n
S72WS256ND0 Valid Combinations
Base Ordering
Part Number
Package &
Temperature
BFW
S72WS256ND0
BAW, BFW
KFW
NOR Flash
Burst Speed
SDRAM Supplier
SDRAM
Burst
Speed
93
66 MHz
Supplier 5
133 MHz
B7
54 MHz
Supplier 1
Model
Number
BB
Packing
Type
0, 2, 3
(Note 1)
D3
66 MHz
S72WS256NDE Valid Combinations
Base Ordering
Part Number
Package &
Temperature
S72WS256NDE
BAW, BFW
Model
Number
Packing
Type
U7
0, 2, 3
(Note 1)
UB
S72WS256NEE Valid Combinations
Base Ordering
Part Number
Package &
Temperature
S72WS256NEE
BAW, BFW
Model
Number
Packing
Type
U7
0, 2, 3
(Note 1)
UB
S72WS512NFF Valid Combinations
Base Ordering
Part Number
Package &
Temperature
Model
Number
Supplier 2
Packing
Type
NOR Flash
Burst Speed
54 MHz
Flash
Burst Speed
54 MHz
Flash
Speed
Supplier 5
SDRAM Supplier
Supplier 1
Supplier 2
SDRAM Supplier
Supplier 1
Supplier 2
DRAM Supplier
104 MHz
133 MHz
S72WS512NFF
Z2
KFW
66 MHz
DRAM Type 5
BAW, BFW
ZT
DRAM Type 2
KFW
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
(Note 2)l
15x15x1.25mm
160-ball
Package
Marking
104 MHz
9x12x1.4mm
137-ball
(Note 2)
SDRAM
Burst
Speed
Package Type
Package
Marking
104 MHz
9x12x1.4mm
137-ball
(Note 2)
DRAM
Speed
Package
Package
Marking
11 x 13 mm
137-ball
DRAM Type 1
0, 2, 3
(Note 1)
9x12x1.2mm
137-ball
Package Type
15 x 15 5mm
160-ball
KFW
BAW, BFW
Package
Marking
SDRAM
Burst
Speed
BAW, BFW
ZJ
Package Type
133 MHz
11 x 13 mm
137-ball
15 x 15 5mm
160-ball
(Note 2)
11 x 13 mm
137-ball
15 x 15 5mm
160-ball
17
A d v a n c e
S72WS512NFG Valid Combinations
Base Ordering
Part Number
Package &
Temperature
Model
Number
Packing
Type
Flash
Burst Speed
I n f o r m a t i o n
SDRAM Supplier
SDRAM
Burst
Speed
Package Type
Package
Marking
104 MHz
11x13x1.4mm
137-ball
(Note 2)
L7
L6
L5
DRAM Type 4
47
46
45
LZ
LY
LW
DRAM Type 2
4Z
4Y
S72WS512NFG
BAW, BFW
4W
N7
0, 2, 3
(Note 1)
54 MHz
N6
N5
DRAM Type 4
67
66
65
NZ
NY
NW
DRAM Type 2
6Z
6Y
6W
S72WS512NEG Valid Combinations
Base Ordering
Part Number
Package &
Temperature
Model
Number
Packing
Type
Flash
Burst Speed
SDRAM Supplier
SDRAM
Burst
Speed
Package Type
Package
Marking
54 MHz
DRAM Type 2
104 MHz
11x13.1x1.4mm
137-ball
(Note 2)
LZ
LY
LW
4Z
4Y
S72WS512NEG
BAW, BFW
4W
NZ
0, 2, 3
(Note 1)
NY
NW
6Z
6Y
6W
18
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
I n f o r m a t i o n
S72WS512NEF Valid Combinations
Base Ordering
Part Number
Package &
Temperature
Model
Number
Packing
Type
S72WS512NEF
KFW
HJ
0, 2, 3
(Note 1)
Notes:
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S” and packing type
designator from ordering part number.
June 1, 2006 S72WS-N_00_A8
Flash
Burst Speed
SDRAM Supplier
SDRAM
Burst
Speed
Package Type
Package
Marking
66 MHz
DRAM Type 2
133 MHz
15x15x1.2 mm
160-ball
(Note 2)
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
S72WS-N Based MCP/PoP Products
19
A d v a n c e
5
5.1
I n f o r m a t i o n
Physical Dimensions
TLD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package
D1
A
D
eD
0.15 C
(2X)
10
9
SE 7
8
7
6
E
E1
5
4
eE
3
2
1
P N M L K J
INDEX MARK
PIN A1
CORNER
B
10
TOP VIEW
H G F
E D C
B A
PIN A1
CORNER
7
SD
0.15 C
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
137X
0.08 C
SIDE VIEW
6
b
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
TLD 137
JEDEC
N/A
DxE
12.00 mm x 9.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.17
---
---
A2
0.81
---
0.97
NOTE
PROFILE
BODY SIZE
E
9.00 BSC.
BODY SIZE
D1
10.40 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
14
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
137
0.35
0.40
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
12.00 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BALL HEIGHT
D
φb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
G5,H5,H6
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3393\ 16-038.22a
20
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
5.2
I n f o r m a t i o n
FEA137—137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package
0.15
D1
A
D
eD
C
(2X)
10
9
SE
8
7
7
6
E
E1
5
4
eE
3
2
1
P N M L K J
INDEX MARK
PIN A1
CORNER
B
9
TOP VIEW
H G F
E D C
B A
7
SD
C
0.15
Pin A1
Corner
(2X)
A A2
A1
137X
0.15
0.08
C
SIDE VIEW
6
0.20
C
0.08
C
BOTTOM VIEW
b
M C A B
M C
NOTES:
PACKAGE
FEA 137
N/A
JEDEC
DXE
SYMBOL
A
A1
A2
D
E
D1
MIN.
MAX.
-
-
1.40
0.10
-
-
-
1.26
1.11
b
SD/SE
June 1, 2006 S72WS-N_00_A8
BALL HEIGHT
BODY SIZE
BODY SIZE
10.40 BSC
MATRIX FOOTPRINT
7.20 BSC
MATRIX FOOTPRINT
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
1.37
0.45
BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
4.
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
10
0.40
ALL DIMENSIONS ARE IN MILLIMETERS.
BODY THICKNESS
9.00 BSC
0.80 BSC
2.
SPP-010.
PROFILE
12.00 BSC
14
0.35
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
3.
NOM.
MD
ME
n
eE
eD
NOTE
12.00mm X 9.00mm PACKAGE
1.
BALL DIAMETER
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL PITCH
0.80 BSC
BALL PITCH
0.40 BSC
SOLDER BALL PLACEMENT
G5, H5, H8
DEPOPULATED SOLDER BALLS
S72WS-N Based MCP/PoP Products
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
21
A d v a n c e
5.3
I n f o r m a t i o n
FVD137—137-ball Fine-Pitch Ball Grid Array (FBGA) 11 x 13 mm Package
A
D
D1
eD
0.15 C
(2X)
10
9
8
7
6
E
eE
SE
7
E1
5
4
3
2
1
P
PIN A1
CORNER
9
B
INDEX MARK
L K
J
H G F
E
D C B
A
PIN A1
CORNER
7
SD
0.15 C
TOP VIEW
N M
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
137X
C
SIDE VIEW
6
0.08 C
b
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
FVD 137
JEDEC
N/A
DxE
13.00 mm x 11.00 mm
PACKAGE
SYMBOL
NOTE
MIN
NOM
MAX
A
---
---
1.40
A1
0.10
---
---
A2
1.09
---
1.24
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BODY THICKNESS
E
11.00 BSC.
BODY SIZE
10.40 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MD
14
MATRIX SIZE D DIRECTION
MATRIX FOOTPRINT
ME
10
MATRIX SIZE E DIRECTION
137
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
5.
D1
0.40
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
4.
BODY SIZE
0.35
2.
PROFILE
13.00 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BALL HEIGHT
D
Øb
1.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD SE
0.40 BSC.
SOLDER BALL PLACEMENT
G5,H5,H6
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3522 \ 16-038.21 \ 09.29.05
22
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
5.4
I n f o r m a t i o n
BWA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
A
D
PIN A1
CORNER
D1
9
INDEX MARK
PIN A1
CORNER
eD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
E
eE
0.10 C
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
(2X)
B
TOP VIEW
SD
2
SE 7
E1
1
7
0.10 C
BOTTOM VIEW
(2X)
0.20 C
A A2
A1
C
0.10 C
SIDE VIEW
6
b
160X
0.15
0.08
M C A B
M C
NOTES:
PACKAGE
BWA 160
JEDEC
N/A
DxE
15.00 mm x 15.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.25
A1
0.35
---
---
A2
0.74
---
0.84
NOTE
PROFILE
BODY SIZE
E
15.00 BSC.
BODY SIZE
D1
13.65 BSC.
MATRIX FOOTPRINT
E1
13.65 BSC.
MATRIX FOOTPRINT
MD
22
MATRIX SIZE D DIRECTION
ME
22
MATRIX SIZE E DIRECTION
n
160
BALL COUNT
N
160
MAXIMUM NUMBER OF BALLS
eE
2
0.40
0.45
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
15.00 BSC.
R
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BALL HEIGHT
D
Øb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
NUMBER OF LAND PARAMETERS
0.50
0.65 BSC.
BALL DIAMETER
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
BALL PITCH
eD
0.65 BSC.
BALL PITCH
SD SE
0.325 BSC.
SOLDER BALL PLACEMENT
C3~C20,D3~D20,E3~E20,F3~F20
G3~G20,H3~H20,J3~J20,K3~K20
L3~L20,M3~M20,N3~N20,P3~P20
R3~R20,T3~T20,U3~U20,V3~V20
W3~W20,Y3~Y20
DEPOPULATED SOLDER BALLS
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3518 \ 16-038.46 \ 02.23.06
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
23
A d v a n c e
5.5
I n f o r m a t i o n
BWB160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
A
D
PIN A1
CORNER
D1
9
INDEX MARK
PIN A1
CORNER
eD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
E
eE
0.10 C
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
(2X)
B
TOP VIEW
SD
2
E1
1
7
0.10 C
BOTTOM VIEW
(2X)
A
3
SE 7
0.20 C
A2
A1
C
0.10 C
SIDE VIEW
6
b
160X
0.15
0.08
M C A B
M C
NOTES:
PACKAGE
BWB 160
JEDEC
N/A
DxE
15.00 mm x 15.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.30
A1
0.40
---
---
A2
0.74
---
0.84
NOTE
PROFILE
BODY SIZE
E
15.00 BSC.
BODY SIZE
D1
13.65 BSC.
MATRIX FOOTPRINT
E1
13.65 BSC.
MATRIX FOOTPRINT
MD
22
MATRIX SIZE D DIRECTION
ME
22
MATRIX SIZE E DIRECTION
n
160
BALL COUNT
N
160
MAXIMUM NUMBER OF BALLS
eE
2
0.45
0.50
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
15.00 BSC.
R
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
BALL HEIGHT
D
Øb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
NUMBER OF LAND PARAMETERS
0.55
BALL DIAMETER
0.65 BSC.
BALL PITCH
eD
0.65 BSC.
BALL PITCH
SD / SE
0.325 BSC.
SOLDER BALL PLACEMENT
C3~C20,D3~D20,E3~E20,F3~F20
G3~G20,H3~H20,J3~J20,K3~K20
L3~L20,M3~M20,N3~N20,P3~P20
R3~R20,T3~T20,U3~U20,V3~V20
W3~W20,Y3~Y20
DEPOPULATED SOLDER BALLS
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3523 \ 16-038.46 \ 02.23.06
24
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
5.6
I n f o r m a t i o n
BTA160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
A
D
PIN A1
CORNER
D1
9
INDEX MARK
PIN A1
CORNER
eD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
E
eE
0.10 C
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
(2X)
B
TOP VIEW
SD
2
SE 7
E1
1
7
0.10 C
BOTTOM VIEW
(2X)
0.20 C
A A2
A1
C
160X
0.10 C
SIDE VIEW
6
b
0.15 M
0.08 M
C A B
C
NOTES:
PACKAGE
BTA 160
JEDEC
N/A
DxE
15.00 mm x 15.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.30
A1
0.40
---
---
A2
0.74
---
0.84
NOTE
PROFILE
BODY SIZE
E
15.00 BSC.
BODY SIZE
D1
13.65 BSC.
MATRIX FOOTPRINT
E1
13.65 BSC.
MATRIX FOOTPRINT
MD
22
MATRIX SIZE D DIRECTION
ME
22
MATRIX SIZE E DIRECTION
n
160
BALL COUNT
N
160
MAXIMUM NUMBER OF BALLS
2
0.45
eE
0.50
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BALL HEIGHT
15.00 BSC.
R
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
D
Øb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
NUMBER OF LAND PARAMETERS
0.55
0.65 BSC.
BALL DIAMETER
eD
0.65 BSC.
BALL PITCH
SD SE
0.325 BSC.
SOLDER BALL PLACEMENT
C3~C20,D3~D20,E3~E20,F3~F20
G3~G20,H3~H20,J3~J20,K3~K20
L3~L20,M3~M20,N3~N20,P3~P20
R3~R20,T3~T20,U3~U20,V3~V20
W3~W20,Y3~Y20
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
BALL PITCH
DEPOPULATED SOLDER BALLS
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3550 \ 16-038.55 \ 02.23.06
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
25
A d v a n c e
5.7
I n f o r m a t i o n
ALH160—160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
A
D
PIN A1
CORNER
D1
PIN A1
CORNER
eD
9
INDEX MARK
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
E
eE
0.10 C
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
(2X)
SD
B
TOP VIEW
0.10 C
2
SE 7
E1
1
7
BOTTOM VIEW
(2X)
0.10 C
A A2
A1
C
160X
0.10 C
SIDE VIEW
6
b
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
ALH 160
JEDEC
N/A
DxE
15.00 mm x 15.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.10
A1
0.40
---
---
A2
0.53
---
0.65
NOTE
PROFILE
BALL HEIGHT
BODY THICKNESS
D
15.00 BSC.
BODY SIZE
E
15.00 BSC.
BODY SIZE
D1
13.65 BSC.
MATRIX FOOTPRINT
E1
13.65 BSC.
MATRIX FOOTPRINT
MD
22
MATRIX SIZE D DIRECTION
ME
22
MATRIX SIZE E DIRECTION
n
160
BALL COUNT
N
160
MAXIMUM NUMBER OF BALLS
R
2
Øb
eE
0.45
0.50
eD
0.65 BSC
0.325 BSC.
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL
POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
NUMBER OF LAND PERIMETERS
0.55
0.65 BSC.
SE SD
1.
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
BALL PITCH
BALL PITCH
SOLDER BALL PLACEMENT
C3-C20,D3-D20,E3-E20,
F3-F20,G3-G20,H3-H20,
J3-J20,K3-K20,L3-L20,
M3-M20,N3-N20,P3-P20,
R3-R20,T3-T20,U3-U20,
V3-V20,W3-W20,Y3-Y20
DEPOPULATED SOLDER BALLS
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3553 \ 16-038.24 \ 3.21.06
26
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006
A d v a n c e
6
I n f o r m a t i o n
MCP Revision Summary
Revision A (August 26, 2004)
Initial release
Revision A 1 (June 1, 2005)
Added SDRAM Type 2 module
Added Lead (Pb)-free options
Added FEA137 package diagram
Revision A2 (October 7, 2005)
Global
Updated the S29WS-N NOR Flash Module
Added the S30MS-P ORNAND Flash Module
Added SDRAM Type 4 module
Product Selector Guide
Updated the Product Selector Guide
Connection Diagrams
Added two diagrams for the x8 and x16 ORNAND connections
Pin Descriptions
Updated descriptions and added descriptions for ORNAND signals
Ordering Information
Added new options
Added Package-on-Package (PoP) options
Valid Combinations
Updated the valid combinations tables
Physical Dimensions
Added the FGA137 package diagram
Added the BWA160 package diagram
Added the BWB160 package diagram
Revision A3 (November 9, 2005)
Updated the SDRAM Type 1 module
Changed the status of all RAM modules to Preliminary from Advanced.
Revision A4 (December 14, 2005)
Product Selector Guides
Updated the tables
Connection Diagrams
Added the 512 Mb NOR Flash with 512 Mb NAND on Bus 1 and 512 Mb SDRAM on Bus 2 diagram
Ordering Information
Added new model number, package modifier and SDRAM & Data Flash density options
June 1, 2006 S72WS-N_00_A8
S72WS-N Based MCP/PoP Products
27
A d v a n c e
I n f o r m a t i o n
Valid Combinations
Updated all tables with new options
Revision A5 (December 16, 2005)
Connection Diagrams
Updated the pinouts to include DDR signals
Qualified 133 MHz as DDR based frequency
Revision A6 (March 21, 2006)
NOR Flash + ORNAND Flash + DRAM MCPs Product Selector Guide
Updated the model numbers
Ordering Information Table
Updated the table
Valid Combinations
Updated the tables
Physical Dimensions
Added the ALH160 package
Revision A7 (April 18, 2006)
Connection Diagrams
Updated the pinouts
Revision A8 (June 1, 2006)
Added 2 OPNs for products with DRAM Type 5
Updated product selector guide
Updated valid combination table
Added BTA160 package diagram
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels
and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development
by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004-2006 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.
28
S72WS-N Based MCP/PoP Products
S72WS-N_00_A8 June 1, 2006