S71PL-J Based MCPs Data Sheet (Retired Product) S71PL-J Based MCPs Cover Sheet This product has been retired and is not recommended for new designs. For new designs, S71GL-A or S71GL-N supersedes S71PL-J. Please contact your local Spansion sales office to determine the appropriate migration device, specifications, and ordering information. Availability of this document is retained for reference and historical purposes only. Publication Number S71PL-J_00 Revision B Amendment 6 Issue Date February 17, 2010 Da ta 2 Shee t (Retire d S71PL-J Based MCPs Pro duct) S71PL-J_00_B6 February 17, 2010 S71PL-J Based MCPs Stacked Multi-Chip Product (MCP) Flash Memory and RAM 256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation Page Mode Flash Memory and 64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static RAM/pSRAM Data Sheet Note: This product has been retired and is not recommended for new designs. For new designs, S71GL-A or S71GL-N supersedes S71PL-J. Please contact your local Spansion sales office to determine the appropriate migration device, specifications, and ordering information. Availability of this document is retained for reference and historical purposes only. Features Power supply voltage of 2.7 V to 3.1 V – 8 x 11.6 x 1.2 mm 64 ball FBGA – 8 x 11.6 x 1.4 mm 84 ball FBGA High performance Operating Temperature – 65 ns (65 ns Flash, 70 ns pSRAM) – –25°C to +85°C – –40°C to +85°C Packages – 7 x 9 x 1.2 mm 56 ball FBGA General Description The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One or more S29PL (Simultaneous Read/Write) Flash memory die pSRAM or SRAM The 256 Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2 is used to access the second Flash and no extra address lines are required. The products covered by this document are listed in the table below: Flash Memory Density 32Mb (1) pSRAM Density 64Mb (1) 4 Mb S71PL032J40 8 Mb S71PL032J80 S71PL064J80 16 Mb S71PL032JA0 S71PL064JA0 32 Mb S71PL064JB0 64 Mb 128Mb (2) 256Mb (2) S71PL127JB0 S71PL127JC0 S71PL254JC0 Flash Memory Density 32Mb SRAM Density (1) 4 Mb S71PL032J04 8 Mb S71PL032J08 16 Mb 64Mb S71PL064J08 S71PL064J0A Notes 1. Not recommended for new designs; contact your local Spansion sales representative for details. 2. Not recommended for new designs: use S71PL127N and S71PL256N instead. Publication Number S71PL-J_00 Revision B Amendment 6 Issue Date February 17, 2010 D at a S hee t For detailed specifications, please refer to the individual data sheets listed in the following table. Document Publication Identification Number (PID) S29PL-J S29PL-J_M0 pSRAM Type 1 psram_12 pSRAM Type 2 psram_15 8 Mb pSRAM Type 3 psram_25 16 Mb pSRAM Type 3 psram_06 pSRAM Type 4 psram_18 pSRAM Type 5 psram_21 pSRAM Type 6 psram_14 pSRAM Type 7 psram_13 4 Mb/8 Mb SRAM Type 1 sram_02 16 Mb SRAM Type 1 sram_06 SRAM Type 4 sram_07 32 Mb pSRAM Type 8 psram_31 Note None of these RAM specifications are applicable for new designs. Please contact your local Spansion sales representative for details. 4 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data 1. Product Selector Guide 1.1 32 Mb Flash Memory 1.2 1.3 She et Device-Model# Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns) pSRAM type Package S71PL032J04-0B 65 4M SRAM 70 SRAM1 TSC056 S71PL032J04-0K 65 4M SRAM 70 SRAM4 TSC056 S71PL032J40-0K 65 4M pSRAM 70 pSRAM4 TLC056 S71PL032J08-0B 65 8M SRAM 70 SRAM1 TSC056 S71PL032J80-0F 65 8M pSRAM 70 pSRAM5 TSC056 S71PL032J80-Q7 65 8M pSRAM 70 pSRAM1 TSC056 S71PL032J80-QF 65 8M pSRAM 70 pSRAM3 TSC056 S71PL032JA0-0K 65 16 Mb pSRAM 70 pSRAM1 TSC056 S71PL032JA0-QF 65 16 Mb pSRAM 70 pSRAM3 TSC056 S71PL032JA0-0Z 65 16M pSRAM 70 pSRAM7 TLC056 64 Mb Flash Memory Device-Model# Flash Access time (ns) (p)SRAM density (p)SRAM Access time (ns) (p)SRAM type Package S71PL064J80-07 65 8M pSRAM 70 pSRAM4 TSC056 S71PL064J0A-0S 65 16M SRAM 70 SRAM 4 TLC056 S71PL064JA0-0Z 65 16M pSRAM 70 pSRAM7 TLC056 S71PL064JA0-0B 65 16M pSRAM 70 pSRAM3 TLC056 S71PL064JA0-07 65 16M pSRAM 70 pSRAM1 TLC056 S71PL064JA0-0P 65 16M pSRAM 70 pSRAM7 TLC056 S71PL064JB0-QB 65 32M pSRAM 70 pSRAM2 TLC056 S71PL064JB0-0U 65 32M pSRAM 70 pSRAM8 TLC056 Package 128 Mb Flash Memory Not recommended for new designs; use S71PL127N instead. 1.4 Device-Model# Flash Access time (ns) pSRAM density pSRAM Access time (ns) pSRAM type S71PL127JB0-9Z 65 32M pSRAM 70 pSRAM7 TLA064 S71PL127JB0-9U 65 32M pSRAM 70 pSRAM6 TLA064 S71PL127JB0-9B 65 32M pSRAM 70 pSRAM2 TLA064 S71PL127JC0-9B 65 64M pSRAM 70 pSRAM2 TLA064 S71PL127JC0-9Z 65 64M pSRAM 70 pSRAM7 TLA064 S71PL127JC0-9U 65 64M pSRAM 70 pSRAM6 TLA064 256Mb Flash Memory (2xS29PL127J) Not recommended for new designs: use S71PL256N instead. Device-Model# Flash Access time (ns) pSRAM density pSRAM Access time (ns) pSRAM type Package S71PL254JC0-TB 65 64M pSRAM 70 pSRAM2 FTA084 S71PL254JC0-TZ 65 64M pSRAM 70 pSRAM7 FTA084 February 17, 2010 S71PL-J_00_B6 S71PL-J Based MCPs 5 D at a 2. S hee t MCP Block Diagram VCCf VCC CE#f1 WP#/ACC RESET# Flash-only Address Flash 1 Shared Address OE# WE# VSS RY/BY# Flash 2 (Note 2) CE#f2 (Note 1) VCCS DQ15 to DQ0 VCC pSRAM/SRAM IO15-IO0 CE#s CE# UB#s UB# LB#s LB# CE2 Notes 1. For 1 Flash + pSRAM, CE#f1=CE#. For 2 Flash + pSRAM, CE#=CE#f1 and CE#f2 is the chip-enable for the second Flash. 2. For 256Mb only, Flash 1 = Flash 2 = S29PL127J. 6 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data 3. She et Connection Diagrams Figure 3.1 S71PL032J Connection Diagram 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A2 A3 A4 A5 A6 A7 A7 LB# WP/ACC WE# A8 A11 Legend B1 B2 B3 B4 B5 B6 B7 B8 A3 A6 UB# RST#f CE2s A19 A12 A15 C1 C2 C3 C4 C5 C6 C7 C8 RY/BY# A20 A2 A5 A18 A9 A13 RFU D1 D2 D3 D6 D7 D8 A1 A4 A17 A10 A14 RFU E1 E2 E3 E6 E7 E8 A0 VSS DQ1 DQ6 RFU A16 F1 F2 F3 F4 F5 F6 F7 F8 CE1#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU G1 G2 G3 G4 G5 G6 G7 G8 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS H2 H3 H4 H5 H6 H7 DQ8 DQ2 DQ11 RFU DQ5 DQ14 Shared (Note 1) Flash only RAM only Reserved for Future Use Notes 1. May be shared depending on density. – A19 is shared for the 16M pSRAM configuration. – A18 is shared for the 8M pSRAM and above configurations. 2. Connecting all VCC and VSS balls to VCC and VSS is recommended. MCP Flash-only Addresses Shared Addresses S71PL032JA0 A20 A19-A0 S71PL032J80 A20-A19 A18-A0 S71PL032J08 A20-A19 A18-A0 S71PL032J40 A20-A18 A17-A0 S71PL032J04 A20-A18 A17-A0 February 17, 2010 S71PL-J_00_B6 S71PL-J Based MCPs 7 D at a S hee t Figure 3.2 S71PL064J Connection Diagram 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A2 A3 A4 A5 A6 A7 Legend A7 LB# WP/ACC WE# A8 A11 B1 B2 B3 B4 B5 B6 B7 B8 A3 A6 UB# RST#f CE2s A19 A12 A15 C1 C2 C3 C4 C5 C6 C7 C8 A2 A5 A18 RY/BY# A20 A9 A13 A21 D1 D2 D3 D6 D7 D8 A1 A4 A17 A10 A14 RFU E1 E2 E3 E6 E7 E8 A0 VSS DQ1 DQ6 RFU A16 F1 F2 F3 F4 F5 F6 F7 F8 CE1#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU G1 G2 G3 G4 G5 G6 G7 G8 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS H2 H3 H4 H5 H6 H7 DQ8 DQ2 DQ11 RFU DQ5 DQ14 Shared (Note 1) Flash only RAM only Reserved for Future Use Notes 1. May be shared depending on density. – A20 is shared for the 32M pSRAM configuration. – A19 is shared for the 16M pSRAM and above configurations. – A18 is shared for the 8M pSRAM and above configurations. 2. Connecting all VCC and VSS balls to VCC and VSS is recommended. 8 MCP Flash-only Addresses Shared Addresses S71PL064JB0 A21 A20-A0 S71PL064JA0 A21-A20 A19-A0 S71PL064J0A A21-A20 A19-A0 S71PL064J80 A21-A19 A18-A0 S71PL064J08 A21-A19 A18-A0 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data She et Figure 3.3 S71PL127J Connection Diagram 64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 A10 NC NC B5 B6 RFU RFU Legend C3 C4 C5 C6 C7 C8 A7 LB# WP/ACC WE# A8 A11 D2 D3 D4 D5 D6 D7 D8 D9 A3 A6 UB# RST#f CE2s A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RY/BY# A20 A9 A13 A21 F2 F3 F4 F7 F8 F9 A1 A4 A17 A10 A14 A22 G2 G3 G4 G7 G8 G9 A0 VSS DQ1 DQ6 RFU A16 H2 H3 H4 H5 H6 H7 H8 H9 CE#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU J2 J3 J4 J5 J6 J7 J8 J9 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS K3 K4 K5 K6 K7 K8 DQ8 DQ2 DQ11 RFU DQ5 DQ14 L5 L6 RFU* RFU M1 Shared (Note 1) Flash only RAM only Reserved for Future Use M10 NC NC *See notes below Notes 1. May be shared depending on density. – A21 is shared for the 64M pSRAM configuration. – A20 is shared for the 32M pSRAM and above configurations. 2. A19 is shared for the 16M pSRAM and above configurations MCP Flash-only Addresses Shared Addresses S71PL127JC0 A22 A21-A0 S71PL127JB0 A22-A21 A20-A0 3. Connecting all VCC and VSS balls to VCC & VSS is recommended. 4. Ball L5 will be VCCF in the 84-ball density upgrades. Do not connect to VSS or any other signal. February 17, 2010 S71PL-J_00_B6 S71PL-J Based MCPs 9 D at a S hee t Figure 3.4 S71PL254J Connection Diagram 84-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 A10 NC NC B2 B3 B4 B5 B6 B7 B8 B9 RFU RFU RFU CE#F2 RFU RFU RFU RFU C2 C3 C4 C5 C6 C7 C8 C9 RFU A7 LB# WP/ACC WE# A8 A11 RFU D2 D3 D4 D5 D6 D7 D8 D9 A3 A6 UB# RST#f CE2s A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RY/BY# A20 A9 A13 A21 F2 F3 F4 H5 H6 F7 F8 F9 A1 A4 A17 RFU RFU A10 A14 A22 G2 G3 G4 H5 H6 G7 G8 G9 A0 VSS DQ1 RFU RFU DQ6 RFU A16 H2 H3 H4 H5 H6 H7 H8 H9 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU J2 J3 J4 J5 J6 J7 J8 J9 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS K2 K3 K4 K5 K6 K7 K8 K9 RFU DQ8 DQ2 DQ11 RFU DQ5 DQ14 RFU L2 L3 L4 L5 L6 L7 L8 L9 RFU RFU RFU VCCf RFU RFU RFU RFU Legend Shared (Note 1) Flash only RAM only Reserved for Future Use 2nd Flash Only M1 M10 NC NC Notes 1. May be shared depending on density. – A21 is shared for the 64M pSRAM configuration. – A20 is shared for the 32M pSRAM configuration. MCP Flash-only Addresses Shared Addresses S71PL254JC0 A22 A21-A0 2. Connecting all VCC & VSS balls to VCC & VSS is recommended. Special Handling Instructions For FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150° C for prolonged periods of time. 10 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data 4. She et Pin Description Signal Description A21–A0 22 Address Inputs (Common) DQ15–DQ0 16 Data Inputs/Outputs (Common) CE1#f Chip Enable 1 (Flash) CE#f2 Chip Enable 2 (Flash) CE1#ps Chip Enable 1 (pSRAM) CE2ps Chip Enable 2 (pSRAM) OE# Output Enable (Common) WE# Write Enable (Common) RY/BY# Ready/Busy Output (Flash 1) UB# Upper Byte Control (pSRAM) LB# Lower Byte Control (pSRAM) RESET# Hardware Reset Pin, Active Low (Flash 1) WP#/ACC Hardware Write Protect/Acceleration Pin (Flash) VCCf Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VCCps pSRAM Power Supply VSS Device Ground (Common) NC Pin Not Connected Internally 5. Logic Symbol 22 A21–A0 16 CE1#f DQ15–DQ0 CE2#f CE1#ps CE2ps R Y/BY# OE# WE# WP #/ACC RES ET# UB# LB# February 17, 2010 S71PL-J_00_B6 S71PL-J Based MCPs 11 D at a 6. S hee t Ordering Information The order number is formed by a valid combinations of the following: S71PL 127 J B0 BA W 9 Z 0 Packing Type 0 = Tray 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER See the Valid Combinations table. Package Modifier 0 = 7 x 9 mm, 1.2 mm height, 56 balls (TLC056 or TSC065) 9 = 8 x 11.6 mm, 1.2 mm height, 64 balls (TLA064 or TSB064) T = 8 x 11.6 mm, 1.4 mm height, 84 balls (FTA084) Q = See the Valid Combinations table Temperature Range W = Wireless (-25° C to +85° C) Package Type BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package pSRAM Density C0 = 64 Mb pSRAM B0 = 32 Mb pSRAM A0 = 16 Mb pSRAM 80 = 8 Mb pSRAM 40 = 4 Mb pSRAM 0A = 16 Mb pSRAM 08 = 8 Mb SRAM 04 = 4 Mb SRAM Process Technology J = 110 nm, Floating Gate Technology Flash Density 254= 256 Mb 127= 128 Mb 064= 64 Mb 032= 32 Mb Product Family S71PL Multi-chip Product (MCP)3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM 6.1 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 12 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data She et Table 6.1 S71PL032J Valid Combinations Base Ordering Part Number Package & Temperature Package Modifier/ Model Number Packing Type Speed Options (ns) (p)SRAM Type/ Access Time (ns) S71PL032J04 0B S71PL032J04 0K SRAM4 / 70 S71PL032J40 0K pSRAM4 / 70 S71PL032J80 0F pSRAM5 / 70 S71PL032J08 0B BAW SRAM2 / 70 SRAM2 / 70 0, 2, 3 (1) 65 (2) S71PL032J80 Q7 pSRAM1 / 70 S71PL032J80 QF pSRAM3 / 70 S71PL032JA0 07 pSRAM1 / 70 S71PL032JA0 QF pSRAM3 / 70 S71PL032JA0 0Z pSRAM7 / 70 S71PL032J04 0B SRAM2 / 70 S71PL032J04 0K SRAM4 / 70 S71PL032J40 0K pSRAM4 / 70 S71PL032J80 0F pSRAM5 / 70 S71PL032J08 0B BFW SRAM2 / 70 0, 2, 3 (1) S71PL032J80 Q7 Package Marking 65 (2) pSRAM1 / 70 S71PL032J80 QF pSRAM3 / 70 S71PL032JA0 07 pSRAM1 / 70 S71PL032JA0 QF pSRAM3 / 70 S71PL032JA0 0Z pSRAM7 / 70 Table 6.2 S71PL064J Valid Combinations Base Ordering Part Number Package & Temperature Package Modifier/ Model Number Packing Type Speed Options (ns) (p)SRAM Type/ Access Time (ns) S71PL064J80 07 S71PL064J0A 0S SRAM1 / 70 S71PL064JA0 0B pSRAM3 / 70 S71PL064JA0 BAW 07 pSRAM 4/70 0, 2, 3 (1) 65 pSRAM1 / 70 S71PL064JA0 0P S71PL064JB0 QB pSRAM2 / 70 S71PL064JB0 0U pSRAM8 / 70 S71PL064J80 07 pSRAM7 /70 S71Pl064J0A 0S SRAM1 / 70 S71PL064JA0 0B pSRAM3 / 70 S71PL064JA0 BFW 07 Package Marking (2) pSRAM7 / 70 0, 2, 3 (1) 65 pSRAM1 / 70 S71PL064JA0 0P pSRAM7 / 70 S71PL064JB0 QB pSRAM2 / 70 S71PL064JB0 0U pSRAM8 / 70 (2) Notes 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. February 17, 2010 S71PL-J_00_B6 S71PL-J Based MCPs 13 D at a S hee t Table 6.3 S71PL127J Valid Combinations Base Ordering Part Number Package & Temperature Package Modifier/ Model Number Packing Type Speed Options (ns) (p)SRAM Type/ Access Time (ns) S71PL127JB0 9Z S71PL127JB0 9U pSRAM6 /70 S71PL127JC0 9B pSRAM2 /70 BAW pSRAM7 / 70 0, 2, 3 (1) 65 (2) S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 9U pSRAM6 / 70 S71PL127JB0 9B pSRAM2 / 70 S71PL127JB0 9Z pSRAM7 / 70 S71PL127JB0 9U pSRAM6 / 70 S71PL127JC0 9B BFW Package Marking pSRAM2 /70 0, 2, 3 (1) 65 (2) S71PL127JC0 9Z pSRAM7 / 70 S71PL127JC0 9U pSRAM6 / 70 S71PL127JB0 9B pSRAM2 / 70 Notes 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Table 6.4 S71PL254J Valid Combinations Base Ordering Part Number Package & Temperature S71PL254JC0 Model Number 0, 2, 3 (1) 65 TB BAW S71PL254JC0 Package Marking (2) pSRAM7 / 70 TB BFW (p)SRAM Type/ Access Time (ns) pSRAM2 / 70 TZ S71PL254JC0 S71PL254JC0 Packing Type Speed Options (ns) pSRAM2 / 70 0, 2, 3 (1) 65 (2) TZ pSRAM7 / 70 Notes 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. 14 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data 7. She et Physical Dimensions TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package D1 A D eD 0.15 C (2X) 8 7 SE 6 7 5 E E1 4 3 eE 2 1 H INDEX MARK PIN A1 CORNER B 10 TOP VIEW G F E D C B A 7 SD 0.15 C (2X) PIN A1 CORNER BOTTOM VIEW 0.20 C A A2 A1 C 56X 0.08 C SIDE VIEW 6 b 0.15 M C A B 0.08 M C NOTES: PACKAGE TLC 056 JEDEC N/A DxE 9.00 mm x 7.00 mm PACKAGE 1. SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.20 --- --- A2 0.81 --- 0.97 NOTE PROFILE BODY SIZE E 7.00 BSC. BODY SIZE D1 5.60 BSC. MATRIX FOOTPRINT E1 5.60 BSC. MATRIX FOOTPRINT MD 8 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION n 56 0.35 0.40 ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BALL HEIGHT 9.00 BSC. φb 2. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 eE 0.80 BSC. BALL PITCH 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A1,A8,D4,D5,E4,E5,H1,H8 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eD DEPOPULATED SOLDER BALLS DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3348 \ 16-038.22a February 17, 2010 S71PL-J_00_B6 S71PL-J Based MCPs 15 D at a S hee t TSC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package D1 A D eD 0.15 C (2X) 8 7 SE 6 7 5 E E1 4 3 eE 2 1 INDEX MARK PIN A1 CORNER H B 10 TOP VIEW G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW 0.20 C A A2 A1 C 0.08 C SIDE VIEW 6 b 56X 0.15 0.08 M C A B M C NOTES: PACKAGE TSC 056 JEDEC N/A DxE 9.00 mm x 7.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.17 --- --- A2 0.81 --- 0.97 NOTE PROFILE BODY SIZE E 7.00 BSC. BODY SIZE D1 5.60 BSC. MATRIX FOOTPRINT E1 5.60 BSC. MATRIX FOOTPRINT MD 8 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION 56 0.35 0.40 ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 eE 0.80 BSC. BALL PITCH 0.80 BSC BALL PITCH 0.40 BSC. SOLDER BALL PLACEMENT A1,A8,D4,D5,E4,E5,H1,H8 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eD SD / SE 2. BODY THICKNESS 9.00 BSC. n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BALL HEIGHT D φb 1. DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3427 \ 16-038.22 16 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data She et TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package D1 A D eD 0.15 C 10 (2X) 9 8 SE 7 7 6 E E1 5 4 eE 3 2 1 M INDEX MARK PIN A1 CORNER B 10 TOP VIEW L K J H G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW A A2 0.20 C A1 C SIDE VIEW 6 0.08 C b 64X 0.15 0.08 M C A B M C NOTES: PACKAGE TLA 064 JEDEC N/A DxE 11.60 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.17 --- --- A2 0.81 --- 0.97 NOTE PROFILE BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION 64 0.35 0.40 ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10, F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 February 17, 2010 S71PL-J_00_B6 2. BALL HEIGHT 11.60 BSC. n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BODY THICKNESS D φb 1. S71PL-J Based MCPs WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3352 \ 16-038.22a 17 D at a S hee t TSB064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package D1 A D eD 0.15 C 10 (2X) 9 8 SE 7 7 6 E E1 5 4 eE 3 2 1 M INDEX MARK PIN A1 CORNER B 10 TOP VIEW L K J H G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW A A2 0.20 C A1 C SIDE VIEW 6 b 64X 0.15 0.08 M C A B M C NOTES: PACKAGE TSB 064 JEDEC N/A DxE 11.60 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 017 --- --- A2 0.81 --- 0.97 NOTE ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BODY THICKNESS E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MD 12 ME 10 MATRIX SIZE E DIRECTION n 64 BALL COUNT MATRIX FOOTPRINT SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. MATRIX SIZE D DIRECTION 0.45 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH 0.40 BSC. SOLDER BALL PLACEMENT SD / SE 2. BALL HEIGHT BODY SIZE 0.40 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 4. 11.60 BSC. 0.35 1. PROFILE D φb 0.08 C A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10 F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9 WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3351 \ 16-038.22a 18 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data She et FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package D1 A D eD 0.15 C 10 (2X) 9 SE 7 8 7 6 E E1 5 4 eE 3 2 1 M L K J INDEX MARK PIN A1 CORNER B 10 TOP VIEW H G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW 0.20 C A A2 A1 C 84X 0.08 C SIDE VIEW 6 b 0.15 M C A B 0.08 M C NOTES: PACKAGE FTA 084 JEDEC N/A DxE 11.60 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.40 A1 0.17 --- --- A2 1.02 --- 1.17 NOTE PROFILE BODY SIZE E 8.00 BSC. BODY SIZE D1 8.80 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 12 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION 84 0.35 0.40 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS 11.60 BSC. n DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. BALL HEIGHT D φb 1. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10,E1,E10 F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9 WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3388 \ 16-038.21a February 17, 2010 S71PL-J_00_B6 S71PL-J Based MCPs 19 D at a S hee t 8. Revision History Section Description Revision A (May 3, 2004) Initial release Revision A1 (May 6, 2004) Features Corrected the high performance access times. Connection Diagrams Added reference points on all diagrams. Ordering Information Corrected package types. Corrected the description of product family to Page Mode Flash memory. Revision A2 (May 11, 2004) General Description Corrected the tables to reflect accurate device configurations. Revision A3 (June 16, 2004) Ordering Information Corrected the Valid Combinations tables to reflect accurate device configurations. Revision A4 (July 16, 2004) Global Global Change of FASL to Spansion. Global change to remove space between M and Mb callouts. Replaced “S71PL032J08-07” with “S71PL032J08-0B”. 32 Mb Flash Memory Replaced “S71PL032JA0” with “S71PL032JA0-07”. Replaced “S71PL032JA0-08” with “S71PL032JA0-0F”. Added row with the following content: S71PL032JA0-08; 65; 16Mb pSRAM; 70; pSRAM3; TLC056. Replaced “S71PL064J08-0K” with “S71PL064J08-0B”. Replaced “S71PL064J08-0P” with “S71PL064J08-0U”. 64 Mb Flash Memory Deleted “S71PL064J80-05” row. Replaced “S71PL064JA0-07” with “S71PL064JA0-0K”. Replaced “S71PL064JA0-0Z” with Added row with the following content:S71PL064JB0-07; 65; 32M pSRAM; 70; Psram 1; TLC056. Added row with the following content: S71PL127JB0-9; 65; 32M pSRAM; 70; pSRAM; TLA064. Replaced “S71PL127JB0-97” with “S71PL127JB0-9Z”. 128 Mb Flash Memory Added row with the following content: S71PL127JC0-97; 65; 64M pSRAM; 70; pSRAM1; TLA064. Replaced “S71PL127JC0-9P” with “S71PL127JC0-9Z”. In the S71Pl254JB0-TB row changed pSRAM type from “pSRAM3” to “pSRAM2”. 256 Mb Flash Memory Added row with the following content: S71PL254JB0-TB; 65; 32M pSRAM; 70; pSRAM3; FTA084. Added row with the following content: S71PL254JC0-TB; 65; 64M pSRAM; 70; pSRAM2; FTA084. Updated pins D8, D9, and L5. Connection Diagrams Added notes 2 and 3 to drawing. Updated pins D8 and D9. Added Note 2 to drawing. Changed S71PL032J08 (p)SRAM Type Access Time (ns) from “SRAM1” to “SRAM2” (4 changes made in table). S71PL032J Valid Combinations Changed S71PL032JA0 (p)SRAM Type Access Time (ns) from “SRAM3 / 70” to pSRAM3 /70”. Deleted all cells with the following collaborated text: “BAW,BFW, BAI. BFI”. Merged previous place holder with cell above. In (p)SRAM Type/Access Time (ns) changed all instances of “stet” to “pSRAM1/70”. S71PL064J Valid Combinations In Package Modifier/Model Number changed all instances of “stet” to “07”. Added row to BAW Package and Temperature sections with the following content: S71PL064JB0; 07; 65 (previously inclusive); pSRAM1/70. S71PL127J Valid Combinations S71PL254J Valid Combinations 20 Changed the S71PL127JA0 Package Modifier/Model Number from “9Z” to “9P” (4 instances). Added 4 rows with the following content: S71PL127JC0; 97; pSRAM1/70. Added 4 rows with the following content: S71PL254JC0; TB; pSRAM2/70. Added 4 rows with the following content: S71PL254JB0; TB; pSRAM2/70. S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010 Data She et Section S71PL-J Based MCPs Description Added 254M to Megabit indicator. Added 16 to CMOS indicator Revision A5 (September 14, 2004) Product Selector Guide Updated the 128Mb Flash Memory table. Valid Combinations Table Updated the S71PL127J Valid Combinations table. Revision A6 (November 22, 2004) Product Selector Guide Updated the 32Mb and 64Mb tables. Valid Combinations Table Updated the 32Mb and 64Mb combinations. Physical Dimensions Added the TSB064 package. Revision A7 (February 8, 2005) pSRAM Type 7 Updated all information in this section Revision A8 (April 6, 2005) S29PL-J Flash Updated all information in this section Revision A9 (May 12, 2005) Global Added the S71PL064J0A option to cover the inclusion of the 16M SRAM Revision A10 (June 22, 2005) Global Removed 127/16 and 254/32 pSRAM and updated OPN for 64/16SRAM Revision A11 (July 29, 2005) pSRAM Type 7 Updated this module Revision B (September 29, 2005) S29PL-J Flash Updated this module SRAM Type 1 Updated this module Revision B1 (October 25, 2005) pSRAM Type 5 Added this module Revision B2 (January 25, 2006) Added notices for devices not recommended for new designs Global Modified the Product Selection Guide Modified the S71PL032J, S71PL064J, S71PL127JValid Combinations tables Revision B3 (March 17, 2006) Modified the stucture of the document. Related data sheets are referenced rather than be embedded. Added data sheet reference table to that effect. Global Added the SRAM Type 4 option Added the 8Mb pSRAM Type 3 option Revision B4 (December 22, 2006) Global Added the S71PL064J80-07 for pSRAM Type 4 Removed the S71PL064J08-0B Revision B5 (July 17, 2007) Global Updated product status for all listed products Ordering Information Revised ordering information for S71PL032JA0 and S71PL064JB0 MCPs Revision B6 (February 17, 2010) Ordering Information February 17, 2010 S71PL-J_00_B6 Added Q description under Package Modifier S71PL-J Based MCPs 21 D at a S hee t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004-2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 22 S71PL-J Based MCPs S71PL-J_00_B6 February 17, 2010