STMICROELECTRONICS 74AC163M

74AC163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
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HIGH SPEED:
fMAX = 200MHz (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 8µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC163 is an advanced high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS tecnology. It is a
4 bit binary counter with Synchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine the
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
74AC163B
74AC163M
T&R
74AC163MTR
74AC163TTR
mode of operation as shown in the Truth Table. A
LOW signal on CLEAR overrides counting and
parallel loading and sets all outputs on LOW state
on the next rising edge of CLOCK. A LOW signal
on LOAD overrides counting and allows
information on Parallel Data inputs to be loaded
into the flip-flop on the next rising edge of CLOCK.
With LOAD and CLEAR HIGH, PE and TE permit
counting when both are HIGH. Conversely, a
LOW signal on either PE and TE inhibits counting.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/13
74AC163
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
2
CLEAR
CLOCK
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
8
16
A, B, C, D
PE
TE
LOAD
QA to QD
Master Reset
Clock Input (LOW to
HIGH Edge Trigger)
Data Inputs
Count Enable Input
Count Enable Carry Input
Parallel Enable Input
Flip-Flop Outputs
CARRY OUT Terminal Count Output
GND
Ground (0V)
Positive Supply Voltage
VCC
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLEAR
LOAD
PE
TE
L
X
X
X
L
L
L
L
RESET TO "0"
H
L
X
X
A
B
C
D
PRESET DATA
H
H
X
L
NO CHANGE
NO COUNT
H
H
L
X
NO CHANGE
NO COUNT
H
H
H
H
COUNT UP
COUNT
H
X
X
X
NO CHANGE
NO COUNT
CK
X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT : TE x QA x QB x QC x QD
LOGIC DIAGRAM
2/13
74AC163
TIMING CHART
3/13
74AC163
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 50
mA
± 300
mA
VI
DC Input Voltage
VO
DC Output Voltage
IIK
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
Unit
2 to 6
V
VI
Input Voltage
0 to VCC
V
VO
Output Voltage
0 to VCC
V
Top
Operating Temperature
-55 to 125
°C
8
ns/V
dt/dv
Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1)
1) VIN from 30% to 70% of V CC
4/13
Value
74AC163
DC SPECIFICATIONS
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
ICC
IOLD
IOHD
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
TA = 25°C
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
Value
VO = 0.1 V or
VCC-0.1V
Min.
Typ.
2.1
3.15
3.85
1.5
2.25
2.75
1.5
2.25
2.75
VO = 0.1 V or
VCC-0.1V
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
2.1
3.15
3.85
0.9
1.35
1.65
Max.
2.1
3.15
3.85
0.9
1.35
1.65
V
0.9
1.35
1.65
3.0
IO=-50 µA
2.9
2.99
2.9
2.9
4.5
IO=-50 µA
4.4
4.49
4.4
4.4
5.5
IO=-50 µA
5.4
5.49
5.4
5.4
3.0
IO=-12 mA
2.56
2.46
2.4
4.5
IO=-24 mA
3.86
3.76
3.7
5.5
IO=-24 mA
4.86
4.76
4.7
Unit
V
V
3.0
IO=50 µA
0.002
0.1
0.1
0.1
4.5
IO=50 µA
0.001
0.1
0.1
0.1
5.5
IO=50 µA
0.001
0.1
0.1
0.1
3.0
IO=12 mA
0.36
0.44
0.5
4.5
IO=24 mA
0.36
0.44
0.5
5.5
IO=24 mA
0.36
0.44
0.5
5.5
VI = VCC or GND
± 0.1
±1
±1
µA
5.5
VI = VCC or GND
8
80
160
µA
VOLD = 1.65 V max
75
50
mA
VOHD = 3.85 V min
-75
-50
mA
5.5
V
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
5/13
74AC163
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time CLOCK to Q
tPLH tPHL Propagation Delay
Time CLOCK to
CARRY OUT
tPLH tPHL Propagation Delay
Time TE to CARRY
OUT
tW
CK pulse Width,
(Count) HIGH or
LOW
tW
CK pulse Width,
(Load) HIGH or
LOW
ts
Setup Time HIGH
or LOW (INPUT to
CLOCK)
tn
Hold Time HIGH or
LOW (INPUT to
CLOCK)
ts
Setup Time HIGH
or LOW (CLEAR to
CLOCK)
th
Hold Time HIGH or
LOW (CLEAR to
CLOCK)
ts
Setup Time HIGH
or LOW ( LOAD to
CLOCK)
th
Hold Time HIGH or
LOW (LOAD to
CLOCK)
ts
Setup Time HIGH
or LOW (PE or TE
to CLOCK)
th
Hold Time HIGH or
LOW (PE or TE to
CLOCK)
fMAX
Maximum Clock
Frequency
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
6/13
VCC
(V)
Value
TA = 25°C
-55 to 125°C
Min.
Min.
Typ.
Max.
(*)
7.0
12.0
13.0
13.0
(**)
5.0
5.0
9.0
9.5
9.5
3.3(*)
8.0
14.0
15.0
15.0
5.0(**)
6.0
10.5
11.5
11.5
3.3(*)
5.5
9.5
11.0
11.0
5.0(**)
4.0
6.5
7.5
7.5
3.3(*)
2.0
4.5
7.5
7.5
5.0(**)
2.0
4.0
4.5
4.5
3.3(*)
2.0
3.0
3.5
3.5
5.0(**)
2.0
2.5
3.0
3.0
3.3(*)
2.0
4.0
5.0
5.0
(**)
5.0
1.5
3.0
4.0
4.0
3.3(*)
-1.5
-0.5
0
0
5.0(**)
-1.0
0.5
1.0
1.0
3.3(*)
1.0
3.0
4.0
4.0
(**)
5.0
1.0
3.5
4.5
4.5
3.3(*)
-0.5
0.5
1.0
1.0
5.0(**)
-0.3
0.5
1.0
1.0
3.3(*)
3.0
5.0
8.0
8.0
5.0(**)
2.5
6.0
7.0
7.0
3.3(*)
-2.5
-1.0
-0.5
-0.5
5.0(**)
-1.5
0
0.5
0.5
3.3(*)
3.0
6.0
7.0
7.0
5.0(**)
2.0
4.0
5.0
5.0
3.3(*)
-2.0
-0.5
0
0
(**)
-1.5
0
0.5
0.5
3.3
Min.
-40 to 85°C
5.0
Max.
3.3(*)
70
200
60
60
5.0(**)
110
200
95
95
Unit
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
74AC163
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
TA = 25°C
VCC
(V)
CIN
Input Capacitance
5.0
CPD
Power Dissipation
Capacitance
(note1)
5.0
Value
Min.
fIN = 10MHz
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
4.5
pF
37
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit)
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAYS, COUNT MODE (f=1MHz; 50% duty cycle)
7/13
74AC163
WAVEFORM 2: PROPAGATION DELAYS CLEAR MODE (f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAYS PRESET MODE (f=1MHz; 50% duty cycle)
8/13
74AC163
WAVEFORM 4: PROPAGATION DELAYS COUNTABLE MODE (f=1MHz; 50% duty cycle)
WAVEFORM 5: PROPAGATION DELAYS CASCADE MODE (f=1MHz; 50% duty cycle)
9/13
74AC163
Plastic DIP-16 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
10/13
74AC163
SO-16 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.004
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8 (max.)
P013H
11/13
74AC163
TSSOP16 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
A
MAX.
MIN.
MAX.
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
4.9
5
5.1
0.193
0.197
0.201
E
6.25
6.4
6.5
0.246
0.252
0.256
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0o
4o
8o
0o
4o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A
A2
A1
b
e
K
c
E1
PIN 1 IDENTIFICATION
1
L
E
D
12/13
TYP.
74AC163
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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13/13