ETC 74ACT174MTR

74ACT174
HEX D-TYPE FLIP FLOP WITH CLEAR
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HIGH SPEED:
fMAX = 200MHz (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT174 is an advanced high-speed CMOS
HEX D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS tecnology.
Information signals applied to D inputs are
transferred to the Q output on the positive going
edge of the clock pulse.
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
74ACT174B
74ACT174M
T&R
74ACT174MTR
74ACT174TTR
When the CLEAR input is held low, the Q outputs
are held low independentely of the other inputs.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/11
74ACT174
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
CLEAR
2, 5, 7, 10,
12, 15
3, 4, 6, 11,
13, 14
9
Q0 to Q5
Asynchronous Master
Reset (Active LOW)
Flip-Flop Outputs
D0 to D5
Data Inputs
CLOCK
8
16
GND
VCC
Clock Input (LOW-to-HIGH,
Edge Trigger)
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUT
FUNCTION
CLEAR
D
CLOCK
Q
L
X
X
L
H
L
L
H
H
H
H
X
Qn
X : Don’t Care
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
2/11
CLEAR
NO CHANGE
74ACT174
ABSOLUTE MAXIMUM RATINGS
Symbol
V CC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
VI
DC Input Voltage
VO
DC Output Voltage
IIK
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
± 50
mA
± 300
mA
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Value
Unit
Supply Voltage
4.5 to 5.5
V
VI
Input Voltage
0 to VCC
V
VO
Output Voltage
0 to VCC
V
Top
Operating Temperature
-55 to 125
°C
8
ns/V
V CC
dt/dv
Parameter
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
1) VIN from 0.8V to 2.0V
3/11
74ACT174
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
1.5
2.0
2.0
1.5
2.0
VO = 0.1 V or
VCC-0.1V
V IL
Low Level Input
Voltage
4.5
5.5
VO = 0.1 V or
VCC-0.1V
VOH
High Level Output
Voltage
4.5
IO=-50 µA
4.4
4.49
5.5
IO=-50 µA
5.4
5.49
4.5
IO =-24 mA
3.86
4.86
II
Input Leakage Current
Max ICC/Input
0.8
0.8
Unit
Max.
2.0
2.0
0.8
0.8
V
0.8
0.8
4.4
4.4
5.4
5.4
3.76
3.7
V
5.5
4.5
IO=50 µA
0.001
0.1
0.1
0.1
5.5
IO=50 µA
0.001
0.1
0.1
0.1
4.76
4.7
V
4.5
IO =24 mA
0.36
0.44
0.5
5.5
IO =24 mA
0.36
0.44
0.5
5.5
VI = VCC or GND
± 0.1
±1
±1
µA
1.5
1.6
mA
40
80
µA
VOLD = 1.65 V max
75
50
mA
VOHD = 3.85 V min
-75
-50
mA
5.5
VI = VCC - 2.1V
Quiescent Supply
Current
5.5
VI = VCC or GND
IOLD
Dynamic Output
Current (note 1, 2)
5.5
IOHD
1.5
1.5
Max.
IO =-24 mA
ICC
ICCT
Min.
2.0
5.5
Low Level Output
Voltage
Min.
Typ.
4.5
VOL
-55 to 125°C
Min.
High Level Input
Voltage
VIH
Max.
-40 to 85°C
0.6
4
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time CLOCK to Y
tPLH tPHL Propagation Delay
Time CLEAR to Y
tWL
CLEAR Pulse
Width, LOW
tW
CLOCK Pulse
Width
ts
Setup Time D to
CLOCK, HIGH or
LOW
th
Hold Time D to
CLOCK, HIGH or
LOW
tREM
Recovery Time
CLEAR to CLOCK
fMAX
Maximum CLOCK
Frequency
(*) Voltage range is 5.0V ± 0.5V
4/11
VCC
(V)
Value
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Min.
Min.
Typ.
Max.
5.0 (*)
1.5
6.0
10.5
11.5
11.5
ns
5.0 (*)
1.5
7.0
9.5
11.0
11.0
ns
5.0 (*)
3.0
4.5
5.0
5.0
ns
5.0 (*)
3.0
4.5
5.0
5.0
ns
5.0 (*)
0.5
1.5
1.5
1.5
ns
5.0 (*)
1.0
2.0
2.0
2.0
ns
5.0 (*)
0.0
0.5
0.5
0.5
ns
5.0 (*)
165
200
140
Max.
Unit
140
Max.
MHz
74ACT174
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
TA = 25°C
VCC
(V)
CIN
Input Capacitance
5.0
C PD
Power Dissipation
Capacitance (note
1)
5.0
Value
Min.
fIN = 10MHz
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
4
pF
35
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT
C L = 50pF or equivalent (includes jig and probe capacitance)
R L = R1 = 500Ω or equivalent
R T = ZOUT of pulse generator (typically 50Ω)
5/11
74ACT174
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
6/11
74ACT174
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
7/11
74ACT174
Plastic DIP-16 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
8/11
74ACT174
SO-16 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.004
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45 (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8 (max.)
P013H
9/11
74ACT174
TSSOP16 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
A
MAX.
MIN.
MAX.
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
4.9
5
5.1
0.193
0.197
0.201
E
6.25
6.4
6.5
0.246
0.252
0.256
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
0.65 BSC
0.0256 BSC
K
0o
4o
8o
0o
4o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A
A2
A1
b
e
K
c
E1
PIN 1 IDENTIFICATION
1
L
E
D
10/11
TYP.
74ACT174
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information
previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or
systems without express written approval of STMicroelectronics.
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11/11