STMICROELECTRONICS RHRXH162373K1

54VCXH162373
Rad hard low voltage CMOS 16-bit D-type latch (3-state)
with 3.6 V tolerant inputs and outputs
Features
■
1.65 to 3.6 V inputs and outputs
■
High speed:
– tPD = 3.3 ns (Max.) at VCC = 3.0 to 3.6 V
– tPD = 4.5 ns (Max.) at VCC = 2.3 to 2.7 V
■
Symmetrical impedance outputs:
– |IOH| = IOL = 12 mA (Min.) at VCC = 3.0 V
– |IOH| = IOL = 8 mA (Min.) at VCC = 2.3 V
■
Power down protection on inputs and outputs
■
26 Ω serie resistors in outputs
■
Operating voltage range:
– VCC(Opr) = 1.65 V to 3.6 V
■
Pin and function compatible with 54 series
HR162373
■
Bus hold provided on both sides
■
Cold spare function
■
Latch-up performance exceeds
300 mA (JESD 17)
■
ESD performance:
– HBM > 2000 V
(MIL STD 883 method 3015); MM > 200 V
■
300 krad Mil1019.6 condition A, (RHA QML
qualification extension undergone)
■
No SEL, no SEUand no SET under 110
Mev/cm2/mg LET heavy ions irradiation
■
QML qualified product
■
Device fully compliant with
DSCC SMD 5962-05211
■
100 mV typical input hysteresis
August 2011
Flat-48
The upper metallic lid is not electrically connected to any
pins, nor to the IC die inside the package.
Description
The 54VCXH162373 is a low voltage CMOS 16
bit d-type latch with 3 state outputs non inverting
fabricated with sub-micron silicon gate and fivelayer metal wiring C²MOS technology. It is ideal
for low power and very high speed 1.65 to 3.6 V
applications; it can be interfaced to 3.6 V signal
environment for both inputs and outputs. These
16 bit D-type latches are bite controlled by two
latch enable inputs (nLE) and two output enable
inputs (OE). While the nLE input is held at a high
level, the nQ outputs will follow the data input
precisely. When the nLE is taken low, the nQ
outputs will be in a normal logic state (high or low
logic level) and while high level the outputs will be
in a high impedance state. Bus hold on data
inputs is provided in order to eliminate the need
for external pull-up or pull-down resistor. The
device circuits is including 26 Ω series resistance
in the outputs. These resistors permit to reduce
line noise in high speed applications. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2 kV ESD
immunity and transient excess voltage.
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18
Contents
54VCXH162373
Contents
1
Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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54VCXH162373
1
Logic symbols and I/O equivalent circuit
Logic symbols and I/O equivalent circuit
Figure 1.
IEC logic symbols
Figure 2.
Input and output equivalent circuit
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Logic symbols and I/O equivalent circuit
Figure 3.
Logic diagram
Note:
This logic diagram has not to be used to estimate propagation delays
4/18
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54VCXH162373
54VCXH162373
Pin settings
2
Pin settings
2.1
Pin connection
Figure 4.
Pin connection (top through view)
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Pin settings
2.2
54VCXH162373
Pin description
Table 1.
Pin description
Pin n°
Symbol
1
1OE
2, 3, 5, 6, 8, 9, 11, 12
Name and function
3 state output enable input (active LOW)
1Q0 to 1Q7 3-state outputs
13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7 3-state outputs
24
2OE
3 state output enable input (active LOW)
25
2LE
Latch enable input
36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7 Data inputs
47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7 Data inputs
2.3
48
1LE
Latch enable input
4, 10, 15, 21, 28, 34, 39, 45
GND
Ground (0 V)
7, 18, 31, 42
VCC
Positive supply voltage
Truth table
Table 2.
Truth table
Inputs
Output
OE
LE
D
Q
H
X
X
Z
L
L
X
No change (1)
L
H
L
L
L
H
H
H
1. Q outputs are latched at the time when the LE input is taken low logic level.
Note:
6/18
X = Do not care; Z = High impedance
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54VCXH162373
3
Maximum rating
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 3.
Absolute maximum ratings
Symbol
Value
Unit
Supply voltage
-0.5 to +4.6
V
VI
DC input voltage
-0.5 to +4.6
V
VO
DC output voltage (OFF state)
-0.5 to +4.6
V
-0.5 to VCC + 0.5
V
VCC
Parameter
(1)
VO
DC output voltage (High or low state)
IIK
DC input diode current
- 50
mA
IOK
DC output diode current (2)
- 50
mA
IO
DC output current
± 50
mA
DC VCC or ground current per supply pin
± 100
mA
400
mW
-65 to +150
°C
260
°C
ICC or
IGND
PD
Power dissipation
Tstg
Storage temperature
TL
Lead temperature (10 sec)
1. IO absolute maximum rating must be observed
2. VO < GND, VO > VCC
3.1
Recommended operating conditions
Table 4.
Recommended operating conditions
Symbol
Value
Unit
Supply voltage
1.8 to 3.6
V
VI
Input voltage
-0.3 to 3.6
V
VO
Output voltage (OFF state)
0 to 3.6
V
VO
Output voltage (high or low state)
0 to VCC
V
VCC
Parameter
IOH, IOL
High or low level output current (VCC = 3.0 to 3.6 V)
± 12
mA
IOH, IOL
High or low level output current (VCC = 2.3 to 2.7 V)
±8
mA
-55 to 125
°C
0 to 10
ns/V
Top
dt/dv
Operating temperature
Input rise and fall time
(1)
1. VIN from 0.8 V to 2 V at VCC = 3.0 V
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Electrical characteristics
4
54VCXH162373
Electrical characteristics
2.7 V < VCC < 3.6 V unless otherwise specified
Table 5.
DC specifications
Test condition
Symbol
Parameter
High level input voltage
VIL
Low level input voltage
VOH
-55 to 125°C
VCC
(V)
VIH
Min.
2.0
V
0.8
High level output
voltage
2.7 to 3.6
IO=-100 μA
VCC-0.2
2.7
IO=-6 mA
2.2
IO=-8 mA
2.4
IO=-12 mA
2.2
Low level output
voltage
Input leakage current
IO=100 μA
0.2
2.7
IO=6 mA
0.4
IO=8 mA
0.55
IO=12 mA
0.8
VI = 0 to 3.6 V
±5
2.7 to 3.6
3.0
II(HOLD) Input hold current
8/18
V
2.7 to 3.6
3.0
II
Unit
Max.
2.7 to 3.6
3.0
VOL
Value
V
VI = 0.8 V
75
VI = 2 V
-75
μA
μA
3.6
VI = 0 to 3.6 V
± 500
0
VI or VO = 0 to 3.6 V
10
μA
VI = VIH or VIL
VO = 0 to 3.6 V
± 10
μA
VI = VCC or GND
20
VI or VO = VCC to 3.6 V
± 20
VIH = VCC - 0.6 V
750
Ioff
Power Off leakage
current
IOZ
High impedance output
leakage current
2.7 to 3.6
ICC
Quiescent supply
current
2.7 to 3.6
ΔICC
ICC incr. per Input
2.7 to 3.6
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μA
μA
54VCXH162373
Electrical characteristics
2.3 V < VCC < 2.7 V unless otherwise specified
Table 6.
DC specifications
Test condition
Symbol
Parameter
-55 to 125 °C
VCC
(V)
VIH
High level input voltage
VIL
Low level input voltage
Min.
0.7
IO = -100 μA
VCC-0.2
IO = -4 mA
2.0
2.3
IO = -6 mA
1.8
IO = -8 mA
1.7
2.3 to 2.7
IO = 100 μA
0.2
VOL
IO = 6 mA
0.4
IO = 8 mA
0.6
II
High level output voltage
Low level output voltage
Input leakage current
2.3
2.3 to 2.7
II(HOLD) Input hold current
Ioff
Power Off leakage
current
IOZ
ICC
V
V
±5
VI = VCC or GND
2.3
Unit
Max.
1.6
2.3 to 2.7
2.3 to 2.7
VOH
Value
VI = 0.7 V
45
VI = 1.7 V
-45
V
μA
μA
0
VI or VO = 0 to 3.6 V
10
μA
High impedance output
leakage current
2.3 to 2.7
VI = VIH or VIL
VO = 0 to 3.6 V
± 10
μA
Quiescent supply
current
VI = VCC or GND
20
2.3 to 2.7
VI or VO =
VCC to 3.6 V
± 20
μA
TA = 25 °C, Input tr = tf = 2.0 ns, CL = 30 pF, RL = 500 Ω
Table 7.
Dynamic switching characteristics
Test condition
Symbol
Parameter
TA = 25 °C
VCC
(V)
VOLV
Dynamic valley low voltage
quiet output (1) (2)
VOHV
Dynamic valley high voltage
quiet output (2) (3)
VOHV
Dynamic valley high voltage
quiet output (2) (3)
2.5
3.3
2.5
3.3
2.5
3.3
Value
VIL = 0 V
VIH = VCC
VIL = 0 V
VIH = VCC
VIL = 0 V
VIH = VCC
Unit
Min.
Typ.
Max.
-
0.25
-
-
0.35
-
-
-0.25
-
-
-0.35
-
-
2.05
-
-
2.65
-
V
V
V
1. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to
HIGH. The remaining output is measured in the LOW state.
2. Parameters guaranteed by design.
3. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to
HIGH. The remaining output is measured in the HIGH state.
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Electrical characteristics
54VCXH162373
CL = 30 pF, RL = 500 Ω, Input tr = tf = 2.0 ns
Table 8.
AC electrical characteristics
Test condition
Symbol
Parameter
VCC
(V)
Value
Unit
-55 to 125 °C
Min.
Max.
Propagation delay
time Dn to Qn
2.3 to 2.7
1.0
5.2
tPLH tPHL
3.0 to 3.6
0.8
4.0
Propagation delay
time LE to Qn
2.3 to 2.7
1.0
5.7
tPLH tPHL
3.0 to 3.6
0.8
4.2
2.3 to 2.7
1.0
6.2
tPZL tPZH
Output enable time
3.0 to 3.6
0.8
4.7
2.3 to 2.7
1.0
5.1
tPLZ tPHZ
Output disable time
3.0 to 3.6
0.8
4.8
Setup tIme, HIGH or
LOW level Dn to LE
2.3 to 2.7
1.0
ts
3.0 to 3.6
1.0
Hold time HIGH or
LOW level Dn to LE
2.3 to 2.7
1.5
th
3.0 to 3.6
1.5
2.3 to 2.7
1.5
tw
LE pulse width, HIGH
3.0 to 3.6
1.5
tOSLH tOSHL
Output to output skew
time (1) (2)
ns
ns
ns
ns
ns
ns
ns
2.3 to 2.7
0.5
3.0 to 3.6
0.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|,
tOSHL = | tPHLm - tPHLn|)
2. Parameter guaranteed by design
Table 9.
Capacitive characteristics
Test condition
Symbol
CIN
Parameter
Value
TA = 25 °C
VCC
(V)
Unit
Min.
Typ.
Max.
Input capacitance
2.5 or 3.3
VIN = 0 or VCC
-
6
-
pF
COUT
Output capacitance
2.5 or 3.3
VIN = 0 or VCC
-
7
-
pF
CPD
Power dissipation
capacitance (1)
2.5 or 3.3
fIN = 10MHz
VIN = 0 or VCC
-
20
-
pF
1. CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the
operating current consumption without load. (Refer to Test Circuit). Average operating current can be
obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit)
10/18
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54VCXH162373
5
Test circuit
Test circuit
Figure 5.
Test circuit
Table 10.
Test circuit
Test
tPLH, tPHL
Switch
Open
tPZL, tPLZ (VCC = 3.0 to 3.6 V)
6V
tPZL, tPLZ (VCC = 2.3 to 2.7 V)
2 VCC
tPZH, tPHZ
GND
CL = 30 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500 Ω or equivalent
RT = ZOUT of pulse generator (typically 50 Ω)
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Waveforms
6
54VCXH162373
Waveforms
Table 11.
Waveform symbol value
VCC
Symbol
Figure 6.
12/18
3.0 to 3.6 V
2.3 to 2.7 V
VIH
2.7 V
VCC
VM
1.5 V
VCC/2
VX
VOL +0.3 V
VOL +0.15 V
VY
VOH -0.3 V
VOH -0.15 V
Waveform - LE TO Qn propagation delays, LE minimum pulse width, Dn to
LE setup and hold times (f = 1 MHz; 50% duty cycle)
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54VCXH162373
Waveforms
Figure 7.
Waveform - output enable and disable time (f = 1 MHz; 50% duty cycle)
Figure 8.
Waveform - propagation delay time (f = 1 MHz; 50% duty cycle)
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Package mechanical data
7
54VCXH162373
Package mechanical data
54VCXH162373 products are supplied into ceramic body / metal lid hermetic Flat 48-pin
space package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 12.
Flat-48 (MIL-STD-1835) mechanical data
mm
inch
Dim.
14/18
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.18
2.47
2.72
0.086
0.097
0.107
b
0.20
0.254
0.30
0.008
0.010
0.012
c
0.12
0.15
0.18
0.005
0.006
0.007
D
15.57
15.75
15.92
0.613
0.620
0.627
E
9.52
9.65
9.78
0.375
0.380
0.385
E2
6.22
6.35
6.48
0.245
0.250
0.255
E3
1.52
1.65
1.78
0.060
0.065
0.070
e
0.635
0.025
f
0.20
0.008
L
6.85
8.38
9.40
0.270
0.330
0.370
Q
0.66
0.79
0.92
0.026
0.031
0.036
S1
0.25
0.43
0.61
0.010
0.017
0.024
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54VCXH162373
Figure 9.
Package mechanical data
Package dimension
7330585B
Note:
The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the
package. Connecting unused pins or metal lid to ground or to the power supply will not affect
the electrical characteristics.
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15/18
Order codes
54VCXH162373
8
Order codes
Table 13.
Ordering information
Package
48-pin flat
16/18
Min op.
voltage
Lead
finish
Radiation
level
1.8 V
Gold plated
300 krad
Flight models
Engineering model
Packing
RHRXH162373K1
Conductive strip pack
QML-V
RHFXH162373K03V
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54VCXH162373
9
Revision history
Revision history
Table 14.
Document revision history
Date
Revision
Changes
09-Jul-2004
1
First release
17-May-2005
2
SMD qualified
19-Jun-2006
3
300 krad bullet updated, new template, mechanical data updated
30-Jul-2007
4
Typo in Table 12 on page 14.
17-Sep-2008
5
Updated cover page
23-Sep-2009
6
Updated Table 13 on page 16
02-Aug-2011
7
Added Note: on page 15 and in the "Pin connections" diagram on the
coverpage
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54VCXH162373
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