A5970AD Up to 1 A switch step down switching regulator for automotive applications Features ■ Qualified following the AEC-Q100 requirements (temperature grade 3), see PPAP for more details. ■ Temperature range -40 °C to 85 °C ■ 1 A DC output current ■ Operating input voltage from 4.4 V to 36 V ■ 3.3 V / (±2 %) reference voltage ■ Output voltage adjustable from 1.235 V to 35 V ■ Low dropout operation: 100 % duty cycle ■ 500 kHz Internally fixed frequency ■ Voltage feedforward ■ Zero load current operation ■ Internal current limiting ■ Inhibit for zero current consumption ■ Synchronization ■ Protection against feedback disconnection ■ Thermal shutdown SO-8 Description The A5970AD is a step down monolithic power switching regulator with a switch current limit of 1.35 A so it is able to deliver more than 1 A DC current to the load depending on the application conditions. The output voltage can be set from 1.235 V to 35 V. The device uses an internal P-channel D-MOS transistor (with a typical RDS(on) of 250 mΩ) as switching element to avoid the use of bootstrap capacitor and guarantee high efficiency. An internal oscillator fixes the switching frequency at 500 kHz to minimize the size of external components. Having a minimum input voltage of 4.4 V only, it is particularly suitable for 5 V bus, available in all computer related applications. Applications ■ Pulse by pulse current limit with the internal frequency modulation offers an effective constant current short circuit protection. Dedicated to automotive applications Figure 1. Application schematic L1 15uH VIN=4.4V to 35V VCC 8 1 4 2 SYNCH COMP C4 C1 A5970AD 22nF R1 STPS340U 5k6 C2 100uF 10V 5 6 35V May 2008 D1 FB 10uF CERAMIC Vout=3.3V OUT C3 R3 220pF 4k7 VREF 3.3V 7 GND 3 INH R2 3k3 Rev 1 1/16 www.st.com 1 A5970AD 1 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 6 4.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 Oscillator and synchronizator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.7 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/16 A5970AD 1 Pin settings 1.1 Pin connection Figure 1. 1.2 Pin connection (top view) Pin description Table 1. Pin description N Pin 1 OUT Description Regulator output. SYNCH Master/slave synchronization. When it is open, a signal synchronous with the turn-off of the internal power is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. Connecting together the SYNC pin of two devices, the one with the higher frequency works as master and the other one, works as slave. 3 INH A logical signal (active high) disables the device. With IHN higher than 2.2 V the device is OFF and with INH lower than 0.8 V, the device is ON. If INH is not used the pin must be grounded. When it is open, an internal pullup disables the device. 4 COMP 2 E/A output for frequency compensation. Feedback input. Connecting directly to this pin results in an output voltage of 1.235 V. An extenal resistive divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7 k). 5 FB 6 VREF 3.3 V VREF. No cap is requested for stability. 7 GND Ground. 8 VCC Unregulated DC input voltage. 3/16 A5970AD 2 Electrical data 2.1 Maximum ratings Table 2. Absolute maximum ratings Symbol Value Unit 40 V V V V8 Input voltage V1 OUT pin DC voltage OUT pin peak voltage at ∆t = 0.1µs -1 to 40 -5 to 40 I1 Maximum output current int. limit. V4 , V5 Analog pins 4 V -0.3 to VCC V -0.3 to 4 V 0.75 W Operating junction temperature range -40 to 150 °C Storage temperature range -55 to 150 °C SO8 Unit 120 (1) °C/W V3 INH V2 SYNCH PTOT Tj TSTG 2.2 Parameter Power dissipation at TA ≤ 70 °C Thermal data Table 3. Thermal data Symbol RthJA Parameter Maximum thermal resistance junction-ambient 1. Package mounted on board 4/16 A5970AD Electrical characteristics Table 4. Electrical characteristics (TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified) Symbol VCC RDS(on) IL fSW Parameter Test condition Operating input voltage range Min MOSFET on resistance Maximum limiting current Typ 4.4 0.250 VCC= 4.4 to 36 V Switching frequency Duty cycle 1.35 1.8 430 500 0 Max Unit 36 V 0.5 Ω A 570 kHz 100 % 1.25 V Dynamic characteristics (see test circuit). V5 Voltage feedback 4.4 V < VCC < 36 V η Efficiency V0 = 5 V, VCC = 12 V 1.220 1.235 90 % DC characteristics Iqop Total operating quiescent current Iq Quiescent current Duty cycle = 0; VFB=1.5 V Iqst-by Total stand-by quiescent current Vinh > 2.2 V 5 50 7 mA 2.7 mA 100 µA 0.8 V Inhibit Device ON INH threshold voltage Device OFF 2.2 V 3.5 V Error amplifier VOH High level output voltage VFB = 1 V VOL Low level output voltage VFB = 1.5 V Io source Io sink Source output current Sink output current VCOMP = 1.9 V; 0.4 VCOMP = 1.9 V; V 190 300 µA 1 1.5 mA VFB = 1 V VFB = 1 V Ib Source bias current DC open loop gain gm Transconductance 2.5 RL= 8 3 ICOMP = -0.1 mA to 0.1 mA; 50 4 µA 57 dB 2.3 mS VCOMP = 1.9 V 5/16 A5970AD Table 4. Electrical characteristics (continued) (TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit VREF V 0.74 V 0.25 0.45 mA Synch function High input voltage VCC = 4.4 to 36 V; Low input voltage VCC = 4.4 to 36 V; Slave synch current Vsynch = 0.74 V(1) Vsynch = 2.33 V 2.5 0.11 0.21 Master output amplitude Isource= 3 mA 2.75 3 V Output pulse width No load, Vsynch= 1.65 V 0.20 0.35 µs 3.234 3.3 3.366 V 3.2 3.3 3.399 V 5 10 mV 8 15 mV 18 30 mA Reference section Reference voltage IREF = 0 to 5 mA VCC = 4.4 V to 36 V Line regulation Load regulation Short circuit current IREF = 0 mA VCC = 4.4 V to 36 V IREF = 0 mA 5 1. Guaranteed by design. 6/16 A5970AD 4 Functional description The main internal blocks are shown in Figure 2, where is reported the device block diagram. They are: ■ A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3 V reference voltage is externally available. ■ A voltage monitor circuit that checks the input and internal voltages. ■ A fully integrated sawtooth oscillator whose frequency is 500 kHz ■ Two embedded current limitations circuitries which control the current that flows through the power switch. The pulse by pulse current limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the Frequency Shifter reduces the switching frequency in order to strongly reduce the duty cycle. ■ A transconductance error amplifier. ■ A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power. ■ An high side driver for the internal P-MOS switch. ■ An inhibit block for stand-by operation ■ A circuit to realize the thermal protection function. Figure 2. Block diagram 7/16 A5970AD 4.1 Power supply and voltage reference The internal regulator circuit (shown in Figure 2) consists of a start-up circuit, an internal voltage preregulator, the bandgap voltage reference and the bias block that provides current to all the blocks. The starter gives the start-up currents to the whole device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). The preregulator block supplies the bandgap cell with a preregulated voltage VREG that has a very low supply voltage noise sensitivity. 4.2 Voltages monitor An internal block senses continuously the VCC, VREF and VBG. If the voltages go higher than their thresholds, the regulator starts to work. There is also an hysteresis on the VCC (UVLO). Figure 3. 4.3 Internal regulator circuit Oscillator and synchronizator Figure 4 shows the block diagram of the oscillator circuit. The clock generator provides the switching frequency of the device that is internally fixed at 500 kHz. The frequency shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the ramp generator and Synchronizator blocks. The ramp generator circuit provides the sawtooth signal, used to realize the PWM control and the internal voltage feed forward, while the synchronizator circuit generates the synchronization signal. Infact the device has a synchronization pin that can works both as master and slave. As master to synchronize external devices to the internal switching frequency. 8/16 A5970AD As slave to synchronize itself by external signal. In particular, connecting together two devices, the one with the lower switching frequency works as slave and the other one works as master. To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization threshold with a duty cycle that can vary approximately from 10 % to 90 %, depending also on the signal frequency and amplitude. The frequency of the synchronization signal must be at least higher than the internal switching frequency of the device (500 kHz). Figure 4. 4.4 Oscillator circuit Current protection The A5970AD has two current limit protections, pulse by pulse and frequency fold back. The schematic of the current limitation circuitry for the pulse by pulse protection is shown in Figure 5. The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series, RSENSE. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a sufficiently low duty cycle at 500 kHz, the output current, in strong overcurrent or short circuit conditions, could increase again. For this reason the switching frequency is also reduced, so keeping the inductor current under its maximum threshold. The frequency shifter (see Figure 4) depends on the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decreases too. 9/16 A5970AD Figure 5. 4.5 Current limitation circuitry Error amplifier The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. The output (COMP) is connected to the external compensation network. The uncompensated error amplifier has the following characteristics: Table 5. Uncompensated error amplifier Tranconductance Low frequency gain Minimum sink/source voltage Output voltage swing Input bias current 2300 µS 65 dB 1500 µA/300 µA 0.4 V/3.65 V 2.5 µA Note: The error amplifier output is compared with the oscillator sawtooth to perform PWM control. 4.6 PWM comparator and power stage This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM signal for the driving stage. The power stage is a very critical block cause it has to guarantee a correct turn on and turn OFF of the PDMOS. The turn ON of the power element, or better, the rise time of the current at turn on, is a very critical parameter to compromise. At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses. But there is a limit introduced by the recovery time of the recirculation diode. In fact when the current of the power element equals the inductor current, the diode turns off and the drain of the power is free to go high. But during its recovery time, the diode can be considered as an 10/16 A5970AD high value capacitor and this produces a very high peak current, responsible of many problems: ● Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics. ● Turn ON overcurrent causing a decrease of the efficiency and system reliability. ● Big EMI problems. ● Shorter freewheeling diode life. The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the parasitics elements of the board) that increase the voltage drop across the PDMOS. In order to minimize all these problems, a new topology of driving circuit has been used and its block diagram is shown in Figure 6. The basic idea is to change the current levels used to turn on and off the power switch, according with the PDMOS status and with the gate clamp status. This circuitry allow to turn off and on quickly the power switch and to manage the above question related to the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that Vgs of the internal switch goes higher than Vgsmax. The ON/OFF control block avoids any cross conduction between the supply line and ground. Figure 6. Driving circuitry 11/16 A5970AD 4.7 Inhibit function The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2 V the device is disabled and the power consumption is reduced to less than 100 µA. With INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible. 4.8 Thermal shutdown The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 °C). The sensing element of the chip is very close to the PDMOS area, so ensuring an accurate and fast temperature detection. An hysteresis of approximately 20 °C avoids that the devices turns on and off continuously 12/16 A5970AD 5 Additional features and protections 5.1 Feedback disconnection In case of feedback disconnection, the duty cycle increases versus the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this dangerous condition, the device is turned off if the feedback pin remains floating. 5.2 Output overvoltage protection The overvoltage protection, OVP, is realized by using an internal comparator, which input is connected to the feedback, that turns off the power stage when the OVP threshold is reached. This threshold is typically 30 % higher than the feedback voltage. When a voltage divider is requested for adjusting the output voltage (see test application circuit), the OVP intervention will be set at: Equation 1 R 1 + R2 V OVP = 1.3 × --------------------- × V FB R2 Where R1 is the resistor connected between the output voltage and the feedback pin, while R2 is between the feedback pin and ground. 5.3 Zero load Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so, the device works properly also with no load at the output. In this condition it works in burst mode, with random repetition rate of the burst. 13/16 A5970AD 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 14/16 A5970AD Table 6. SO-8 mechanical data mm inch Dim Min Typ Max Min Typ Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D(1) 4.80 5.00 0.1890 0.197 E 3.80 4.00 0.15 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k 0° (min), 8° (max) ccc Figure 7. 0.10 0.0039 Package dimensions 15/16 A5970AD 7 Revision history 7 Table 7. Document revision history Date Revision 2-May-2008 1 Changes Initial release. 16/16 A5970AD Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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